Multi-clock-source low-jitter burr-free switching audio clock management device

Abstract

The invention relates to the field of digital audio equipment, provides a multi-clock-source low-jitter burr-free switching audio clock management device, and aims to solve the problems that multi-clock switching generates shock-wave lock falling and forced resampling loses tone quality. The device comprises a multi-channel clock source module, a clock selection and gating module and an audio processing unit. The clock selection and gating module comprises a burr-free multiplexer and an interlocking logic unit, and ensures that only one path of clock is enabled and output at any moment; the device physically monitors the audio word clock frequency through the independent external microcontroller, and outputs a hardware trigger signal, thereby realizing clock source autonomous interlocking switching without a main control chip, and controlling the audio processing unit to realize bypass straight-through transmission. The method is suitable for high-fidelity audio equipment such as a Bluetooth receiver and the like.

Description

Technical Field

[0001] This invention relates to the field of digital audio device structure, and more particularly to an audio clock management device with low jitter and glitch-free switching of multiple clock sources. Background Technology

[0002] In digital audio equipment, common solutions to adapt to different sampling rates include a single clock source with a phase-locked loop (PLL) / frequency division, or unifying the input to a fixed sampling rate through resampling. However, these solutions may introduce additional jitter or processing errors, making it difficult to meet the requirements of low jitter and output stability in high-fidelity scenarios. Another solution involves multi-clock source switching; if it lacks glitch-free gating, interlocking structures, and isolation design from the RF / main control power supply, glitches or phase jumps may occur during switching, causing the subsequent decoder to lose lock or generate audible noise.

[0003] Furthermore, existing technologies commonly employ highly integrated wireless audio master control chips (such as Bluetooth system-on-a-chip (SoC)) to implement functions such as sampling rate identification, clock management, and sampling rate conversion (SRC). Their internal clock paths and algorithms are often fixed by the original manufacturer. Modifying the underlying firmware to achieve external low-jitter clock synchronization or bypass pass-through is not only difficult to develop and time-consuming to verify, but also struggles to guarantee system stability in abnormal scenarios such as lock-down or system crashes. Additionally, the uncontrollable internal SRC strategy may prevent the guarantee of a true native sampling rate output. Therefore, a structural solution is needed that can independently acquire the input sampling rate and drive clock switching and bypass pass-through via hardware, without intervention from the master control chip's underlying firmware. Summary of the Invention

[0004] This invention provides an audio clock management device with low jitter and glitch-free switching across multiple clock sources, achieved through the following product structure: (1) The multi-channel clock source module works in conjunction with the interlocking gate control structure to achieve glitch-free clock switching, ensuring that only one clock signal is enabled and output at any given time; (2) Set up an independent clock power rail power supply module, adopt a low-noise voltage regulator and filter isolation network, and separate it from the RF / main control power rail topology to reduce noise coupling and jitter degradation; (3) In some embodiments, the audio processing unit (30) includes a sampling rate conversion module (32) and a parallel bypass path (33); by controlling the bypass switch (34), the input audio data can be selectively bypassed by the sampling rate conversion module (32), thereby achieving bit-perfect transmission when the input sampling rate matches the target clock, and avoiding signal damage caused by forced resampling. Attached Figure Description

[0005] Figure 1This is a system block diagram of the device of the present invention, showing the connection relationship of the multi-channel clock source module 10, clock selection and gating module 20, audio processing unit 30, output interface 40, independent clock power rail power supply module 50 and external power interface 80, etc. Figure 2 This is a schematic diagram of a multi-clock source and glitch-free switching structure, showing the connection relationship between the first TCXO 11, the second TCXO 12, the glitch-free clock multiplexer 21, the gating unit 22, the interlocking logic unit 23, and the output clock 24. Figure 3 This is a schematic diagram of an independent clock power rail isolation structure, showing the power supply relationship between the battery / input power supply 51, low-noise regulator 52, filter isolation network 53, decoupling capacitor 54 and clock-related modules, as well as their topological separation from the RF / main control power rail 70; Figure 4 This is a schematic diagram of the sampling rate conversion bypass structure, showing the connection relationship between the sampling rate conversion module 32, the bypass path 33, the bypass switch 34, and the control logic 25. Detailed Implementation The present invention will be further described below with reference to the accompanying drawings. It should be understood that the following embodiments are only used to explain the present invention and do not constitute a limitation on the scope of protection.

[0006] 1. Overall Structure (see...) Figure 1 ) like Figure 1 As shown, this device includes a multi-channel clock source module 10, a clock selection and gating module 20, an audio processing unit 30, an output interface 40, and an independent clock power rail power supply module 50. In some embodiments, it may also include a sampling rate / status information input terminal 60 (e.g., from wireless protocol negotiation results, decoder status, or clock measurements). The output interface 40 may include an S / PDIF coaxial output interface 401 and / or an S / PDIF optical fiber output interface 402. In addition, this device may also include an external power interface 80 (e.g., a USB interface) for external power supply or charging. 2. Glitch-free switching structure with multiple clock sources (see...) Figure 2 ) like Figure 2 As shown, the multi-channel clock source module 10 includes at least a first TCXO 11 and a second TCXO 12. The clock selection and gating module 20 includes a glitch-free clock multiplexer 21, a gating unit 22, and an interlock logic unit 23; the interlock logic unit 23 is used to control the selection and gating process, ensuring that only one clock signal is enabled and output at any given time, thereby achieving glitch-free switching and reducing the risk of subsequent stage lock-up. The output clock can be denoted as 24.

[0007] Regarding frequency selection, the first TCXO 11 can be an integer multiple of 44.1kHz×512, and the second TCXO 12 can be an integer multiple of 48kHz×512; in a preferred embodiment, the first TCXO is 22.5792MHz and the second TCXO is 24.576MHz. 3. Independent clock power rail isolation structure (see...) Figure 3 ) like Figure 3 As shown, the independent clock power rail power supply module 50 may include a battery / input power supply 51, a low-noise regulator 52, and a filtering isolation network 53 (ferrite bead and / or RC network). The filtering isolation network 53 is used to isolate noise coupling of the RF / master power rail 70. To further suppress ripple and transient interference, decoupling capacitors 54 may be placed near the power supply pins of the multi-clock source module 10. 4. Sampling rate conversion bypass structure (see...) Figure 4 ) like Figure 4As shown, in some embodiments, the audio processing unit 30 may include a sampling rate conversion module 32 and a bypass path 33 connected in parallel with it. The bypass path 33 includes a bypass switch 34. When the bypass switch 34 is closed, the input audio data 301 bypasses the sampling rate conversion module 32 and is directly transmitted to the output audio data 302, thereby forming an output path that does not require forced resampling. The control logic (25) includes an independent frequency sensing microcontroller (MCU) (e.g., an external microcontroller), whose input is bypassed and coupled to the word clock (LRCLK) signal line of the synchronous serial audio interface (I2S) of the audio processing unit (30). To ensure signal integrity, the input of the frequency sensing microcontroller (MCU) may be bypassed and coupled to the word clock (LRCLK) signal line through a high-impedance buffer unit and / or a level matching unit to complete frequency measurement without significantly loading the word clock (LRCLK) signal line. The frequency sensing microcontroller (MCU) does not participate in the decryption or processing of audio data (DATA). It only measures the physical frequency of the word clock (LRCLK) in real time to determine the frequency series to which the input sampling rate belongs, and outputs a hardware trigger signal to the clock selection and gating module 20 and / or bypass switch 34. When the input sampling rate is detected to match the target clock source, the bypass switch 34 is controlled to close. When the input sampling rate is detected to be mismatched with the target clock source or the link is unstable, the sampling rate conversion module 32 is activated and / or the bypass switch 34 is disconnected to improve output compatibility and avoid abnormal popping, locking, or playback interruption. The closing of the bypass switch 34 enables the signal path to pass-through at the physical level and avoid SRC algorithm processing, thereby achieving bit-perfect transmission. Since the sampling rate determination and clock / bypass control are independently completed by the external microcontroller, the clock management system of this device is completely decoupled from the underlying code of the wireless audio main control chip, ensuring the determinism of bypass pass-through at the physical path.

[0008] Terminology Explanation (Bug / No-Bug Switching): In this application, "glitch" refers to an unwanted transient anomaly on the output clock signal that occurs at the moment of clock source switching or within a short time window before and after switching. This includes, but is not limited to: brief jumps in amplitude or logic level, glitch pulses, abnormal multiple flips, and short-term irregular edges caused by switching contention / metastable states. The glitch typically manifests as a transient pulse or edge that does not conform to the target clock cycle within one or more output cycles, potentially introducing additional phase errors or jitter components. "Glitch-free switching" refers to controlling the switching timing and isolating the signal path to prevent the output clock from generating the aforementioned unwanted transient anomalies during switching, or to suppressing these transient anomalies within a range that will not be recognized as valid edges by subsequent clock receiving / phase-locked loop / sampling circuits.

[0009] Preferred embodiment (disabling idle TCXOs to suppress spatial crosstalk / phase noise degradation): As a preferred embodiment, in the clock architecture of high-fidelity (Hi-Fi) audio equipment, it is common to need to switch clock sources at different frequencies between different sampling rate families, such as 22.5792MHz and 24.576MHz. When multiple high-frequency TCXOs oscillate simultaneously in the same circuit board space, their harmonic components and near-field electromagnetic radiation may be coupled to the target clock channel through spatial coupling, parasitic capacitance / inductance coupling of traces, and high-frequency impedance paths of power / ground networks, forming high-frequency spatial crosstalk. In audio systems, this crosstalk can further manifest as increased noise floor, increased spurious components, and deterioration of system phase noise and jitter. To suppress the aforementioned effects at the physical source, the frequency sensing microcontroller (MCU) can implement deep control over the enable and / or output enable (EN / OE) terminals of each TCXO: when the target TCXO is selected as the output clock source, the MCU synchronously controls the unselected TCXOs to enter the off state, stopping their oscillation. This reduces high-frequency energy injection and spatial electromagnetic radiation from inactive clock sources, thereby reducing coupling interference to the target clock signal and improving system phase noise / jitter performance. Furthermore, the MCU can combine clock source stability criteria (including frequency sensing results, stability timing, or lock confirmation signals) to determine the off / on timing sequence, achieving lower system noise and jitter while ensuring switching reliability. In a specific circuit implementation, the control signal output by the frequency sensing microcontroller (MCU) can be directly connected, or indirectly connected to the enable terminal and / or output enable terminal (EN / OE) of each TCXO via a level conversion circuit or a buffer / drive circuit, so as to safely adapt to TCXO devices with different operating voltages. To facilitate understanding, a set of example scenarios are provided (which do not constitute a limitation on the scope of protection): (1) When the frequency sensing microcontroller (MCU) measures the word clock (LRCLK) frequency to correspond to the 44.1kHz frequency series, the control module enables the first TCXO (11) and selects the corresponding path; if the frequency sensing microcontroller (MCU) determines that the input sampling rate matches the target clock, the bypass switch (34) is closed, so that the audio data is directly output through the bypass path (33) to achieve perfect bit transmission.

[0010] (2) When the frequency sensing microcontroller (MCU) measures the word clock (LRCLK) frequency to correspond to the 48kHz frequency system, the control module enables the second TCXO (12) and selects the corresponding path; when the matching condition is met, the bypass switch (34) is also closed to achieve direct output.

[0011] (3) When the frequency sensing microcontroller (MCU) detects that the input sampling rate is an integer multiple of the target clock (e.g., 88.2kHz, 96kHz, etc.), the control module selects the corresponding clock source and its multiplication / division link (if any) according to the preset mapping relationship; if the matching conditions are met, bypass can continue to be used.

[0012] (4) When the word clock (LRCLK) frequency measurement result does not match the available clock source, the frequency drift is obvious, or the link is unstable, the bypass switch (34) remains open, and the audio data is processed by the sampling rate conversion module (32) and output to avoid abnormal popping, lockout or playback interruption.

[0013] Other notes This device can be used in Bluetooth receivers, digital turntables, network players, and other similar devices. Output interface 40 may also include an S / PDIF optical output interface 402 or other digital audio output interfaces. Explanation of Terms and Abbreviations Master Clock Signal (MCLK): The master clock used to drive audio processing and digital-to-analog conversion; Input (IN): The input terminal for signals or data; Output (OUT): The output terminal for signals or data; Temperature-compensated crystal oscillator (TCXO): An oscillator used to generate low-jitter clock signals; Sampling Rate Conversion (SRC): A functional module used to convert between different sampling rates; Pass-through: refers to a working mode in which the signal bypasses the sampling rate conversion (SRC) process and is directly output; Bit-Perfect: refers to audio data that has not undergone any changes in bit depth or sampling rate during transmission; Phase-locked loop (PLL): Phase-locked loop circuit; Low dropout linear regulator (LDO): Low dropout linear regulator circuit; Universal Serial Bus (USB): Universal Serial Bus interface; Synchronous Serial Audio Interface (I2S): A commonly used digital audio serial bus interface; Sony / Philips Digital Interface (S / PDIF): Digital audio interface; Symbol Explanation 10—Multi-channel clock source module; 11—First TCXO; 12—Second TCXO; 20—Clock selection and gating module; 21—Glitch-free clock multiplexer; 22—Gating unit; 23—Interlock logic unit; 24—Output clock; 30—Audio processing unit; 40—Output interface; 401—S / PDIF coaxial output interface; 402—S / PDIF fiber optic output interface; 50—Independent clock power rail powered module; 51—Battery / input power supply; 52—Low-noise regulator; 53—Filter isolation network; 54—Decoupling capacitor; 60—Sampling rate / status information input (optional); 70—RF / main control power rail; 80—External power interface (USB interface preferred); 25—Control logic; 32—Sampling rate conversion module; 33—Bypass path; 34—Bypass switch; 301—Input audio data; 302—Output audio data.

Claims

1. An audio clock management device with low jitter and glitch-free switching across multiple clock sources, applied to audio equipment, characterized in that, include: (1) A multi-channel clock source module (10) containing at least two independent clock sources; (2) Clock selection and gating module (20), which is connected to the multi-channel clock source module (10). The clock selection and gating module (20) includes at least a glitch-free clock multiplexer (21) and an interlock logic unit (23), which is used to select the target clock source and enable output under interlock conditions, ensuring that only one clock signal is enabled and output at any given time.

2. The apparatus according to claim 1, characterized in that, Also includes: An independent clock power rail power supply module (50) is used to provide an independent clock power rail for the multi-channel clock source module (10) and / or the clock selection and gating module (20), the independent clock power rail power supply module (50) including a low-noise regulator (52) and a filter isolation network (53).

3. The apparatus according to claim 2, characterized in that, The independent clock power rail power supply module (50) meets at least one of the following technical features: A. The filtering isolation network (53) includes ferrite beads and / or RC networks, and the independent clock power rail is separated from the RF / master power rail (70) in circuit topology; B. Place a decoupling capacitor (54) near the power supply pin of the multi-channel clock source module (10).

4. The apparatus according to claim 1, characterized in that, The multi-channel clock source module (10) is a multi-channel temperature-compensated crystal oscillator (TCXO), including at least a first TCXO (11) and a second TCXO (12); and the nominal frequencies of the first TCXO and the second TCXO satisfy at least one of the following conditions: A. These are integer multiples of 44.1kHz × 512 and 48kHz × 512, respectively; B. Approximately 22.5792MHz and 24.576MHz respectively.

5. The apparatus according to claim 1 or 2, characterized in that, Also includes: An audio processing unit (30) is connected to the clock selection and gating module (20); and an output interface (40) is connected to the audio processing unit (30).

6. The apparatus according to claim 5, characterized in that, The device satisfies at least one of the following technical features: A. The clock selection and gating module (20) further includes a gating unit (22), which cooperates with the interlock logic unit (23) to achieve glitch-free timing control during the switching process and output a clock signal (24) to the audio processing unit (30). B. The output interface (40) includes a Sony / Philips Digital Interface (S / PDIF) coaxial output interface (401) and / or an S / PDIF fiber optic output interface (402).

7. The apparatus according to claim 5, characterized in that, The audio processing unit (30) includes a sampling rate conversion module (32) and a bypass path (33) connected in parallel with the sampling rate conversion module (32). The bypass path (33) includes a bypass switch (34) for bypassing or disabling the transmission of input audio data to the output interface (40) when a target clock source is selected and the bypass switch (34) is closed.

8. The apparatus according to claim 7, characterized in that, The control logic (25) integrated within or communicating with the clock selection and gating module (20) includes an independent frequency sensing microcontroller (MCU); the input of the frequency sensing microcontroller (MCU) is bypassed and coupled to the word clock (LRCLK) signal line of the synchronous serial audio interface (I2S) of the audio processing unit (30), and is configured to measure the physical frequency of the word clock (LRCLK) in real time to determine the input sampling rate, and output a hardware trigger signal to the clock selection and gating module (20) and / or the bypass switch (34) according to the frequency measurement result, so as to control the bypass switch (34) to close when the input sampling rate matches the target clock source, and control the sampling rate conversion module (32) to work when they do not match.

9. The apparatus according to claim 8, characterized in that, The input of the frequency sensing microcontroller (MCU) is bypassed and coupled to the word clock (LRCLK) signal line through a high-impedance buffer unit and / or a level matching unit to perform frequency measurement without significantly loading the word clock (LRCLK) signal line.

10. The audio clock management device with low jitter and glitch-free switching for multiple clock sources according to claim 8, characterized in that: The control signal output by the frequency sensing microcontroller (MCU) is directly or indirectly connected to the enable terminal and / or output enable terminal (EN / OE) of each temperature compensated crystal oscillator (TCXO) via a level conversion circuit or a buffer / drive circuit. When the clock selection and gating module (20) selects a target TCXO as the output clock source, the frequency sensing microcontroller (MCU) synchronously outputs a control signal to turn off the EN / OE of at least one unselected TCXO, so as to stop the internal oscillation of the unselected TCXO and / or prohibit its clock signal output.

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