Method and device for automatically synthesizing general set communication algorithm for switch topology awareness

Abstract

The invention discloses an automatic synthesis method and device of a general set communication algorithm for switch topology awareness. According to the method, a physical topology is abstracted into a directed graph containing equipment and switch nodes, topological features and resource constraints are modeled in a unified mode, AllGather and AlltoAll operators are described by adopting preposed / postposed conditions, and automatic synthesis of an algorithm is achieved in combination with a time extension network and event-driven greedy scheduling. The method adapts to a complex multi-stage switch topology, supports multiple core set communication operators, realizes efficient and high-quality set communication algorithm synthesis, is irrelevant to a network layer protocol, and effectively overcomes the defects that an existing method is poor in topology adaptability, low in synthesis efficiency and narrow in operator support range.

Description

Technical Field

[0001] This invention relates to the fields of distributed high-performance computing, data center networks and communication scheduling technology, and in particular to a method and apparatus for automatically synthesizing a general aggregate communication algorithm with switch topology awareness. Background Technology

[0002] As the scale of distributed training and scientific computing continues to expand, modern computing clusters typically employ multi-layered, heterogeneous interconnect architectures. For example, NVLink / PCIe is used within machines, InfiniBand / RoCE is used between machines, and connections are made through multiple levels of switches. These topologies exhibit significant differences in link bandwidth, latency, and switch forwarding behavior, making it difficult for traditional, manually designed aggregation communication algorithms (such as Ring and Halving-Doubling) to fully utilize hardware resources, resulting in low communication efficiency.

[0003] Existing research proposes to automatically generate communication schedulers through algorithmic synthesis. Traditional operator generation algorithms based on time-extended networks can only synthesize the AllGather algorithm and do not support multi-level switch topologies and AlltoAll operators. On the other hand, the TECLL algorithm based on mixed-integer linear programming modeling has extremely high solution overhead on complex networks and is difficult to scale to large-scale nodes. Therefore, how to achieve efficient, general, and scalable automatic synthesis of set communication algorithms for general multi-level topologies while ensuring scheduling quality has become a key technical challenge in this field. Summary of the Invention

[0004] The purpose of this invention is to address the shortcomings of existing technologies by proposing an automatic synthesis method and apparatus for a general set communication algorithm with switch topology awareness.

[0005] The objective of this invention is achieved through the following technical solution: an automatic synthesis method for a general aggregate communication algorithm with switch topology awareness, comprising the following steps:

[0006] S1. Model the physical interconnection topology of switches and computing devices as a weighted directed graph;

[0007] S2. Constructing communication operators based on directed graphs;

[0008] S3. Construct a time-extended network to obtain the transmission time matrix for each computing device;

[0009] S4. Generate preconditions and postconditions according to the communication operator type, calculate the priority of preconditions and postconditions according to the transmission time matrix, and initialize the time queue and data volume.

[0010] S5. Extract the minimum time step from the time queue, process all arrival events at that moment, update the operator and delete the satisfied postconditions, traverse the unsatisfied postconditions according to priority, select the source device and transmission target according to the operator type, perform resource reservation, and if successful, generate a new arrival event and add it to the time queue.

[0011] S6. For different types of target operators, execute dedicated optimization strategies to complete data block replacement or hop-by-hop routing advancement and priority update; input the updated data into step S5 until the termination condition is met to obtain the final scheduling combination and completion time.

[0012] Furthermore, the step of modeling the physical interconnection topology of the switches and computing devices as a weighted directed graph includes:

[0013] The physical topology is abstracted as a directed physical graph containing device nodes and switch nodes. The nodes include computing devices and relay components. Each directed edge is associated with bandwidth and static latency. Each switch in the relay component is configured with cut-through forwarding mode and store-and-forward mode, and the concurrent capacity of the inbound and outbound ports is also configured.

[0014] Furthermore, the construction of communication operators based on directed graphs includes:

[0015] The requirements of the set communication operator are uniformly described by a set of preconditions and a set of postconditions. The preconditions indicate that the device already has data blocks, and the postconditions indicate that the device needs data blocks. Data block partitioning strategy is supported. After each device partitions data, the data block number is mapped to a tuple form: the block number of the AllGather operator includes the source device and the block number, and the block number of the AlltoAll operator includes the source device, the destination device, and the block number.

[0016] Furthermore, the process of constructing the transmission time matrix includes:

[0017] Based on link static latency, link bandwidth, and data volume, and with link transmission time as the edge cost, Dijkstra's shortest path search is performed on each source device to construct a transmission time matrix, representing the shortest transmission time between each node.

[0018] Furthermore, the time-extended network maintains two types of resource occupancy states: the busy deadline of link resources and the time occupancy interval set of switch ports. When the synthesizer attempts to schedule a transmission, the time-extended network performs a route feasibility check to verify whether the link and port resources are available. If successful, resource reservation is completed. At the same time, the T-time-extended network converts each successfully scheduled transmission into an arrival event, inserts it into the event queue, and drives the synthesizer to advance in chronological order, avoiding the redundant overhead of fixed time steps.

[0019] Furthermore, the calculation of the priorities for preconditions and postconditions based on the transmission time matrix includes: selecting the shortest time between each switch and each computing device as the initial priority based on the time spread matrix, and then using the AllGather operator according to... Sort in ascending order, AlltoAll operator by Sort in descending order.

[0020] Furthermore, the step of selecting the source device and transmission target based on the operator type and performing resource reservation includes:

[0021] For the AllGather operator, from the set of direct adjacent devices of the target device d, select the source device s that contains the data block required by the target device and has the shortest transmission time as the sending source, and set the transmission target directly as d;

[0022] For the AlltoAll operator, the source device that minimizes the transmission time is selected from the source devices that contain the data blocks required by the target device. If the target device d belongs to the direct adjacent set of s, then the transmission target is set to d; otherwise, the next-hop device n from the direct adjacent set of s, whose transmission time to the target device d is less than the transmission time between s and d, is selected as the transmission target, thus achieving hop-by-hop advancement.

[0023] After selecting the source device s and the transmission destination dst, the time-extended network module is invoked to perform a route feasibility check, verifying that all links on the path between the source device and the transmission destination are within the time interval. Whether the device is idle, t is the minimum time step, T[s][dst] is the time from the source device to the transmission target, and the concurrent number of inbound and outbound ports of the switches along the route is verified to be within the set capacity; if the check passes, resource reservation is completed, this transmission is added to the scheduling set, and an arrival event is generated and inserted into the event queue.

[0024] Furthermore, the specific optimization strategy includes:

[0025] For the AllGather operator, during scheduling, the optimal source device is selected from the direct adjacency list of the target device. After the resource reservation is successful, an arrival event is generated. When processing the arrival event, if the data block already exists in the target device, the original data block is replaced with a data block that is missing in the target device but already possessed by the optimal source device.

[0026] For the AlltoAll operator, after selecting the optimal source device during scheduling, if the target device is a direct neighbor of the source device, it will be transmitted directly; otherwise, the optimal next hop will be selected for hop-by-hop advancement. The set is maintained to avoid repeated scheduling. When the data block reaches the intermediate node, the priority is updated and the postconditions are rearranged locally to reduce tail latency.

[0027] According to another aspect of the specification, an automatic synthesis device for a general set communication algorithm for switch topology awareness is provided, including a memory and one or more processors. The memory stores executable code, and when the processor executes the executable code, it implements the aforementioned method for automatic synthesis of a general set communication algorithm for switch topology awareness.

[0028] According to another aspect of the specification, a computer-readable storage medium is provided having a program stored thereon, which, when executed by a processor, implements the aforementioned method for automatically synthesizing a general set communication algorithm for switch topology awareness.

[0029] The beneficial effects of this invention are as follows: Addressing the problems of low synthesis efficiency and poor scheduling quality in aggregate communication algorithms under complex heterogeneous interconnection topologies, this invention achieves accurate modeling of multi-level switch topologies by constructing a directed graph model containing switch nodes; designs an event-driven greedy synthesis framework, significantly reducing the time overhead of operator synthesis; designs a direct-access neighbor source selection and dynamic replacement mechanism, improving the bandwidth efficiency of aggregate communication; proposes a hop-by-hop advancement and dynamic priority strategy, solving the tail latency problem in All-to-All multi-hop communication; and simplifies the deployment process for integration into existing communication libraries through fine-grained and dynamic priority modulation mechanisms. These innovations provide an efficient and adaptive aggregate communication solution for high-performance clusters. Attached Figure Description

[0030] Figure 1 This is a flowchart of an automatic synthesis method for a general aggregated communication algorithm based on switch topology awareness;

[0031] Figure 2 A schematic diagram illustrating the construction of a Time Extended Network (TEN);

[0032] Figure 3 A schematic diagram of a typical topology used in the experiment;

[0033] Figure 4 A comparison chart of the solution time of the AllGather operator in different scenarios;

[0034] Figure 5 A comparison chart showing the solution time of the AlltoAll operator in different scenarios;

[0035] Figure 6 This is a schematic diagram of an automatic synthesis device for a general set communication algorithm with switch topology awareness provided in an embodiment of the present invention. Detailed Implementation

[0036] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0037] like Figure 1As shown, the present invention provides an automatic synthesis method for a general aggregated communication algorithm with switch topology awareness. The method includes the following steps:

[0038] Step 1: Topology modeling, abstracting the physical topology into a directed physical graph containing device nodes and switch nodes. The set of device nodes For computing devices such as GPUs / NPUs, the set of switch nodes Corresponding to trunk components such as NVSwitch and IB switch, Each directed edge This represents a physical unidirectional link, associated bandwidth. Static delay This directed graph modeling method supports the representation of multi-level switch structures (such as multi-hop paths from device to switch to switch to device) and parallel links (multiple physical links between the same pair of nodes), accurately depicting the complex interconnection relationships of real clusters. To characterize the forwarding behavior of switches, for each switch... Configure forwarding mode ,include:

[0039] 1) Cut-Through (CT) Mode: The switch can forward data downstream simultaneously while receiving the data stream, and the data exhibits pipelined processing characteristics within the switch. In this mode, multiple links on the path work in near parallel, and the end-to-end transmission time is mainly limited by the slowest link, modeled as the maximum transmission time of each link in the path. This mode is suitable for on-chip high-speed switching architectures such as NVSwitch and modern high-performance InfiniBand / RoCE switches;

[0040] 2) Store-and-Forward (SAF) mode: The switch must receive the entire data block before forwarding it. Data undergoes a complete storage and retransmission process within the switch. In this mode, the transmission time of each link segment is accumulated along the path, and the end-to-end transmission time is modeled as the sum of the transmission times of each link segment. This mode is used to characterize switching structures with significant buffering and segmented forwarding characteristics, or to provide an upper bound estimate of network forwarding behavior under conservative modeling assumptions.

[0041] Meanwhile, to limit the number of data streams that a switch can process in parallel at any given time, this invention provides each switch node with... Configure inbound port concurrency capacity Concurrent capacity of outgoing ports , , represent the maximum number of data streams that the switch can simultaneously receive and send at any given time. This parameter is used to characterize the switch's concurrent processing capacity constraint. During the scheduling process, the Time Extended Network (TEN) will check the concurrency of transmissions passing through the switch to ensure that the number of overlapping transmission intervals at any given time does not exceed the concurrent capacity of the corresponding port, thereby ensuring the actual executability of the synthesis algorithm.

[0042] Step 2: Operator construction, using a set of preconditions. With postcondition set A unified description of the requirements for set communication operators. Preconditions. Indicates equipment Data blocks already owned Postconditions Indicates equipment Data blocks are needed To support fine-grained scheduling, a data partitioning strategy is used, with each device's data block being divided into [number]. Depending on the operator type, data block numbering uses different binary tuple mapping methods:

[0043] 1) AllGather operator: for each source device The data is divided into Block, block number is recorded as ,in For data source devices, Number the blocks. In the initial state, for any... and ,have That is, each device owns all its own blocks; the set of postconditions is That is, each device needs to acquire all the blocks from all other devices, and the total number of postconditions is . .

[0044] 2) AlltoAll operator: for each source device Need to be sent to each destination device Send data and divide it into Block, block number is recorded as ,in For source devices, For the purpose of the equipment, Number the blocks. In the initial state, for any... ,have That is, each data block is initially located on its source device; the set of postconditions is That is, each destination device needs to obtain all the blocks sent to it by all source devices, and the total number of postconditions is also 1. .

[0045] Step 3: Time-scaling network construction, such as... Figure 2 As shown, firstly, based on the linear communication delay model (i.e. The model calculates the single-hop transmission time of a physical link. For any directed link... Its transmission time consists of both static delay and data-related transmission delay, i.e. ,in This refers to the static delay of the link. For link bandwidth, The data block size is used. Secondly, the end-to-end multi-hop transmission time is calculated based on the switch's forwarding mode. For switches using Cut-Through mode, data can be piped forwarded, and the end-to-end time is modeled as the maximum value of each segment of the path: For Store-and-Forward mode, it is the sum of the transmission times of each segment. Then, with... For edge cost, for each source device Perform Dijkstra's shortest path search and construct the transit time matrix. ,in Indicates the amount of data. Time from node To the node Link transmission time; Indicates from arrive The static latency of the link; Indicates from arrive Link bandwidth; A set of device nodes; For the transmission time matrix, Indicates from node To the node The shortest transmission time is determined. Based on this, the Time Extended Network (TEN) maintains two types of resource occupancy states: the busy deadline for link resources and the set of time occupancy intervals for switch ports. When the synthesizer attempts to schedule a transmission, TEN performs a route feasibility check to verify the availability of link and port resources; if successful, resource reservation is completed. Simultaneously, TEN converts each successfully scheduled transmission into an arrival event, inserts it into the event queue EQ, and drives the synthesizer forward in chronological order. This event-driven mechanism avoids the redundant traversal overhead of fixed time steps and is one of the core innovations in improving the efficiency of the algorithm's synthesis.

[0046] Step 4: Building an event-driven greedy composition framework. The core process is as follows:

[0047] 1) Initialization: Based on the set of preconditions constructed in step two. With postcondition set Combined with the transmission time matrix generated in step three Calculate each postcondition Initial priority: This priority indicates the shortest possible transmission time required to satisfy the postcondition in the current state. (Based on operator type) Sort: For the AllGather operator, use... Ascending order sorting prioritizes postconditions with shorter transmission times to accelerate data diffusion; for the AlltoAll operator, [the following is used]. Sort in descending order, prioritizing later conditions with longer transmission times to reduce tail latency. Simultaneously, initialize the event queue. , indicating in Start scheduling at any time; initialize the scheduling set. It is used to record all successfully scheduled transmissions.

[0048] 2) Event handling: from the event queue Extract the minimum time step Process all events arriving at that moment. For each arrival event, first update the preconditions. , indicating equipment Data block obtained ; then from the set of postconditions Remove all conditions that have been met. If the current operator is AllGather and the data block In the target device The place already exists (i.e.) If this is the case, the dynamic data block replacement mechanism described in the operator optimization step is triggered, and an attempt is made to use... Missing and Another data block replacement This means that the current transmission still contributes to the fact that the postconditions were not met.

[0049] 3) Greedy scheduling: Iterate through the set of unmet postconditions in order of current priority. For each postcondition The source device and transmission destination are selected based on the operator type:

[0050] a) For the AllGather operator, from the target device direct access device adjacency set In the middle, select the one that satisfies And transmission time Minimum source device As the sending source, the transmission destination is directly set to... ;

[0051] b) For the AlltoAll operator, from satisfying Select the device to make Minimum source device If the target device Then directly set Otherwise from Select to satisfy Next-hop device As This allows for progressive advancement by jumping each time step.

[0052] Select source device With the transmission target Then, the time-extended network module is invoked to perform a route feasibility check and verify the path. All links in the time interval Check if the internal resources are available, and whether the concurrent number of inbound and outbound ports of the switch passing through it exceeds the set capacity. If the checks pass, resource reservation is completed, and this transmission is added to the scheduling set. and generate arrival events. Insert Event Queue .

[0053] 4) Operator optimization: For different target operators, execute specific optimization strategies to complete data block replacement or hop-by-hop route advancement and priority updates.

[0054] a) For the AllGather operator, scheduling starts from the target device. direct adjacency list Select the optimal source device An arrival event is generated after successful resource reservation. When processing the arrival event, if the data block... Already exists Then use Missing and Replacement of existing data blocks Improve transmission efficiency;

[0055] b) For the AlltoAll operator, the optimal source device is selected during scheduling. Afterwards, if the target device for If the neighbor is directly accessible, the data is transmitted directly; otherwise, the optimal next hop is selected. Progress by hop. Maintain a set to avoid redundant scheduling; when a data block reaches an intermediate node, update the priority and perform a local rearrangement. Reduce tail delay;

[0056] 5) Termination condition: Repeat steps 2-4 until... If empty, output the scheduling set. Completion Time .

[0057] The system consists of four main modules:

[0058] Topology modeling module: responsible for physical topology analysis and graph model construction;

[0059] Operator construction module: responsible for the initialization of set communication operator conditions;

[0060] Time Extension Network Module: Responsible for transmission time calculation, resource status maintenance, and event management;

[0061] Synthesizer module: Responsible for executing event-driven scheduling and implementing dedicated synthesis logic for the two types of operators.

[0062] This invention is based on a variety of typical topologies ( Figure 3 The proposed automatic generation method for set communication operators was verified through numerical experiments, which were completed using C++. The experiments were designed from the following aspects:

[0063] The experiment was set with three data volumes (1MB, 64MB, 1GB) and two block counts (1, 2). The evaluation metrics included algorithm bandwidth (the ratio of data transmitted to completion time) and synthesis time.

[0064] Algorithm bandwidth comparison: Comparison of the algorithm bandwidth of the AllGather operator in different scenarios Figure 4 As shown, in complex topologies (DGX2-2, NDv2-4, AMD-2), the algorithm of this invention (FTACAS) significantly outperforms TECCL in bandwidth, reaching up to 3.05 times. In directly connected topologies (Mesh, DGX1-1), the performance of both is comparable, approaching the theoretical optimal value. A comparison of the bandwidth of the AlltoAll operator algorithm in different scenarios is provided. Figure 4 As shown, the overall performance of the method of the present invention is comparable to that of TECCL. In the DGX1-1 topology, the algorithm bandwidth can reach 1.5 times that of TECCL, and the difference in other topologies does not exceed 11%, demonstrating good stability.

[0065] Synthesis Time Comparison: Comparison of the solution time of the AllGather operator in different scenarios Figure 5 As shown, the synthesis time of the method of this invention is significantly better than TECCL, by 2 to 4 orders of magnitude, and the increase in solution time is smaller with the increase in the number of blocks, resulting in better scalability. For scenarios with 2 blocks in NDv2-4 and AMD-2 topologies, TECCL cannot complete the solution within 2 hours, while the method of this invention can still be completed within a few seconds. The solution time comparison of the AlltoAll operator in different scenarios is as follows: Figure 5As shown, the synthesis time of the method of the present invention is also 2 to 4 orders of magnitude faster than TECCL. Under the same configuration, the solution time of AlltoAll is slightly higher than AllGather, but it is still at a low level, which meets the needs of engineering applications.

[0066] In summary, the method of this invention achieves high-quality and high-efficiency automatic synthesis of ensemble communication algorithms under complex multi-level switch topologies through unified topology modeling, flexible operator representation, and efficient greedy scheduling strategy. It has significant advantages over existing technologies and can be widely applied to high-performance computing scenarios such as distributed training.

[0067] Corresponding to the aforementioned embodiment of the automatic synthesis method of a general set communication algorithm for switch topology awareness, the present invention also provides an embodiment of an automatic synthesis device for a general set communication algorithm for switch topology awareness.

[0068] See Figure 6 The present invention provides an automatic synthesis device for a general set communication algorithm for switch topology awareness, comprising a memory and one or more processors. The memory stores executable code, and when the processor executes the executable code, it is used to implement an automatic synthesis method for a general set communication algorithm for switch topology awareness as described in the above embodiment.

[0069] The embodiment of the automatic synthesis device for a general aggregated communication algorithm with switch topology awareness provided by this invention can be applied to any device with data processing capabilities, such as a computer. The device embodiment can be implemented in software, hardware, or a combination of both. Taking software implementation as an example, as a logical device, it is formed by the processor of any data processing device loading the corresponding computer program instructions from non-volatile memory into memory and executing them. From a hardware perspective, such as... Figure 6 The diagram shown is a hardware structure diagram of any device with data processing capabilities, which is an automatic synthesis device for a general aggregate communication algorithm with switch topology awareness provided by the present invention. Except for... Figure 6 In addition to the processor, memory, network interface, and non-volatile memory shown, any data processing device in the embodiment may also include other hardware depending on the actual function of the data processing device, which will not be described in detail here.

[0070] The specific implementation process of the functions and roles of each unit in the above device can be found in the implementation process of the corresponding steps in the above method, and will not be repeated here.

[0071] For the device embodiments, since they basically correspond to the method embodiments, the relevant parts can be referred to in the description of the method embodiments. The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of the present invention according to actual needs. Those skilled in the art can understand and implement this without creative effort.

[0072] This invention also provides a computer-readable storage medium storing a program thereon, which, when executed by a processor, implements an automatic synthesis method for a general aggregate communication algorithm for switch topology awareness as described in the above embodiments.

[0073] The computer-readable storage medium can be an internal storage unit of any data processing device described in any of the foregoing embodiments, such as a hard disk or memory. The computer-readable storage medium can also be an external storage device of any data processing device, such as a plug-in hard disk, smart media card (SMC), SD card, flash card, etc., equipped on the device. Furthermore, the computer-readable storage medium can include both internal storage units and external storage devices of any data processing device. The computer-readable storage medium is used to store the computer program and other programs and data required by the data processing device, and can also be used to temporarily store data that has been output or will be output.

[0074] The present invention also provides a computer program product, including a computer program, which, when executed by a processor, implements the aforementioned method for automatically synthesizing a general set communication algorithm for switch topology awareness.

[0075] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of this application are indicated by the claims.

[0076] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this application. This application is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A method for automatically synthesizing a general set communication algorithm with switch topology awareness, characterized in that, Includes the following steps: S1. Model the physical interconnection topology of switches and computing devices as a weighted directed graph; S2. Constructing communication operators based on directed graphs; S3. Construct a time-extended network to obtain the transmission time matrix for each computing device; S4. Generate preconditions and postconditions according to the communication operator type, calculate the priority of preconditions and postconditions according to the transmission time matrix, and initialize the event queue and data volume. S5. Extract the minimum time step from the event queue, process all arrival events at that moment, update the operator and delete the satisfied postconditions, traverse the unsatisfied postconditions according to priority, select the source device and transmission target according to the operator type, perform resource reservation, and if successful, generate a new arrival event and add it to the time queue. S6. For different types of target operators, execute dedicated optimization strategies to complete data block replacement or hop-by-hop routing advancement and priority update; input the updated data into step S5 until the termination condition is met to obtain the final scheduling combination and completion time.

2. The automatic synthesis method of a general set communication algorithm with switch topology awareness according to claim 1, characterized in that, The step of modeling the physical interconnection topology of switches and computing devices as a weighted directed graph includes: The physical topology is abstracted as a directed physical graph containing device nodes and switch nodes. The nodes include computing devices and relay components. Each directed edge is associated with bandwidth and static latency. Each switch in the relay component is configured with cut-through forwarding mode and store-and-forward mode, and the concurrent capacity of the inbound and outbound ports is also configured.

3. The automatic synthesis method of a general set communication algorithm with switch topology awareness according to claim 1, characterized in that, The communication operator based on directed graph construction includes: The requirements of the set communication operator are uniformly described by a set of preconditions and a set of postconditions. The preconditions indicate that the device already has data blocks, and the postconditions indicate that the device needs data blocks. Data block partitioning strategy is supported. After each device partitions data, the data block number is mapped to a tuple form: the block number of the AllGather operator includes the source device and the block number, and the block number of the AlltoAll operator includes the source device, the destination device, and the block number.

4. The automatic synthesis method of a general set communication algorithm with switch topology awareness according to claim 1, characterized in that, The process of constructing the transmission time matrix includes: Based on link static latency, link bandwidth, and data volume, and with link transmission time as the edge cost, Dijkstra's shortest path search is performed on each source device to construct a transmission time matrix, representing the shortest transmission time between each node.

5. The automatic synthesis method of a general set communication algorithm with switch topology awareness according to claim 1, characterized in that, The time-extended network maintains two types of resource occupancy states: the busy deadline of link resources and the time occupancy interval set of switch ports. When the synthesizer attempts to schedule a transmission, the time-extended network performs a route feasibility check to verify whether the link and port resources are available. If the check passes, the resource reservation is completed. At the same time, the time-extended network converts each successfully scheduled transmission into an arrival event, inserts it into the event queue, and drives the synthesizer to advance in chronological order, avoiding the redundant overhead of fixed time steps.

6. The automatic synthesis method of a general set communication algorithm with switch topology awareness according to claim 1, characterized in that, The priority calculation of preconditions and postconditions based on the transmission time matrix includes: selecting the shortest time between each switch and each computing device as the initial priority based on the time spread matrix, and then using the AllGather operator according to... Sort in ascending order, AlltoAll operator by Sort in descending order.

7. The automatic synthesis method of a general set communication algorithm with switch topology awareness according to claim 1, characterized in that, The step of selecting the source device and transmission destination based on the operator type and performing resource reservation includes: For the AllGather operator, from the set of direct adjacent devices of the target device d, select the source device s that contains the data block required by the target device and has the shortest transmission time as the sending source, and set the transmission target directly as d; For the AlltoAll operator, the source device that minimizes the transmission time is selected from the source devices that contain the data blocks required by the target device. If the target device d belongs to the direct adjacent set of s, then the transmission target is set to d; otherwise, the next-hop device n from the direct adjacent set of s, whose transmission time to the target device d is less than the transmission time between s and d, is selected as the transmission target, thus achieving hop-by-hop advancement. After selecting the source device s and the transmission destination dst, the time-extended network module is invoked to perform a route feasibility check, verifying that all links on the path between the source device and the transmission destination are within the time interval. Whether the device is idle, t is the minimum time step, T[s][dst] is the time from the source device to the transmission target, and the concurrent number of inbound and outbound ports of the switches along the route is verified to be within the set capacity; if the check passes, resource reservation is completed, this transmission is added to the scheduling set, and an arrival event is generated and inserted into the event queue.

8. The automatic synthesis method of a general set communication algorithm with switch topology awareness according to claim 1, characterized in that, The specific optimization strategies include: For the AllGather operator, during scheduling, the optimal source device is selected from the direct adjacency list of the target device. After the resource reservation is successful, an arrival event is generated. When processing the arrival event, if the data block already exists in the target device, the original data block is replaced with a data block that is missing in the target device but already possessed by the optimal source device. For the AlltoAll operator, after selecting the optimal source device during scheduling, if the target device is a direct neighbor of the source device, it will be transmitted directly; otherwise, the optimal next hop will be selected for hop-by-hop advancement. The set is maintained to avoid repeated scheduling. When the data block reaches the intermediate node, the priority is updated and the postconditions are rearranged locally to reduce tail latency.

9. An automatic synthesis device for a general aggregated communication algorithm with switch topology awareness, comprising a memory and one or more processors, wherein the memory stores executable code, characterized in that, When the processor executes the executable code, it implements a method for automatically synthesizing a general set communication algorithm for switch topology awareness as described in any one of claims 1-8.

10. A computer-readable storage medium having a program stored thereon, characterized in that, When the program is executed by the processor, it implements the automatic synthesis method of a general set communication algorithm for switch topology awareness as described in any one of claims 1-8.

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