Semiconductor structure and manufacturing method thereof

Abstract

The invention relates to the technical field of semiconductors, in particular to a semiconductor structure and a manufacturing method thereof. The manufacturing method comprises the steps of providing a substrate; sequentially forming a sacrificial material layer and a lamination layer on the substrate, wherein the lamination layer is formed by alternately stacking a first semiconductor layer and a second semiconductor layer; patterning the sacrificial material layer and the lamination layer to form a fin structure extending in the first direction, the fin structure comprising a sacrificial layer and a fin on the sacrificial layer; forming a dummy gate structure across the fin, wherein the fin comprises a first fin part spanned by the dummy gate structure and a second fin part except the first fin part; removing the second fin part to expose the side wall of the first fin part; removing the sacrificial layer to form a first space below the first fin part; forming a first dielectric layer filling the first space; and extending a first semiconductor material above the parts of the substrate on the two sides of the dummy gate structure to form a source region and a drain region.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for manufacturing the same. Background Technology

[0002] Against the backdrop of integrated circuit miniaturization, the gate control capability of three-gate 3D transistors decreases as device size shrinks.

[0003] In order to improve gate control capability and pursue higher device performance, related technologies have begun to adopt multi-channel field-effect transistors (MCFETs) with a four-gate structure. Summary of the Invention

[0004] According to one aspect of the present disclosure, a method for manufacturing a semiconductor structure is provided, the method comprising: providing a substrate; sequentially forming a sacrificial material layer and a stack of layers on the substrate, the stack of layers being formed by alternating stacks of a first semiconductor layer and a second semiconductor layer; patterning the sacrificial material layer and the stack of layers to form a fin structure extending in a first direction, the fin structure including a sacrificial layer and fins on the sacrificial layer, the sacrificial layer being the remaining portion of the patterned sacrificial material layer, and the fins being the remaining portion of the patterned stack of layers; forming a pseudo-gate structure spanning the fins, the fins including a first fin portion spanned by the pseudo-gate structure and a second fin portion excluding the first fin portion; removing the second fin portion to expose the sidewalls of the first fin portion; removing the sacrificial layer to form a first space below the first fin portion; forming a first dielectric layer filling the first space; and epitaxially forming a first semiconductor material above portions of the substrate located on both sides of the pseudo-gate structure to form source and drain regions.

[0005] According to some embodiments of this disclosure, the manufacturing method further includes, before epitaxially forming the first semiconductor material,: forming a protective layer covering the sidewalls of the first fin portion; after forming the protective layer, epitaxially forming a second semiconductor material on the surfaces of the substrate located on both sides of the dummy gate structure to form a semiconductor layer, wherein the second semiconductor material is an intrinsic semiconductor material or a semiconductor material with a doping type opposite to that of the first semiconductor material; and after forming the semiconductor layer, removing the protective layer, wherein the first semiconductor material is epitaxially formed on the surface of the second semiconductor material.

[0006] According to some embodiments of this disclosure, forming a first dielectric layer that fills the first space includes: depositing a first dielectric material to form the first dielectric layer and a second dielectric layer that covers the sidewalls of the first fin portion.

[0007] According to some embodiments of this disclosure, the protective layer includes the second dielectric layer.

[0008] According to some embodiments of this disclosure, the manufacturing method further includes: removing the second dielectric layer; and forming a third dielectric layer covering the sidewall of the first fin portion, the thickness of the third dielectric layer being less than the thickness of the second dielectric layer, and the protective layer including the third dielectric layer.

[0009] According to some embodiments of this disclosure, after removing the second fin portion, the manufacturing method further includes: removing a portion of both ends of the first semiconductor layer in the first fin portion in the first direction to form a gap in the first fin portion; and forming an inner spacer layer to fill the gap.

[0010] According to some embodiments of this disclosure, forming an inner spacer layer that fills the gap includes: depositing a second dielectric material to form the inner spacer layer and a fourth dielectric layer covering the sidewall of the first fin portion, the protective layer including the fourth dielectric layer.

[0011] According to some embodiments of this disclosure, forming a first dielectric layer filling the first space includes: after forming the inner spacer layer and the fourth dielectric layer, depositing a first dielectric material to form the first dielectric layer and a second dielectric layer covering the fourth dielectric layer together. The manufacturing method further includes: removing the second dielectric layer.

[0012] According to some embodiments of this disclosure, the thickness of the second dielectric layer is greater than the thickness of the fourth dielectric layer.

[0013] According to some embodiments of this disclosure, the first dielectric layer and the inner spacer layer are formed together by depositing a first dielectric material.

[0014] According to another aspect of the present disclosure, a semiconductor structure is provided, comprising: a substrate; one or a plurality of second semiconductor layers arranged vertically at intervals along a first direction on the substrate; a gate structure encapsulating each second semiconductor layer; a first dielectric layer located between the gate structure and the substrate; semiconductor layers located on the surfaces of the substrate on both sides of the gate structure; and source and drain regions located on the semiconductor layers, each source and drain region contacting each second semiconductor layer. The source and drain regions comprise a first semiconductor material, and the semiconductor layers comprise a second semiconductor material, wherein the second semiconductor material is an intrinsic semiconductor material or a semiconductor material with a doping type opposite to that of the first semiconductor material. Attached Figure Description

[0015] The accompanying drawings form part of this specification, illustrating exemplary embodiments of the present disclosure, and together with the specification serve to explain the principles of the present disclosure.

[0016] This disclosure will become clearer with reference to the accompanying drawings and the following detailed description, in which:

[0017] Figure 1A This is a schematic flowchart of a method for manufacturing a semiconductor structure according to some embodiments of the present disclosure.

[0018] Figure 1B This is a schematic flowchart of a method for manufacturing a semiconductor structure according to other embodiments of the present disclosure.

[0019] Figure 1C This is a schematic flowchart of a method for manufacturing a semiconductor structure according to some embodiments of the present disclosure.

[0020] Figures 2-12 This is a schematic diagram of various stages of a method for manufacturing a semiconductor structure according to some embodiments of the present disclosure.

[0021] Figures 13-17 This is a schematic diagram of the various stages of forming a semiconductor layer 240 in a method for manufacturing a semiconductor structure according to some embodiments of the present disclosure.

[0022] Figures 18-22 This is a schematic diagram of the various stages of execution steps S51, S52, S60 and S70 according to some embodiments of the present disclosure.

[0023] It should be understood that the same or similar reference numerals indicate the same or similar components. Detailed Implementation

[0024] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. The descriptions of the exemplary embodiments are merely illustrative and are in no way intended to limit the present disclosure or its application or use. The present disclosure may be implemented in many different forms and is not limited to the embodiments described herein. These embodiments are provided so that the present disclosure will be thorough and complete, and will fully express the scope of the disclosure to those skilled in the art. It should be noted that, unless specifically stated otherwise, the relative arrangement of components and steps, the composition of materials, numerical expressions, and values ​​set forth in these embodiments should be interpreted as exemplary only and not as limiting.

[0025] The terms "first," "second," and similar words used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different parts. Words such as "including" or "containing" mean that the element preceding the word encompasses the element listed after the word, and do not exclude the possibility of encompassing other elements as well. Terms such as "above" and "below" are used only to indicate relative positional relationships, and these relative positional relationships may also change accordingly when the absolute position of the described object changes.

[0026] In this disclosure, when a specific component is described as being located between a first component and a second component, an intermediary component may or may not be present between the specific component and the first or second component. When a specific component is described as connecting to other components, the specific component may be directly connected to the other components without having an intermediary component, or it may not be directly connected to the other components but may have an intermediary component.

[0027] All terms used in this disclosure (including technical or scientific terms) have the same meaning as understood by one of ordinary skill in the art to which this disclosure pertains, unless otherwise specifically defined. It should also be understood that terms defined in a general dictionary, such as a dictionary, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or highly formalized meaning, unless expressly defined herein.

[0028] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0029] In the structure of MCFET, the substrate area under the channel is relatively large, and the gate has poor control over this area, resulting in a large leakage current between the source and drain regions through this area, which has a significant impact on the electrical performance of the device.

[0030] In related technologies, leakage current between the source and drain regions is blocked by forming a dielectric isolation layer under the source and drain regions or under the entire device.

[0031] However, the inventors noted that although the dielectric isolation layer below the source and drain regions can block leakage current, the source and drain regions formed above the dielectric isolation layer are of poor quality because the dielectric isolation layer is not suitable for epitaxial semiconductor materials, which also affects the electrical performance of the device.

[0032] In view of this, the present disclosure proposes the following technical solution, which can take into account both the epitaxial quality of the source and drain regions and the leakage current.

[0033] Figure 1A This is a schematic flowchart of a method for manufacturing a semiconductor structure according to some embodiments of the present disclosure. Figure 1B It is a flowchart of a method for manufacturing a semiconductor structure according to some other embodiments of the present disclosure. Figure 1C It is a flowchart of a method for manufacturing a semiconductor structure according to some other embodiments of the present disclosure.

[0034] Figures 2-12 It is a schematic diagram of each stage of a method for manufacturing a semiconductor structure according to some embodiments of the present disclosure.

[0035] Next, first, in combination with Figure 1A , Figure 1B , Figures 2-12 the methods for forming semiconductor structures according to different embodiments of the present disclosure will be described.

[0036] First, referring to [[ID=2​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​ Figure 3 In step S30, the sacrificial material layer 200a and the stack 300a are patterned to form a fin structure 2300 extending in the first direction O1.

[0043] like Figure 3 As shown, the fin structure 2300 includes a sacrificial layer 200 and fins 300 on the sacrificial layer 200. The sacrificial layer 200 is the remaining part after the sacrificial material layer 200a is patterned, and the fins 300 are the remaining part after the stack 300a is patterned.

[0044] Figure 3 A first mask structure 310 for forming the fin structure 2300 is also shown, which is removed after the fin structure 2300 is formed.

[0045] In some embodiments, such as Figure 4 As shown, after forming the fin structure 2300, isolation regions 210 can be formed on both sides of the fin structure 2300 to isolate adjacent fin structures 2300, thereby isolating the ultimately formed adjacent MCFETs. The material of the isolation region 210 may include silicon oxide, such as silicon oxide.

[0046] As one implementation method, the upper surface of the isolation zone 210 can be flush with (e.g.) Figure 4 (as shown), above or below the upper surface of the sacrificial layer 200.

[0047] As one implementation method, the isolation region 210 can be formed directly on the surface of the substrate 100 after the patterned sacrificial material layer 200. In this case, such as Figure 4 As shown, the lower surface of the isolation zone 210 is flush with the lower surface of the sacrificial layer 200.

[0048] As another implementation, the substrate 100 can be further etched after the patterned sacrificial material layer 200, and the etched area of ​​the substrate 100 can be filled with an isolation material to form an isolation region 210. In this case, the lower surface of the isolation region 210 is lower than the lower surface of the sacrificial layer 200.

[0049] In some embodiments, such as Figure 4 As shown, after forming the fin structure 2300, a cover layer 320 may be formed covering the fin 300 and the isolation region 210 (if present). The material of the cover layer 320 may include silicon oxide, such as silicon oxide.

[0050] All the following figures are in the style of Figure 4 The description is based on the formation of an isolation zone 210 followed by a covering layer 320.

[0051] Subsequently, reference Figure 1A, Figure 5 and Figure 6 In step S40, a pseudo-gate structure 400 is formed across the fin 300.

[0052] In some embodiments, such as Figure 5 As shown, the pseudo-gate structure 400 includes a pseudo-gate 401 spanning the fin 300 and a second mask structure 402 located on the pseudo-gate 401. For example, the pseudo-gate material can be patterned using the second mask structure 402 to form the pseudo-gate 401. As some implementations, the second mask structure 402 may include a multi-layer structure, for example... Figure 5 The three-layer structure shown.

[0053] In some embodiments, such as Figure 6 As shown, further coverage can be formed. Figure 5 The dielectric layer structure 403 shown can be a single-layer or multi-layer structure. Each layer of the dielectric layer structure 403 can be a dielectric material composed of one or more of oxygen, nitrogen, and carbon combined with silicon, such as silicon nitride, silicon carbonitride, or silicon oxynitride. The dummy gate structure 400 also includes a portion of the dielectric layer structure 403 located on the sidewall of the dummy gate 401, i.e., a sidewall 404, to isolate the gate, source, and drain regions of the ultimately formed device.

[0054] In some embodiments, the pseudo-gate structure 400 further includes a portion of the cover layer 320 located between the pseudo-gate 401 and the fin 300, namely the pseudo-gate dielectric layer.

[0055] After forming the pseudo-gate structure 400, as Figure 6 As shown, the fin 300 at this time includes two parts: a first fin portion 300' spanned by the dummy gate structure 400 and a second fin portion 300' excluding the first fin portion 300'. It can be understood that the second fin portion 300' exists on both sides of the dummy gate structure 400. The second semiconductor layer 302 in the first fin portion 300' corresponds to the channel of the finally formed MCFET.

[0056] Subsequently, reference Figure 1A and Figure 7 In step S50, the second fin portion 300” is removed to expose the sidewall of the first fin portion 300’.

[0057] In some embodiments, such as Figure 7 As shown, while removing the second fin portion 300", the portion of the sacrificial layer 200 located below the second fin portion 300" can also be removed.

[0058] In other embodiments, the second fin portion 300" may not be removed or may be partially removed (e.g., as shown in the image). Figure 18(As shown) The sacrificial layer 200 is located below the second fin portion 300”.

[0059] In some embodiments, in step S50, a portion of the second mask structure 402 and a portion of the dielectric layer structure 403 located on the second mask structure 402 may be removed. For example, a portion of the uppermost layer of the second mask structure 402 may be removed.

[0060] Subsequently, reference Figure 1A and Figure 9 In step S60, the sacrificial layer 200 is removed to form a first space 220 below the first fin portion 300'.

[0061] As some implementation methods, wet etching or dry etching can be used to remove the sacrificial layer 200.

[0062] In some embodiments, such as Figure 1B As shown, the method for manufacturing a semiconductor structure further includes steps S51 and S52 after step S50.

[0063] In step S51, a portion of both ends of the first semiconductor layer 301 in the first fin portion 300' along the first direction O1 is removed to form a notch 303 in the first fin portion 300'. As some implementations, wet etching or dry etching can be used to form the notch 303.

[0064] like Figure 8 As shown, step S51 is performed to form the notch 303 before step S60 removes the sacrificial layer 200. It should be understood that, although not shown in the figures, step S51 can also be performed after step S60, i.e., the notch 302 is formed first, and then the sacrificial layer 200 is removed.

[0065] In step S52, an inner spacer layer 330 is formed to fill the gap 303. The material of the inner spacer layer 330 may include insulating materials such as silicon oxide and silicon nitride.

[0066] Subsequently, reference Figure 1A and Figure 11 In step S70, a first dielectric layer 230 is formed to fill the first space 220. It should be understood that the first dielectric layer 230 covers the surface of the substrate 100 located below the dummy gate structure 400, but does not cover the surfaces of the substrate 100 located on either side of the dummy gate structure 400. In other words, the first dielectric layer 230 only fills the first space 220.

[0067] In some embodiments, such as Figure 10 As shown, in Figure 9 A first dielectric material is deposited on the structure shown, and the portion of the first dielectric material filling the first space 220 serves as the first dielectric layer 230.

[0068] The first dielectric material can be one or more of oxygen, nitrogen, and carbon combined with silicon, such as silicon nitride, silicon carbonitride, or silicon oxynitride. Alternatively, the first dielectric material can also be an oxide of aluminum, such as aluminum oxide.

[0069] In some embodiments, such as Figure 11 As shown, steps S52 and S70 are performed together, that is, the first dielectric layer 230 and the inner spacer layer 330 are formed together by depositing the first dielectric material. For example, in Figure 9 A first dielectric material is deposited on the structure shown, and the portion of the first dielectric material filling the first space 220 and the portion of the first dielectric material filling the gap 303 are retained to form the first dielectric layer 230 and the inner spacer layer 330, respectively. In this way, the process can be effectively simplified.

[0070] Afterwards, refer to Figure 1A and Figure 12 In step S80, a first semiconductor material is epitaxially grown on the portion of the substrate 100 located on both sides of the dummy gate structure 400 to form a source region 500 and a drain region 500'.

[0071] The first semiconductor material can be epitaxially grown directly on the surface of the substrate 100, or other materials can be epitaxially grown on the surface of the substrate 100 before the first semiconductor material is epitaxially grown. This will be explained in detail later.

[0072] The type of the first semiconductor material is the same as the type of the transistor ultimately formed. For example, for NMOS, the first semiconductor material is an N-type semiconductor material, such as phosphorus or arsenic-doped silicon or silicon germanide; for PMOS, the first semiconductor material is a P-type semiconductor material, such as boron or aluminum-doped silicon or silicon germanide.

[0073] Through the above steps S10-S80, a semiconductor structure with a dielectric isolation layer (i.e., the first dielectric layer 230) below the first fin portion (corresponding to the channel) is formed. Compared with the method of blocking leakage current in related technologies, the embodiment of this disclosure does not form a dielectric isolation layer unsuitable for epitaxial semiconductor materials below the source region 500 and the drain region 500', which helps to improve the epitaxial quality of the source region 500 and the drain region 500'. At the same time, the first dielectric layer 230 below the channel can effectively block the leakage current at the bottom of the device, thereby effectively improving the electrical performance of the device.

[0074] The first dielectric layer 230 is formed by first forming a sacrificial material layer 200a on the substrate 100 and then removing it, which provides greater flexibility and control in the process implementation. For example, the thickness and composition of the sacrificial material layer can be adjusted according to actual needs. Furthermore, when the sacrificial material layer is made of a semiconductor material, it helps to ensure the quality of the stack-up.

[0075] Furthermore, this approach is compatible with semiconductor manufacturing processes and has lower requirements for the substrate 100. For example, only conventional semiconductor substrates are needed, which helps reduce costs.

[0076] In subsequent processes, the dummy gate 401 (and the second mask structure 402, if present) and all the first semiconductor layers 301 in the first fin portion 300' can be removed to form a space. In this space where the dummy gate 401 and the first semiconductor layers 301 were originally located, a gate dielectric layer (e.g., a high dielectric constant dielectric layer such as hafnium oxide) and a work function layer (e.g., titanium nitride) enclosing the second semiconductor layer 302 are sequentially formed, and then filled with metal material to form a metal gate. In this way, an MCFET with a dielectric isolation layer under the channel is formed, wherein the leakage current under the channel can be effectively blocked.

[0077] In some embodiments, such as Figure 1C As shown, the semiconductor structure manufacturing method further includes steps S53, S54, and S55, which are executed sequentially before step S80. The following... Figure 11 Based on the structure shown, combined with Figures 13-17 Please provide an explanation.

[0078] Figures 13-17 This is a schematic diagram of the various stages of forming a semiconductor layer 240 in a method for manufacturing a semiconductor structure according to some embodiments of the present disclosure.

[0079] refer to Figure 1C and Figure 14 In step S53, a protective layer 410 is formed covering the sidewall of the first fin portion 300'.

[0080] In some embodiments, such as Figure 14 As shown, the protective layer 410 can also cover the sidewall of the pseudo-gate structure 400, that is, cover the sidewall 404 in the pseudo-gate structure 400.

[0081] In some embodiments, step S53 may be performed as follows.

[0082] like Figure 13 As shown, a covering is formed Figure 11 The protective medium layer 410' of the structure shown.

[0083] like Figure 14 As shown, the portion of the protective dielectric layer 410' located on the surface of the substrate 100 is removed, and the portion of the protective dielectric layer 410' located on the sidewall of the first fin portion 300' is retained (in some cases, the portion of the protective dielectric layer 410' located on the sidewall of the dummy gate structure 400 may also be retained) as the protective layer 410.

[0084] As one implementation method, anisotropic etching can be used to remove the portion of the protective dielectric layer 410' located on the surface of the substrate 100. For example, anisotropic etching can remove the portion of the protective dielectric layer 410' in the horizontal direction (i.e., the direction parallel to the surface of the substrate 100) while retaining the portion of the protective dielectric layer 410' in the vertical direction (i.e., the direction perpendicular to the surface of the substrate 100).

[0085] Subsequently, reference Figure 1C and Figure 15 In step S54, after forming the protective layer 410, a second semiconductor material is epitaxially grown on the surface of the substrate 100 located on both sides of the dummy gate structure 400 to form a semiconductor layer 240.

[0086] The protective layer 410 can prevent the second semiconductor material from being epitaxially extended onto the sidewalls of the first fin portion 300' (especially the surfaces of the two ends of the second semiconductor layer 302 in the first direction O1), thereby affecting the quality of the source region 500 and the drain region 500'.

[0087] In some embodiments, the second semiconductor material is an intrinsic semiconductor material or a semiconductor material with a doping type opposite to that of the first semiconductor material.

[0088] As one implementation, the second semiconductor material can be an intrinsic semiconductor material such as silicon, germanium, or silicon germanide (e.g., silicon germanide). In this case, the resistance of the semiconductor layer 240 is relatively high.

[0089] In other implementations, for NMOS, the second semiconductor material can be a P-type semiconductor material, such as boron or aluminum-doped silicon or silicon germanide; for PMOS, the second semiconductor material can be an N-type semiconductor material, such as phosphorus or arsenic-doped silicon or silicon germanide. In this case, the semiconductor layer 240 forms PN junctions with the source region 500 and the drain region 500', respectively, and one of the PN junctions is reverse-biased when the device is in operation.

[0090] Subsequently, reference Figure 1C and Figure 16 In step S55, after the semiconductor layer 240 is formed, the protective layer 410 is removed. After the protective layer 410 is removed, the sidewall of the first fin portion 300' is exposed again.

[0091] Finally, refer to Figure 1C and Figure 17 Step S80 is executed to epitaxially grow a first semiconductor material on the surface of a second semiconductor material to form a source region 500 and a drain region 500'.

[0092] By performing steps S53-S55 prior to step S80, a semiconductor layer 240 can be formed beneath the source and drain regions 500, thereby enabling higher-quality epitaxy of the first semiconductor material in the source and drain regions 500' on the semiconductor layer 240. Furthermore, whether utilizing the inherently high resistance of the semiconductor material or forming a reverse-biased PN junction, the semiconductor layer 240 can further block leakage current from the source and drain regions 500 through the substrate 100 beneath the channel, thereby further improving the electrical performance of the device.

[0093] The specific implementation method and timing of step S53, forming the protective layer 410, are explained in detail below with some embodiments.

[0094] In some embodiments, in step S70, a first dielectric material is deposited to form a first dielectric layer 230 and a second dielectric layer 250 covering the sidewall of the first fin portion 300'.

[0095] As some implementation methods, such Figure 10 As shown, in the previous structure (e.g.) Figure 9 Based on the structure shown, a first dielectric material is deposited, retaining the portion of the first dielectric material that fills the first space 220 (in... Figure 10 The portion of the first fin portion 300' covered by the first dielectric material (not shown) serves as the first dielectric layer 230, while the portion of the first dielectric material covering the first fin portion 300' serves as the second dielectric layer 250.

[0096] In the case of forming a second dielectric layer 250 covering the sidewall of the first fin portion 300', the protective layer 410 can be implemented in different ways.

[0097] In some implementations, the protective layer 410 may include a second dielectric layer 250. In other words, the second dielectric layer 250 serves as the protective layer 410. Furthermore, by forming the second dielectric layer 250 together with the first dielectric layer 230, the step of forming additional material layers as the protective layer 410 can be eliminated, thereby effectively simplifying the process.

[0098] In other implementations, refer to Figure 11 Remove Figure 10 A second dielectric layer 250 is formed together with the first dielectric layer 230; furthermore, referring to Figure 13 and Figure 14 A third dielectric layer 420 is formed covering the sidewall of the first fin portion 300'. The thickness of the third dielectric layer 420 is less than the thickness of the second dielectric layer 250. In these implementations, the protective layer 410 includes the third dielectric layer 420.

[0099] Although the protective layer 410 can prevent the second semiconductor material from being epitaxially extended on the sidewall of the first fin portion 300', the thickness of the protective layer 410 will compress the area of ​​the second semiconductor material epitaxially extended in the horizontal direction over a certain length, thereby compressing the area of ​​the first semiconductor material epitaxially extended as well as the areas of the source region 500 and the drain region 500'.

[0100] In the above implementation, by removing the second dielectric layer 250 and forming an additional third dielectric layer 420 with a smaller thickness to act as a protective layer 410, the area of ​​the source region 500 and the drain region 500' can be prevented from being too small, thus reducing the risk of device performance damage.

[0101] The material of the third dielectric layer 420 can be one or more of oxygen, nitrogen, and carbon combined with silicon, such as silicon nitride, silicon carbonitride, or silicon oxynitride. Alternatively, the material of the third dielectric layer 420 can also be an oxide of aluminum, such as aluminum oxide.

[0102] In some embodiments, Figure 1B In step S52, a second dielectric material is deposited to form an inner spacer layer 330 and a fourth dielectric layer 430 covering the sidewalls of the first fin portion 300'. In this case, the protective layer 410 includes the fourth dielectric layer 430. The positional relationship between the fourth dielectric layer 430 and the inner spacer layer 330 can be referenced. Figure 20 and Figure 21 .

[0103] The second dielectric material can be one or more of oxygen, nitrogen, and carbon combined with silicon, such as silicon nitride, silicon carbonitride, or silicon oxynitride. Alternatively, the second dielectric material can also be an oxide of aluminum, such as aluminum oxide.

[0104] In the above embodiment, the fourth dielectric layer 430 serves as the protective layer 410. Furthermore, by forming the fourth dielectric layer 430 together with the inner spacer layer 330, the step of forming additional material layers as the protective layer 410 can be eliminated, thereby effectively simplifying the process.

[0105] In some embodiments, Figure 1A In step S70, after forming the inner spacer layer 330 and the fourth dielectric layer 430, a first dielectric material is deposited to form the first dielectric layer 230 and the second dielectric layer 250 covering the fourth dielectric layer 430 together. In this case, the fourth dielectric layer 430 and the second dielectric layer 250 are present on the sidewall of the first fin portion 300'.

[0106] When the fourth dielectric layer 430 and the second dielectric layer 250 are simultaneously present on the sidewall of the first fin portion 300', the protective layer 410 may also be implemented in different ways.

[0107] In some implementations, the protective layer 410 includes a fourth dielectric layer 430 and a second dielectric layer 250, that is, the fourth dielectric layer 430 and the second dielectric layer 250 together serve as the protective layer 410.

[0108] In some implementations, the second dielectric layer 250 can be removed. That is, the fourth dielectric layer 430 alone serves as the protective layer 410. Compared to the fourth dielectric layer 430 and the second dielectric layer 250 jointly serving as the protective layer 410, removing the second dielectric layer 250 can provide a larger area for the epitaxial first semiconductor material, preventing the areas of the source region 500 and the drain region 500' from being too small.

[0109] For example, the thickness of the second dielectric layer 250 is greater than the thickness of the fourth dielectric layer 430. In this case, the second dielectric layer 250 is thicker, and the combined thickness of the second dielectric layer 250 and the fourth dielectric layer 430 is greater, thus significantly compressing the area of ​​the epitaxial first semiconductor material. By removing the second dielectric layer 250, the area of ​​the epitaxial first semiconductor material can be prevented from becoming too small, thereby providing a larger area for the epitaxial first semiconductor material.

[0110] In the case where the semiconductor structure manufacturing method includes steps S51 and S52 (i.e., forming the inner spacer layer 330), steps S51, S52, S60 and S70 can be performed in a variety of different orders.

[0111] Figures 8-11 The example illustrates the execution sequence as S51→S60→(S52 and S70 are executed simultaneously). Several examples are given below to illustrate other execution sequences of steps S51, S52, S60, and S70.

[0112] In some cases, the steps can be executed in the following order: S51→S60→S52→S70, or S51→S60→S70→S52.

[0113] In other cases, the following order can be followed: S60→S51→(S52 and S70 are executed simultaneously), S60→S51→S52→S70, or S60→S51→S70→S52.

[0114] It should be noted that, since step S60 is executed first, the bottom surface of the lowest first semiconductor layer 301 in the first fin portion 300' will be exposed. During the process of executing step S51 to form the notch 303, the lowest first semiconductor layer 301 will also be removed from the bottom, resulting in the thickness of the lowest first semiconductor layer 301 becoming thinner, which affects the performance of the gate formed after the first semiconductor layer 301 is removed.

[0115] To address this issue, in some embodiments, the thickness of the lowest first semiconductor layer 301 in the first fin portion 300' is greater than the thickness of the other first semiconductor layers 301.

[0116] In some cases, the following sequence can be followed: S60→S70→S51→S52.

[0117] In some cases, the following sequence can be followed: S51→S52→S60→S70.

[0118] Figures 18-22 This is a schematic diagram of the various stages of execution steps S51, S52, S60 and S70 according to some embodiments of the present disclosure.

[0119] The following is combined Figures 18-22 The sequence S51→S52→S60→S70 will be explained.

[0120] like Figure 18 As shown, the sidewall of the first fin portion 300' is exposed after step S50 is executed. Figure 18 and Figure 7 The difference is: Figure 7 The portion of the sacrificial layer 200 located below the second fin portion 300” was completely removed, and Figure 18 The portion of the sacrificial layer 200 located below the second fin portion 300 was partially removed, while a portion was retained.

[0121] like Figure 19 As shown, step S51 is performed to form a notch 303 in the first fin portion 300'.

[0122] like Figure 20 As shown, step S52 is performed to form an inner spacer layer 330 that fills the gap 303. Figure 20 The image also shows a fourth dielectric layer 430 formed together with the inner spacer layer 330.

[0123] like Figure 21 As shown, step S60 is performed to form a first space 220 below the first fin portion 300'.

[0124] like Figure 22 As shown, step S70 is performed to form a first dielectric layer 230 that fills the first space 220.

[0125] Figure 22 The illustration shows the fourth dielectric layer 430 being removed. As previously mentioned, in some embodiments, the fourth dielectric layer 430 may be retained as a protective layer 410.

[0126] When the process is executed in the order of S51→S52→S60→S70, when the fourth dielectric layer 430 is formed in step S52 and the second dielectric layer 250 is formed in step S70, the second dielectric layer 250 covers the fourth dielectric layer 430.

[0127] This disclosure also proposes a semiconductor structure, which and its various further embodiments can be manufactured by the methods proposed in the above embodiments.

[0128] like Figure 17 As shown, the semiconductor structure includes: a substrate 100, one or more second semiconductor layers 302 (as a channel), a gate structure 400', a first dielectric layer 230, a semiconductor layer 240, and a source region 500 and a drain region 500'.

[0129] It is understood that the space occupied by the gate structure 400' is the total space occupied by the aforementioned pseudo-gate structure 400 and the first semiconductor layer 301, and the gate structure 400' wraps around each second semiconductor layer 302 and is located above the substrate 100.

[0130] The gate structure 400' includes sidewalls 404. In some embodiments, the gate structure 400' may further include a high-dielectric-constant dielectric layer, a work function layer, and a metal gate enclosing each second semiconductor layer 302 between the sidewalls 404 on both sides.

[0131] The second semiconductor layer 302 extends along the first direction O1, and when multiple second semiconductor layers 302 are present, they are arranged vertically at intervals. Since they are enclosed by the gate structure 400', the second semiconductor layer 302 is not shown. The position of the second semiconductor layer 302 can be referenced to the position of the second semiconductor layer 302 in the remaining figures.

[0132] The first dielectric layer 230 is located between the gate structure 400' and the substrate 100. The location of the first dielectric layer 230 can be referenced for example... Figure 11 The position of the first dielectric layer 230 in the middle.

[0133] Semiconductor layer 240 is located on the surface of substrate 100 on both sides of gate structure 400'.

[0134] The source region 500 and the drain region 500' are located on the semiconductor layer 240, and the source region 500 and the drain region 500' are each in contact with each of the second semiconductor layers 302.

[0135] In the semiconductor structure, the source region 500 and the drain region 500' include a first semiconductor material, the semiconductor layer 240 includes a second semiconductor material, and the second semiconductor material is an intrinsic semiconductor material or a semiconductor material with a doping type opposite to that of the first semiconductor material.

[0136] In some embodiments, when the semiconductor structure includes a plurality of second semiconductor layers 302, the metal gate between two adjacent second semiconductor layers 302 may have an inner spacer layer 330 at both ends in the first direction O1.

[0137] The embodiments of this disclosure have now been described in detail. To avoid obscuring the concept of this disclosure, some details known in the art have not been described. Those skilled in the art can fully understand how to implement the technical solutions disclosed herein based on the above description.

[0138] While specific embodiments of this disclosure have been described in detail by way of examples, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of this disclosure. Those skilled in the art should understand that modifications can be made to the above embodiments or equivalent substitutions can be made to some technical features without departing from the scope and spirit of this disclosure. The scope of this disclosure is defined by the appended claims.

Claims

1. A method for manufacturing a semiconductor structure, comprising: Provide substrate; A sacrificial material layer and a stack are sequentially formed on the substrate, the stack being formed by alternating stacking of a first semiconductor layer and a second semiconductor layer; The sacrificial material layer and the stack are patterned to form a fin structure extending in a first direction, the fin structure including a sacrificial layer and fins on the sacrificial layer, the sacrificial layer being the remaining portion of the sacrificial material layer after patterning, and the fins being the remaining portion of the stack after patterning. A pseudo-gate structure is formed across the fin, the fin including a first fin portion spanned by the pseudo-gate structure and a second fin portion excluding the first fin portion; Remove the second fin portion to expose the sidewall of the first fin portion; Remove the sacrificial layer to form a first space below the first fin portion; A first dielectric layer is formed to fill the first space; as well as A first semiconductor material is epitaxially grown over the portion of the substrate located on both sides of the dummy gate structure to form a source region and a drain region.

2. The method according to claim 1, further comprising, before epitaxially stretching the first semiconductor material: A protective layer is formed covering the sidewall of the first fin portion; After the protective layer is formed, a second semiconductor material is epitaxially grown on the surface of the substrate located on both sides of the dummy gate structure to form a semiconductor layer. The second semiconductor material is an intrinsic semiconductor material or a semiconductor material with a doping type opposite to that of the first semiconductor material. as well as After forming the semiconductor layer, the protective layer is removed. The first semiconductor material is epitaxially bonded to the surface of the second semiconductor material.

3. The method according to claim 2, wherein, The formation of the first dielectric layer filling the first space includes: A first dielectric material is deposited to form the first dielectric layer and a second dielectric layer covering the sidewalls of the first fin portion.

4. The method according to claim 3, wherein, The protective layer includes the second dielectric layer.

5. The method according to claim 3, further comprising: Remove the second dielectric layer; as well as A third dielectric layer is formed covering the sidewall of the first fin portion, the thickness of the third dielectric layer being less than the thickness of the second dielectric layer, and the protective layer includes the third dielectric layer.

6. The method according to claim 2, further comprising, after removing the second fin portion: Remove a portion of both ends of the first semiconductor layer in the first fin portion in the first direction to form a notch in the first fin portion; as well as An inner spacer layer is formed to fill the gap.

7. The method according to claim 6, wherein, The inner spacer layer that fills the gap includes: A second dielectric material is deposited to form the inner spacer layer and a fourth dielectric layer covering the sidewalls of the first fin portion, the protective layer including the fourth dielectric layer.

8. The method according to claim 7, wherein, The formation of the first dielectric layer filling the first space includes: After forming the inner spacer layer and the fourth dielectric layer, a first dielectric material is deposited to form the first dielectric layer and a second dielectric layer covering the fourth dielectric layer together; The method further includes: Remove the second dielectric layer.

9. The method according to claim 8, wherein, The thickness of the second dielectric layer is greater than the thickness of the fourth dielectric layer.

10. The method according to any one of claims 6-9, wherein, The first dielectric layer and the inner spacer layer are formed together by depositing a first dielectric material.

11. A semiconductor structure, comprising: Substrate; One or more second semiconductor layers, arranged vertically at intervals, extending along a first direction on the substrate; A gate structure that encloses each second semiconductor layer; A first dielectric layer is located between the gate structure and the substrate; A semiconductor layer is located on the surfaces of the substrate on both sides of the gate structure; as well as The source and drain regions are located on the semiconductor layer, and each of the source and drain regions is in contact with each second semiconductor layer. The source and drain regions comprise a first semiconductor material, and the semiconductor layer comprises a second semiconductor material, wherein the second semiconductor material is an intrinsic semiconductor material or a semiconductor material with a doping type opposite to that of the first semiconductor material.

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