Thin film transistor, manufacturing method thereof, and display device including the same

Abstract

An object of the present invention is to provide a thin film transistor, a method of manufacturing the same, and a display device including the same. A thin film transistor according to one embodiment of the present invention comprises: an active layer; and a gate electrode overlapping at least a portion of the active layer, where the active layer includes first and second active layers spaced apart from each other, where the first active layer includes a first oxide semiconductor layer; a second oxide semiconductor layer over the first oxide semiconductor layer; a third oxide semiconductor layer over the second oxide semiconductor layer, and wherein the second active layer includes a fourth oxide semiconductor layer; a fifth oxide semiconductor layer over the fourth oxide semiconductor layer; and a sixth oxide semiconductor layer on the fifth oxide semiconductor layer, in which the sum of the thicknesses of the first oxide semiconductor layer and the second oxide semiconductor layer is 10% to 40% of the thickness of the first active layer, and the sum of the thicknesses of the fifth oxide semiconductor layer and the sixth oxide semiconductor layer is 10% to 40% of the thickness of the second active layer.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of priority to Korean Patent Application No. 10-2024-0164745, filed on November 19, 2024, which is incorporated herein by reference as if fully set forth herein. Technical Field

[0003] The present invention relates to a thin-film transistor, a method for manufacturing the thin-film transistor, and a display device including the thin-film transistor. Background Technology

[0004] Because thin-film transistors can be fabricated on glass or plastic substrates, they are widely used as switching or driving elements in display devices such as liquid crystal displays or organic light-emitting devices.

[0005] Display devices may include, for example, switching thin-film transistors and driver thin-film transistors. The driver thin-film transistors, in particular, have a large s-factor, which is advantageous for grayscale representation.

[0006] Typically, thin-film transistors (TFTs) have a small s-factor to ensure switching characteristics. When these TFTs are used as driver TFTs in display devices, it becomes difficult to represent the grayscale of the display device.

[0007] Therefore, in order to easily represent grayscale using driving thin-film transistors in display devices, thin-film transistors with a large s-factor are required. Furthermore, even if a thin-film transistor has a large s-factor, it still needs to have excellent current characteristics in the on-state. Summary of the Invention

[0008] One embodiment of the present invention provides a thin-film transistor having a large s-factor during the threshold voltage period and a large current value in the on state by forming an active layer in a parallel structure.

[0009] One embodiment of the present invention provides a thin-film transistor having a large s-factor during the threshold voltage period and a large current value in the on state by forming two active layers with different widths in a parallel structure.

[0010] One embodiment of the present invention provides a thin-film transistor having a large s-factor during the threshold voltage period and a large current value in the on state by forming two active layers with high mobility oxide semiconductor layers at different positions in a parallel structure.

[0011] Another embodiment of the present invention is to provide a display device including such a thin-film transistor.

[0012] To address the aforementioned technical problems, one embodiment of the present invention provides a thin-film transistor comprising: an active layer; and a gate electrode overlapping at least a portion of the active layer, wherein the active layer comprises a first active layer and a second active layer spaced apart from each other, wherein the first active layer comprises: a first oxide semiconductor layer; a third oxide semiconductor layer located on the first oxide semiconductor layer; and a third oxide semiconductor layer located on the second oxide semiconductor layer, and wherein the second active layer comprises: a fourth oxide semiconductor layer; a fifth oxide semiconductor layer located on the fourth oxide semiconductor layer; and a sixth oxide semiconductor layer located on the fifth oxide semiconductor layer, wherein the sum of the thickness of the first oxide semiconductor layer and the thickness of the second oxide semiconductor layer is 10% to 40% of the thickness of the first active layer, and the sum of the thickness of the fifth oxide semiconductor layer and the thickness of the sixth oxide semiconductor layer is 10% to 40% of the thickness of the second active layer.

[0013] The second oxide semiconductor layer may have a higher mobility than the first oxide semiconductor layer and the third oxide semiconductor layer, and the fifth oxide semiconductor layer may have a higher mobility than the fourth oxide semiconductor layer and the sixth oxide semiconductor layer.

[0014] The mobility of the second and fifth oxide semiconductor layers can be 20 cm⁻¹. 2 / V∙s to 100cm 2 / V∙s.

[0015] The mobility of the first, third, fourth, and sixth oxide semiconductor layers can be 5 cm⁻¹. 2 / V∙s to 15cm 2 / V∙s.

[0016] The second oxide semiconductor layer and the fifth oxide semiconductor layer are each made of a first oxide semiconductor material, and the first oxide semiconductor material may include at least one of the following materials: an IO-based oxide semiconductor material having an In concentration of 30% to 50% relative to the total In and O concentration on an atomic basis; an IGZO-based oxide semiconductor material having an In concentration of 30% or greater relative to the total In, Ga and Zn concentration on an atomic basis; an FIZO-based oxide semiconductor material; a FIGZO-based oxide semiconductor material; and an IZO-based oxide semiconductor material.

[0017] The first oxide semiconductor layer, the third oxide semiconductor layer, the fourth oxide semiconductor layer, and the sixth oxide semiconductor layer are each formed of a second oxide semiconductor material, and the second oxide semiconductor material may include at least one of the following materials: an IGZO-based oxide semiconductor material (InGaZnO) having an In concentration of less than 30% relative to the total concentration of In, Ga, and Zn on an atomic basis; an GZTO-based oxide semiconductor material (GaZnSnO); and a GZO-based oxide semiconductor material (GaZnO).

[0018] The first active layer includes a first channel portion overlapping with the gate electrode; a first connection portion contacting one side of the first channel portion; and a second connection portion contacting the other side of the first channel portion. When the direction of the straight line connecting the first connection portion and the second connection portion with the shortest distance is a first direction and the direction perpendicular to the first direction is a second direction, the width of the first active layer can be greater than the width of the second active layer, with the second direction as a reference.

[0019] The thickness of the second oxide semiconductor layer can be greater than the thickness of the fifth oxide semiconductor layer.

[0020] The thickness of the second oxide semiconductor layer can be 3 nm or greater but less than 5 nm, and the thickness of the fifth oxide semiconductor layer can be 2 nm or greater but less than 3 nm.

[0021] Another embodiment of the present invention provides a method for manufacturing a thin-film transistor, comprising the following steps: preparing a base substrate having a first region and a second region; forming a second oxide semiconductor material layer on the second region and then etching the second oxide semiconductor material layer; forming a first oxide semiconductor material layer on the first region and the second region; forming a photoresist pattern on the first region; using the photoresist pattern as a mask to simultaneously etch the first oxide semiconductor material layer and the second oxide semiconductor material layer to form a first active layer and a second active layer; and forming a gate electrode on the first active layer and the second active layer.

[0022] The first oxide semiconductor material layer is disposed on the second oxide semiconductor material layer and can cover the side surface of the second oxide semiconductor material layer.

[0023] The photoresist pattern does not need to be set on the second area.

[0024] The first active layer includes: a first oxide semiconductor layer; a second oxide semiconductor layer located on the first oxide semiconductor layer; and a third oxide semiconductor layer located on the second oxide semiconductor layer. The second active layer includes: a fourth oxide semiconductor layer; a fifth oxide semiconductor layer located on the fourth oxide semiconductor layer; and a sixth oxide semiconductor layer located on the fifth oxide semiconductor layer. The sum of the thicknesses of the first oxide semiconductor layer and the second oxide semiconductor layer may be 10% to 40% of the thickness of the first active layer, and the sum of the thicknesses of the fifth oxide semiconductor layer and the sixth oxide semiconductor layer may be 10% to 40% of the thickness of the second active layer.

[0025] The shortest distance between the gate electrode and the fifth oxide semiconductor layer can be shorter than the shortest distance between the gate electrode and the second oxide semiconductor layer.

[0026] The method for manufacturing a thin-film transistor further includes the steps of forming a source electrode and a drain electrode, the source electrode and the drain electrode being spaced apart from each other and respectively connected to an active layer including a first active layer and a second active layer, wherein the shortest distance between the source electrode and the fifth oxide semiconductor layer may be shorter than the shortest distance between the source electrode and the second oxide semiconductor layer.

[0027] The shortest distance between the drain electrode and the fifth oxide semiconductor layer can be shorter than the shortest distance between the drain electrode and the second oxide semiconductor layer.

[0028] Another embodiment of the present invention may provide a display device including a thin-film transistor. Attached Figure Description

[0029] The above and other objects, features and advantages of this disclosure will become clearer from the following detailed description taken in conjunction with the accompanying drawings, wherein:

[0030] Figure 1 This is a plan view of a thin-film transistor according to one embodiment of the present invention.

[0031] Figure 2 It is along Figure 1 The cross-sectional view taken from line Ia-Ia'.

[0032] Figure 3 It is along Figure 1 The cross-sectional view taken from line Ib-Ib'.

[0033] Figure 4 It is along Figure 1 The cross-sectional view taken from the line Ic-Ic'.

[0034] Figure 5 This is a cross-sectional view of a thin-film transistor according to another embodiment of the present invention.

[0035] Figure 6 This is a cross-sectional view of a thin-film transistor according to another embodiment of the present invention.

[0036] Figure 7 This is a cross-sectional view of a thin-film transistor according to another embodiment of the present invention.

[0037] Figure 8 This is a threshold voltage curve of a thin-film transistor according to one embodiment of the present invention.

[0038] Figures 9A to 9G This is a plan view illustrating the manufacturing process of a thin-film transistor according to an embodiment of the present invention.

[0039] Figures 10A to 10G This is a cross-sectional view of the manufacturing process of a thin-film transistor according to an embodiment of the present invention.

[0040] Figures 11A to 11G This is a cross-sectional view of the manufacturing process of a thin-film transistor according to an embodiment of the present invention.

[0041] Figure 12 This is a schematic diagram of a display device according to another embodiment of the present invention.

[0042] Figure 13 yes Figure 12 A schematic diagram of a pixel (P). Detailed Implementation

[0043] The advantages and features of this disclosure and its implementation methods will be illustrated by the following embodiments described with reference to the accompanying drawings. However, this disclosure may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art. Furthermore, this disclosure is limited only by the scope of the claims.

[0044] The shapes, dimensions, ratios, angles, and quantities disclosed in the accompanying drawings used to describe embodiments of this disclosure are merely examples, and therefore, this disclosure is not limited to the details shown. Throughout the specification, the same reference numerals refer to the same elements. In the following description, detailed descriptions of relevant known functions or configurations will be omitted where it is determined that such detailed descriptions would unnecessarily obscure the focus of this disclosure.

[0045] When using the terms “including,” “having,” and “containing” as described in this disclosure, an additional part may be added unless “only” is used. Singular terms may include plural forms unless otherwise stated.

[0046] When interpreting the component, it is explained as including a error band, although there is no explicit description.

[0047] When describing positional relationships, such as when the positional relationship is described as "on," "above," "below," and "next to," one or more parts may be placed between two other parts, unless "exactly" or "directly" is used.

[0048] Spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” are used herein to readily describe the relationship between one or more elements and another as shown in the accompanying drawings. It should be understood that these terms are intended to cover different orientations of the device other than those depicted in the drawings. For example, if the device shown in the figures is reversed, a device described as being arranged “below” or “under” another device may be arranged “above” another device. Thus, the exemplary term “below or under” can include both “below or under” and “above” orientations. Similarly, the exemplary term “above” or “upper” can include both “above” and “below or under” orientations.

[0049] When describing temporal relationships, such as when time sequence is described as “after,” “following,” “next,” and “before,” discontinuous cases can be included unless “exactly” or “directly” is used.

[0050] It should be understood that although the terms "first," "second," etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0051] It should be understood that the term "at least one" includes all combinations relating to any one of the items. For example, "at least one of the first element, the second element, and the third element" can include two or more elements selected from the first element, the second element, and the third element, as well as all combinations of each of the first element, the second element, and the third element.

[0052] As will be fully understood by those skilled in the art, the features of the various embodiments of this disclosure may be coupled or combined with each other in part or in whole, and may interoperate differently with each other and be technically driven. Embodiments of this disclosure may be performed independently of each other, or may be performed together in an interdependent relationship.

[0053] Apart from the reference numerals for components in each figure describing embodiments of this disclosure, the same components may have the same symbols that may be shown in other figures.

[0054] In embodiments of this disclosure, for ease of description, the source electrode and drain electrode are distinguished, and the source electrode and drain electrode are interchangeable. A source electrode can be a drain electrode, and vice versa. Furthermore, the source electrode of any embodiment can be a drain electrode in another embodiment, and the drain electrode of any embodiment can be a source electrode in another embodiment.

[0055] In some embodiments of the present invention, for ease of description, the source region and the source electrode are distinguished, and the drain region and the drain electrode are distinguished; however, the embodiments of the present invention are not limited thereto. The source region can be the source electrode, and the drain region can be the drain electrode. Alternatively, the source region can be the drain electrode, and the drain region can be the source electrode.

[0056] Figure 1 This is a plan view of a thin-film transistor 100 according to one embodiment of the present invention. Figure 2 It is along Figure 1 The cross-sectional view taken from line Ia-Ia'. Figure 3 It is along Figure 1 The cross-sectional view taken from line Ib-Ib'. Figure 4 It is along Figure 5 A cross-sectional view taken from line Ic-Ic'. Figure 5 This is a cross-sectional view of a thin-film transistor 200 according to another embodiment of the present invention. Figure 6 This is a cross-sectional view of a thin-film transistor 200 according to another embodiment of the present invention.

[0057] A thin-film transistor 100 according to one embodiment of the present invention includes an active layer 130 and a gate electrode 150.

[0058] The components of the thin-film transistor 100 are described in detail below.

[0059] Glass or plastic can be used as the base substrate 110. Transparent plastics with flexible properties (such as polyimide) can be used as the plastic.

[0060] A light-shielding layer (not shown) may be disposed on the base substrate 110. The light-shielding layer (not shown) blocks light incident from the base substrate 110 and protects the active layer 130. If another structure is used as the light-shielding structure, the light-shielding layer (not shown) may be omitted.

[0061] According to one embodiment of the present invention, the buffer layer 120 may be disposed on the base substrate 110. Figure 2A buffer layer 120 disposed on a base substrate 110 is shown.

[0062] The buffer layer 120 has insulating properties and protects the active layer 130. The buffer layer 120 may include at least one of insulating silicon oxide (SiOx), silicon nitride (SiNx), and metal oxide.

[0063] although Figure 2 The buffer layer 120 is shown to be a single layer, but one embodiment of the invention is not limited thereto and may include multiple layers. Furthermore, another layer may be disposed between the base substrate 110 and the buffer layer 120, and another layer may be disposed between the buffer layer 120 and the active layer 130.

[0064] According to one embodiment of the present invention, the active layer 130 is disposed on the buffer layer 120.

[0065] According to one embodiment of the present invention, the active layer 130 may include a first active layer 131 and a second active layer 132. For example, Figure 1 The first active layer 131 and the second active layer 132, which are spaced apart from each other, are shown.

[0066] Reference Figure 1 The first active layer 131 and the second active layer 132 can be configured to extend along the first direction X and can be configured to be spaced apart from each other with the second direction Y as a reference.

[0067] According to one embodiment of the present invention, the active layer 130 may include a channel portion 130n, a source connection portion 130s, and a drain connection portion 130d.

[0068] According to one embodiment of the present invention, the first active layer 131 may include a first channel portion 131n, a first connecting portion 131s contacting one side of the first channel portion 131n, and a second connecting portion 131d contacting the other side of the first channel portion 131n. (See reference...) Figure 1 The first channel portion 131n overlaps with the gate electrode 150, the first connection portion 131s is connected to the source electrode 161, and the second connection portion 131d is connected to the drain electrode 162.

[0069] According to one embodiment of the present invention, the second active layer 132 may include a second channel portion 132n, a third connecting portion 132s contacting one side of the second channel portion 132n, and a fourth connecting portion 132d contacting the other side of the second channel portion 132n. (See reference) Figure 1 The second channel portion 132n overlaps with the gate electrode 150, the third connection portion 132s is connected to the source electrode 161, and the fourth connection portion 132d is connected to the drain electrode 162.

[0070] According to one embodiment of the present invention, the source connection portion 130s may include a first connection portion 131s and a third connection portion 132s. The drain connection portion 130d may include a second connection portion 131d and a fourth connection portion 132d.

[0071] The first connection portion 131s, the second connection portion 131d, the third connection portion 132s, and the fourth connection portion 132d can be formed by selectively conducting the active layer 130 made of semiconductor material. According to one embodiment of the invention, imparting conductivity to a specific portion of the active layer 130 so that it can function as a conductor is called selective conduction.

[0072] For example, the active layer 130 can be selectively conductive by ion doping. Thus, a first connection portion 131s, a second connection portion 131d, a third connection portion 132s, and a fourth connection portion 132d can be formed. However, one embodiment of the present invention is not limited thereto, and the active layer 130 can also be selectively conductive by other methods known in the art.

[0073] The first connection portion 131s, the second connection portion 131d, the third connection portion 132s, and the fourth connection portion 132d do not overlap with the gate electrode 150. Compared to the channel portion 130n, the first connection portion 131s, the second connection portion 131d, the third connection portion 132s, and the fourth connection portion 132d exhibit excellent conductivity and high mobility. Therefore, the first connection portion 131s, the second connection portion 131d, the third connection portion 132s, and the fourth connection portion 132d can each be used as wiring.

[0074] refer to Figure 1 When the direction of the straight line connecting the first connecting portion 131s and the second connecting portion 131d with the shortest distance is called the first direction X, the direction perpendicular to the first direction X can be called the second direction Y. For example, the first direction X can be called the length direction of the active layer 130, and the second direction Y can be called the width direction of the active layer 130.

[0075] According to one embodiment of the present invention, the first active layer 131 and the second active layer 132 may be arranged parallel to the first direction X.

[0076] According to one embodiment of the present invention, the first active layer 131 may include a first oxide semiconductor layer 131a, a second oxide semiconductor layer 131b, and a third oxide semiconductor layer 131c. For example, Figure 2The diagram illustrates a state where a second oxide semiconductor layer 131b is disposed on a first oxide semiconductor layer 131a and a third oxide semiconductor layer 131c is disposed on the second oxide semiconductor layer 131b. For example, the second oxide semiconductor layer 131b may be disposed between the first oxide semiconductor layer 131a and the third oxide semiconductor layer 131c.

[0077] According to one embodiment of the present invention, the second active layer 132 may include a fourth oxide semiconductor layer 132a, a fifth oxide semiconductor layer 132b, and a sixth oxide semiconductor layer 132c. For example, Figure 3 The diagram illustrates a state where a fifth oxide semiconductor layer 132b is disposed on a fourth oxide semiconductor layer 132a and a sixth oxide semiconductor layer 132c is disposed on the fifth oxide semiconductor layer 132b. For example, the fifth oxide semiconductor layer 132b may be disposed between the fourth oxide semiconductor layer 132a and the sixth oxide semiconductor layer 132c.

[0078] According to one embodiment of the present invention, the second oxide semiconductor layer 131b may have a higher mobility than the first oxide semiconductor layer 131a and the third oxide semiconductor layer 131c, and the fifth oxide semiconductor layer 132b may have a higher mobility than the fourth oxide semiconductor layer 132a and the sixth oxide semiconductor layer 132c.

[0079] For example, the mobility of the second oxide semiconductor layer 131b and the fifth oxide semiconductor layer 132b can be 20 cm⁻¹. 2 / V∙s or greater. Preferably, the mobility of the second oxide semiconductor layer 131b and the fifth oxide semiconductor layer 132b can be 20 cm⁻¹. 2 / V∙s to 100cm 2 / V∙s. For example, the mobility of the first oxide semiconductor layer 131a, the third oxide semiconductor layer 131c, the fourth oxide semiconductor layer 132a, and the sixth oxide semiconductor layer 132c can be less than 20 cm⁻¹. 2 / V∙s. Preferably, the mobility of the first oxide semiconductor layer 131a, the third oxide semiconductor layer 131c, the fourth oxide semiconductor layer 132a, and the sixth oxide semiconductor layer 132c can be 5 cm⁻¹. 2 / V∙s up to 15cm 2 / V∙s.

[0080] When the mobility of the second oxide semiconductor layer 131b and the fifth oxide semiconductor layer 132b is less than 20 cm⁻¹ 2At a voltage factor of / V∙s, it may become difficult to significantly adjust the threshold voltage difference between the parallel-formed first active layer 131 and the second active layer 132. As a result, the thin-film transistor 100 according to the invention may not have a large s-factor.

[0081] Furthermore, when the mobility of the second oxide semiconductor layer 131b and the fifth oxide semiconductor layer 132b is greater than 100 cm⁻¹ 2 At / V∙s, the charge carriers in the first active layer 131 and the second active layer 132 may become too large, making it difficult to accurately set the threshold voltage. Furthermore, in the worst case, the first active layer 131 and the second active layer 132 may actually behave like conductors.

[0082] When the mobility of the first oxide semiconductor layer 131a, the third oxide semiconductor layer 131c, the fourth oxide semiconductor layer 132a, and the sixth oxide semiconductor layer 132c is less than 5 cm⁻¹ 2 At / V∙s, the current characteristics of the thin-film transistor 100 may become too low.

[0083] Furthermore, when the mobility of the first oxide semiconductor layer 131a, the third oxide semiconductor layer 131c, the fourth oxide semiconductor layer 132a, and the sixth oxide semiconductor layer 132c exceeds 15 cm² / V∙s, the threshold voltage (Vth) of the thin-film transistor 100 may be excessively shifted toward the negative (-) direction.

[0084] According to one embodiment of the present invention, the second oxide semiconductor layer 131b and the fifth oxide semiconductor layer 132b may each be formed from a first oxide semiconductor material. For example, the first oxide semiconductor material may include at least one of the following materials: an IO-based oxide semiconductor material having an In concentration of 30% to 50% relative to the total In and O concentration on an atomic basis; an IGZO-based oxide semiconductor material having an In concentration of 30% or greater relative to the total In, Ga, and Zn concentration on an atomic basis; a FIZO-based oxide semiconductor material; a FIGZO-based oxide semiconductor material; and an IZO-based oxide semiconductor material.

[0085] For example, in IO (InO)-based oxide semiconductor materials, when the In concentration in the total In and O concentration is less than 30%, the second oxide semiconductor layer 131b and the fifth oxide semiconductor layer 132b may be insufficient to ensure high mobility, and it may be difficult to implement an In concentration of more than 50% of the total In and O concentration in IO (InO)-based oxide semiconductor materials.

[0086] According to one embodiment of the present invention, the first oxide semiconductor layer 131a, the third oxide semiconductor layer 131c, the fourth oxide semiconductor layer 132a, and the sixth oxide semiconductor layer 132c may each be formed from a second oxide semiconductor material. For example, the second oxide semiconductor material may include at least one of the following materials: an IGZO-based oxide semiconductor material (InGaZnO) having an In concentration of less than 30% atomically relative to the total concentration of In, Ga, and Zn; a GZTO-based oxide semiconductor material (GaZnSnO); and a GZO-based oxide semiconductor material (GaZnO).

[0087] According to one embodiment of the present invention, the sum of the thickness of the first oxide semiconductor layer 131a and the thickness of the second oxide semiconductor layer 131b may be 10% to 40% of the thickness of the first active layer 131. According to one embodiment of the present invention, the sum of the thickness of the fifth oxide semiconductor layer 132b and the thickness of the sixth oxide semiconductor layer 132c may be 10% to 40% of the thickness of the second active layer 132.

[0088] For example, in the case of the first active layer 131, the second oxide semiconductor layer 131b made of a high-mobility material can be disposed away from the gate electrode 150. For example, in the case of the second active layer 132, the fifth oxide semiconductor layer 132b made of a high-mobility material can be disposed close to the gate electrode 150. That is, when the thicknesses of the first active layer 131 and the second active layer 132 are the same, the fifth oxide semiconductor layer 132b is closer to the gate electrode 150 than the second oxide semiconductor layer 131b.

[0089] For example, the shortest distance between the gate electrode 150 and the fifth oxide semiconductor layer 132c can be shorter than the shortest distance between the gate electrode 150 and the second oxide semiconductor layer 131b.

[0090] For example, the shortest distance between the source electrode 161 and the fifth oxide semiconductor layer 132c may be shorter than the shortest distance between the source electrode 161 and the second oxide semiconductor layer 131b. For example, the shortest distance between the drain electrode 162 and the fifth oxide semiconductor layer 132c may be shorter than the shortest distance between the drain electrode 162 and the second oxide semiconductor layer 131b.

[0091] Generally, for grayscale performance, driving thin-film transistors with a large s-factor is advantageous. The s-factor is explained below.

[0092] The s-factor (subthreshold swing) is obtained as the inverse of the slope of the curve of the drain-source current of the thin-film transistor 100 relative to the gate voltage during the threshold voltage (Vth) cycle. For example, the s-factor can be used as an indicator of the degree of change of the drain-source current relative to the gate voltage during the threshold voltage (Vth) cycle of the thin-film transistor 100.

[0093] As the s-factor increases, the drain-source current (Id) during the threshold voltage (Vth) period... DS The rate of change relative to the gate voltage is slower.

[0094] For example, it can be done through Figure 8 The current variation graph shown is used to explain the s-factor. Figure 8 This is a threshold voltage curve of the thin-film transistor 100 according to the present invention. Specifically, Figure 8 The drain-source current (I) is shown. DS Gate voltage (V) GS ).

[0095] exist Figure 8 The curve shown represents the drain-source current (I) during the threshold voltage (Vth) period. DS ) relative to the gate voltage (V GS The reciprocal of the slope of the curve representing the drain-source current (Id) is the s-factor. A steeper slope results in a smaller s-factor, and a shallower slope results in a larger s-factor. A large s-factor indicates a higher drain-source current (Id). DS The rate of change of the gate voltage relative to the threshold voltage (Vth) is smooth over the period of the threshold voltage (Vth).

[0096] As the s-factor increases, the drain-source current (Id) during the threshold voltage (Vth) period... DS The rate of change relative to the gate voltage becomes more gradual, making it easier to adjust the gate voltage (V) GS To control the drain-source current (I) DS ) size.

[0097] In current-driven display devices (e.g., organic light-emitting display devices), the drain-source current (Id) of the driving thin-film transistor can be adjusted. DS The grayscale of a pixel is controlled by the magnitude of its drain-source current (Id). DS The value of the s-factor is determined by the gate voltage. Therefore, in current-driven organic light-emitting display devices, the larger the s-factor of the driving thin-film transistor (driving TR), the easier it is to adjust the grayscale of the pixel.

[0098] For example, the higher the position of the fifth oxide semiconductor layer 132b made of a high-mobility material in the second active layer 132, the more the high-mobility material is distributed at the interface of the second active layer 132 near the gate electrode 150. As a result, the thin-film transistor 100 has the characteristic that its threshold voltage (Vth) is offset in the negative (-) direction. Consequently, the range of the period of the threshold voltage (Vth) becomes wider, and the s-factor of the thin-film transistor 100 increases.

[0099] For example, the lower the position of the second oxide semiconductor layer 131b made of a high-mobility material in the first active layer 131, the less high-mobility material is distributed at the interface of the first active layer 131 near the gate electrode 150. As a result, the thin-film transistor 100 has the characteristic that the threshold voltage (Vth) of the thin-film transistor 100 is offset in the positive (+) direction.

[0100] According to one embodiment of the present invention, it may be difficult to achieve a situation where the sum of the thickness of the first oxide semiconductor layer 131a and the thickness of the second oxide semiconductor layer 131b is less than 10% of the thickness of the first active layer 131.

[0101] Furthermore, when the sum of the thickness of the first oxide semiconductor layer 131a and the thickness of the second oxide semiconductor layer 131b exceeds 40% of the thickness of the first active layer 131, the second oxide semiconductor layer 131b may be positioned too close to the gate electrode 150, thereby causing the threshold voltage (Vth) of the first active layer 131 to shift in the negative (-) direction.

[0102] According to one embodiment of the present invention, it may be difficult to achieve a sum of thicknesses of the fifth oxide semiconductor layer 132b and the sixth oxide semiconductor layer 132c that is less than 10% of the thickness of the second active layer 132.

[0103] Furthermore, when the sum of the thicknesses of the fifth oxide semiconductor layer 132b and the sixth oxide semiconductor layer 132c exceeds 40% of the thickness of the second active layer 132, for example, the thickness of the sixth oxide semiconductor layer 132c may become too thick. Therefore, the fifth oxide semiconductor layer 132b may become too far from the gate electrode 150, and the thin-film transistor 100 may not have the characteristic of its threshold voltage (Vth) shifting in the negative (-) direction. Additionally, for example, the excessive thickness of the fifth oxide semiconductor layer 132b may cause an excessive increase in the current characteristics of the second active layer 132, and a decrease in the s-factor of the thin-film transistor 100, which could lead to problems.

[0104] According to one embodiment of the present invention, with the second direction Y as a reference, the width (W1) of the first active layer 131 can be greater than the width (W2) of the second active layer 132. According to one embodiment of the present invention, the width of the active layer means the shortest length of the active layer with the second direction Y as a reference.

[0105] In the past, increasing the distance between the gate electrode and the channel region was used to increase the s-factor of thin-film transistors (TFTs). However, while this increased the s-factor, it also resulted in a decrease in the on-state current of the TFT.

[0106] When the width (W1) of the first active layer 131 is greater than the width (W2) of the second active layer 132, the current flowing into the first active layer 131 increases. As a result, the thin-film transistor 100 can have a large current value in the on state.

[0107] According to one embodiment of the present invention, the thickness (L1) of the second oxide semiconductor layer 131b can be greater than the thickness (L2) of the fifth oxide semiconductor layer 132b (see [reference]). Figure 5 and Figure 6 ).

[0108] When the thickness (L1) of the second oxide semiconductor layer 131b is greater than the thickness (L2) of the fifth oxide semiconductor layer 132b, the current flowing into the first active layer 131 increases. As a result, the thin-film transistor 200 can have a large current value in the on state.

[0109] In other words, since the thin-film transistor according to the present invention has a first active layer 131 and a second active layer 132, it can have excellent (conduction) current characteristics and a large s factor.

[0110] For example, the thickness (L1) of the second oxide semiconductor layer 131b can be 3 nm or more and less than 5 nm, and the thickness (L2) of the fifth oxide semiconductor layer 132b can be 2 nm or more and less than 3 nm.

[0111] For example, when the thickness (L1) of the second oxide semiconductor layer 131b is less than 3 nm, the thin-film transistor 200 may not have a large current value in the on state. When the thickness (L1) of the second oxide semiconductor layer 131b is 5 nm or greater, the threshold voltage (Vth) in the first active layer 131 may be shifted in the negative (-) direction.

[0112] For example, when the thickness (L2) of the fifth oxide semiconductor layer 132b is less than 2 nm, the thin-film transistor 200 may not have the characteristic of the threshold voltage (Vth) shifting in the negative (-) direction. When the thickness (L2) of the fifth oxide semiconductor layer 132b is 3 nm or greater, the current characteristics in the second active layer 132 may increase excessively, and the s-factor of the thin-film transistor 200 may decrease, which may cause problems.

[0113] According to one embodiment of the present invention, a gate insulating film 140 is disposed on the active layer 130. Specifically, the gate insulating film 140 is disposed between the active layer 130 and the gate electrode 150.

[0114] According to one embodiment of the present invention, the gate insulating film 140 may cover the entire upper surface of the active layer 130. Figure 2 , Figure 3 and Figure 4 The diagram shows a gate insulating film 140 covering the entire upper surface of the active layer 130. However, the invention is not limited thereto, and the gate insulating film 140 may expose the first connection portion 131s and the second connection portion 131d of the active layer 130 (see [reference]). Figure 7 ). Figure 7 Corresponding to Figure 2 The accompanying drawings are shown, and although omitted in the drawings, the gate insulating film 140 may expose the third connection portion 132s and the fourth connection portion 132d of the active layer 130.

[0115] The gate insulating film 140 may include at least one of silicon oxide, silicon nitride, and metal oxide. The gate insulating film 140 may have a single-film structure or a multilayer structure. The gate insulating film 140 protects the active layer 130.

[0116] According to one embodiment of the present invention, the gate electrode 150 may be disposed on the gate insulating film 140.

[0117] According to one embodiment of the present invention, the gate electrode 150 may overlap with the active layer 130. For example, see reference... Figure 1 The gate electrode 150 may overlap with the channel portion 130n of the active layer 130. For example, the gate electrode 150 may overlap with the first channel portion 131n of the first active layer 131 and the second channel portion 132n of the second active layer 132.

[0118] The gate electrode 150 may include at least one of the following materials: aluminum-based metals such as aluminum (Al) or aluminum alloys, silver-based metals such as silver (Ag) or silver alloys, copper-based metals such as copper (Cu) or copper alloys, molybdenum-based metals such as molybdenum (Mo) or molybdenum alloys, chromium (Cr), tantalum (Ta), neodymium (Nd), and titanium (Ti). The gate electrode 150 may also have a multilayer film structure comprising at least two conductive films with different physical properties.

[0119] An interlayer insulating film 180 is disposed on the gate electrode 150. The interlayer insulating film 180 is an insulating layer made of insulating material. Specifically, the interlayer insulating film 180 may be made of organic material, inorganic material, or a laminate of organic material layer and inorganic material layer.

[0120] Source electrode 161 and drain electrode 162 are disposed on interlayer insulating film 180. Source electrode 161 and drain electrode 162 are spaced apart from each other and connected to source connection portion 130s and drain connection portion 130d, respectively. Specifically, source electrode 161 is connected to first connection portion 131s and third connection portion 132s through first-1 contact holes (CH11) and first-2 contact holes (CH12) formed in interlayer insulating film 180. Drain electrode 162 is connected to second connection portion 131d and fourth connection portion 132d through second-1 contact holes (CH21) and second-2 contact holes (CH22) formed in interlayer insulating film 180.

[0121] The source electrode 161 and the drain electrode 162 may each comprise at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and their alloys. The source electrode 161 and the drain electrode 162 may each be formed as a single layer of metal or metal alloy, or may be formed as two or more layers.

[0122] Figure 8 This is a threshold voltage curve of a thin-film transistor 100 according to one embodiment of the present invention. The threshold voltage curve of the thin-film transistor is represented by the drain-source current (Id). DS ) relative to the gate voltage (V GS (The curve graph).

[0123] Figure 8 The curve (3) in the figure is related to Figure 1 The threshold voltage curves of the thin film transistor 100 having the same structure are shown. Curve (1) is the threshold voltage curve of the thin film transistor having only the first active layer 131. Curve (2) is the threshold voltage curve of the thin film transistor having only the second active layer 132.

[0124] Reference Figure 8 It can be confirmed that the thin film transistor with the first active layer 131 has excellent current characteristics, but has the characteristic that the threshold voltage is shifted in the positive (+) direction, and the current flowing through the thin film transistor increases rapidly within the threshold voltage range, thus having a small s factor.

[0125] On the other hand, it can be confirmed that the thin film transistor with the second active layer 132 has low on-current characteristics, but has a threshold voltage that is offset in the negative (-) direction, and the current flowing through the thin film transistor increases rapidly during the period of the threshold voltage, which makes it have a small s factor.

[0126] A thin-film transistor (graph (3)) according to one embodiment of the present invention can have excellent (conduction) current characteristics by having a first active layer 131 and can have a large s factor by having a second active layer 132.

[0127] Figures 9A to 9G This is a plan view illustrating the manufacturing process of a thin-film transistor 100 according to an embodiment of the present invention. Figures 10A to 10G This is a cross-sectional view of the manufacturing process of a thin-film transistor 100 according to an embodiment of the present invention. Figures 11A to 11G This is a cross-sectional view of the manufacturing process of a thin-film transistor 100 according to an embodiment of the present invention.

[0128] Figures 10A to 10A The cross-sectional view shown can correspond to Figure 2 The cross-sectional view shown. Figures 11A to 11G The cross-sectional view shown can correspond to Figure 3 The cross-sectional view shown.

[0129] The description of the configuration already explained above has been omitted.

[0130] Reference Figure 9A , Figure 10A and Figure 11A A base substrate 110 having a first region Area 1 and a second region Area 2 can be fabricated. A first active layer 131 can be disposed in the first region Area 1 of the base substrate 110, and a second active layer 132 can be disposed in the second region Area 2.

[0131] Reference Figure 9A , Figure 10A and Figure 11A A buffer layer 120 can be formed on the base substrate 110. The buffer layer 120 can be formed across the first region Area 1 and the second region Area 2.

[0132] refer to Figure 9A , Figure 10A and Figure 11AAfter forming a second oxide semiconductor material layer 132m in the second region Area 2 of the base substrate 110, the second oxide semiconductor material layer 132m can be etched. The step of forming the second oxide semiconductor material layer 132m may include the steps of sequentially forming a second-first oxide semiconductor material layer 132m1, a second-second oxide semiconductor material layer 132m2, and a second-third oxide semiconductor material layer 132m3.

[0133] refer to Figure 9B , Figure 10B and Figure 11B The first oxide semiconductor material layer 131m can be formed on a first region Area1 and a second region Area2. The steps of forming the first oxide semiconductor material layer 131m may include the steps of sequentially forming a first-1 oxide semiconductor material layer 131m1, a first-2 oxide semiconductor material layer 131m2, and a first-3 oxide semiconductor material layer 131m3.

[0134] The first-second oxide semiconductor material layer 131m2 and the second-second oxide semiconductor material layer 132m2 may be formed of a first oxide semiconductor material. For example, the first oxide semiconductor material may include at least one of the following materials: an IO-based oxide semiconductor material having an In concentration of 30% to 50% relative to the total In and O concentration on an atomic basis; an IGZO-based oxide semiconductor material having an In concentration of 30% or greater relative to the total In, Ga and Zn concentration on an atomic basis; an FIZO-based oxide semiconductor material; a FIGZO-based oxide semiconductor material; and an IZO-based oxide semiconductor material.

[0135] The first-1 oxide semiconductor material layer 131m1, the first-3 oxide semiconductor material layer 131m3, the second-1 oxide semiconductor material layer 132m1, and the second-3 oxide semiconductor material layer 132m3 can be formed of a second oxide semiconductor material. For example, the second oxide semiconductor material may include at least one of the following materials: an IGZO-based oxide semiconductor material (InGaZnO) having an In concentration of less than 30% relative to the total concentration of In, Ga, and Zn on an atomic basis; a GZTO-based oxide semiconductor material (GaZnSnO); and a GZO-based oxide semiconductor material (GaZnO).

[0136] refer to Figure 11BIn the second region Area 2, a first oxide semiconductor material layer 131m may be disposed on a second oxide semiconductor material layer 132m. Specifically, the first oxide semiconductor material layer 131m may cover the side surface of the second oxide semiconductor material layer 132m.

[0137] Reference Figure 9C , Figure 10C and Figure 11C A photoresist pattern 136 can be formed on the first area 1. For example, the photoresist pattern 136 can be disposed on the first oxide semiconductor material layer 131m. For example, the photoresist pattern 136 can be disposed on a portion of the upper surface of the first oxide semiconductor material layer 131m. For example, the photoresist pattern 136 is not disposed on the second area 2. For example, the photoresist pattern 136 does not overlap with the second oxide semiconductor material layer 132m.

[0138] refer to Figure 9D , Figure 10D and Figure 11D The first oxide semiconductor material layer 131m and the second oxide semiconductor material layer 132m can be etched simultaneously using the photoresist pattern 136 as a mask to form the first active layer 131 and the second active layer 132.

[0139] For example, refer to Figure 10D A photoresist pattern 136 can be used as a mask to etch a first oxide semiconductor material layer 131m disposed in the first region Area 1 to form a first active layer 131. (See reference...) Figure 11D The first oxide semiconductor material layer 131m and the second oxide semiconductor material layer 132m disposed in the first region Area1 and the second region Area2 can be etched simultaneously to form the second active layer 132.

[0140] refer to Figure 10D The first active layer 131 may include a first oxide semiconductor layer 131a, a second oxide semiconductor layer 131b located on the first oxide semiconductor layer 131a, and a third oxide semiconductor layer 131c located on the second oxide semiconductor layer 131b. (See reference...) Figure 11D The second active layer 132 may include a fourth oxide semiconductor layer 132a, a fifth oxide semiconductor layer 132b located on the fourth oxide semiconductor layer 132a, and a sixth oxide semiconductor layer 132c located on the fifth oxide semiconductor layer 132b.

[0141] Reference Figure 9E , Figure 10E and Figure 11E It can remove the photoresist pattern 136 set in the first area Area1.

[0142] Reference Figure 9F , Figure 10F and Figure 11F A gate insulating film 140 and a gate electrode 150 can be sequentially formed on the first active layer 131 and the second active layer 132. Furthermore, the gate electrode 150 can be used as a mask to dope dopant ions into the first active layer 131 and the second active layer 132. As a result, the first active layer 131 may include a first channel portion 131n, a first connection portion 131s contacting one side of the first channel portion 131n, and a second connection portion 131d contacting the other side of the first channel portion 131n; and the second active layer 132 may include a second channel portion 132n, a third connection portion 132s contacting one side of the second channel portion 132n, and a fourth connection portion 132d contacting the other side of the second channel portion 132n.

[0143] Since the first channel portion 131n and the second channel portion 132n are covered by the gate electrode 150, no conductivity occurs in the first channel portion 131n and the second channel portion 132n.

[0144] Since the first connection portion 131s, the second connection portion 131d, the third connection portion 132s, and the fourth connection portion 132d are not covered by the gate electrode 150, conductivity occurs in the first connection portion 131s, the second connection portion 131d, the third connection portion 132s, and the fourth connection portion 132d.

[0145] refer to Figure 9G , 10G In the 11G configuration, the interlayer insulating film 180, the source electrode 161, and the drain electrode 162 can be formed on the gate electrode 150. Descriptions of the interlayer insulating film 180, the source electrode 161, and the drain electrode 162 are omitted because they overlap with the foregoing.

[0146] Figure 12 A schematic diagram illustrating a display device 1000 according to another embodiment of the present invention.

[0147] like Figure 12 As shown, a display device 1000 according to another embodiment of the present invention may include a display panel 310, a gate driver 320, a data driver 330, and a controller 340.

[0148] The display panel 310 includes gate lines GL and data lines DL, and a pixel P is disposed in the intersection area of ​​the gate lines GL and data lines DL. An image is displayed by driving the pixel P. The gate lines GL, data lines DL, and pixel P can be disposed on the base substrate 110.

[0149] The controller 340 controls the gate driver 320 and the data driver 330.

[0150] The controller 340 outputs a gate control signal GCS for controlling the gate driver 320 and a data control signal DCS for controlling the data driver 330 using signals provided from an external system (not shown). Furthermore, the controller 340 samples input image data from the external system, realigns the sampled data, and provides the realigned digital image data (RGB) to the data driver 330.

[0151] The gate control signal GCS includes the gate start pulse GSP, the gate shift clock GSC, the gate output enable signal GOE, the start signal Vst, and the gate clock GCLK. Furthermore, control signals for controlling the shift register can be included in the gate control signal GCS.

[0152] The data control signal DCS includes the source start pulse SSP, the source shift clock signal SSC, the source output enable signal SOE, and the polarity control signal POL.

[0153] The data driver 330 supplies data voltage to the data line DL of the display panel 310. Specifically, the data driver 330 converts the image data RGB input from the controller 340 into analog data voltage and supplies the data voltage to the data line DL.

[0154] According to one embodiment of this disclosure, the gate driver 320 may be packaged on the display panel 310. In this way, the structure in which the gate driver 320 is directly packaged on the display panel 310 is referred to as a Gate-in-Panel (GIP) structure. Specifically, in the GIP structure, the gate driver 320 may be disposed on the base substrate 110.

[0155] A display device 1000 according to one embodiment of the present invention may include the thin-film transistors 100 and 200 described above.

[0156] Gate driver 320 may include shift register 350.

[0157] The shift register 350 sequentially supplies one frame of gate pulses to the gate line GL using a start signal and a gate clock sent from the controller 340. In this case, one frame means a time period during which an image is output through the display panel 310. The gate pulses have an on-state voltage capable of turning on the switching devices (thin-film transistors) disposed in the pixel P.

[0158] Furthermore, shift register 350 will be able to provide a gate turn-off signal for the switching device to the gate line GL for an additional period of up to one frame during which no gate pulse is provided. In the following text, the gate pulse and the gate turn-off signal will be collectively referred to as the scan signal SS or Scan.

[0159] Figure 13 It is shown Figure 12 The circuit diagram of any pixel P.

[0160] Figure 13 The circuit diagram is an equivalent circuit diagram of the pixel P of the display device 1000, which includes an organic light-emitting diode (OLED) as a display element 710.

[0161] Reference Figure 13 Pixel P includes a display element 710 and a pixel driving circuit PDC for driving the display element 710. More specifically, a display device 1000 according to one embodiment of this disclosure may include a pixel driving circuit PDC on a base substrate 110.

[0162] Figure 13 The pixel driving circuit (PDC) includes a first thin-film transistor (TR1) as a switching transistor and a second thin-film transistor (TR2) as a driving transistor. The second thin-film transistor (TR2) as a driving transistor may include the thin-film transistors 100 and 200 according to the present invention.

[0163] The first thin-film transistor TR1 is connected to the gate line GL and the data line DL, and is turned on or off by the scan signal SS supplied through the gate line GL.

[0164] The data line DL provides the data voltage Vdata to the pixel driving circuit PDC, and the first thin-film transistor TR1 controls the application of the data voltage Vdata.

[0165] The driving power line PL provides the driving voltage Vdd to the display element 710, and the first thin-film transistor TR1 controls the driving voltage Vdd. The driving voltage Vdd is the pixel driving voltage used to drive the organic light-emitting diode (OLED) that serves as the display element 710.

[0166] When the first thin-film transistor TR1 is turned on by the scan signal SS applied from the gate driver 320 via the gate line GL, the data voltage Vdata supplied via the data line DL is supplied to the gate electrode of the second thin-film transistor TR2 connected to the display element 710. The data voltage Vdata charges the storage capacitor C1 formed between the gate electrode and the source electrode of the second thin-film transistor TR2.

[0167] The amount of current supplied to the organic light-emitting diode (OLED) 710 via the second thin-film transistor TR2 is controlled according to the data voltage Vdata, thereby controlling the grayscale of the light output from the display element 710.

[0168] The pixel driving circuit (PDC) according to another embodiment of the present invention can be formed in various structures different from those described above. The pixel driving circuit (PDC) may include, for example, three or more thin-film transistors.

[0169] Based on this disclosure, the following beneficial effects can be obtained.

[0170] By forming two active layers with different widths and different positions using a parallel structure, a thin-film transistor according to one embodiment of the present invention has a large s-factor during the threshold voltage period and a large current value in the on state.

[0171] In addition to the effects described above, other features and advantages of the present invention will be described below, or may be clearly understood by those skilled in the art from these descriptions and explanations.

[0172] It will be apparent to those skilled in the art that the present disclosure is not limited to the above-described embodiments and drawings, and that various substitutions, modifications, and variations may be made within the present disclosure without departing from its spirit or scope. Therefore, the scope of the present disclosure is defined by the appended claims, and all variations or modifications derived from the meaning, scope, and equivalent concepts of the claims are intended to fall within the scope of the present disclosure.

Claims

1. A thin-film transistor, comprising: Active layer; as well as Gate electrode that overlaps with at least a portion of the active layer. The active layer includes a first active layer and a second active layer spaced apart from each other. The first active layer includes: First oxide semiconductor layer; The second oxide semiconductor layer located on the first oxide semiconductor layer; and A third oxide semiconductor layer located on the second oxide semiconductor layer, and The second active layer includes: Fourth oxide semiconductor layer; The fifth oxide semiconductor layer located on the fourth oxide semiconductor layer; and The sixth oxide semiconductor layer is located on the fifth oxide semiconductor layer. The sum of the thickness of the first oxide semiconductor layer and the thickness of the second oxide semiconductor layer is 10% to 40% of the thickness of the first active layer, and The sum of the thickness of the fifth oxide semiconductor layer and the thickness of the sixth oxide semiconductor layer is 10% to 40% of the thickness of the second active layer.

2. The thin-film transistor of claim 1, wherein the second oxide semiconductor layer has a higher mobility than the first oxide semiconductor layer and the third oxide semiconductor layer, and the fifth oxide semiconductor layer has a higher mobility than the fourth oxide semiconductor layer and the sixth oxide semiconductor layer.

3. The thin-film transistor according to claim 2, wherein the mobility of the second oxide semiconductor layer and the fifth oxide semiconductor layer is 20 cm⁻¹. 2 / V∙s to 100cm 2 / V∙s.

4. The thin-film transistor according to claim 2, wherein the mobility of the first oxide semiconductor layer, the third oxide semiconductor layer, the fourth oxide semiconductor layer and the sixth oxide semiconductor layer is 5 cm⁻¹. 2 / V∙s up to 15cm 2 / V∙s.

5. The thin-film transistor of claim 1, wherein the second oxide semiconductor layer and the fifth oxide semiconductor layer are each made of a first oxide semiconductor material, and The first oxide semiconductor material includes at least one of the following: an IO-based oxide semiconductor material (InO) having an In concentration of 30% to 50% relative to the total In and O concentration on an atomic basis; or an IGZO-based oxide semiconductor material (InGaZnO) having an In concentration of 30% or greater relative to the total In, Ga and Zn concentration on an atomic basis. Oxide semiconductor materials based on FIZO (FInZnO); Oxide semiconductor materials based on FIGZO (FeInGaZnO); And oxide semiconductor materials based on IZO (InZnO).

6. The thin-film transistor of claim 1, wherein the first oxide semiconductor layer, the third oxide semiconductor layer, the fourth oxide semiconductor layer, and the sixth oxide semiconductor layer are each formed of a second oxide semiconductor material, and The second oxide semiconductor material includes at least one of the following: an IGZO-based oxide semiconductor material (InGaZnO) having an In concentration of less than 30% relative to the total concentration of In, Ga and Zn on an atomic basis, an GZTO-based oxide semiconductor material (GaZnSnO), and a GZO-based oxide semiconductor material (GaZnO).

7. The thin-film transistor of claim 1, wherein the first active layer comprises: The first channel portion overlapping the gate electrode; A first connecting portion that contacts one side of the first channel portion; as well as The second connecting portion that contacts the other side of the first channel portion, and When the direction of the straight line connecting the first connecting portion and the second connecting portion with the shortest distance is the first direction and the direction perpendicular to the first direction is the second direction, the width of the first active layer is greater than the width of the second active layer, with the second direction as the reference.

8. The thin-film transistor of claim 1, wherein the thickness of the second oxide semiconductor layer is greater than the thickness of the fifth oxide semiconductor layer.

9. The thin-film transistor according to claim 8, wherein, The thickness of the second oxide semiconductor layer is 3 nm or greater and less than 5 nm, and The thickness of the fifth oxide semiconductor layer is 2 nm or more and less than 3 nm.

10. The thin-film transistor of claim 7, wherein the first active layer and the second active layer are respectively configured to extend along the first direction and spaced apart from each other with respect to the second direction.

11. The thin-film transistor of claim 1, wherein the shortest distance between the gate electrode and the fifth oxide semiconductor layer is shorter than the shortest distance between the gate electrode and the second oxide semiconductor layer.

12. The thin-film transistor of claim 1, further comprising a source electrode and a drain electrode, the source electrode and the drain electrode being spaced apart from each other and each connected to the active layer, and The shortest distance between the source electrode and the fifth oxide semiconductor layer is shorter than the shortest distance between the source electrode and the second oxide semiconductor layer.

13. The thin-film transistor of claim 12, wherein the shortest distance between the drain electrode and the fifth oxide semiconductor layer is shorter than the shortest distance between the drain electrode and the second oxide semiconductor layer.

14. A method for manufacturing a thin-film transistor, comprising the following steps: Prepare a base substrate having a first region and a second region; A second oxide semiconductor material layer is formed on the second region, and then the second oxide semiconductor material layer is etched. A first oxide semiconductor material layer is formed on the first region and the second region; A photoresist pattern is formed on the first region; The photoresist pattern is used as a mask to simultaneously etch the first oxide semiconductor material layer and the second oxide semiconductor material layer to form the first active layer and the second active layer. as well as Gate electrodes are formed on the first active layer and the second active layer.

15. The method for manufacturing a thin-film transistor according to claim 14, wherein the first oxide semiconductor material layer is disposed on the second oxide semiconductor material layer and covers the side surface of the second oxide semiconductor material layer.

16. The method for manufacturing a thin-film transistor according to claim 14, wherein the photoresist pattern is not disposed on the second region.

17. The method for manufacturing a thin-film transistor according to claim 14, wherein the first active layer comprises: First oxide semiconductor layer; The second oxide semiconductor layer is located on the first oxide semiconductor layer; and A third oxide semiconductor layer located on the second oxide semiconductor layer, and The second active layer includes: Fourth oxide semiconductor layer; The fifth oxide semiconductor layer located on the fourth oxide semiconductor layer; and The sixth oxide semiconductor layer located on the fifth oxide semiconductor layer, and The sum of the thicknesses of the first oxide semiconductor layer and the second oxide semiconductor layer is 10% to 40% of the thickness of the first active layer, and The sum of the thickness of the fifth oxide semiconductor layer and the thickness of the sixth oxide semiconductor layer is 10% to 40% of the thickness of the second active layer.

18. The method for manufacturing a thin-film transistor according to claim 17, wherein the shortest distance between the gate electrode and the fifth oxide semiconductor layer is shorter than the shortest distance between the gate electrode and the second oxide semiconductor layer.

19. The method for manufacturing a thin-film transistor as claimed in claim 17, further comprising the step of forming a source electrode and a drain electrode, the source electrode and the drain electrode being spaced apart from each other and respectively connected to an active layer including the first active layer and the second active layer. The shortest distance between the source electrode and the fifth oxide semiconductor layer is shorter than the shortest distance between the source electrode and the second oxide semiconductor layer.

20. The method for manufacturing a thin-film transistor according to claim 19, wherein the shortest distance between the drain electrode and the fifth oxide semiconductor layer is shorter than the shortest distance between the drain electrode and the second oxide semiconductor layer.

21. A display device comprising a thin-film transistor according to any one of claims 1 to 13.

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