Photosensitive diode structure and preparation method thereof
By using centrifugal etching with diluted hydrofluoric acid solution and low-pressure chemical vapor deposition, the oxide layer thickness of the photodiode is precisely controlled, solving the problems of reduced breakdown voltage and poor passivation effect caused by thin oxide layers, thus improving short-wavelength response performance and device reliability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- ADVANCED SEMICON MFG CO LTD
- Filing Date
- 2026-02-13
- Publication Date
- 2026-05-19
AI Technical Summary
In the manufacturing process of existing photodiodes, the reduction in oxide layer thickness leads to a decrease in breakdown voltage, which makes process control difficult. Thin oxide layers affect passivation and dark current, making it difficult to balance short-wavelength response performance and device reliability.
The second oxide layer is precisely thinned to 95-105 Å using a diluted hydrofluoric acid solution and a centrifugal etching process. Combined with a passivation layer grown by low-pressure chemical vapor deposition, an ultra-thin and uniform oxide layer is formed to ensure the quality of interface contact.
This study improved the short-wavelength response performance and quantum efficiency of photodiodes while maintaining reliable breakdown voltage and stable electrical performance, thus optimizing the balance between optical performance and electrical reliability.
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Figure CN122069818A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor device technology, and more specifically, to a photodiode structure and its fabrication method. Background Technology
[0002] As a core photoelectric conversion device, the photodiode works based on the internal photoelectric effect proposed by Einstein. When the photon energy is greater than or equal to the bandgap of the semiconductor material, the photon is absorbed and excited to generate electron-hole pairs, thereby changing the electrical properties of the material, such as resistivity, or generating an induced electromotive force. Structurally, the photodiode is essentially a PN junction device. The P-type and N-type semiconductors contact to form a space charge region. Under the action of the built-in electric field, photogenerated electrons are swept to the N-region, and holes are swept to the P-region. If it forms a loop with an external circuit, a photocurrent related to the intensity of the incident light can be generated.
[0003] Material selection is fundamental to determining the spectral response and performance of photodiodes. Silicon, due to its high technological maturity and stability, has become the most widely used material for photodiodes, with a response wavelength covering approximately 190nm to 1100nm, encompassing the visible to near-infrared region. To meet diverse application requirements, the industry has developed various photodiode structures based on the traditional PN junction, such as PN-type, PIN-type, and Schottky barrier types. Among them, the PIN structure, by inserting an intrinsic semiconductor layer between the P-region and N-region, effectively reduces junction capacitance, improves response speed, increases the light absorption ratio in the depletion region, thereby improving quantum efficiency and allowing the device to operate at higher reverse bias voltages.
[0004] Especially in terms of short-wavelength spectral response, the responsivity and quantum efficiency of the device are strongly dependent on the thickness of the surface oxide layer. A thinner oxide layer helps reduce the absorption of short-wavelength photons by silicon dioxide, allowing more photons to reach the depletion region, thereby enhancing the sensitivity in the blue and ultraviolet bands. At the same time, a thin oxide layer can optimize the surface electric field distribution, suppress surface recombination, improve the collection efficiency of photogenerated carriers, improve the response speed, and reduce tailing phenomena. In addition, the thin oxide layer structure also helps to improve the overall responsivity, enabling the device to exhibit better photoelectric conversion performance in the short-wavelength region.
[0005] However, in actual manufacturing, thinning the oxide layer still faces a series of process and reliability challenges. First, reducing the oxide layer thickness leads to a decrease in its breakdown voltage. Silicon dioxide has limited dielectric breakdown strength, and an excessively thin oxide layer can easily reduce the device's breakdown voltage. Second, growing a uniform, defect-free thin oxide layer requires extremely high process control; uneven thickness directly affects the consistency of device performance. Third, the oxide layer itself has a surface passivation effect, reducing interface state density; excessive thinness may weaken the passivation effect and increase surface recombination. Finally, a thin oxide layer weakens its ability to block impurity ions and contaminants, potentially leading to increased dark current, deteriorated noise characteristics, and affecting the device's signal-to-noise ratio and long-term stability.
[0006] Therefore, how to ensure that the oxide layer is thin enough to improve short-wavelength response performance while taking into account breakdown voltage, passivation quality, dark current and process feasibility has become a key problem that urgently needs to be solved in the current development of photodiode technology.
[0007] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention
[0008] To address the problems in the prior art, the present invention aims to provide a photodiode structure and fabrication method. This fabrication method enables precise and controllable fabrication of an ultrathin oxide layer for the photodiode, thereby improving the short-wavelength response performance of the obtained photodiode.
[0009] Specifically, the first aspect of the present invention provides a method for fabricating a photodiode, the method comprising the following steps: A silicon substrate is provided, a first oxide layer is grown on a surface of the silicon substrate, and the first oxide layer is photolithographically etched and etched to form a first opening to define the active region of the photodiode. A second photolithography and etching process is performed to form a second opening. P-type ion implantation is then performed at the second opening, followed by a first thermal annealing process to activate P-type impurities and form a P+ region. A third photolithography and etching process is performed to form a third opening. N-type ion implantation is performed at the third opening, followed by a second thermal annealing process to activate N-type impurities and form N+ regions. A second oxide layer is then formed on the surface of the silicon substrate. The second oxide layer is thinned by using a pre-prepared diluted hydrofluoric acid solution and a centrifugal etching process until the second oxide layer reaches the pre-prepared thickness. A first passivation layer is deposited on the surface of the silicon substrate; A fourth photolithography and etching process is performed to form a fourth opening. The first passivation layer and the second oxide layer in the area of the fourth opening are removed to expose the surface of the underlying silicon substrate and form a contact hole. A metal layer is deposited on the first passivation layer and inside the contact hole, and a fifth photolithography is performed to etch the metal layer to form a metal interconnect pattern. A second passivation layer is deposited on the metal interconnect pattern and the exposed first passivation layer. A sixth photolithography is performed and the second passivation layer is etched to form a sixth opening. The projection of the sixth opening at least partially overlaps with the metal interconnect pattern to expose the underlying metal interconnect layer. The sixth opening is filled with conductive material to form a contact electrode that is electrically connected to the metal interconnect pattern.
[0010] According to a first aspect of the present invention, the mass percentage of hydrofluoric acid in the pre-prepared diluted hydrofluoric acid solution is 2.5% to 6.0%. In the centrifugal etching process, the rotation speed of the silicon substrate is 155~165 rpm.
[0011] According to a first aspect of the invention, the initial thickness of the second oxide layer is 400 to 500 Å.
[0012] According to a first aspect of the invention, in the step of using a centrifugal etching process to etch the second oxide layer until the second oxide layer is thinned to a predetermined thickness, the predetermined thickness is 95~105 Å.
[0013] According to a first aspect of the present invention, the first passivation layer is a silicon nitride layer.
[0014] According to a first aspect of the invention, the first passivation layer is grown using a low-pressure chemical vapor deposition process; and / or
[0015] The thickness of the first passivation layer is 300~500 Å.
[0016] According to a first aspect of the invention, the second passivation layer comprises a phosphorus silicate glass layer and an undoped silicon glass layer stacked sequentially.
[0017] According to a first aspect of the invention, the thickness of the phosphosilicate glass layer is 1800~2200 Å, and the thickness of the undoped silicon glass layer is 2700~3300 Å.
[0018] According to a first aspect of the invention, the thickness of the silicon substrate is 300~650 μm; and / or
[0019] The thickness of the first oxide layer is 7000~8000 Å; and / or
[0020] The impurity implanted by the P-type ion implantation is boron ion, and the impurity implanted by the N-type ion implantation is phosphorus ion or arsenic ion.
[0021] A second aspect of the present invention provides a photodiode structure, wherein the photodiode structure is prepared by the photodiode preparation method described in the first aspect, and the photodiode structure comprises: silicon substrate; A first oxide layer is located on the upper surface of the silicon substrate, and the first oxide layer has a first opening, a second opening and a third opening; The active region located below the first opening; The P+ region located below the second opening; The N+ region located below the third opening; A second oxide layer covering the surface of the silicon substrate and the first oxide layer, the thickness of the second oxide layer being 95–105 Å; A first passivation layer is applied over the second oxide layer, the first passivation layer having a fourth opening, and the second oxide layer below the fourth opening is also removed to form a contact hole, the contact hole exposing the surface of the silicon substrate; Metal interconnect pattern located within the contact hole and on the first passivation layer; A second passivation layer covers the metal interconnect pattern and the exposed first passivation layer, the second passivation layer having a sixth opening, the projection of the sixth opening at least partially overlapping the metal interconnect pattern; The contact electrode is located within the sixth opening and is electrically connected to the metal interconnect pattern.
[0022] The photodiode fabrication method of the present invention can precisely control the oxide layer thickness, ensure good film quality, facilitate the interface contact between the subsequent passivation layer and the oxide layer, and significantly improve the short-wavelength spectral responsivity and quantum efficiency of the fabricated photodiode, thereby achieving an optimized balance between optical performance and electrical reliability within an acceptable breakdown voltage range. Attached Figure Description
[0023] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. Other features, objects, and advantages of the invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings. It is obvious that the drawings described below are merely some embodiments of the invention, and those skilled in the art can obtain other drawings based on these drawings without inventive effort. Furthermore, the drawings are merely illustrative diagrams of this disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities.
[0024] Figure 1 This is a flowchart of a method for fabricating a photodiode according to an embodiment of the present invention; Figures 2 to 8 These are schematic diagrams of the silicon substrate structure after each step of the fabrication method of a photodiode according to an embodiment of the present invention. Figure 9 This is a top view of a photodiode according to an embodiment of the present invention. Detailed Implementation
[0025] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed herein. The present invention can also be implemented or applied through other different specific embodiments, and various details in the present invention can be modified or changed according to different viewpoints and application systems without departing from the spirit of the present invention. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of the present invention can be combined with each other.
[0026] The present invention will now be described in detail with reference to the accompanying drawings, so that those skilled in the art can readily implement it. The present invention can be embodied in many different forms and is not limited to the embodiments described herein.
[0027] In the representation of this invention, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics represented in connection with that embodiment or example, which are included in at least one embodiment or example of the invention. Furthermore, the specific features, structures, materials, or characteristics represented may be combined in any suitable manner in one or more embodiments or examples. Moreover, those skilled in the art can combine and integrate different embodiments or examples represented in this invention, as well as features of different embodiments or examples, without contradiction.
[0028] To clearly illustrate the present invention, components unrelated to the description are omitted, and the same or similar constituent elements throughout the specification are given the same reference numerals.
[0029] Throughout this specification, when it is said that a device is "connected" to another device, this includes not only "direct connection" but also "indirect connection" by placing other components in between. Furthermore, when it is said that a device "comprises" a certain constituent element, unless otherwise stated otherwise, this does not exclude other constituent elements, but rather implies that other constituent elements may be included.
[0030] When we say that a device is "above" another device, this can mean that it is directly above the other device, or it can mean that other devices are present in between. Conversely, when we say that a device is "directly" "above" another device, there are no other devices present in between.
[0031] Although the terms first, second, etc., are used in some instances herein to refer to various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, first interface and second interface, etc., are used. Furthermore, as used herein, the singular forms “a,” “an,” and “the” are intended to also include the plural forms unless the context indicates otherwise. It should be further understood that the terms “comprising,” “including,” indicate the presence of features, steps, operations, elements, components, items, kinds, and / or groups, but do not exclude the presence, occurrence, or addition of one or more other features, steps, operations, elements, components, items, kinds, and / or groups. The terms “or” and “and / or” as used herein are interpreted as inclusive, or mean any one or any combination thereof. Thus, “A, B, or C” or “A, B, and / or C” means “any one of: A; B; C; A and B; A and C; B and C; A, B, and C.” Exceptions to this definition will only occur if the combination of elements, functions, steps, or operations is inherently mutually exclusive in some way.
[0032] The technical terms used herein are for reference only to specific embodiments and are not intended to limit the invention. The singular form used herein includes the plural form unless the statement explicitly indicates otherwise. The word "comprising" as used in this specification means to specify a particular characteristic, region, integer, step, operation, element, and / or component, and does not exclude the presence or addition of other characteristics, regions, integers, steps, operations, elements, and / or components.
[0033] Unless otherwise defined in this application, all terms, including technical and scientific terms as used herein, shall have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. Terms defined in commonly used dictionaries shall be further interpreted as having a meaning consistent with relevant technical literature and the content of this present instruction, and shall not be over-interpreted as having an ideal or overly formulaic meaning unless otherwise defined.
[0034] The photodiode structure and fabrication method of the present invention are further described below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments are not intended to limit the scope of protection of the present invention.
[0035] This invention provides a method for fabricating a photodiode. Figure 1 This is a flowchart illustrating a method for fabricating a photodiode according to an embodiment of the present invention. Specifically, the fabrication method includes the following steps: Step S100: A silicon substrate 1 is provided, a first oxide layer 2 is grown on a surface of the silicon substrate 1, and the first oxide layer 2 is subjected to a first photolithography and etching to form a first opening. The area defined by the first opening is the active region (OD) of the photodiode. See [link to relevant documentation]. Figure 2 The thickness of the silicon substrate 1 can be 300~650μm, and its conductivity type can be N-type or P-type. In step S100, the unetched portion of the first oxide layer 2 is a field oxide layer (FOX). This layer serves as a high-resistance insulating medium to achieve electrical isolation between devices, preventing leakage current and signal crosstalk; it also isolates different functional regions (such as active regions, P+ regions, and N+ regions) within a single device. Accordingly, the material of the first oxide layer 2 can be silicon dioxide. Preferably, the thickness of the first oxide layer 2 is 7000~8000Å, such as 7600 Å.
[0036] Step S200: Perform a second photolithography and etching process to form a second opening. Perform P-type ion implantation at the second opening, followed by a first thermal annealing process to activate the P-type impurity and form the P+ region 4. Taking silicon substrate 1 as an N-type substrate as an example, the impurity implanted by the P-type ions can be boron ions (B...). + Activating P-type impurities can be achieved through a conventional high-temperature annealing process. If the boron ion concentration is too low, it will not provide sufficient boron ions to the P+ region to form an effective ohmic contact area; if it is too high, it may induce crystal defects and degrade the photodiode's performance. In practice, the concentration of doped boron ions can be designed according to the target performance of the photodiode.
[0037] Step S300: Perform a third photolithography and etching process to form a third opening. Perform N-type ion implantation at the third opening, followed by a second thermal annealing process to activate N-type impurities and form an N+ region 3. During the activation process, a second oxide layer 51 is formed on the surface of the silicon substrate 1. That is, the second oxide layer 51 is a silicon dioxide layer formed on the surface of the silicon substrate 1 after thermal oxidation. See [link to relevant documentation]. Figure 3 Taking silicon substrate 1 as an N-type substrate as an example, the impurity implanted by N-type ions can be phosphorus ions (P... + ) or arsenic ions (As + The initial thickness of the second oxide layer can be controlled between 400 and 500 Å, such as 450 Å.
[0038] Step S400: Using a pre-prepared diluted hydrofluoric acid solution (DHF), the second oxide layer is thinned through a centrifugal etching process until the second oxide layer reaches the pre-prepared thickness. Figure 4 The second oxide layer 5, after etching, effectively removes the surface defect layer that may form during thermal oxidation and provides a clean, hydrophobic silicon oxide surface, optimizing the interface characteristics with which the subsequent silicon nitride (SiN) passivation layer contacts. In the embodiment, the mass percentage of hydrofluoric acid in the pre-prepared diluted hydrofluoric acid solution is 2.5% to 6.0%. In the centrifugal etching process, the rotation speed of the silicon substrate is 155 to 165 rpm. For example, an oxide etching solution prepared with a volume ratio of 20:1 deionized water and hydrofluoric acid can be used, and the rotation speed of the silicon substrate is 160 rpm. The etching time can then be set according to the initial thickness of the second oxide layer, the concentration of the etching solution, the rotation speed, and the target thickness. In this invention, the second oxide layer is etched using a centrifugal etching process until it is thinned to a preset thickness of 95 to 105 Å. Correspondingly, the etching time is typically between 60 and 180 seconds.
[0039] This invention involves thermally activating and simultaneously growing a silicon dioxide layer in the N+ region, followed by centrifugal etching to precisely thin it to the target thickness. Compared to directly growing an ultrathin oxide layer, this method inherits the excellent density and low interface state characteristics of high-temperature oxide films while achieving nanoscale thickness uniformity through spin etching. The resulting ultrathin, uniform, and dense silicon dioxide layer, at its interface with the subsequent silicon nitride (SiN) passivation layer, significantly reduces the recombination rate of surface carriers in the photosensitive region. This substantially enhances the photodiode's responsivity and quantum efficiency to short-wavelength light such as blue and ultraviolet light, while ensuring consistent and reliable device performance.
[0040] Step S500: Deposit a first passivation layer 6 on the surface of the silicon substrate. The first passivation layer 6 may be a silicon nitride layer grown using a low-pressure chemical vapor deposition (LPCVD) process. Preferably, the thickness of the first passivation layer is 300~500 Å.
[0041] Step S600: Perform a fourth photolithography and etching process to form a fourth opening. Sequentially remove the first passivation layer 6 and the second oxide layer 5 within the area of the fourth opening to expose the surface of the underlying silicon substrate 1, forming a contact hole C1. (See...) Figure 5 ; Step S700: Deposit a metal layer 7 on the first passivation layer 6 and inside the contact hole C1, see Figure 6 Metal layer 7 can be an Al-Si-Cu alloy layer with a thickness of ~0.7 μm. A fifth photolithography step is then performed to etch metal layer 7, forming the metal interconnect pattern, as shown in [reference needed]. Figure 7 In the metal interconnect pattern, the interconnection of the metal layer M1 of the contact hole above the N+ region and the metal layer M1 on the field oxide layer of the photodiode cell connects the cathode signal of the photodiode to the preset cathode pad; the metal layer M2 of the contact hole above the P+ region connects to the preset anode pad region.
[0042] Step S800: Deposit a second passivation layer 8 on the metal interconnect pattern and the exposed first passivation layer 6, perform a sixth photolithography and etch the second passivation layer 8 to form a sixth opening. The projection of the sixth opening at least partially overlaps with the metal interconnect pattern to expose the underlying metal interconnect layer. See [link to step S800]. Figure 8 The second passivation layer 8 may include a phosphorus silicate glass layer (PSG) and an undoped silicon glass layer (USG) stacked sequentially. Preferably, the thickness of the phosphorus silicate glass layer is 1800~2200 Å, and the thickness of the undoped silicon glass layer is 2700~3300 Å.
[0043] Step S900: Fill the sixth opening with conductive material to form a contact electrode electrically connected to the metal interconnect pattern. This invention also provides a photodiode structure, which is prepared using the above-described method. The photodiode structure includes: silicon substrate; A first oxide layer is located on the upper surface of a silicon substrate, and the first oxide layer has a first opening, a second opening and a third opening; The active region located below the first opening; The P+ region located below the second opening; The N+ region located below the third opening; A second oxide layer is applied to the surface of the silicon substrate and the first oxide layer, the thickness of which is 95–105 Å. A first passivation layer is covered on the second oxide layer. A fourth opening is provided in the first passivation layer. The second oxide layer below the fourth opening is also removed to form a contact hole, which exposes the surface of the silicon substrate. Metal interconnect pattern located within the contact hole and on the first passivation layer; A second passivation layer is provided on the metal interconnect pattern and the exposed first passivation layer, and the projection of the sixth opening at least partially overlaps with the metal interconnect pattern. The contact electrode is located within the sixth opening and is electrically connected to the metal interconnect pattern.
[0044] Figure 9 This is a top view of a photodiode cell according to an embodiment of the present invention. Figures 2 to 8 Then corresponding Figure 9 The cross-section shown by the dashed line is a structural schematic diagram after each step. This cell contains two photodiode structures symmetrically distributed on both sides of the central field oxide region FOX1. For easy correspondence with the figure, the active regions OD1 on both sides of the field oxide region FOX1 are defined. The P+ and N+ regions of the two structures are electrically isolated through the field oxide layer FOX2. The two N+ regions are connected in parallel to a common cathode pad via a shared metal interconnect M1; while the two P+ regions can be connected separately via independent metal interconnects M2, or interconnected and then connected to a common anode pad. This parallel structure doubles the effective photosensitive area per unit area, improving photocurrent collection capability and device signal-to-noise ratio.
[0045] This invention provides a method for fabricating a photodiode with an ultrathin oxide layer. By optimizing the oxide layer growth and thinning process, precise control over the thickness and quality of key film layers is achieved, resulting in the following technical advantages: Achieving precise and controllable preparation of ultrathin oxide layers is crucial. Traditional furnace tube thermal oxidation methods for directly growing 100 Å-scale ultrathin oxide layers suffer from poor thickness uniformity and narrow process windows. This invention addresses this issue by combining a relatively thick oxide layer formed through thermal oxidation with a highly uniform centrifugal wet etching process for precise thinning. This approach ensures both film density and uniformity while accurately controlling the target thickness, providing an excellent surface condition for subsequent passivation layer interface contact.
[0046] To achieve a balance between performance improvement and optimized manufacturing costs, this invention employs DHF wet etching to thin the oxide layer. This process is simple, cost-controllable, and suitable for mass production. At the device design level, this method achieves a significant improvement in short-wavelength spectral responsivity and quantum efficiency by appropriately reducing the oxide layer thickness. This results in an optimized balance between optical performance and electrical reliability within an acceptable breakdown voltage range, enhancing the overall competitiveness of the product.
[0047] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.
[0048] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.
Claims
1. A method for fabricating a photodiode, characterized in that, The preparation method includes the following steps: A silicon substrate is provided, a first oxide layer is grown on a surface of the silicon substrate, and the first oxide layer is photolithographically etched and etched to form a first opening to define the active region of the photodiode. A second photolithography and etching process is performed to form a second opening. P-type ion implantation is then performed at the second opening, followed by a first thermal annealing process to activate P-type impurities and form a P+ region. A third photolithography and etching process is performed to form a third opening. N-type ion implantation is performed at the third opening, followed by a second thermal annealing process to activate N-type impurities and form N+ regions. A second oxide layer is then formed on the surface of the silicon substrate. The second oxide layer is thinned by using a pre-prepared diluted hydrofluoric acid solution and a centrifugal etching process until the second oxide layer reaches the pre-prepared thickness. A first passivation layer is deposited on the surface of the silicon substrate; A fourth photolithography and etching process is performed to form a fourth opening. The first passivation layer and the second oxide layer in the area of the fourth opening are removed to expose the surface of the underlying silicon substrate and form a contact hole. A metal layer is deposited on the first passivation layer and inside the contact hole, and a fifth photolithography is performed to etch the metal layer to form a metal interconnect pattern. A second passivation layer is deposited on the metal interconnect pattern and the exposed first passivation layer. A sixth photolithography is performed and the second passivation layer is etched to form a sixth opening. The projection of the sixth opening at least partially overlaps with the metal interconnect pattern to expose the underlying metal interconnect layer. The sixth opening is filled with conductive material to form a contact electrode that is electrically connected to the metal interconnect pattern.
2. The method for fabricating a photodiode according to claim 1, characterized in that, The mass percentage of hydrofluoric acid in the pre-prepared diluted hydrofluoric acid solution is 2.5% to 6.0%. In the centrifugal etching process, the rotation speed of the silicon substrate is 155~165 rpm.
3. The method for fabricating a photodiode according to claim 1, characterized in that, The initial thickness of the second oxide layer is 400~500 Å.
4. The method for fabricating a photodiode according to claim 1, characterized in that, The preset thickness in the step of using centrifugal etching to etch the second oxide layer until the second oxide layer is thinned to a preset thickness is 95~105 Å.
5. The method for fabricating a photodiode according to claim 1, characterized in that, The first passivation layer is a silicon nitride layer.
6. The method for fabricating a photodiode according to claim 1, characterized in that, The first passivation layer is grown using a low-pressure chemical vapor deposition process; and / or The thickness of the first passivation layer is 300~500 Å.
7. The method for fabricating a photodiode according to claim 1, characterized in that, The second passivation layer comprises a phosphorus silicate glass layer and an undoped silicon glass layer stacked sequentially.
8. The method for fabricating a photodiode according to claim 7, characterized in that, The thickness of the phosphorus-silicon glass layer is 1800~2200 Å, and the thickness of the undoped silicon glass layer is 2700~3300 Å.
9. The method for fabricating a photodiode according to claim 1, characterized in that, The thickness of the silicon substrate is 300~650μm; and / or The thickness of the first oxide layer is 7000~8000 Å; and / or The impurity implanted by the P-type ion implantation is boron ion, and the impurity implanted by the N-type ion implantation is phosphorus ion or arsenic ion.
10. A photodiode structure, characterized in that, The photodiode structure is prepared by the method for preparing a photodiode according to any one of claims 1 to 9, and the photodiode structure includes: silicon substrate; A first oxide layer is located on the upper surface of the silicon substrate, and the first oxide layer has a first opening, a second opening and a third opening; The active region located below the first opening; The P+ region located below the second opening; The N+ region located below the third opening; A second oxide layer covering the surface of the silicon substrate and the first oxide layer, the thickness of the second oxide layer being 95–105 Å; A first passivation layer is applied over the second oxide layer, the first passivation layer having a fourth opening, and the second oxide layer below the fourth opening is also removed to form a contact hole, the contact hole exposing the surface of the silicon substrate; Metal interconnect pattern located within the contact hole and on the first passivation layer; A second passivation layer covers the metal interconnect pattern and the exposed first passivation layer, the second passivation layer having a sixth opening, the projection of the sixth opening at least partially overlapping the metal interconnect pattern; The contact electrode is located within the sixth opening and is electrically connected to the metal interconnect pattern.