Display device

Abstract

A display device includes: a substrate; a light emitting element over the substrate and including a first element electrode and a second element electrode; a first electrode electrically connected to the first element electrode; and a second electrode electrically connected to the second element electrode, in which the light emitting element includes a first mesa region and a second mesa region spaced apart from each other, and in which the second element electrode is disposed in the first mesa region and the second mesa region is disposed between the first element electrode and the first mesa region.

Description

Technical Field

[0001] This disclosure relates to display devices, and more specifically, for example, but not limited to, display devices including light-emitting elements. Background Technology

[0002] With the development of the information society, the demand for different types of display devices has increased, and flat panel display devices (FPDs) such as liquid crystal displays and light-emitting diode displays have been developed and applied in various fields.

[0003] In flat panel display devices, light-emitting diode (LED) displays emit light due to the radiative recombination of excitons. Excitons are formed by the injection of charge into the light-emitting layer between the cathode (for injecting electrons) and the anode (for injecting holes) in the LED, which is composed of electrons and holes.

[0004] Light-emitting diode (LED) displays offer a variety of advantages and improved characteristics. For example, compared to liquid crystal displays (LCDs), LED displays are self-emissive, resulting in a wider viewing angle, and because they do not require a backlight unit, they are ultra-thin and lightweight. Furthermore, LED displays are also advantageous in terms of power consumption.

[0005] Light-emitting diode (LED) display devices can include inorganic-based and organic-based light-emitting elements. Inorganic-based light-emitting elements have relatively superior stability, fast response characteristics, and high contrast, and miniature LEDs (microLEDs or uLEDs) are widely used as inorganic-based light-emitting elements for high resolution.

[0006] Inorganic light-emitting elements are formed on a substrate and transferred to an array substrate of the display device. Signal electrodes for transmitting signals are then formed on the array substrate of the display device. However, because the light-emitting elements are relatively small and the distance between the signal electrodes is very short, short circuits may occur between the electrodes of the light-emitting elements.

[0007] The descriptions provided in the background section should not be assumed to be prior art simply because they are mentioned or associated with in that section. The background section may include information describing one or more aspects of the subject matter art, and the descriptions in this section do not limit this disclosure. Summary of the Invention

[0008] Therefore, embodiments of this disclosure relate to a display device that substantially eliminates one or more problems caused by the limitations and disadvantages of the prior art.

[0009] One aspect of this disclosure is to provide a display device capable of preventing or reducing electrical short circuits between electrodes of a light-emitting element.

[0010] Additional features and aspects will be set forth in the following description and will be apparent in part from the description, or may be learned by practice of the inventive concept provided herein. Other features and aspects of the inventive concept may be realized and obtained by means of structures particularly pointed out in the written description or deduced from the written description and claims and the drawings.

[0011] To achieve these and other aspects of the inventive concept, as implemented and broadly described herein, a display device includes: a substrate; a light-emitting element above the substrate and including a first element electrode and a second element electrode; a first electrode electrically connected to the first element electrode; and a second electrode electrically connected to the second element electrode, wherein the light-emitting element includes a first mesa region and a second mesa region spaced apart from each other, and wherein the second element electrode is disposed in the first mesa region, and the second mesa region is disposed between the first element electrode and the first mesa region.

[0012] Other systems, methods, features, and advantages will be or will become apparent to those skilled in the art upon examination of the following figures and detailed description. All such additional systems, methods, features, and advantages are intended to be included in this specification, within the scope of this disclosure, and protected by the appended claims. Nothing in this section should be construed as limiting these claims. Further aspects and advantages are discussed below in conjunction with embodiments of this disclosure.

[0013] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory, and are intended to provide further explanation of the claimed inventive concept. Attached Figure Description

[0014] The accompanying drawings are included to provide a further understanding of this disclosure and are incorporated in and constitute a part of this application. The drawings illustrate embodiments of the disclosure and, together with the description, serve to explain the various principles of the disclosure. In the drawings:

[0015] Figure 1 This is a schematic diagram illustrating a display device according to one embodiment of the present disclosure;

[0016] Figure 2 This is a schematic cross-sectional view of a display device according to an embodiment of the present disclosure;

[0017] Figure 3 This is a schematic plan view of the display panel of a display device according to one embodiment of the present disclosure;

[0018] Figure 4 This is a schematic cross-sectional view of the display panel of a display device according to another example of an embodiment of the present disclosure; and

[0019] Figures 5A to 5J This is a schematic cross-sectional view of a display panel during the manufacturing process of a display device according to an embodiment of the present disclosure. Detailed Implementation

[0020] Reference will now be made in detail to embodiments of this disclosure, examples of which are illustrated in the accompanying drawings. In the following description, detailed descriptions of well-known functions or configurations relevant to this document will be omitted or may be briefly discussed where it is determined that such detailed descriptions would unnecessarily obscure the essential points of the inventive concept. The described process steps and / or order of operations are exemplary; however, the order of steps and / or operations is not limited to the order set forth herein and may be varied as is known in the art, except for steps and / or operations that must occur in a specific order. The same reference numerals always refer to the same elements. The names of the corresponding elements used in the following explanation may be chosen solely for the convenience of writing the specification and may therefore differ from those used in actual products.

[0021] The advantages and features of this disclosure, as well as the methods for achieving these advantages and features, will become clear from the embodiments described below in detail with reference to the accompanying drawings. However, this disclosure may be implemented in many different forms and should not be construed as limited to the embodiments set forth herein. Embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art to which this disclosure pertains.

[0022] The shapes, sizes, dimensions (e.g., length, width, height, thickness, radius, diameter, area, etc.), scales, angles, number of elements, etc. shown in the accompanying drawings used to describe embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto.

[0023] Any implementation described in this article as an "example" is not necessarily to be interpreted as preferred or advantageous over other implementations.

[0024] For ease of description, dimensions including the size and thickness of each component shown in the accompanying drawings are illustrated, and this disclosure is not limited to the size and thickness of the components shown. However, it should be noted that the relative dimensions including the relative size, position, and thickness of the components shown in the various drawings submitted herein are part of this disclosure.

[0025] Throughout this disclosure, the same reference numerals refer to the same components.

[0026] Furthermore, in the following description of this disclosure, when a detailed description of known related technologies is determined to unnecessarily obscure the spirit of this disclosure, such detailed description will be omitted or may be briefly discussed herein.

[0027] When using terms such as “including,” “having,” or “comprising” as used in this disclosure, other components may be added unless the term “only” is used herein.

[0028] Furthermore, when a component is represented as singular, plural forms are included unless otherwise stated.

[0029] When analyzing components, the error range is interpreted as included, even if there is no explicit description.

[0030] When describing positional relationships, for example, when the positional relationship between two components / layers is described as "above", "on top", "above", "below", "below", "next to", etc., one or more other components / layers may be placed between the two components / layers unless used with the terms "exactly" or "directly".

[0031] When describing temporal relationships, such as when describing temporal precedence as "after", "following", "next", "before", etc., discontinuous or sequential cases may also be included unless "immediately" or "directly" is used.

[0032] As used herein, the terms “connection” and “linkage” are intended to have the broadest possible meaning. Specifically, the phrase “A connects to B” covers both direct connections (where no intermediate components or elements exist) and indirect connections (where one or more intermediate components or elements exist between A and B). In other words, “A connects to B” includes both direct physical or electrical connections and indirect connections via one or more intermediate components. Unless otherwise expressly stated, these terms do not require direct physical or electrical contact. The terms “linkage” and “contact” should be interpreted in the same way. For example, as used herein, the term “contact” covers both “indirect contact” and “direct contact.” Therefore, when the phrase “A is in contact with B” is used, unless explicitly specified as “A is in direct contact with B,” it implies that other components may exist between A and B.

[0033] Although the terms first, second, etc., are used to describe various components, these components are not substantially limited by these terms. These terms are only used to distinguish one component from another and do not limit any order or sequence. Therefore, within the technical concept of this disclosure, the first component described below can be substantially the second component.

[0034] The expressions "first element," "second element," and " / or" "third element" should be understood as one of the first element, the second element, and the third element, or any or all combinations of the first element, the second element, and the third element. For example, A, B, and / or C can refer to only A; only B; only C; any or some combinations of A, B, and C; or all of A, B, and C.

[0035] The term “at least one” should be understood to include any and all combinations of one or more of the associated listed items. For example, “at least one of the first element, the second element and the third element” means that the meaning covers all combinations of the three listed elements, any combination of any two of the three elements, and each individual element, the first element, the second element or the third element.

[0036] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which the example embodiments pertain. It should also be understood that terms such as those defined in common dictionaries should be interpreted as having a meaning consistent with, for example, their meaning in the context of the relevant field, and should not be interpreted in an idealized or overly formal sense unless explicitly defined herein. For example, as one of ordinary skill in the art will understand, the terms “component” or “unit” can be applied to, for example, a single circuit or structure, an integrated circuit, a computational block of a circuit device, or any structure configured to perform the described functions.

[0037] In contrast, these embodiments may be provided to make this disclosure sufficiently thorough and complete to assist those skilled in the art in fully understanding its scope. Furthermore, this disclosure is limited only by the scope of the claims.

[0038] Features of the various embodiments of this disclosure may be partially or completely unified or combined with each other, various interlocks and drives are technically possible, and each embodiment may be implemented independently of each other or together in a related relationship.

[0039] In the following description, exemplary embodiments of the present disclosure will be specifically described with reference to the accompanying drawings.

[0040] Figure 1 This diagram schematically illustrates a display device according to one embodiment of the present disclosure. The display device may be a micro-LED (light-emitting diode) display device or a mini-LED display device. However, the embodiments of the present disclosure are not limited thereto, and in other embodiments, for example, the display device may be an organic light-emitting diode (OLED) display device.

[0041] exist Figure 1 In one embodiment of the present disclosure, the display device may include a display panel PN, a timing controller TC, a data driver DD, and a strobe driver GD.

[0042] The timing controller TC can use image signals sent from external systems such as graphics cards or TV systems and multiple timing signals such as data enable signals, horizontal synchronization signals, vertical synchronization signals and clocks to generate image data RGB, data control signals DCS and gating control signals GCS.

[0043] In addition, the timing controller TC can send the generated image data RGB and the generated data control signal DCS to the data driver DD, and can send the generated gating control signal GCS to the gating driver GD.

[0044] The data driver DD can generate a data voltage as a data signal using the image data RGB and data control signal DCS sent from the timing controller TC, and can apply the generated data voltage to the data line DL of the display panel PN.

[0045] The gating driver GD can generate a gating voltage as a gating signal using the gating control signal GCS sent from the timing controller TC, and can apply the generated gating voltage to the gating line GL of the display panel PN.

[0046] Here, the gating driver GD can be configured as an in-panel gating (GIP) type formed together on the substrate of the display panel PN, on which gating lines GL, data lines DL and sub-pixels SP are formed, and can be set in the non-display area NDA.

[0047] exist Figure 1 In one embodiment, the gating driver GD can be located on one side of the display panel PN, but in other embodiments, the two gating drivers can be located on opposite sides of the display panel PN.

[0048] The display panel PN may include a display area DA for displaying an image and a non-display area NDA surrounding the display area DA. The display panel PN can display the image using a gating voltage provided from a gating driver GD and a data voltage provided from a data driver DD. To this end, the display panel PN may include multiple pixels P, multiple gating lines GL, and multiple data lines DL disposed in the display area DA.

[0049] Each of the plurality of pixels P may include a plurality of subpixels SP, and the gate line GL and the data line DL may intersect each other to define each pixel P and / or subpixel SP. For example, each of the plurality of pixels P may include a first subpixel SP1, a second subpixel SP2, and a third subpixel SP3, and the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3 may be a red subpixel, a green subpixel, and a blue subpixel, respectively.

[0050] At least one light-emitting diode, multiple thin-film transistors, and at least one storage capacitor may be provided in each sub-pixel SP.

[0051] Reference Figure 2 A detailed description of the cross-sectional structure of the display device according to embodiments of the present disclosure.

[0052] Figure 2 This is a schematic cross-sectional view of a display device according to an embodiment of the present disclosure, and shows a cross-section corresponding to a sub-pixel.

[0053] exist Figure 2 In this embodiment of the present disclosure, the display panel 100 of the display device may include a thin-film transistor TR and a light-emitting element 140 above a substrate 110. A first element electrode 141 of the light-emitting element 140 may be connected to the thin-film transistor TR, and a second element electrode 142 of the light-emitting element 140 may be connected to a power line.

[0054] Specifically, the light-shielding layer 121 may be disposed on the substrate 110. The substrate 110 may be a glass substrate or a plastic substrate. For example, polyimide may be used for the plastic substrate, and the plastic substrate may have a laminated structure including at least one polyimide layer and at least one inorganic layer. However, the embodiments of this disclosure are not limited thereto.

[0055] The light-shielding layer 121 can be formed of a conductive material such as a metal. For example, the light-shielding layer 121 can be formed of one or more of the following: aluminum (Al), copper (Cu), molybdenum (Mo), titanium (Ti), chromium (Cr), nickel (Ni), tungsten (W), and alloys thereof. The light-shielding layer 121 can have a single-layer structure or a multi-layer structure.

[0056] A buffer layer 111 may be disposed on the light-shielding layer 121. The buffer layer 111 may be substantially disposed over the entire substrate 110. The buffer layer 111 may be formed as a single layer or multiple layers of inorganic insulating material. The inorganic insulating material of the buffer layer 111 may include silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxide nitride (SiON).

[0057] The active layer 122 can be disposed on the buffer layer 111. The active layer 122 can overlap with the light-shielding layer 121, and the light-shielding layer 121 can block the light incident on the active layer 122 and prevent the active layer 122 from being degraded due to light.

[0058] The active layer 122 may include a channel region located in its central portion and source and drain regions located on both sides of the channel region. The active layer 122 may be formed of an oxide semiconductor material. Alternatively, the active layer 122 may be formed of polysilicon, in which case the ends of the active layer 122 may be doped with impurities.

[0059] A gate insulating layer 112 may be disposed on the active layer 122 and the buffer layer 111. The gate insulating layer 112 may be substantially disposed over the entire substrate 110. The gate insulating layer 112 may be formed as a single layer or multiple layers of inorganic insulating material. The inorganic insulating material of the gate insulating layer 112 may include silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxide nitride (SiON).

[0060] Gate electrode 123 and auxiliary electrode 124 can be formed on gate insulating layer 112. Gate electrode 123 can overlap with active layer 122 and can be configured to correspond to the central portion of active layer 122. Therefore, gate electrode 123 can also overlap with light-shielding layer 121.

[0061] The auxiliary electrode 124 can be spaced apart from the active layer 122 and can overlap with the light-shielding layer 121. The auxiliary electrode 124 can contact the light-shielding layer 121 through contact holes provided in the buffer layer 111 and the gate insulating layer 112.

[0062] The gate electrode 123 and the auxiliary electrode 124 can be formed of a conductive material such as a metal. For example, the gate electrode 123 and the auxiliary electrode 124 can be formed of one or more of the following: aluminum (Al), copper (Cu), molybdenum (Mo), titanium (Ti), chromium (Cr), nickel (Ni), tungsten (W), and alloys thereof. The gate electrode 123 and the auxiliary electrode 124 can have a single-layer structure or a multi-layer structure.

[0063] The first interlayer insulating layer 113 can be disposed on the gate electrode 123 and the auxiliary electrode 124. The first interlayer insulating layer 113 can be disposed substantially over the entire substrate 110. The first interlayer insulating layer 113 can be formed as a single layer or multiple layers of inorganic insulating material. The inorganic insulating material of the first interlayer insulating layer 113 may include silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxide nitride (SiON).

[0064] The capacitor electrode 125 may be disposed on the first interlayer insulating layer 113. The capacitor electrode 125 may overlap with the gate electrode 123 to form a storage capacitor, and the first interlayer insulating layer 113 therebetween serves as a dielectric. The capacitor electrode 125 may also overlap with the light-shielding layer 121.

[0065] The capacitor electrode 125 can be formed of a conductive material such as a metal. For example, the capacitor electrode 125 can be formed of one or more of the following: aluminum (Al), copper (Cu), molybdenum (Mo), titanium (Ti), chromium (Cr), nickel (Ni), tungsten (W), and alloys thereof. The capacitor electrode 125 can have a single-layer structure or a multi-layer structure.

[0066] The second interlayer insulating layer 114 can be disposed on the capacitor electrode 125. The second interlayer insulating layer 114 can be substantially disposed over the entire substrate 110. The second interlayer insulating layer 114 can be formed as a single layer or multiple layers of inorganic insulating material. The inorganic insulating material of the second interlayer insulating layer 114 may include silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxide nitride (SiON).

[0067] The source electrode 126 and the drain electrode 127 can be disposed on the second interlayer insulating layer 114. The source electrode 126 and the drain electrode 127 can be spaced apart from each other, and the gate electrode 123 is located therebetween. It can contact the two ends of the active layer 122 through contact holes disposed in the gate insulating layer 112, the first interlayer insulating layer 113, and the second interlayer insulating layer 114.

[0068] Additionally, the source electrode 126 may overlap with the capacitor electrode 125 and may contact the capacitor electrode 125 through contact holes provided in the second interlayer insulating layer 114. The drain electrode 127 may overlap with the auxiliary electrode 124 and may contact the auxiliary electrode 124 through contact holes provided in the first interlayer insulating layer 113 and the second interlayer insulating layer 114.

[0069] The active layer 122, gate electrode 123, source electrode 126, and drain electrode 127 can constitute a thin-film transistor TR. The thin-film transistor TR can be a driving transistor.

[0070] The source electrode 126 and drain electrode 127 can be formed of a conductive material such as a metal. For example, the source electrode 126 and drain electrode 127 can be formed of one or more of the following: aluminum (Al), copper (Cu), molybdenum (Mo), titanium (Ti), chromium (Cr), nickel (Ni), tungsten (W), and alloys thereof. The source electrode 126 and drain electrode 127 can have a single-layer structure or a multi-layer structure.

[0071] The first passivation layer 115 and the outer coating layer 116 can be disposed on the source electrode 126 and the drain electrode 127. The first passivation layer 115 and the outer coating layer 116 can be disposed substantially over the entire substrate 110.

[0072] The first passivation layer 115 can be formed as a single layer or multiple layers of inorganic insulating material. The inorganic insulating material of the first passivation layer 115 may include silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxide nitride (SiON). The first passivation layer 115 may be omitted.

[0073] The outer coating 116 can eliminate step differences caused by the underlying layer and can have a substantially flat top surface. For example, the outer coating 116 can be formed from an organic insulating material such as photoacrylic polymer.

[0074] The reflective electrode 132 can be disposed on the outer coating layer 116. The reflective electrode 132 can overlap with the thin-film transistor TR. The reflective electrode 132 can contact the source electrode 126 through contact holes disposed in the first passivation layer 115 and the outer coating layer 116. Therefore, the reflective electrode 132 can be electrically connected to the capacitor electrode 125 through the source electrode 126.

[0075] The reflective electrode 132 can be formed of a metal with relatively high reflectivity. For example, the reflective electrode 132 can be formed of aluminum (Al), silver (Ag), or chromium (Cr).

[0076] The second passivation layer 117 can be disposed on the reflective electrode 132. The second passivation layer 117 can be disposed substantially over the entire substrate 110.

[0077] The second passivation layer 117 can be formed as a single layer or multiple layers of inorganic insulating material. The inorganic insulating material of the second passivation layer 117 may include silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxide nitride (SiON). The second passivation layer 117 may be omitted.

[0078] The adhesive layer 118 can be disposed on the second passivation layer 117. The adhesive layer 118 can be disposed substantially above the entire substrate 110, and can fix the light-emitting element 140 to be transferred thereto.

[0079] The adhesive layer 118 may have a substantially flat top surface. For example, the adhesive layer 118 may be formed of an organic insulating material such as photoacryl. Alternatively, the adhesive layer 118 may be formed of one of polyimide (PI) resin, epoxy resin, urethane resin, and polydimethylsiloxane (PDMS) resin.

[0080] The light-emitting element 140 can be disposed on the adhesive layer 118. The light-emitting element 140 can overlap with the reflective electrode 132. Alternatively, the light-emitting element 140 can also overlap with the thin-film transistor TR and the light-shielding layer 121.

[0081] The light-emitting element 140 may be provided in the form of a micro LED chip (or uLED chip) including an n-electrode, an n-type layer, an active layer, a p-type layer, and a p-electrode. The light-emitting element 140 may have a lateral structure in which the n-electrode and the p-electrode are provided on the same side (e.g., a first side opposite to the second side facing the substrate 110) and light is emitted through the first side provided with the n-electrode and the p-electrode (e.g., a first side opposite to the second side facing the substrate 110).

[0082] However, the embodiments disclosed herein are not limited thereto. In other embodiments, the light-emitting element 140 may have a flip-chip structure in which the n-electrode and p-electrode are disposed on the same side (e.g., the second side facing the substrate 110) and light is emitted through a first side opposite to the second side where the n-electrode and p-electrode are disposed. Alternatively, the light-emitting element 140 may have a vertical structure in which the n-electrode and p-electrode are respectively disposed on opposite sides (e.g., the second side facing the substrate 110 and the first side opposite to the second side).

[0083] The light-emitting element 140 may include a first element electrode 141, a second element electrode 142, light-emitting structures 143, 144 and 145, and a protective layer 146.

[0084] The first element electrode 141 and the second element electrode 142 can be disposed on the light-emitting structures 143, 144, and 145, and can be spaced apart from each other. The first element electrode 141 and the second element electrode 142 can be disposed at different heights. For example, the second element electrode 142 can be disposed at a higher position than the first element electrode 141.

[0085] Here, the first element electrode 141 can be an n-electrode, and the second element electrode 142 can be a p-electrode. The first element electrode 141 can be a cathode, and the second element electrode 142 can be an anode.

[0086] However, the embodiments disclosed herein are not limited thereto. Alternatively, in other embodiments, the first element electrode 141 may be a p-electrode, and the second element electrode 142 may be an n-electrode. In this case, the first element electrode 141 may be an anode, and the second element electrode 142 may be a cathode.

[0087] The first element electrode 141 and the second element electrode 142 may be formed of a conductive material. For example, the first element electrode 141 and the second element electrode 142 may be formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) or an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or alloys thereof. However, embodiments of this disclosure are not limited thereto.

[0088] The light-emitting structures 143, 144, and 145 may include a first semiconductor layer 143, a light-emitting layer 144, and a second semiconductor layer 145. The light-emitting layer 144 may be disposed between the first semiconductor layer 143 and the second semiconductor layer 145.

[0089] Furthermore, the light-emitting structures 143, 144, and 145 may have a first mesa region MS1 ​​and a second mesa region MS2. The first mesa region MS1 ​​may include a first semiconductor layer 143, a light-emitting layer 144, and a second semiconductor layer 145. The second mesa region MS2 may include the first semiconductor layer 143. Therefore, the height of the second mesa region MS2 may be lower than the height of the first mesa region MS1, and the second mesa region MS2 may be positioned lower than the light-emitting layer 144 and the second semiconductor layer 145. Additionally, the width of the second mesa region MS2 may be smaller than the width of the first mesa region MS1.

[0090] The second element electrode 142 can be disposed in the first mesa region MS1, the first element electrode 141 can be spaced apart from the first mesa region MS1 ​​and the second mesa region MS2, and the second mesa region MS2 can be disposed between the first element electrode 141 and the first mesa region MS1.

[0091] The first semiconductor layer 143 and the second semiconductor layer 145 can be formed by doping an n-type impurity or a p-type impurity into the semiconductor material. For example, the first semiconductor layer 143 and the second semiconductor layer 145 can be formed by doping an n-type impurity or a p-type impurity into gallium nitride (GaN), indium aluminum phosphide (InAlP), or gallium arsenide (GaAs). Alternatively, for example, the n-type impurity can be silicon (Si), germanium (Ge), or indium (Sn), and the p-type impurity can be magnesium (Mg), zinc (Zn), or beryllium (Be). However, embodiments of this disclosure are not limited thereto.

[0092] The first semiconductor layer 143 may have a larger area than the second semiconductor layer 145. At least a portion of the first semiconductor layer 143 may protrude beyond the second semiconductor layer 145. In this case, the first element electrode 141 and the second mesa region MS2 may be disposed on the first semiconductor layer 143 protruding from the second semiconductor layer 145.

[0093] The light-emitting layer 144 can receive electrons and holes from the first semiconductor layer 143 and the second semiconductor layer 145, respectively, and emit light. The light-emitting layer 144 can be formed of a single quantum well (SQW) structure or a multiple quantum well (MQW) structure. For example, the light-emitting layer 144 can be formed of indium gallium nitride (InGaN) or gallium nitride (GaN), but is not limited thereto.

[0094] The protective layer 146 can be disposed on the light-emitting structures 143, 144, and 145 on which the first element electrode 141 and the second element electrode 142 are disposed. The protective layer 146 can cover and protect the first element electrode 141, the second element electrode 142, and the light-emitting structures 143, 144, and 145, and can partially expose the top surfaces of the first element electrode 141 and the second element electrode 142.

[0095] The protective layer 146 can be formed as a single layer or multiple layers of inorganic insulating material. The inorganic insulating material of the protective layer 146 may include silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxide nitride (SiON).

[0096] The first planarization layer 119 can be disposed on the adhesive layer 118 on which the light-emitting element 140 is disposed. The first planarization layer 119 can be disposed substantially over the entire substrate 110.

[0097] The first planarization layer 119 may partially surround the side surface of the light-emitting element 140 and may fix and protect the light-emitting element 140. The thickness of the first planarization layer 119 may be smaller than the thickness of the light-emitting element 140 and smaller than the thickness of the first semiconductor layer 143. The first planarization layer 119 may be configured to be lower than the first element electrode 141 and the second element electrode 142 of the light-emitting element 140, thereby exposing the first element electrode 141 and the second element electrode 142.

[0098] The first planarization layer 119 may be formed of an organic insulating material such as photoacryl. The first planarization layer 119 may have a substantially flat top surface.

[0099] The first electrode 152 may be disposed on the first planarization layer 119. The first electrode 152 may partially overlap with the light-emitting element 140 and may contact the first element electrode 141 of the light-emitting element 140. The first electrode 152 may be spaced apart from the first mesa region MS1 ​​and the second mesa region MS2.

[0100] In addition, the first electrode 152 can overlap with the reflective electrode 132, and can contact the reflective electrode 132 through contact holes provided in the second passivation layer 117, adhesive layer 118 and first planarization layer 119.

[0101] Therefore, the first electrode 152 can be electrically connected to the source electrode 126 of the thin-film transistor TR via the reflective electrode 132. The first element electrode 141 of the light-emitting element 140 can be electrically connected to the source electrode 126 of the thin-film transistor TR via the first electrode 152 and the reflective electrode 132.

[0102] Furthermore, the first dummy pattern 154 and the second dummy pattern 156 can also be disposed on the first planarization layer 119 and the light-emitting element 140, and can be formed of the same material as the first electrode 152. The first dummy pattern 154 can be disposed between the first mesa region MS1 ​​and the second mesa region MS2. The first dummy pattern 154 can be spaced apart from the first electrode 152 and the second dummy pattern 156, and can be disposed between the first electrode 152 and the second dummy pattern 156. Therefore, the second mesa region MS2 can be disposed between the first electrode 152 and the first dummy pattern 154.

[0103] Additionally, the second dummy pattern 156 can be disposed outside the light-emitting element 140 corresponding to the first platform area MS1, and can contact the protective layer 146 and the first planarization layer 119. The second dummy pattern 156 can be omitted.

[0104] The first electrode 152, the first dummy pattern 154, and the second dummy pattern 156 may be formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). Alternatively, the first electrode 152, the first dummy pattern 154, and the second dummy pattern 156 may be formed of a metal such as aluminum (Al), copper (Cu), molybdenum (Mo), titanium (Ti), chromium (Cr), nickel (Ni), tungsten (W), or alloys thereof.

[0105] The second planarization layer 120 can be disposed on the first electrode 152, the first dummy pattern 154, and the second dummy pattern 156. The second planarization layer 120 can be disposed substantially over the entire substrate 110.

[0106] The second planarization layer 120 may partially surround the side surface of the light-emitting element 140, and together with the first planarization layer 119, planarize the top surface of the substrate 110 on which the light-emitting element 140 is disposed. The second planarization layer 120, together with the adhesive layer 118 and the first planarization layer 119, can fix and protect the light-emitting element 140.

[0107] The second planarization layer 120 may cover the light-emitting element 140, the first electrode 152, the first dummy pattern 154, and the second dummy pattern 156, and may expose a portion of the light-emitting element 140. Specifically, the second planarization layer 120 may cover the first element electrode 141, the first electrode 152, the first dummy pattern 154, and the second dummy pattern 156, and may partially expose the second element electrode 142 of the light-emitting element 140.

[0108] The second planarization layer 120 can be formed from an organic insulating material such as photosensitive acrylic polymer.

[0109] Next, a second electrode 162 can be disposed on the second planarization layer 120. The second electrode 162 can overlap with the light-emitting element 140.

[0110] Specifically, the second electrode 162 may overlap with the first element electrode 141 and the second element electrode 142 of the light-emitting element 140, and may contact the exposed second element electrode 142. In addition, the second electrode 162 may also overlap with the first electrode 152, the first dummy pattern 154 and the second dummy pattern 156.

[0111] The second electrode 162 may be formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). Alternatively, the second electrode 162 may be formed of a metal such as aluminum (Al), copper (Cu), molybdenum (Mo), titanium (Ti), chromium (Cr), nickel (Ni), tungsten (W), or alloys thereof.

[0112] A dam layer 172 can be disposed on the second planarization layer 120 on which the second electrode 162 is disposed. The dam layer 172 can be a black dam portion that blocks light. The dam layer 172 may not overlap with the light-emitting element 140 and may be spaced apart from the light-emitting element 140. The dam layer 172 can prevent or reduce light from the light-emitting element 140 disposed in the sub-pixel from being output through its adjacent sub-pixel. Here, the dam layer 172 may partially overlap with and contact the second electrode 162.

[0113] The embankment 172 may include a backing component that absorbs light. For example, the black component may include black pigment and / or carbon black. However, embodiments of this disclosure are not limited thereto.

[0114] The third planarization layer 174 can be disposed on the dam layer 172. The third planarization layer 174 can be substantially disposed above the entire substrate 110. The third planarization layer 174 can cover and contact the second electrode 162, the dam layer 172 and the second planarization layer 120.

[0115] The third planarization layer 174 can be formed of an organic insulating material such as photoacryl and can have a substantially flat top surface.

[0116] Therefore, in the display device according to the embodiments of the present disclosure, by providing a second mesa region MS2 between the first element electrode 141 and the first mesa region MS1, and forming a first dummy pattern 154 separated from the first electrode 152 by the second mesa region MS2, the problem of electrical short circuit between the first element electrode 141 and the second element electrode 142 of the light-emitting element 140 due to contact between the first electrode 152 and the second electrode 162 can be prevented or reduced. This will be described in detail later.

[0117] Reference Figure 3 The planar arrangement of the light-emitting elements of a display device according to embodiments of the present disclosure is described.

[0118] Figure 3 This is a schematic plan view of the display panel of a display device according to one embodiment of the present disclosure, and shows the light-emitting element, the first electrode, and the second electrode.

[0119] like Figure 3 As shown, in a display device according to an embodiment of the present disclosure, the light-emitting element 140 may have a first mesa region MS1 ​​and a second mesa region MS2 spaced apart from each other in a first direction X. A second element electrode 142 of the light-emitting element 140 may be disposed in the first mesa region MS1. The first element electrode 141 may be spaced apart from the first mesa region MS1 ​​and the second mesa region MS2 in the first direction X. The second mesa region MS2 may be disposed between the first element electrode 141 and the first mesa region MS1 ​​in the first direction X.

[0120] The first electrode 152, the first dummy pattern 154, and the second dummy pattern 156 can be configured to overlap with the light-emitting element 140. The first dummy pattern 154 can be disposed between the first electrode 152 and the second dummy pattern 156 in the first direction X.

[0121] The first electrode 152 may overlap and contact the first element electrode 141, and may be spaced apart from the second element electrode 142. The first electrode 152 may be spaced apart from the first dummy pattern 154 and the second dummy pattern 156 and electrically separated.

[0122] The second mezzanine region MS2 can be disposed between the first electrode 152 and the first dummy pattern 154 in the first direction X, and the first mezzanine region MS1 ​​and the second mezzanine region MS2 can be disposed between the first electrode 152 and the second dummy pattern 156 in the first direction X.

[0123] Additionally, the first dummy pattern 154 can be disposed in the first direction X between the first mesa region MS1 ​​and the second mesa region MS2. The first dummy pattern 154 can be spaced apart from and electrically isolated from the first element electrode 141 and the second element electrode 142.

[0124] Furthermore, the second electrode 162 can be configured to overlap with the light-emitting element 140. The second electrode 162 can overlap with the first mesa region MS1 ​​and the second element electrode 142, and can be in contact with the second element electrode 142. The second electrode 162 can overlap with the first dummy pattern 154 and the second dummy pattern 156, and can also overlap with the second mesa region MS2.

[0125] Alternatively, the second electrode 162 can also be the first electrode 152 and the first element electrode 141. However, embodiments of this disclosure are not limited thereto. Alternatively, the second electrode 162 can be spaced apart from the first electrode 152 and the first element electrode 141.

[0126] Figure 4 This is a schematic cross-sectional view of a display panel of a display device according to another example of an embodiment of the present disclosure, primarily showing the connection configuration between the light-emitting elements and the electrodes. Besides the thin-film transistors and insulating layers, Figure 4 The display panel has the same Figure 2 The display panels have basically the same or similar configurations. Regarding... Figure 2 The same parts of the display panel shall be designated with the same or identical reference numerals, and the descriptions of the same parts shall be shortened or omitted.

[0127] exist Figure 4 In this configuration, the reflective electrode 132, the power line 134, and the pad electrode 136 can be disposed above the substrate 110.

[0128] Furthermore, although not shown in the figure, Figure 2 The thin-film transistor TR, multiple insulating layers, and multiple electrodes can also be disposed between the substrate 110 and the reflective electrode 132.

[0129] Power line 134 can transmit a high-potential voltage VDD. Pad electrode 136 can be positioned... Figure 1 It is located in the non-display area NDA, and can be an electrode used to provide signals from the outside to the signal lines in the display area DA.

[0130] The reflective electrode 132, the electric field line 134, and the pad electrode 136 can be formed of the same material on the same layer.

[0131] The adhesive layer 118 can be disposed on the reflective electrode 132, the electric field line 134, and the pad electrode 136, and can be substantially disposed over the entire substrate 110. Furthermore, Figure 2 The second passivation layer 117 can also be disposed between the adhesive layer 118 and the reflective electrode 132.

[0132] A light-emitting element 140 having a first mesa region MS1, a second mesa region MS2, and a first planarization layer 119 can be disposed on an adhesive layer 118. The first planarization layer 119 can partially surround the side surface of the light-emitting element 140 and can fix and protect the light-emitting element 140.

[0133] The first electrode 152, the first dummy pattern 154, and the second dummy pattern 156 can be disposed on the light-emitting element 140 and the first planarization layer 119.

[0134] The first electrode 152 can overlap and contact the first element electrode 141 of the light-emitting element 140, and can contact the reflective electrode 132 through the contact holes provided in the adhesive layer 118 and the first planarization layer 119.

[0135] The first dummy pattern 154 can be disposed between the first mesa region MS1 ​​and the second mesa region MS2. The first dummy pattern 154 can be separated from the second dummy pattern 156 through the first mesa region MS1, and can be separated from the first electrode 152 through the second mesa region MS2.

[0136] The second planarization layer 120 may be disposed on the first electrode 152, the first dummy pattern 154 and the second dummy pattern 156, and may be disposed substantially above the entire substrate 110. The second planarization layer 120 may partially surround the side surface of the light-emitting element 140 and may partially expose the second element electrode 142 of the light-emitting element 140.

[0137] Additionally, the second planarization layer 120 may have contact holes that expose 134 and pad electrode 136, as well as the adhesive layer 118 and the first planarization layer 119 below them.

[0138] The second electrode 162 can be disposed on the second planarization layer 120. The second electrode 162 can overlap with the light-emitting element 140 and can contact the second element electrode 142. In addition, the second electrode 162 can extend to overlap with the electric field line 134 and can contact the electric field line 134 through contact holes provided in the adhesive layer 118, the first planarization layer 119 and the second planarization layer 120.

[0139] In addition, the auxiliary pad 164 can also be disposed on the second planarization layer 120. The auxiliary pad 164 can overlap with the pad electrode 136 and can contact the pad electrode 136 through contact holes disposed in the adhesive layer 118, the first planarization layer 119 and the second planarization layer 120.

[0140] Reference Figures 5A to 5J A method for manufacturing a display device according to embodiments of the present disclosure is described.

[0141] Figures 5A to 5J This is a schematic cross-sectional view of a display panel during the manufacturing process of a display device according to an embodiment of the present disclosure, and illustrates the manufacturing process of the device. Figure 4 The display panel.

[0142] exist Figure 5A In this process, the reflective electrode 132, the electric field line 134, and the pad electrode 136 can be formed on the substrate 110 by depositing conductive materials and patterning them through a photolithography process.

[0143] Then, an adhesive layer 118 can be formed on the reflective electrode 132, the electric field line 134, and the pad electrode 136 by applying an adhesive material, and the light-emitting element 140 can be transferred on the adhesive layer 118 corresponding to the reflective electrode 132. The light-emitting element 140 can overlap with the reflective electrode 132.

[0144] As described above, the light-emitting element 140 may include a first element electrode 141, a second element electrode 142, a light-emitting structure 143, a light-emitting structure 144 and a light-emitting structure 145, and a protective layer 146, and may have a first mesa region MS1 ​​and a second mesa region MS2.

[0145] Here, the protective layer 146 of the light-emitting element 140 may not be exposed and may cover the first element electrode 141 and the second element electrode 142.

[0146] Next, in Figure 5B In this process, the organic material layer 119a can be formed on the light-emitting element 140 and the adhesive layer 118 by substantially applying an organic insulating material over the entire substrate 110, and can be patterned by photolithography to partially expose the top surface of the adhesive layer 118 corresponding to the reflective electrode 132, the electric field line 134 and the pad electrode 136.

[0147] In this case, the organic material layer 119a can have a thickness greater than that of the light-emitting element 140. Therefore, the organic material layer 119a can completely cover the light-emitting element 140.

[0148] Then, in Figure 5C In this process, the organic material layer 119a can be partially removed from its top surface by an ashing process, thereby forming a first planarization layer 119 with a thickness smaller than that of the organic material layer 119a. In this case, the adhesive layer 118 can also be partially removed by an ashing process.

[0149] The thickness of the first planarization layer 119 can be less than the thickness of the light-emitting element 140, thereby exposing the protective layer 146 on the first element electrode 141, the second element electrode 142, and the second mesa region MS2.

[0150] Next, in Figure 5D In this process, the first photoresist pattern 192 can be formed on the first planarization layer 119 by a photolithography process in which the photoresist is applied, exposed, and developed. The first photoresist pattern 192 can expose the light-emitting element 140.

[0151] Then, the protective layer 146 of the light-emitting element 140 can be selectively removed, thereby partially exposing the first element electrode 141 and the second element electrode 142. In this case, the protective layer 146 can be removed by a dry etching process.

[0152] Next, in Figure 5E In this process, the first photoresist pattern 192 can be peeled off and removed, and a second photoresist pattern 194 can be formed on the first planarization layer 119 and the light-emitting element 140 by a photolithography process in which the photoresist is applied, exposed, and developed. The second photoresist pattern 194 can partially expose the top surface of the adhesive layer 118 corresponding to the reflective electrode 132.

[0153] Then, the exposed adhesive layer 118 can be selectively removed using the second photoresist pattern 194 as an etching mask, thereby partially exposing the top surface of the reflective electrode 132.

[0154] Next, in Figure 5F In this process, the second photoresist pattern 194 can be stripped and removed, and a conductive material layer 150 can be formed on the first planarization layer 119 and the light-emitting element 140 by depositing a conductive material substantially over the entire substrate 110. The conductive material layer 150 can cover the light-emitting element 140 and can contact the first element electrode 141, the second element electrode 142, and the reflective electrode 132.

[0155] Then, a third photoresist pattern 196 covering the light-emitting element 140 can be formed on the conductive material layer 150 by a photolithography process in which photoresist is applied, exposed, and developed. The third photoresist pattern 196 can be partially removed by an ashing process, thereby exposing the conductive material layer 150 on the first mesa region MS1 ​​and the second mesa region MS2.

[0156] Furthermore, the third photoresist pattern 196 can cover the conductive material layer 150 on the reflective electrode 132 and can expose the conductive material layer 150 on the power lines 134 and the pad electrode 136.

[0157] Next, in Figure 5G In this process, a third photoresist pattern 196 can be used as an etching mask to selectively remove the conductive material layer 150, thereby forming a first electrode 152, a first dummy pattern 154, and a second dummy pattern 156.

[0158] Then, in Figure 5HIn the process, the third photoresist pattern 196 can be peeled off and removed. Then, the second planarization layer 120 can be formed on the light-emitting element 140, the first electrode 152, the first dummy pattern 154 and the second dummy pattern 156 by substantially coating an organic insulating material on the substrate 110, and can be patterned by photolithography to expose the adhesive layer 118 on the power lines 134 and the pad electrodes 136.

[0159] Next, the second planarization layer 120 can be partially removed by an ashing process, thereby partially exposing the second element electrode of the light-emitting element 140.

[0160] Next, in Figure 5I In this process, a fourth photoresist pattern 198 can be formed on the second planarization layer 120 by photolithography, which involves applying, exposing, and developing the photoresist. The fourth photoresist pattern 198 can cover the second planarization layer 120 and the light-emitting element 140, and can expose the adhesive layer 118 on the power lines 134 and the pad electrodes 136.

[0161] Then, the exposed adhesive layer 118 can be selectively removed using the fourth photoresist pattern 198 as an etching mask, thereby exposing the power lines 134 and the pad electrodes 136.

[0162] Next, in Figure 5J In this process, the fourth photoresist pattern 198 can be stripped and removed, and the second electrode 162 and auxiliary pad 164 can be formed on the second planarization layer 120 by depositing conductive material and then patterning it by photolithography.

[0163] The second electrode 162 can cover the light-emitting element 140 and can contact the exposed second element electrode 142 of the light-emitting element 140. Alternatively, the second electrode 162 can also contact the power line 134 through contact holes provided in the adhesive layer 118, the first planarization layer 119, and the second planarization layer 120. Furthermore, the auxiliary pad 164 can contact the pad electrode 136 through contact holes provided in the adhesive layer 118, the first planarization layer 119, and the second planarization layer 120.

[0164] Considering the margin for process deviation, the second electrode 162 can be configured to overlap with the first element electrode 141 and the second element electrode 142. In this case, during the formation and subsequent removal of the first planarization layer 119 and the first photoresist pattern 192, the second photoresist pattern 194 and the third photoresist pattern 196 on the first element electrode 141, if the organic material is not completely removed, the distance between the first electrode 152 connected to the first element electrode 141 and the second electrode 162 connected to the second element electrode 142 can be shorter.

[0165] Therefore, if the second platform area MS2 is not provided, the first dummy pattern 154 can be connected to the first electrode 152, and the second electrode 162 can contact the first dummy pattern 154, so that the second electrode 162 can be electrically connected to the first electrode 152, and the first element electrode 141 and the second element electrode 142 of the light-emitting element can be electrically short-circuited.

[0166] However, in the embodiments of this disclosure, since the first dummy pattern 154 is separated from the first electrode 152 through the second mesa region MS2, even if the second electrode 162 comes into contact with the first dummy pattern 154, electrical connection between the second electrode 162 and the first electrode 152 can be prevented. Therefore, electrical short circuits between the first element electrode 141 and the second element electrode 142 of the light-emitting element 140 can be prevented or reduced.

[0167] In the display device disclosed herein, by providing a first mesa region and a second mesa region in the light-emitting element, and forming an electrically isolated dummy pattern between the first mesa region and the second mesa region, electrical short circuits between the electrodes of the light-emitting element can be prevented or reduced.

[0168] Since light-emitting elements and virtual patterns do not require additional processes, the manufacturing process of display devices can be optimized and production energy reduced.

[0169] It will be apparent to those skilled in the art that various modifications and variations can be made to the display device and its manufacturing method disclosed herein without departing from the technical concept or scope of this disclosure. Therefore, this disclosure is intended to cover modifications and variations thereof, provided they fall within the scope of the appended claims and their equivalents.

[0170] Cross-references to related applications

[0171] This application claims priority to Korean Patent Application No. 10-2024-0164118, filed in Korea on November 18, 2024, the entire contents of which are hereby expressly incorporated by reference.

Claims

1. A display device, the display device comprising: substrate; A light-emitting element, the light-emitting element being located above the substrate, and the light-emitting element comprising a first element electrode and a second element electrode; A first electrode, which is electrically connected to the first element electrode; as well as The second electrode is electrically connected to the second element electrode. The light-emitting element includes a first mesa region and a second mesa region spaced apart from each other, and The second element electrode is disposed in the first mesa region, and the second mesa region is disposed between the first element electrode and the first mesa region.

2. The display device according to claim 1, wherein, The height of the second countertop area is lower than the height of the first countertop area.

3. The display device according to claim 1, wherein the display device further comprises a first dummy pattern between the first tabletop area and the second tabletop area.

4. The display device according to claim 3, wherein, The first dummy pattern is formed of the same material as the first electrode and is formed on the same layer as the first electrode.

5. The display device according to claim 3, further comprising a second dummy pattern formed of the same material as the first electrode and formed on the same layer as the first electrode. in, The first tabletop area is located between the first dummy pattern and the second dummy pattern.

6. The display device according to claim 1, wherein, The light-emitting element further includes a first semiconductor layer, a light-emitting layer, and a second semiconductor layer, and The first mesa region includes the first semiconductor layer, the light-emitting layer, and the second semiconductor layer, and the second mesa region includes the first semiconductor layer.

7. The display device according to claim 1, wherein, The second electrode overlaps with the second mesa region.

8. The display device according to claim 1, further comprising a reflective electrode between the substrate and the light-emitting element. in, The first electrode is connected to the reflective electrode.

9. The display device according to claim 8, further comprising a thin-film transistor located between the substrate and the reflective electrode. in, The reflective electrode is connected to the thin-film transistor.

10. The display device according to claim 8, further comprising electric field lines formed of the same material as the reflective electrode and formed on the same layer as the reflective electrode. in, The second electrode is connected to the power line.

11. The display device according to claim 1, wherein, One of the first element electrode and the second element electrode is a p electrode, and the other of the first element electrode and the second element electrode is an n electrode.

12. The display device according to claim 1, wherein, One of the first element electrode and the second element electrode is a cathode, and the other of the first element electrode and the second element electrode is an anode.

13. The display device according to claim 1, wherein, The width of the second countertop area is smaller than the width of the first countertop area.

14. The display device according to claim 5, wherein, The first electrode, the first dummy pattern, and the second dummy pattern comprise a transparent conductive material.

15. The display device according to claim 5, wherein, The first dummy pattern is separated from the first electrode through the second platform area.

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