Display device

Abstract

A display device according to the present disclosure includes: a substrate including a display area and at least one non-display area; a light emitting element disposed on the substrate; a first thin film transistor including a first semiconductor layer, a first gate electrode, and a first source electrode and a first drain electrode; a second thin film transistor including a second semiconductor layer, a second gate electrode, and a second source electrode and a second drain electrode; a separation structure in the non-display area and disposed to break the organic light emitting layer of the light emitting element; and a first upper interlayer insulating layer, a second upper interlayer insulating layer, and a third upper interlayer insulating layer interposed between the second gate electrode and the second source electrode and the second drain electrode of the second thin film transistor, and disposed in this order.

Description

[0001] This application is a divisional application of the original invention patent application No. 202111560805.8 (filed on December 20, 2021, invention title: display device). Technical Field

[0002] This disclosure relates to a display device including a substrate hole that penetrates the substrate. Background Technology

[0003] Recently, as our society develops towards an information society, the field of display devices for visually representing electrical information signals has developed rapidly. Correspondingly, various display devices with excellent performance in terms of thinness, lightness, and low power consumption are being developed.

[0004] Typically, electronic devices such as monitors, TVs, laptops, and digital cameras include display devices that realize images. For example, a display device may include light-emitting elements. Each light-emitting element may emit light of a specific color. For example, each light-emitting element may include a light-emitting layer located between a first electrode and a second electrode.

[0005] The display device may have built-in peripheral devices, such as cameras, speakers, and sensors. For example, the display device may include substrate holes that penetrate the element substrate supporting the light-emitting elements. The substrate holes may be located between the light-emitting elements. The peripheral devices may be inserted into the substrate holes.

[0006] However, in display devices, external moisture can penetrate the substrate holes. This external moisture can then travel through the light-emitting layer to the light-emitting elements adjacent to the substrate holes. Therefore, in display devices, the light-emitting elements adjacent to the substrate holes may be damaged by the external moisture that has penetrated them. Summary of the Invention

[0007] One aspect of this disclosure is to provide a display device that can prevent or at least reduce damage to the light-emitting element caused by external moisture penetrating through a substrate hole.

[0008] Another aspect of this disclosure is to provide a display device that can reduce the degradation of a second semiconductor layer from an insulating layer, including hydrogen, located above the second semiconductor layer.

[0009] Another aspect of this disclosure is to provide a display device that can reduce substrate warping caused by multiple inorganic insulating layers above the substrate.

[0010] The purpose of this disclosure is not limited to the above-mentioned purposes, and other purposes not mentioned above will be clearly understood by those skilled in the art from the following description.

[0011] A display device according to an exemplary embodiment of the present disclosure may include: a substrate including a display area and at least one non-display area, wherein a transparent area and a separation area are located in the non-display area; a light-emitting element disposed in the display area on the substrate; a first thin-film transistor including a first semiconductor layer formed of a first material and including a first source region, a first channel region and a first drain region, a first gate electrode overlapping the first semiconductor layer, wherein a lower gate insulating layer is inserted between the first semiconductor layer and the first gate electrode, and a first source electrode and a first drain electrode electrically connected to the first semiconductor layer; and a second thin-film transistor, wherein the second thin film... The transistor includes a second semiconductor layer formed of a second material and including a second source region, a second channel region, and a second drain region; a second gate electrode overlapping the second semiconductor layer, wherein an upper gate insulating layer is inserted between the second semiconductor layer and the second gate electrode; and a second source electrode and a second drain electrode electrically connected to the second semiconductor layer; a separation structure located in the separation region and configured to disconnect the organic light-emitting layer of the light-emitting element; and a first upper interlayer insulating layer, a second upper interlayer insulating layer, and a third upper interlayer insulating layer inserted between the second gate electrode, the second source electrode, and the second drain electrode of the second thin-film transistor, and arranged sequentially.

[0012] Further details of the exemplary embodiments are included in the detailed specification and accompanying drawings.

[0013] According to an exemplary embodiment of the display device based on this disclosure, the path of hydrogen diffusion into the second semiconductor layer can be shielded by sequentially forming a second interlayer insulating layer and a third upper interlayer insulating layer between the second gate electrode, the second source electrode, and the second drain electrode of the second thin-film transistor. The second interlayer insulating layer and the third upper interlayer insulating layer are formed of silicon nitride (SiNx) and have different hydrogen contents and thicknesses. Therefore, the reliability of the device can be improved, thereby providing a high-quality display device.

[0014] The technical problems to be solved, the means of solving the problems, and the effects described above in the specification are not intended to limit the basic features of the claims. Therefore, the scope of the claims is not limited by the content described in the specification. Attached Figure Description

[0015] Figure 1 This is a diagram showing the front surface of a display panel according to an exemplary embodiment of the present disclosure.

[0016] Figure 2 By magnification Figure 1 Area A in the diagram shows a plan view of the display area.

[0017] Figure 3 It is along Figure 2A cross-sectional view of the sub-pixel intercepted by line II′ in the image.

[0018] Figure 4 By magnification Figure 1 The area B shown in the diagram is a plan view of the camera aperture.

[0019] Figure 5 It is along Figure 4 A cross-sectional view of the area of ​​the camera hole intercepted by line II-IV in the diagram.

[0020] Figure 6 This is a cross-sectional view illustrating an exemplary embodiment of the present disclosure, and is Figure 5 An enlarged view of region D in the image. Detailed Implementation

[0021] By referring to the following text and appendix Figure 1 The advantages and features of this disclosure, as well as methods for achieving these advantages and features, will become clear from the detailed description of exemplary embodiments herein. However, this disclosure is not limited to the exemplary embodiments disclosed herein, but will be implemented in various forms. Exemplary embodiments are provided by way of example only to enable those skilled in the art to fully understand the content and scope of this disclosure. Therefore, this disclosure will be limited only by the scope of the appended claims.

[0022] The shapes, dimensions, ratios, angles, quantities, etc., illustrated in the accompanying drawings to describe exemplary embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto. The same reference numerals generally denote the same elements throughout the specification. Furthermore, in the following description of the present disclosure, detailed descriptions of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter. Terms such as “comprising,” “having,” and “including” as used herein are generally intended to allow for the addition of other components, unless these terms are used in conjunction with the term “only.” Unless expressly stated otherwise, any singular reference may include the plural.

[0023] Even if not explicitly stated, components are interpreted as including common error ranges.

[0024] When using terms such as “on top of,” “above,” “below,” and “near,” to describe the positional relationship between two components, one or more components may be placed between the two components unless these terms are used in conjunction with the terms “immediately following” or “directly.”

[0025] When using terms such as “after,” “following,” “next,” and “before” to describe the temporal order between two or more events, the two or more events may be discontinuous unless these terms are used in conjunction with the terms “immediately” or “directly.”

[0026] Although the terms "first," "second," etc., are used to describe various components, these components are not bound by these terms. These terms are only used to distinguish one component from others. Therefore, the first component mentioned below can be the second component within the technical concept of this disclosure.

[0027] In describing the elements of this disclosure, terms such as “first,” “second,” “A,” “B,” “(a),” and “(b)” may be used. These terms are used only to distinguish one element from another, and the substance, order, sequence, or number of the respective elements are not limited by these terms. It should be understood that when an element or layer is described as “connected,” “joined,” or “adheded” to another element or layer, the element or layer may be directly connected or adhered to the other element or layer, but other elements or layers may be “placed” between the element or layer and the other element or layer, or the element or layer and the other element or layer may be “connected,” “joined,” or “adheded” to each other through other elements or layers.

[0028] The term "display device" as used herein can be used to include display devices in the narrow sense, which include display panels and driving units for driving the display panels, such as liquid crystal modules (LCMs), organic light-emitting diode (OLED) modules, and quantum dot modules. Additionally, the term "display device" as used herein can also include equipment display devices that comprise complete or final products including LCMs, OLEDs, QD modules, etc. (e.g., notebook computers, televisions, computer monitors, automotive displays, or other displays in vehicles), as well as assemblies of electronic devices or assemblies of equipment (e.g., mobile electronic devices such as smartphones or electronic boards).

[0029] Therefore, the display device here can include application products or complete sets of equipment, such as end products including LCM, OLED and QD modules, as well as the display device itself in a narrow sense, such as LCM, OLED and QD modules.

[0030] If necessary, LCM, OLED, and QD modules, which include display panels, driving units, etc., can be narrowly defined as "display devices," and electronic devices that are final products including LCM, OLED, and QD modules can be defined as "equipment assemblies." For example, a display device in the narrow sense may include display panels such as LCD, OLED, and QD modules, and a source printed circuit board (source PCB) corresponding to a control unit for driving the display panel. In the case of an equipment assembly, it may include an assembly PCB corresponding to an assembly control unit electrically connected to the source PCB, in order to control the entire equipment assembly.

[0031] The display panel used in this exemplary embodiment can be any type of display panel, such as a liquid crystal display panel, an organic light-emitting diode (OLED) display panel, a quantum dot (QD) display panel, and an electroluminescent display panel. The display panel in this embodiment is not limited to a specific display panel; it includes a flexible substrate for an OLED display panel and a backplate support structure below the substrate that allows the bezel to be bent. Furthermore, the display panel used in the display device according to the exemplary embodiment of this disclosure is not limited to its shape or size.

[0032] More specifically, if the display panel is an OLED display panel, the display panel may include multiple gate lines, multiple data lines, and multiple pixels formed at the intersections of the gate lines and data lines. Additionally, the display panel may include an array, an OLED layer on the array, an encapsulation substrate or encapsulation layer disposed on the array to cover the OLED layer, etc., said array including thin-film transistors configured to selectively apply voltage to each pixel. The encapsulation layer can protect the thin-film transistors and the OLED layer from external impacts and inhibit moisture and oxygen permeation into the OLED layer. Furthermore, the layers formed on the array may include inorganic light-emitting layers, such as nanoscale material layers or quantum dots.

[0033] Figure 1 An exemplary organic light-emitting diode (OLED) display panel 100 that can be incorporated into a display device is shown here.

[0034] Figure 1 This is a plan view of a display panel 100 according to an exemplary embodiment of the present disclosure. (Refer to...) Figure 1 In the organic light-emitting diode (OLED) display panel 100, the aperture CH of the camera and sensor is located within the display area DA, thereby reducing the bezel area that is a non-display area and increasing the display area DA. Products with a design that increases the display area DA can improve the user's screen immersion and are therefore more aesthetically pleasing.

[0035] The aperture CH of the camera and sensor can be as follows: Figure 1 The example shown is a single hole, but it is not limited to this, and it can be arranged in various ways. For example, one or two holes can be arranged within the display area DA, and a camera can be arranged in the first hole, while a distance detection sensor or a face recognition sensor and a wide-angle camera can be arranged in the second hole.

[0036] Figure 2 This is a magnified view of region A. Region A is Figure 1 A portion of the display area DA of the display panel 100, and Figure 2 The planar shape of the subpixel set in the display area DA is shown.

[0037] exist Figure 2 In the display panel 100, multiple anode electrodes 151 are disposed in the display area DA, and a dam 154 can fill the area between the anode electrodes 151. The dam 154 can be configured to cover the edges of the anode electrodes 151 and can only allow the central region of the anode electrodes 151 to contact the organic light-emitting stack, thereby defining the light-emitting area of ​​the sub-pixel. Spacers 155 can be disposed in a portion of the area where the dam 154 is disposed. The spacers 155 can be configured to have a constant density throughout the display panel 100. The spacers 155 can be used to support the mask such that when the deposition process is performed to form the organic light-emitting stack, the deposition mask covering or opening the organic layer in each sub-pixel does not directly contact the display panel 100. Although Figure 2 The example illustrates a pentile-type planar structure with subpixels arranged in a dotted pattern. This disclosure is not limited to this; a real-type planar structure may also be used.

[0038] Figure 3 It shows Figure 2 The cross-sectional structure of the sub-pixels I-I' in the diagram.

[0039] Reference Figure 3 A substrate 101, a multi-buffer layer 102, and a lower buffer layer 103 can be disposed thereon, and a first thin-film transistor 120 can be disposed on the lower buffer layer 103. The first thin-film transistor 120 includes a first semiconductor layer 123 and a first gate electrode 122, and a lower gate insulating layer 104 can be disposed on the first semiconductor layer 123 for insulating the first semiconductor layer 123 and the first gate electrode 122. A first lower interlayer insulating layer 105 and a second lower interlayer insulating layer 106 can be sequentially disposed on the first gate electrode 122, and an upper buffer layer 107 can be disposed on the first lower interlayer insulating layer 105 and the second lower interlayer insulating layer 106.

[0040] The substrate 101 can support various components of the display device. The substrate 101 can be formed of a flexible glass or plastic material. When the substrate 101 is formed of a plastic material, it can be formed of, for example, polyimide (PI). When the substrate 101 is formed of polyimide (PI), the display device manufacturing process is performed with a support substrate formed of glass disposed below the substrate 101, and the support substrate can be released after the display device manufacturing process is completed. When the substrate 101 is formed of polyimide (PI), moisture can permeate through the substrate 101 formed of polyimide (PI) into the first thin-film transistor 120 or the light-emitting element 150, thereby degrading the performance of the display device. The display device according to an exemplary embodiment of this disclosure can be formed of two polyimides (PI) to prevent performance degradation of the display device due to moisture permeation. Furthermore, by forming an inorganic layer between the two polyimides (PI), the permeation of moisture components through the lower polyimide (PI) can be blocked or at least reduced, thereby improving product performance reliability.

[0041] The multiple buffer layer 102 can delay the diffusion of moisture or oxygen that permeates into the substrate 101, and the multiple buffer layer 102 can be formed by alternately stacking silicon nitride (SiNx) and silicon oxide (SiOx) at least once.

[0042] The lower buffer layer 103 protects the first semiconductor layer 123 and blocks or at least reduces various types of defects introduced from the substrate. The lower buffer layer 103 may be formed of a-Si, silicon nitride (SiNx), or silicon oxide (SiOx).

[0043] The first semiconductor layer 123 of the first thin-film transistor 120 may be formed of a polycrystalline semiconductor layer, and the first semiconductor layer 123 may include a channel region, a source region, and a drain region.

[0044] Polycrystalline semiconductor layers offer lower power consumption and superior reliability compared to amorphous and oxide semiconductor layers. These advantages make polycrystalline semiconductor layers suitable for driving transistors.

[0045] The first gate electrode 122 can be disposed on the lower gate insulating layer 104 and can be configured to overlap with the first semiconductor layer 123.

[0046] The second thin-film transistor 130 can be disposed on the upper buffer layer 107, and the light-shielding layer 136 can be disposed below the region corresponding to the second thin-film transistor 130. (Refer to...) Figure 3A light-shielding layer 136 is disposed on a first lower interlayer insulating layer 105 in a region corresponding to the second thin-film transistor 130, and a second semiconductor layer 133 of the second thin-film transistor 130 may be disposed on the second lower interlayer insulating layer 106 and the upper buffer layer 107 to overlap with the light-shielding layer 136. An upper gate insulating layer 137 for insulating the second gate electrode 132 and the second semiconductor layer 133 may be disposed on the second semiconductor layer 133, and then a first upper interlayer insulating layer 108 may be disposed on the second gate electrode 132. A second upper interlayer insulating layer 109 may be disposed on the first upper interlayer insulating layer 108. The first gate electrode 122 and the second gate electrode 132 may be a single layer or multiple layers formed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or their alloys, but this disclosure is not limited thereto.

[0047] The first lower interlayer insulating layer 105 and the second lower interlayer insulating layer 106 can be formed from inorganic layers with a higher hydrogen particle content compared to the first upper interlayer insulating layer 108. For example, the first lower interlayer insulating layer 105 and the second lower interlayer insulating layer 106 can be formed from silicon nitride (SiNx) formed using a deposition process using NH3 gas, and the first upper interlayer insulating layer 108 can be formed from silicon oxide (SiOx). The hydrogen particles included in the first lower interlayer insulating layer 105 and the second lower interlayer insulating layer 106 can diffuse into the polycrystalline semiconductor layer during the hydrogenation process to fill the voids in the polycrystalline semiconductor layer with hydrogen. Therefore, the polycrystalline semiconductor layer can be stabilized, thereby preventing the characteristics of the first thin-film transistor 120 from deteriorating. After the activation and hydrogenation process of the first semiconductor layer 123 of the first thin-film transistor 120, the second semiconductor layer 133 of the second thin-film transistor 130 can be formed, and in this case, the second semiconductor layer 133 can be formed from an oxide semiconductor. Since the second semiconductor layer 133 is not exposed to the high-temperature atmosphere of the activation and hydrogenation process of the first semiconductor layer 123, damage to the second semiconductor layer 133 can be prevented, and reliability can be improved. The second upper interlayer insulating layer 109a and the third upper interlayer insulating layer 109b can be sequentially disposed on the first upper interlayer insulating layer 108. The second upper interlayer insulating layer 109a and the third upper interlayer insulating layer 109b can include insulating materials. The second upper interlayer insulating layer 109a and the third upper interlayer insulating layer 109b can include materials different from those of the first upper interlayer insulating layer 108. For example, the second upper interlayer insulating layer 109a and the third upper interlayer insulating layer 109b can include silicon nitride-based (SiNx) materials. That is, the second upper interlayer insulating layer 109a and the third upper interlayer insulating layer 109b can be formed from the same material. However, the hydrogen content of the second upper interlayer insulating layer 109a and the third upper interlayer insulating layer 109b can be different from each other. The second upper interlayer insulating layer 109a may include more hydrogen than the third upper interlayer insulating layer 109b. The thickness of the second upper interlayer insulating layer 109a may be less than the thickness of the third upper interlayer insulating layer 109b.

[0048] After the first upper interlayer insulating layer 108, the second upper interlayer insulating layer 109a, and the third upper interlayer insulating layer 109b are formed, the first source contact hole 125S and the first drain contact hole 125D can be formed to correspond to the source region and drain region of the first thin-film transistor, and the second source contact hole 135S and the second drain contact hole 135D can be formed to correspond to the source region and drain region of the second thin-film transistor 130. (Refer to...) Figure 3The first source contact hole 125S and the first drain contact hole 125D are formed such that the holes can be continuously formed from the third upper interlayer insulating layer 109b to the lower gate insulating layer 104. Furthermore, the second source contact hole 135S and the second drain contact hole 135D can also be formed in the second thin-film transistor 130. The first source electrode 121 and the first drain electrode 124 corresponding to the first thin-film transistor 120, and the second source electrode 131 and the second drain electrode 134 corresponding to the second thin-film transistor 130 can be formed simultaneously, thereby reducing the number of processes required to form the source and drain electrodes of each of the first thin-film transistor 120 and the second thin-film transistor 130.

[0049] The first source electrode 121 and the first drain electrode 124, as well as the second source electrode 131 and the second drain electrode 134, may be a single layer or multiple layers formed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or their alloys, but this disclosure is not limited thereto.

[0050] The storage capacitor 140 can be disposed between the first thin-film transistor 120 and the second thin-film transistor 130. For example... Figure 3 As shown, the storage capacitor 140 can be formed by overlapping the storage lower electrode 141 and the storage upper electrode 142, with a first lower interlayer insulating layer 105 inserted between the storage lower electrode 141 and the storage upper electrode 142.

[0051] The lower storage electrode 141 is located on the lower gate insulating layer 104 and can be formed on the same layer as the first gate electrode 122 and can be formed of the same material as the first gate electrode 122. The upper storage electrode 142 can be electrically connected to the pixel circuit via the storage supply line 143. The upper storage electrode 142 can be formed of the same material as the light-shielding layer 136. The upper storage electrode 142 is exposed through the storage contact hole 144, which penetrates the second lower interlayer insulating layer 106, the upper buffer layer 107, the upper gate insulating layer 137, the first upper interlayer insulating layer 108, the second upper interlayer insulating layer 109a, and the third upper interlayer insulating layer 109b, and the upper storage electrode 142 is connected to the storage supply line 143. Meanwhile, although... Figure 3 The storage upper electrode 142 shown is spaced apart from the light-shielding layer 136, but they can also be formed as a single unit connected to each other. The storage supply line 143 can be formed on the same layer and made of the same material as the first source electrode 121 and the first drain electrode 124, as well as the second source electrode 131 and the second drain electrode 134, so that the storage supply line 143 can be formed simultaneously using the same masking process as the first source electrode 121 and the first drain electrode 124, as well as the second source electrode 131 and the second drain electrode 134.

[0052] A passivation layer 110 can be formed by depositing an inorganic insulating material such as SiNx or SiOx on a substrate 101 on which a first source electrode 121 and a first drain electrode 124, a second source electrode 131 and a second drain electrode 134, and a storage supply line 143 are formed. A first planarization layer 111 can be formed on the substrate 101 on which the passivation layer 110 is formed. Specifically, the first planarization layer 111 can be formed by applying an organic insulating material such as acrylic resin to the entire surface of the substrate 101 on which the passivation layer 110 is formed.

[0053] A passivation layer 110 and a first planarization layer 111 are provided, and a contact hole exposing the first source electrode 121 or the first drain electrode 124 of the first thin-film transistor 120 can be formed by photolithography. A connection electrode 145 formed of a material of Mo, Ti, Cu, AlNd, Al or Cr or their alloys can be disposed in the region of the contact hole exposing the first drain electrode 124.

[0054] The second planarization layer 112 can be disposed on the connecting electrode 145, and a contact hole for exposing the connecting electrode 145 is formed in the second planarization layer 112, thereby allowing the light-emitting element 150 connected to the first thin-film transistor 120 to be disposed.

[0055] The light-emitting element 150 may include an anode electrode 151 connected to the first drain electrode 124 of the first thin film transistor 120, at least one light-emitting stack 152 formed on the anode electrode 151, and a cathode electrode 153 formed on the light-emitting stack 152.

[0056] The light-emitting stack 152 may include a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer. In a tandem structure of multiple overlapping light-emitting layers, a charge generation layer may be additionally disposed between the light-emitting layers. In the case of the light-emitting layers, they can emit different colors in their respective sub-pixels. For example, a red light-emitting layer, a green light-emitting layer, and a blue light-emitting layer can be formed separately for each sub-pixel. However, the common light-emitting layer is formed to emit white light, without color differentiation for each pixel, and a color filter for color differentiation can be provided separately. In addition to forming their respective light-emitting layers, the light-emitting stack 152 is generally set as a common layer, and the light-emitting stack 152 can be equally disposed in each sub-pixel.

[0057] The anode electrode 151 can be connected to the connection electrode 145 exposed through a contact hole penetrating the second planarization layer 112. The anode electrode 151 can be formed as a multilayer structure including a transparent conductive layer and an opaque conductive layer with high reflectivity. The transparent conductive layer is formed of a material with a relatively large work function value, such as indium tin oxide (ITO) or indium zinc oxide (IZO), and the opaque conductive layer is formed of a single layer or multiple layers containing Al, Ag, Cu, Pb, Mo, or Ti or alloys thereof. For example, the anode electrode 151 can be formed as a structure in which transparent conductive layers, opaque conductive layers, and transparent conductive layers are stacked sequentially, or as a structure in which transparent conductive layers and opaque conductive layers are stacked sequentially. The anode electrode 151 is disposed on the second planarization layer 112 to overlap with the light-emitting area provided by the embankment 154 and the pixel circuit area in which the first thin-film transistor 120 and the second thin-film transistor 130 and the storage capacitor 140 are disposed, thereby allowing an increase in the light-emitting area.

[0058] The light-emitting stack 152 can be formed by stacking a hole transport layer, an organic light-emitting layer, and an electron transport layer on the anode electrode 151 in sequence or in reverse order. Additionally, the light-emitting stack 152 may further include a first light-emitting stack and a second light-emitting stack facing each other, with a charge-generating layer between them.

[0059] The dam 154 can be formed to expose the anode electrode 151. The dam 154 can be formed of an organic material such as photoacrylic resin, and can be formed of a translucent material, but is not limited thereto, and can also be formed of an opaque material to prevent light interference between sub-pixels.

[0060] The cathode electrode 153 can be formed on the upper surface of the light-emitting stack 152, facing the anode electrode 151, and the light-emitting stack 152 is inserted between the cathode electrode 153 and the anode electrode 151. When the cathode electrode 153 is applied to a top-emitting organic light-emitting display device, a transparent conductive layer can be formed by forming a relatively thin layer of indium tin oxide (ITO), indium zinc oxide (IZO), or magnesium silver (Mg-Ag).

[0061] To prevent or at least reduce the oxidation of the light-emitting material and electrode material, an encapsulation layer 170 can be provided on the cathode electrode 153 to prevent or at least reduce the penetration of oxygen and moisture from the outside. When the light-emitting stack 152 is exposed to moisture or oxygen, pixel shrinkage or black spots may occur in the light-emitting area, resulting in a reduction in the light-emitting area. The encapsulation layer can be formed of an inorganic layer made of glass, metal, or aluminum oxide (AlOx) or silicon (Si) based materials, or it can have a structure with alternating organic and inorganic layers. In this case, the first inorganic insulating layer 171 and the second inorganic insulating layer 173 are used to block or at least reduce the penetration of moisture or oxygen, and the organic layer 172 is used to planarize the surfaces of the first inorganic insulating layer 171 and the second inorganic insulating layer 173. The organic layer 172 can be referred to as a foreign matter compensation layer. When the encapsulation layer is formed as a multilayer film, the movement path of moisture or oxygen is longer and more complex compared to the case where the encapsulation layer is formed as a single layer, making it difficult for moisture / oxygen to penetrate into the organic light-emitting element.

[0062] A barrier film may be located on the encapsulation layer 170 and encapsulate the entire substrate 101. The barrier film may be a delay film or an optically isotropic film. In this case, an adhesive layer may be located between the barrier film and the encapsulation layer 170. The adhesive layer bonds the encapsulation layer 170 and the barrier film. The adhesive layer may be a thermosetting adhesive or a naturally curing adhesive. For example, the adhesive layer may be formed of a material such as barrier pressure-sensitive adhesive (B-PSA).

[0063] Figure 4 Is with Figure 1 A magnified plan view of region B corresponding to the region CH of the camera aperture (hereinafter referred to as the "camera aperture CH region"). (Refer to...) Figure 4 A large circular space exists in the center, and a camera module can be housed within it. The camera hole CH region can be removed using a laser during the panel finishing stage. Therefore, except for a portion of the camera hole CH region, substrate 101 can be removed. A non-display area NA can be disposed between the camera hole CH region and the display area AA. A dam structure 300 and a separation structure 200 can be disposed in the non-display area NA surrounding the camera hole CH region. (See reference...) Figure 4The dam structure 300 may be composed of a first dam 301 and a second dam 302, and the separation structure 200 may be composed of a first separation unit 201 and a second separation unit 202. The first dam 301, the first separation unit 201, the second dam 302, and the second separation unit 202 may be sequentially arranged around the camera hole CH region. Typically, the dam structure prevents or at least reduces the flow of the foreign matter compensation layer 172, which is part of the encapsulation layer, downwards to the end of the outer portion of the display panel 100, thus aiming to maintain the adhesion between the upper and lower substrates constituting the display panel 100. The dam structure 300 around the camera hole CH region may be formed by multiple structures such as the first dam 301 and the second dam 302 to protect the light-emitting element 150, for example, by preventing or at least reducing the introduction or leakage of the foreign matter compensation layer 172 of the encapsulation layer 170 into the camera hole CH region. While this disclosure proposes two dams, this disclosure is not limited thereto, and additional dam arrangements may be possible depending on the spatial arrangement. (Refer to...) Figure 4 The first separation unit 201 may be disposed inside the first dam 301, and the second separation unit 202 may be disposed inside the second dam 302. The first separation unit 201 and the second separation unit 202 may be configured to protect the light-emitting element 150 of the display area from moisture or oxygen that may be introduced from the camera hole CH area. The light-emitting stack 152 for the light-emitting element 150 may be deposited on the front surface of the display panel 100 and may also be uniformly deposited on the camera hole CH area. The light-emitting stack 152 can transmit moisture and oxygen to the light-emitting element 150 of the display area AA because the light-emitting stack 152 has high reactivity and propagation characteristics to moisture and oxygen due to the properties of organic materials. To prevent this, the first separation unit 201 and the second separation unit 202 may allow the light-emitting stack 152 to be partially separated. This specification describes two separation structures, but is not limited thereto.

[0064] In the non-display area NA near the camera hole CH region, various lines can be arranged in addition to the dam structure 300 and the separation structure 200. Due to the arrangement of the camera hole CH region, the light-emitting elements 150 and pixel circuits in the corresponding area are removed, but the light-emitting elements 150 and pixel circuits arranged on the top, bottom, left, and right sides of the camera hole CH region should be electrically connected. For this purpose, in the non-display area NA near the camera hole CH region, the high-potential power line PL and the gate line SL can be arranged to bypass the camera hole CH region and be connected vertically and horizontally.

[0065] Figure 5 It is shown Figure 4The diagram shows a cross-sectional view of structures II-IV. First dam 301 and second dam 302 are arranged in a closed loop around the camera hole CH region, and the first separation unit 201 can be arranged in a closed loop between the first dam 301 and the second dam 302. When observing the cross-section near the camera hole CH region, various insulating layers can be provided in the substrate 101 and the display area AA. For example, multiple buffer layers 102, lower buffer layers 103, first lower interlayer insulating layers 105, second lower interlayer insulating layers 106, upper buffer layers 107, first upper interlayer insulating layers 108, second upper interlayer insulating layers 109a, and third upper interlayer insulating layers 109b can be sequentially stacked on the substrate 101. The camera hole CH region can vary depending on the size of the camera to be applied to the product, and although the corresponding area is shown as an empty space, some insulating layers or line structures can be provided therein. However, when the camera hole CH region is removed using a laser, since the camera hole CH region is a dummy area not retained in the finished product, its separate representation is omitted. The laser can be irradiated in a circular or elliptical shape along the shape of the camera aperture CH region, and all areas on the substrate, including the substrate 101, can be removed by laser irradiation. There may be a difference between the actual camera aperture CH region and the laser irradiation area; for example, the laser irradiation area may be an area approximately 100µm inward from the camera aperture CH region. In this way, when there is a difference between the laser irradiation area and the camera aperture CH region, the insulating layer of the camera aperture CH region can be undamaged during laser irradiation. The laser can be a picosecond laser or a femtosecond laser, but is not limited to these. Lasers use light that is sensed and emitted by amplifying light generated by applying energy to a specific material. Lasers have the same properties as electromagnetic waves and are directional for monochromatic light, so they are used for communication, medical, and industrial purposes. If a laser is used, patterns can be formed on a desired area, or specific areas can be easily removed. The aforementioned picosecond and femtosecond lasers can be classified based on the laser irradiation time. Picoseconds and femtoseconds are units of time. A picosecond is one trillionth of a second (10⁻¹² seconds), and a femtosecond is one trillionth of a second (10⁻¹⁵ seconds)—extremely short time intervals imperceptible to humans. Lasers are categorized by time because a picosecond laser pulse lasts one trillionth of a second, while a femtosecond laser pulse lasts one trillionth of a second. Lasers use energy to form or remove patterns, and when laser energy strikes an object, thermal energy melts the object to form the pattern. As the pulse is applied for a longer duration, thermal effects can occur that travel to the vicinity of the patterned area. This thermal effect can cause heat buildup around the laser-irradiated area of ​​the object and can potentially burn or deform into adjacent areas larger than the set pattern. Due to these properties of lasers, if the laser-irradiated area overlaps with or is adjacent to an insulating layer, the laser's thermal energy can also cause deformation of the insulating layer.Because deformation of the insulating layer can cause cracks, and these cracks can propagate through the insulating layer, leading to stratification or penetration of moisture and oxygen, for example, to prevent deformation or stratification of insulating layers such as the multi-buffer layer 102, lower buffer layer 103, first lower interlayer insulating layer 105, second lower interlayer insulating layer 106, upper buffer layer 107, first upper interlayer insulating layer 108, and second upper interlayer insulating layer 109, all insulating layers can be removed at a distance of approximately 100 μm from the laser irradiation location. See reference. Figure 6 The first dam 301 and the second dam 302 may have an overall width of approximately 50 μm and may have a cap-like structure, wherein the left and right surfaces have gentle slopes, but the central region has a steep slope. For example, the width of the dam may be approximately 30 μm to 60 μm, but is not limited thereto. In this case, the width of the central region with the steep slope may be approximately 25 μm, but is not limited thereto. The first dam 301 and the second dam 302 may be formed by stacking the second planarization layer 112, the dike 154, and the spacer 155, but is not limited thereto. The first dam 301 and the second dam 302 may further include the first planarization layer 111 or may be configured to include another layer.

[0066] The encapsulation layer 170 can be disposed in the same manner as in the display area AA, on the region in which the first dam 301, the second dam 302, and the first separation unit 201 are disposed, and the encapsulation layer 170 may include a first inorganic insulating layer 171, a foreign matter compensation layer 172, and a second inorganic insulating layer 173. However, the foreign matter compensation layer 172 may only exist in a portion of the region adjacent to the second dam 302, and may not be disposed in the region of the first dam 301.

[0067] Figure 6 This is a cross-sectional view illustrating an exemplary embodiment of the present disclosure, and is Figure 5 A magnified view of region D.

[0068] Reference Figure 6 The separation region can be located between the display area and the penetration area where the camera is located. The separation structure 312 can be located within the separation region.

[0069] The separation structure 312 is provided to disconnect the light-emitting stack 152. This is because when the light-emitting stack 152 is exposed to the outside, it may become a path for moisture penetration. Since the light-emitting stack 152 may be exposed to the outside in the separation area, the separation structure 312 is necessary.

[0070] The separation structure 312 can be formed of the same material as the second planarization layer 112 used to planarize the upper portion of the second thin-film transistor 130. That is, the separation structure 312 can be formed in a columnar shape, with the second planarization layer 112 located on the second upper interlayer insulating layer 109a and the third upper interlayer insulating layer 109b. The second upper interlayer insulating layer 109a and the third upper interlayer insulating layer 109b below the outer portion of the separation structure 312 can then be removed. The removal process can be performed by a dry etching process or a wet etching process.

[0071] When the second upper interlayer insulating layer 109a and the third upper interlayer insulating layer 109b below the outer portion of the separation structure 312 are undercut to remove them inward, the layers deposited on the separation structure 312 (e.g., reference numeral 152) do not completely cover the lower part of the outer portion of the separation structure 312, and their connection is broken as shown in the figure. By using this phenomenon, a specific layer can be separated by partially removing the layer below the separation structure 312. As mentioned above, since the light-emitting stack 152 serves as a moisture transport path and may cause defects in the display device, it is important to completely separate the light-emitting stack 152. In order to completely separate the light-emitting stack 152, as mentioned above, it is necessary to achieve undercut by partially removing the second upper interlayer insulating layer 109a and the third upper interlayer insulating layer 109b below the separation structure 312. In addition, as the height of the undercut structure increases, the separation of the light-emitting stack 152 can be advantageous. That is, the thickness of the second upper interlayer insulating layer 109a and the third upper interlayer insulating layer 109b can be increased to increase the height of the undercut structure. However, in the display area AA, when the thicknesses of the second upper interlayer insulating layer 109a and the third upper interlayer insulating layer 109b on the second semiconductor layer 133 of the second thin-film transistor 130 are formed to be large enough to separate the light-emitting stack 152 in the separation region, the second semiconductor layer 133 of the second thin-film transistor 130 may degrade. That is, when the thicknesses of the second upper interlayer insulating layer 109a and the third upper interlayer insulating layer 109b, which include silicon nitride-based (SiNx) materials, increase, the hydrogen content of the second upper interlayer insulating layer 109a and the third upper interlayer insulating layer 109b increases, causing the second semiconductor layer 133 of the second thin-film transistor 130, which is formed of oxide semiconductor, to degrade. Therefore, there are limitations to increasing the distance between the lower surface of the separation structure 312 and the upper surface of the first upper interlayer insulating layer 108 by increasing the thickness of the second upper interlayer insulating layer 109a and the third upper interlayer insulating layer 109b.

[0072] In an exemplary embodiment of this disclosure, in order to reduce the degradation of the second semiconductor layer 133 of the second thin film transistor 130 while increasing the distance between the separation structure 312 and the first upper interlayer insulating layer 108, the insulating layer between the first upper interlayer insulating layer 108 and the separation structure 312 can be configured as two layers, such as a second upper interlayer insulating layer 109a and a third upper interlayer insulating layer 109b.

[0073] The second upper interlayer insulating layer 109a and the third upper interlayer insulating layer 109b may comprise insulating materials. The second upper interlayer insulating layer 109a and the third upper interlayer insulating layer 109b may comprise materials different from those of the first upper interlayer insulating layer 108. For example, the second upper interlayer insulating layer 109a and the third upper interlayer insulating layer 109b may comprise silicon nitride-based (SiNx) materials. That is, the second upper interlayer insulating layer 109a and the third upper interlayer insulating layer 109b may be formed of the same material. However, the hydrogen content of the second upper interlayer insulating layer 109a and the third upper interlayer insulating layer 109b may differ from each other. The second upper interlayer insulating layer 109a may comprise more hydrogen than the third upper interlayer insulating layer 109b. The thickness of the second upper interlayer insulating layer 109a may be less than the thickness of the third upper interlayer insulating layer 109b.

[0074] By forming the second upper interlayer insulating layer 109a, which has a high hydrogen content, smaller than the third upper interlayer insulating layer 109b, which has a low hydrogen content, the diffusion of hydrogen into the second semiconductor layer 133 can be reduced. Furthermore, by forming the second upper interlayer insulating layer 109a and the third upper interlayer insulating layer 109b separately, an interface is formed between these two layers, and the diffusion of hydrogen from the upper portion of the third upper interlayer insulating layer 109b into the second semiconductor layer 133 can be suppressed. For example, the path of hydrogen diffusion from the encapsulation layer 170 above the third upper interlayer insulating layer 109b into the second semiconductor layer 133 can be blocked or at least reduced.

[0075] Furthermore, the upper buffer layer 107, upper gate insulating layer 137, and first upper interlayer insulating layer 108, formed of silicon oxide (SiOx) and located above the substrate 101, as well as the second upper interlayer insulating layer 109a, formed of silicon nitride (SiNx) and including a high hydrogen content, can have high compressive stress. For example, the upper buffer layer 107, upper gate insulating layer 137, and first upper interlayer insulating layer 108 formed of silicon oxide (SiOx) can have a compressive stress of approximately -300 MPa to -400 MPa, and the second upper interlayer insulating layer 109a can have a compressive stress of approximately -200 MPa. Due to these layers, the substrate 101 released from the glass substrate may bulge and warp. That is, due to the compressive stress of the upper buffer layer 107, upper gate insulating layer 137, first upper interlayer insulating layer 108, and second upper interlayer insulating layer 109a, the central portion of the substrate may bulge and warp.

[0076] Unlike the second upper interlayer insulating layer 109a, the third upper interlayer insulating layer 109b, formed of the same silicon nitride (SiNx) as the second upper interlayer insulating layer 109a but having a lower hydrogen content, can have a tensile stress of approximately 150 to 200 MPa. The compressive stresses of the upper buffer layer 107, the upper gate insulating layer 137, the first upper interlayer insulating layer 108, and the second upper interlayer insulating layer 109a are offset by the tensile stress of the third upper interlayer insulating layer 109b, thereby suppressing warping of the substrate 101.

[0077] As described above, hydrogen diffusion into the second semiconductor layer can be shielded by sequentially forming a second upper interlayer insulating layer 109a and a third upper interlayer insulating layer 109b, made of silicon nitride (SiNx) and having different hydrogen contents and thicknesses, between the second gate electrode 132 and the second source electrode 131 and the second drain electrode 134 of the second thin-film transistor 130. Furthermore, the height of the undercut structure can be sufficiently formed so that the light-emitting element can be disconnected via the separation structure 312 in the separation region. Additionally, the compressive stress of the upper buffer layer 107, the upper gate insulating layer 137, the first upper interlayer insulating layer 108, and the second upper interlayer insulating layer 109a is offset by the tensile stress of the third upper interlayer insulating layer 109b, thereby suppressing warping of the substrate 101. This prevents defects in the display device and provides a highly reliable display device.

[0078] Exemplary embodiments of this disclosure can also be described as follows: According to one aspect of this disclosure, a display device includes: a substrate including a display area and at least one non-display area, wherein a transparent area and a separation area are located in the non-display area; a light-emitting element disposed in the display area on the substrate; a first thin-film transistor including a first semiconductor layer formed of a first material and including a first source region, a first channel region and a first drain region, a first gate electrode overlapping the first semiconductor layer, wherein a lower gate insulating layer is disposed between the first semiconductor layer and the first gate electrode, and a first source electrode and a first drain electrode electrically connected to the first semiconductor layer; and a second thin-film transistor, wherein the second thin-film transistor includes a display area and at least one non-display area, wherein a transparent area and a separation area are located in the non-display area; a lower gate insulating layer is disposed between the first semiconductor layer and the first gate electrode; and a first source electrode and a first drain electrode electrically connected to the first semiconductor layer; and a second thin-film transistor including a display area and at least one non-display area, wherein a transparent area and a separation area are located in the display area; a first ... The transistor includes a second semiconductor layer formed of a second material and including a second source region, a second channel region, and a second drain region; a second gate electrode overlapping the second semiconductor layer, wherein an upper gate insulating layer is located between the second semiconductor layer and the second gate electrode; and a second source electrode and a second drain electrode electrically connected to the second semiconductor layer; a separation structure located in the separation region and configured to disconnect the organic light-emitting layer of the light-emitting element; and a first upper interlayer insulating layer, a second upper interlayer insulating layer, and a third upper interlayer insulating layer, which are inserted between the second gate electrode and the second source electrode and the second drain electrode of the second thin-film transistor and are arranged sequentially.

[0079] The display device may further include a first planarization layer disposed on the second thin-film transistor and a second planarization layer disposed on the first planarization layer.

[0080] The separation structure can be formed from the same material as the second planarization layer.

[0081] The first upper interlayer insulation layer, the second upper interlayer insulation layer, and the third upper interlayer insulation layer can extend into the separation region.

[0082] The first upper interlayer insulating layer can be a silicon oxide (SiOx) layer.

[0083] The second and third upper interlayer insulating layers can be silicon nitride (SiNx) layers.

[0084] The hydrogen content of the second upper interlayer insulation layer can be greater than that of the third upper interlayer insulation layer.

[0085] The widths of the second and third upper interlayer insulation layers below the separation structure can be smaller than the width of the separation structure.

[0086] The separation structure can be positioned around the penetration area.

[0087] The display device may also include an encapsulation layer that covers the display area and the separation area, and includes a first inorganic insulating layer, a foreign matter compensation layer, and a second inorganic insulating layer.

[0088] The thickness of the second upper interlayer insulation layer can be less than the thickness of the third upper interlayer insulation layer.

[0089] The camera module or sensor can be placed in the penetrating area.

[0090] The display device may further include a first lower interlayer insulating layer and a second lower interlayer insulating layer inserted between the first gate electrode and the first source electrode and the first drain electrode of the first thin-film transistor. The hydrogen content of the first lower interlayer insulating layer and the second lower interlayer insulating layer is greater than the hydrogen content of the first upper interlayer insulating layer.

[0091] The display device may further include a storage capacitor disposed between the first thin-film transistor and the second thin-film transistor. The storage capacitor may be formed by overlapping the lower storage electrode and the upper storage electrode and inserting a first lower interlayer insulating layer between the lower storage electrode and the upper storage electrode.

[0092] The display device may also include a dam structure positioned around the penetrating area. The dam structure may consist of a first dam and a second dam, and the separation structure may consist of a first separation unit and a second separation unit, and the first dam, the first separation unit, the second dam, and the second separation unit may be sequentially arranged around the penetrating area.

[0093] The first and second dams can be arranged in a closed loop around the penetration area, the first separation unit can be arranged in a closed loop between the first and second dams, and the second separation unit can be arranged in a closed loop around the second dam.

[0094] Although exemplary embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto and may be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the exemplary embodiments of the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above exemplary embodiments are illustrative in all respects and do not limit the present disclosure. The scope of protection of the present disclosure should be interpreted based on the appended claims, and all technical concepts within their equivalent scope should be interpreted as falling within the scope of the present disclosure.

[0095] Cross-references to related applications

[0096] This application claims the benefit and priority of Korean Patent Application No. 10-2020-0185148, filed in Korea on December 28, 2020, the entire contents of which are hereby expressly incorporated by reference.

Claims

1. A display device, the display device comprising: A substrate, the substrate including a display area and at least one non-display area, the at least one non-display area including a penetrating area and a separating area, the penetrating area including a hole through the thickness of the substrate; A light-emitting element is disposed in the display area of ​​the substrate, and the light-emitting element includes an organic light-emitting layer; A first thin-film transistor includes a first semiconductor layer comprising a first material and including a first source region, a first channel region and a first drain region, a first gate electrode overlapping the first semiconductor layer, and a first source electrode and a first drain electrode electrically connected to the first semiconductor layer, wherein a lower gate insulating layer is inserted between the first semiconductor layer and the first gate electrode. The second thin-film transistor includes a second semiconductor layer comprising a second material and including a second source region, a second channel region and a second drain region, a second gate electrode overlapping the second semiconductor layer, and a second source electrode and a second drain electrode electrically connected to the second semiconductor layer, wherein an upper gate insulating layer is inserted between the second semiconductor layer and the second gate electrode. A separation structure located in the separation region, the separation structure being configured to disconnect the organic light-emitting layer of the light-emitting element from another organic light-emitting layer in the separation region; A dam, the dam being in the separation area such that the separation structure is between the display area and the dam; as well as A support structure, which overlaps with the dam in the separated region.

2. The display device according to claim 1, further comprising: A planarization layer is located above the first thin-film transistor and the second thin-film transistor; as well as A dam, the dam being located on a portion of the organic light-emitting layer; The dam comprises the same material as either the leveling layer or the embankment.

3. The display device according to claim 1, further comprising: In the plan view of the display device, the spacer is located between a first sub-pixel including a first anode electrode and a second sub-pixel including a second anode electrode; In the plan view, the shapes of the first anode electrode and the second anode electrode are symmetrical with respect to the spacer.

4. The display device according to claim 1, wherein, The other organic light-emitting layer includes a first portion on the upper surface of the separation structure and a second portion disconnected from the first portion, the second portion being below the separation structure and overlapping the first portion of the other organic light-emitting layer.

5. The display device according to claim 1, wherein, The dam includes a first end and a second end, the second end being further away from the substrate than the first end, and the width of the second end being less than the width of the first end.

6. The display device according to claim 1, further comprising: An encapsulation layer is provided above the light-emitting element in the display area, and the encapsulation layer extends to the dam in the separation area.

7. The display device according to claim 6, further comprising: A barrier film is provided on the encapsulation layer; as well as An adhesive layer is provided between the barrier film and the encapsulation layer, which attaches the barrier film and the encapsulation layer together.

8. The display device according to claim 1, wherein, The display device is flexible.

9. The display device according to claim 1, further comprising: In the plan view of the display device, the scan line surrounds the hole.

10. The display device according to claim 1, further comprising: A multiple buffer layer is provided between the substrate and the first thin-film transistor.

11. The display device according to claim 1, further comprising: A first upper interlayer insulating layer, a second upper interlayer insulating layer, and a third upper interlayer insulating layer are sequentially disposed, and the first upper interlayer insulating layer, the second upper interlayer insulating layer, and the third upper interlayer insulating layer are inserted between the second gate electrode of the second thin film transistor and the second source electrode and the second drain electrode of the second thin film transistor.

12. The display device according to claim 11, wherein, The first upper interlayer insulating layer extends to the hole in the penetration region.

13. The display device according to claim 1, wherein, The first source electrode, the first drain electrode, the second source electrode, and the second drain electrode are on the same layer.

14. The display device according to claim 1, further comprising: A storage capacitor is disposed between the first thin-film transistor and the second thin-film transistor, the storage capacitor including a storage lower electrode and a storage upper electrode that overlap each other, such that the storage lower electrode is closer to the substrate than the storage upper electrode.

15. The display device according to claim 14, wherein, The lower surface of the storage electrode is on the upper surface of the same layer as the lower surface of the first gate electrode.

16. The display device according to claim 14, wherein, The storage lower electrode comprises the same material as the first gate electrode.

17. The display device according to claim 14, further comprising: A light-shielding layer, which overlaps with the second thin-film transistor and is on the same layer as the storage upper electrode.

18. The display device according to claim 14, further comprising: A first insulating layer is located between the upper storage electrode and the lower storage electrode, and is located above the first gate electrode in the display area.

19. The display device according to claim 18, wherein, The first insulating layer extends from the display area to the hole in the penetration area.

20. The display device according to claim 1, wherein, The first thin-film transistor and the second thin-film transistor are included in the same sub-pixel.

21. The display device according to claim 1, in, The first semiconductor layer of the first thin-film transistor is formed of polycrystalline semiconductor, and The second semiconductor layer of the second thin-film transistor is formed of an oxide semiconductor.

22. The display device according to claim 1, further comprising: A second insulating layer is provided between the dam and the supporting structure in the separation region.

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