Display panel and display device

Abstract

The embodiment of the invention provides a display panel and a display device. The display panel comprises a substrate, gate lines and pixels, wherein the gate lines and the pixels are located on one side of the substrate, and the pixels comprise pixel circuits; the gate line extends along a first direction, the pixel circuit comprises a function transistor, the function transistor comprises a graphical conductive structure, and a gate electrode of the function transistor is located in the conductive structure; wherein the conductive structure is electrically connected with the gate line through the via hole, and the sheet resistance of a film layer where the gate line is located is smaller than that of a film layer where the conductive structure is located; the pixel circuit comprises a first transistor and a second transistor, an active layer of the first transistor comprises silicon, an active layer of the second transistor comprises a metal oxide, the gate line comprises a first gate line and a second gate line, a conductive structure of the first transistor is connected with the first gate line through a via hole, and a conductive structure of the second transistor is connected with the second gate line. The conductive structure of the second transistor is connected with the second gate line through a via hole, and the first gate line and the second gate line are located on the same layer. According to the invention, the voltage drop of the gate line transmission signal can be reduced.

Description

[0001] This application is a divisional application filed on February 22, 2023, with application number 202310162416.2, entitled "Display Panel and Display Device". Technical Field

[0002] This invention relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0003] OLED (Organic Light-Emitting Diode) boasts advantages such as self-illumination, high brightness, low power consumption, fast response, high definition, good flexibility, and high luminous efficiency, meeting consumers' evolving demands for display technology. Current OLED display panels mostly employ active-matrix driving, incorporating pixel circuits within the panel with multiple signal lines connected to them. Currently, the high load on some signal lines negatively impacts display uniformity. Summary of the Invention

[0004] This invention provides a display panel and a display device to solve the technical problem of improving display uniformity.

[0005] In a first aspect, embodiments of the present invention provide a display panel, the display panel including a substrate, a gate line located on one side of the substrate, and pixels, each pixel including a pixel circuit; the gate line extends along a first direction, the pixel circuit including a functional transistor, the functional transistor including a patterned conductive structure, and the gate of the functional transistor being located in the conductive structure; wherein... The conductive structure is electrically connected to the gate line through a via, and the sheet resistance of the film layer where the gate line is located is less than the sheet resistance of the film layer where the conductive structure is located. The pixel circuit includes a first transistor and a second transistor. The active layer of the first transistor comprises silicon, and the functional transistor includes at least one of the first transistors. The active layer of the second transistor comprises metal oxide, and the functional transistor includes at least one of the second transistors. The gate line includes a first gate line, and the conductive structure of the first transistor is electrically connected to the first gate line through a via; the gate line also includes a second gate line, and the conductive structure of the second transistor is electrically connected to the second gate line through a via. The first gate line and the second gate line are located on the same layer.

[0006] Secondly, embodiments of the present invention provide a display panel, the display panel including a substrate, a gate line located on one side of the substrate, and pixels, each pixel including a pixel circuit; the gate line extends along a first direction, the pixel circuit includes a functional transistor, the functional transistor including a patterned conductive structure, and the gate of the functional transistor being located in the conductive structure; wherein... The conductive structure is electrically connected to the gate line through a via, and the sheet resistance of the film layer where the gate line is located is less than the sheet resistance of the film layer where the conductive structure is located. The pixel circuit includes a second transistor, the active layer of the second transistor comprising a metal oxide, and the functional transistor includes at least one of the second transistors. The gate line includes a second gate line, and the conductive structure of the second transistor is electrically connected to the second gate line through a via; The conductive structure of the second transistor includes a first conductive structure and a second conductive structure; the first gate of the second transistor is located in the first conductive structure, and the second gate of the second transistor is located in the second conductive structure; Along a plane perpendicular to the substrate, the first conductive structure and the second conductive structure are located on opposite sides of the active layer of the second transistor. The second gate line includes a first sub-gate line and a second sub-gate line. The first conductive structure is electrically connected to the first sub-gate line through a via, and the second conductive structure is electrically connected to the second sub-gate line through a via.

[0007] Thirdly, based on the same inventive concept, embodiments of the present invention also provide a display device, including the display panel provided in any embodiment of the present invention.

[0008] The display panel and display device provided in this embodiment of the invention have the following beneficial effects: The functional transistors in the pixel circuit include patterned conductive structures, the gates of the functional transistors are located in the conductive structures, the conductive structures are electrically connected to the gate lines through vias, and the sheet resistance of the film layer where the gate lines are located is set to be less than the sheet resistance of the film layer where the conductive structures are located. This reduces the resistance of the gate lines, thereby reducing the voltage drop of the signals transmitted through the gate lines. The conductive structure configuration in this embodiment of the invention ensures the characteristic performance of the functional transistors, while also reducing the voltage drop of the signals transmitted through the gate lines and improving display uniformity. Attached Figure Description

[0009] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 This is a schematic diagram of a pixel circuit in a display panel provided by an embodiment of the present invention; Figure 2 A schematic diagram of the pixel circuit of another display panel provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of another display panel provided in an embodiment of the present invention; Figure 4 for Figure 3 A schematic diagram of a cross-section at the position of the tangent AA′; Figure 5 This is a schematic diagram of another display panel provided in an embodiment of the present invention; Figure 6 This is a schematic diagram of another display panel provided in an embodiment of the present invention; Figure 7 for Figure 5 A schematic diagram showing the film layer disassembly at the location of the middle pixel circuit; Figure 8 for Figure 5 A schematic diagram of a cross-section at the location of the tangent line BB′; Figure 9 This is a schematic diagram of a pixel circuit in a display panel provided in an embodiment of the present invention; Figure 10 This is a schematic diagram of another display panel provided in an embodiment of the present invention; Figure 11 This is a schematic diagram of another display panel provided in an embodiment of the present invention; Figure 12 This is a schematic diagram of another display panel provided in an embodiment of the present invention; Figure 13 This is a schematic diagram of another display panel provided in an embodiment of the present invention; Figure 14 This is a schematic diagram of another display panel provided in an embodiment of the present invention; Figure 15 This is a schematic diagram of another display panel provided in an embodiment of the present invention; Figure 16 This is a schematic diagram of another display panel provided in an embodiment of the present invention; Figure 17 This is a simplified schematic diagram of another display panel provided in an embodiment of the present invention; Figure 18 This is a schematic diagram of another display panel provided in an embodiment of the present invention; Figure 19 for Figure 18 A schematic diagram of a cross-section at the position of the tangent CC′; Figure 20 This is a schematic diagram of another display panel provided in an embodiment of the present invention; Figure 21 This is a schematic diagram of a display device provided in an embodiment of the present invention. Detailed Implementation

[0011] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0012] The terminology used in the embodiments of this invention is for the purpose of describing particular embodiments only and is not intended to limit the invention. The singular forms “a,” “the,” and “the” as used in the embodiments of this invention and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0013] This invention provides a display panel, which includes pixels. Each pixel includes a light-emitting device and a pixel circuit, and the light-emitting device is electrically connected to the pixel circuit. The light-emitting device can be an organic light-emitting device or an inorganic light-emitting device. Figure 1 This is a schematic diagram of a pixel circuit in a display panel provided by an embodiment of the present invention, such as... Figure 1As shown, the pixel circuit 10 includes a driving transistor Tm, a data writing transistor M1, an electrode reset transistor M2, a gate reset transistor M3, a threshold compensation transistor M4, a first light-emitting control transistor M5, and a second light-emitting control transistor M6. The driving transistor Tm is connected in series between the first light-emitting control transistor M5 and the second light-emitting control transistor M6. The gate of the driving transistor Tm is connected to the first node N1, the first electrode of the driving transistor Tm is connected to the second node N2, and the second electrode of the driving transistor Tm is connected to the third node N3. The gate reset transistor M3 is connected to the first node N1. The data writing transistor M1 and the first light-emitting control transistor M5 are connected to the second node N2. The threshold compensation transistor M4 is connected in series between the first node N1 and the third node N3. The first electrode of the second light-emitting control transistor M6 is connected to the third node N3, and the second electrode of the second light-emitting control transistor M6 is connected to the fourth node N4. The electrode reset transistor M2 is connected to the fourth node N4. One electrode of the light-emitting device PD is connected to the fourth node N4, and the other electrode receives the negative power supply signal Pvee. In this circuit, the gates of data writing transistor M1 and threshold compensation transistor M4 receive scan signal S1; the gates of gate reset transistor M3 and electrode reset transistor M2 receive scan signal S2; and the gates of the first light-emitting control transistor M5 and the second light-emitting control transistor M6 receive light-emitting control signal Emit. To drive the pixel circuit 10, scan lines and light-emitting control lines need to be provided in the display panel. The scan lines provide scan signals, and the light-emitting control lines provide light-emitting control signals. Additionally, a reset signal line providing a reset signal Ref, a data line providing a data signal Data, and a positive power supply line providing a positive power supply signal Pvdd are also required. In the pixel circuit 10, one plate of the storage capacitor Cst is connected to the first node N1, and the other plate is connected to the positive power supply signal Pvdd.

[0014] Figure 1 In the schematic diagram, each transistor in the pixel circuit 10 is a p-type transistor. In other embodiments, each transistor in the pixel circuit 10 is an n-type transistor.

[0015] in addition, Figure 1 In the illustration, electrode reset transistor M2 and gate reset transistor M3 receive the same reset signal Ref. In other embodiments, gate reset transistor M3 receives a first reset signal, and electrode reset transistor M2 receives a second reset signal; the voltage values ​​of the first and second reset signals are different.

[0016] The display panel also includes a scan drive circuit and a light emission shift circuit, each comprising multiple cascaded shift registers. The cascaded shift registers in the scan drive circuit are used to sequentially output scan signals, while the cascaded shift registers in the light emission shift circuit are used to sequentially output light emission control signals. Figure 1 In the illustration, reset transistor M2 and gate reset transistor M3 receive the same scan signal, thus connecting them to the same stage of shift registers in the scan drive circuit. In other embodiments, reset transistor M2 and gate reset transistor M3 are respectively connected to two adjacent stages of shift registers in the scan drive circuit, thus receiving scan signals sequentially output from the two adjacent stages of shift registers.

[0017] In some implementations... Figure 2 This is a schematic diagram of the pixel circuit of another display panel provided in an embodiment of the present invention, as shown below. Figure 2 As shown, in the pixel circuit 10, the gate reset transistor M3 and the threshold compensation transistor M4 are n-type transistors, while the remaining transistors are p-type transistors. The active layers of the gate reset transistor M3 and the threshold compensation transistor M4 contain metal oxide, such as indium gallium zinc oxide, while the active layers of the remaining transistors contain silicon. This configuration results in lower leakage current in the off-state of the gate reset transistor M3 and the threshold compensation transistor M4, reducing leakage current from them to the first node N1, thereby stabilizing the potential of the first node N1 and improving screen flickering issues at low frequencies and in sunlight. Furthermore, Figure 2 The diagram illustrates that gate reset transistor M3 receives the first reset signal Ref1, and electrode reset transistor M2 receives the second reset signal Ref2. The voltage values ​​of the first reset signal Ref1 and the second reset signal Ref2 are different. The gate of data write transistor M1 receives scan signal Sp1, the gate of threshold compensation transistor M4 receives scan signal Sn2, the gate of gate reset transistor M3 receives scan signal Sn1, and the gate of electrode reset transistor M2 receives scan signal Sp2. Scan signals Sn1 and Sn2 are provided by two adjacent shift registers in one set of shift drive circuits, and scan signals Sp1 and Sp2 are provided by two adjacent shift registers in another set of shift drive circuits.

[0018] In some other embodiments, one of the gate reset transistor M3 and the threshold compensation transistor M4 in the pixel circuit 10 is an n-type transistor, and the other transistors are p-type transistors, which will not be shown in the accompanying drawings.

[0019] In the display panel, the pixel circuits 10 are arranged in a row-column array. Multiple pixel circuits 10 are arranged in the row direction to form a pixel circuit row, and multiple pixel circuits 10 are arranged in the column direction to form a pixel circuit column. A scan line connects multiple pixel circuits 10 arranged in the row direction. The load on the scan line is large and the voltage drop is large, which affects the uniformity of the display.

[0020] To improve display uniformity, this embodiment of the invention provides another display panel in which the gates of some transistors in the pixel circuit and the gate lines that provide signals to the gates are located on different layers, and the sheet resistance of the film layer where the gate lines are located is less than the sheet resistance of the film layer where the gates are connected, thereby reducing the voltage drop of the signals transmitted by the gate lines and improving display uniformity.

[0021] In some implementations... Figure 3 This is a schematic diagram of another display panel provided in an embodiment of the present invention. Figure 4 for Figure 3 A schematic diagram of a cross-section at the location of the tangent AA′. Figure 3 The diagram illustrates some signal lines in the display panel and a pixel circuit 10 in the i-th pixel circuit row, where i is an integer greater than or equal to 2. The transistors in pixel circuit 10 and their interconnections can be found above. Figure 1 The examples are used for understanding. Figure 3 As shown, the gates of data writing transistor M1 and threshold compensation transistor M4 are electrically connected to scan line S1_i. The gates of electrode reset transistor M2 and gate reset transistor M3 are electrically connected to scan line S2_i. The gates of the first light-emitting control transistor M5 and the second light-emitting control transistor M6 are electrically connected to light-emitting control line Emit_i. When electrode reset transistor M2, electrically connected to scan line S2_i, is turned on, it resets the light-emitting devices connected to pixel circuit 10 in the (i-1)th pixel circuit row. Scan lines S1_i and S2_i are respectively connected to two adjacent shift registers of the same shift drive circuit. Furthermore, Figure 3 The diagram also illustrates the positive power line Pvdd and the data line Data. The positive power line Pvdd uses the same marking as the positive power signal Pvdd, and the data line Data uses the same marking as the data signal Data. The reset signal line Ref provides the reset signal Ref.

[0022] like Figure 3 As shown, the gate line X extends along the first direction a. The pixel circuit 10 includes a functional transistor TG, which includes a patterned conductive structure TGg. The gate of the functional transistor TG is located within the conductive structure TGg. The patterned conductive structure TGg is an isolated island structure within its film layer. For example, the conductive structures TGg included in the functional transistor TG, which have the same function in at least two adjacent pixel circuits, are not directly connected. The sheet resistance of the film layer containing the gate line X is less than the sheet resistance of the film layer containing the conductive structure TGg. Figure 4As shown, the gate line X and the functional transistor TG are located on one side of the substrate 00, and the conductive structure TGg is electrically connected to the gate line X through the via V. It can be understood that the transistor includes a gate and an active layer. The active layer includes a source region, a drain region, and a channel region. The channel region is connected between the source region and the drain region, wherein the gate and the channel region of the active layer overlap.

[0023] Figure 3 The schematic diagram shows a functional transistor TG comprising a data write transistor M1, a threshold compensation transistor M4, an electrode reset transistor M2, and a gate reset transistor M3. In other embodiments, the functional transistor TG may include only some of the transistors in the data write transistor M1, threshold compensation transistor M4, electrode reset transistor M2, and gate reset transistor M3, which are not illustrated in the diagram here.

[0024] In existing technologies, the gate line and the gate of the transistor connected to it are typically located on the same layer, with a portion of the gate line being reused as the gate of the transistor. That is, the material of the gate line and the transistor gate are the same. However, in this embodiment of the invention, the functional transistor TG includes a patterned conductive structure TGg. The gate of the functional transistor TG is located within the conductive structure TGg, which is electrically connected to the gate line X via a via. Furthermore, the sheet resistance of the film layer containing the gate line X is set to be less than the sheet resistance of the film layer containing the conductive structure TGg, thereby reducing the resistance of the gate line X and thus lowering the voltage drop across the signal transmitted through the gate line X. In this embodiment of the invention, the conductive structure TGg ensures the performance characteristics of the functional transistor TG while also reducing the voltage drop across the signal transmitted through the gate line X and improving display uniformity.

[0025] In some implementations, such as Figure 4 As shown, the display panel includes a first semiconductor layer 01, a gate metal layer 02, a capacitor metal layer 03, a first metal layer 04, and a second metal layer 05 located on one side of the substrate 00. The first semiconductor layer 01, gate metal layer 02, capacitor metal layer 03, first metal layer 04, and second metal layer 05 are sequentially disposed away from the substrate 00. The active layer of the functional transistor TG is located on the first semiconductor layer 01, the conductive structure TGg of the functional transistor TG is located on the gate metal layer 02, and the gate line X is located on the first metal layer 04. The active layer of the driving transistor Tm is located on the first semiconductor layer 01, the gate of the driving transistor Tm is located on the gate metal layer 02, and the gate of the driving transistor Tm is multiplexed as one plate of the storage capacitor Cst. The other plate of the storage capacitor Cst is located on the capacitor metal layer 03. The positive power line Pvdd is located on the second metal layer 05, and the plate of the storage capacitor Cst located on the capacitor metal layer 03 is connected to the positive power line Pvdd through a via.

[0026] In some embodiments, the gate metal layer 02 is made of molybdenum, the first metal layer 04 is made of aluminum and titanium, the pass line X is made of aluminum and titanium, and the conductive structure TGg is made of molybdenum. The first metal layer 04 is a stacked structure of titanium / aluminum / titanium metals. Optionally, the capacitor metal layer 03 is made of the same material as the gate metal layer 02, and the second metal layer 05 is made of the same material as the first metal layer 04.

[0027] In other implementations, Figure 5 This is a schematic diagram of another display panel provided in an embodiment of the present invention. Figure 5 The diagram illustrates some signal lines in the display panel and a pixel circuit 10 in the i-th pixel circuit row, where i is an integer greater than or equal to 2. The transistors in pixel circuit 10 and their interconnections can be found above. Figure 2 The examples are used for understanding. Figure 5 As shown, the gate of data writing transistor M1 is electrically connected to scan line Sp1_i; the gate of electrode reset transistor M2 is electrically connected to scan line Sp2_i; the gate of gate reset transistor M3 is electrically connected to scan line Sn1_i; the gate of threshold compensation transistor M4 is electrically connected to scan line Sn2_i; and the gates of the first light-emitting control transistor M5 and the second light-emitting control transistor M6 are electrically connected to the light-emitting control line Emit_i. Scan lines Sp1_i and Sp2_i are respectively connected to two adjacent shift registers in the same shift drive circuit, and scan lines Sn1_i and Sn2_i are respectively connected to two adjacent shift registers in the same shift drive circuit. Figure 5 The diagram also illustrates the positive power line Pvdd and the data line Data. The positive power line Pvdd and the positive power signal Pvdd are marked with the same symbol, and the data line Data and the data signal Data are marked with the same symbol.

[0028] like Figure 5 As shown, the gate line X extends along the first direction a, and the pixel circuit 10 includes a functional transistor TG. The functional transistor TG includes a conductive structure TGg, and the gate of the functional transistor TG is located in the conductive structure TGg. Figure 5 The schematic diagram shows that the functional transistor TG includes a gate reset transistor M3, a threshold compensation transistor M4, a data write transistor M1, and an electrode reset transistor M2. Figure 5 The small diagram on the right shows the conductive structure TGg of the data writing transistor M1. The sheet resistance of the film layer containing the gate line X is less than the sheet resistance of the film layer containing the conductive structure TGg. The conductive structure TGg is electrically connected to the gate line X through a via in the insulating layer.

[0029] In this embodiment of the invention, the functional transistor TG includes a conductive structure TGg. The conductive structure TGg is electrically connected to the gate line X through a via. Furthermore, the sheet resistance of the film layer containing the gate line X is set to be lower than the sheet resistance of the film layer containing the conductive structure TGg, which reduces the resistance of the gate line X and thus lowers the voltage drop of the signal transmitted through the gate line X. The conductive structure TGg ensures the characteristic performance of the functional transistor TG, while using a film layer with lower sheet resistance to fabricate the gate line X reduces the voltage drop of the signal transmitted through the gate line X and improves display uniformity.

[0030] In some implementations, combined Figure 3 and Figure 4 As can be seen, in the plane direction e perpendicular to the substrate 00, the gate of the functional transistor TG and the gate line X connected to it at least partially overlap. The gate of the functional transistor TG is the portion of the conductive structure TGg that overlaps with the active layer. This arrangement can save wiring space in the display panel.

[0031] like Figure 4 As shown, the conductive structure TGg is located in the gate metal layer 02, and the gate line X is located in the first metal layer 04. In the plane direction e perpendicular to the substrate 00, the thickness of the insulating layer separating the gate metal layer 02 and the first metal layer 04 is relatively small. In some embodiments, the gate line X is provided to cover the conductive structure TGg connected to it along the plane direction e perpendicular to the substrate 00. This arrangement avoids unevenness caused by ramping of the gate line X fabricated on the conductive structure TGg.

[0032] In other embodiments, the conductive structure TGg and the gate line X connected thereto are disposed along the plane direction e perpendicular to the substrate 00, and at least partially do not overlap. In other words, the conductive structure TGg and the gate line X connected thereto are misaligned, which can reduce the light transmittance of the display panel.

[0033] In some embodiments, the pixel circuit 10 includes a first transistor, the active layer of the first transistor is silicon, each transistor in the pixel circuit 10 is a first transistor, and the functional transistor TG includes at least one first transistor. Figure 3 In the embodiment, the illustrated functional transistor TG includes four first transistors: a data write transistor M1, a threshold compensation transistor M4, an electrode reset transistor M2, and a gate reset transistor M3. In other embodiments, the functional transistor TG includes one, two, or three of the data write transistor M1, threshold compensation transistor M4, electrode reset transistor M2, and gate reset transistor M3, which are not illustrated in the accompanying drawings.

[0034] In other implementations, Figure 6 This is another schematic diagram of a display panel provided in an embodiment of the present invention, such as... Figure 6As shown, the functional transistor TG also includes a first light-emitting control transistor M5 and a second light-emitting control transistor M6, and the gate line X includes a light-emitting control line. That is, both the first light-emitting control transistor M5 and the second light-emitting control transistor M6 include a conductive structure TGg, which is connected to the light-emitting control line Emit_i through a via.

[0035] In other embodiments, the pixel circuit 10 includes a first transistor and a second transistor, the active layer of the first transistor comprising silicon, the active layer of the second transistor comprising metal oxide, and the functional transistor comprising at least one first transistor and at least one second transistor. Figure 5 In this embodiment, threshold compensation transistor M4 and gate reset transistor M3 are second transistors, and the remaining transistors are first transistors. Figure 5 The illustrated embodiment shows that the functional transistor TG includes a data write transistor M1, a threshold compensation transistor M4, an electrode reset transistor M2, and a gate reset transistor M3, that is, the functional transistor TG includes two first transistors and two second transistors.

[0036] In some other embodiments, the functional transistor TG includes at least one of a data write transistor M1, a threshold compensation transistor M4, a gate reset transistor M3, and an electrode reset transistor M2, wherein the active layer of the data write transistor M1 and the electrode reset transistor M2 comprises silicon, and the active layer of the threshold compensation transistor M4 and the gate reset transistor M3 comprises metal oxide, which will not be illustrated in the figures here.

[0037] In some implementations... Figure 7 for Figure 5 A schematic diagram showing the film layer disassembly at the location of the middle pixel circuit. (This can be combined with...) Figure 7 right Figure 5 Understand the schematic pixel circuit. For example... Figure 7 As shown, the display panel includes a first semiconductor layer 01, a gate metal layer 02, a capacitor metal layer 03, a first metal layer 04, a second metal layer 05, a second semiconductor layer 06, and a second gate metal layer 07, all located on a substrate 00. The first semiconductor layer 01, gate metal layer 02, capacitor metal layer 03, second semiconductor layer 06, second gate metal layer 07, first metal layer 04, and second metal layer 05 are sequentially disposed away from the substrate 00. The gate reset transistor M3 and the threshold compensation transistor M4 are n-type transistors, while the remaining transistors are p-type transistors. The active layers of the gate reset transistor M3 and the threshold compensation transistor M4 are located on the second semiconductor layer 06, while the active layers of the remaining transistors are located on the first semiconductor layer 01.

[0038] Figure 5In this embodiment, the first transistor includes a data writing transistor M1, an electrode reset transistor M2, a first light-emitting control transistor M5, and a second light-emitting control transistor M6, and the second transistor includes a threshold compensation transistor M4 and a gate reset transistor M3. The functional transistor TG includes a data writing transistor M1, an electrode reset transistor M2, a threshold compensation transistor M4, and a gate reset transistor M3. Figure 5 The diagram illustrates the graphical conductive structure TGg of the data writing transistor M1. The gate line X includes a first gate line 1X and a second gate line 2X. The conductive structure of the first transistor is electrically connected to the first gate line 1X via a via; the conductive structure of the second transistor is electrically connected to the second gate line 2X via a via. The first gate line 1X and the second gate line 2X are located on the same layer. Figure 7 Both the first gate line 1X and the second gate line 2X are located in the first metal layer 04. In this embodiment of the invention, the functional transistor TG includes two types of transistors: a first transistor and a second transistor. The first gate line 1X is connected to the conductive structure of the first transistor, and the second gate line 2X is connected to the conductive structure of the second transistor. By setting the first gate line 1X and the second gate line 2X to extend in the same direction and be located in the same layer, they can be fabricated in the same process, which simplifies the process.

[0039] In some implementations, such as Figure 5 and Figure 7 As shown, the second transistor includes a threshold compensation transistor M4 and a gate reset transistor M3. The threshold compensation transistor M4 will be used as an example for explanation. Figure 8 for Figure 5 A schematic diagram of a cross-section at the location of the tangent line BB′. (See diagram below.) Figure 8 As shown, the conductive structure of the threshold compensation transistor M4 includes a first conductive structure 1TGg and a second conductive structure 2TGg; the first gate of the threshold compensation transistor M4 is located in the first conductive structure 1TGg, and the second gate of the threshold compensation transistor M4 is located in the second conductive structure 2TGg. The active layer of the threshold compensation transistor M4 (i.e., the second transistor) is located on the second semiconductor layer 06, along the direction e perpendicular to the plane of the substrate 00, with the first conductive structure 1TGg and the second conductive structure 2TGg located on opposite sides of the active layer of the threshold compensation transistor M4 (i.e., the second transistor). Figure 5 Looking at the second gate line 2X, it includes a first sub-gate line 2Xa and a second sub-gate line 2Xb. The first conductive structure 1TGg is electrically connected to the first sub-gate line 2Xa through a via O1, and the second conductive structure 2TGg is electrically connected to the second sub-gate line 2Xb through a via O2. Additionally, by... Figure 7It can also be seen that the conductive structure of the gate reset transistor M3 includes a first conductive structure 1TGg and a second conductive structure 2TGg. The first conductive structure 1TGg of the gate reset transistor M3 and the first conductive structure 1TGg of the threshold compensation transistor M4 are located on the same layer, and the second conductive structure 2TGg of the gate reset transistor M3 and the second conductive structure 2TGg of the threshold compensation transistor M4 are also located on the same layer. In this embodiment, the second transistor is set as a dual-gate transistor, which can improve the characteristic performance of the second transistor. Furthermore, two sub-gated lines are set for the first second transistor and connected to the two conductive structures respectively, which can further reduce the voltage drop of the signal transmitted on the second gated line 2X and improve the display uniformity.

[0040] In some implementations, such as Figure 5 As shown, the second transistor includes a threshold compensation transistor M4 and a gate reset transistor M3. The threshold compensation transistor M4 includes a first conductive structure 1TGg and a second conductive structure 2TGg, and the gate reset transistor M3 includes a first conductive structure 1TGg and a second conductive structure 2TGg. Specifically, for the first second transistor, the via between the first conductive structure 1TGg and the first sub-gated line 2Xa, and the via between the second conductive structure 2TGg and the second sub-gated line 2Xb, are located on the same side of the active layer of the second transistor. The active layer of the second transistor is located on the second semiconductor layer 06 (e.g., ...). Figure 7 (Illustration in the diagram). In this embodiment, the second transistor is configured as a dual-gate transistor, which improves its performance characteristics. Furthermore, by configuring the two vias connecting the two conductive structures of the second transistor to the gate line X to be located on the same side of the active layer, the width occupied by the second transistor in the first direction a is smaller, saving space and improving the compactness of the arrangement of structures in the pixel circuit.

[0041] In some implementations, combined Figure 7 and Figure 8 In this configuration, the first plate C1 of the storage capacitor Cst is located on the same layer as the gate of the driving transistor Tm, and the second plate C2 of the storage capacitor Cst is located on the side of the first plate C1 away from the substrate 00. For the threshold compensation transistor M4, the first conductive structure 1TGg of the threshold compensation transistor M4 is located on the side of the second plate C2 away from the substrate 00, and the second conductive structure 2TGg is located on the same layer as the second plate C2.

[0042] like Figure 5 As shown, the threshold compensation transistor M4 is the first sub-transistor in the second transistor. (The last part, "combined," appears to be a fragment and doesn't translate directly.) Figure 7Looking at the first conductive structure 1TGg and the second conductive structure 2TGg of the threshold compensation transistor M4: in the second direction b, the first conductive structure 1TGg is located between the second conductive structure 2TGg and the second plate C2 of the storage capacitor Cst. The second direction b intersects with the first direction a, and the second direction b is parallel to the plane where the substrate 00 is located. Combined with... Figure 7 The second conductive structure 2TGg of the threshold compensation transistor M4 and the second plate C2 of the storage capacitor Cst are both located in the capacitor metal layer 03. In the planar wiring diagram of the pixel circuit 10, the first conductive structure 1TGg is set between the second conductive structure 2TGg and the second plate C2 of the storage capacitor Cst. Then, the distance between the first conductive structure 1TGg and the second plate C2 in the second direction b can be relatively small, thereby saving the wiring space of the pixel circuit 10 in the second direction b.

[0043] In some implementations, combined Figure 5 , Figure 7 and Figure 8 The display panel also includes a cover portion 20, which is located on the side of the driving transistor Tm away from the substrate 00; in the direction e perpendicular to the plane of the substrate 00, the cover portion 20 overlaps with the active layer w of the driving transistor Tm. Figure 7 The diagram illustrates that the active layer w of the driving transistor Tm is located in the first semiconductor layer O1. A cover portion 20 overlaps and covers the active layer w of the driving transistor Tm. The cover portion 20 is made of a metal material and has a certain ability to block light. The cover portion 20 can block light from hitting the active layer w of the driving transistor Tm, thereby ensuring the stability of the driving transistor Tm's characteristics and ensuring the display effect. In the second direction b, the cover portion 20 is adjacent to the first sub-gated line 2Xa. The end of the cover portion 20 near the first sub-gated line 2Xa has a notch K, and the notch K partially surrounds the via O1 between the first conductive structure 1TGg and the first sub-gated line 2Xa. The notch K in the cover portion 20 ensures a safe distance between the cover portion 20 and the first sub-gated line 2Xa when the cover portion 20 and the gated line X are fabricated in the same layer.

[0044] In some implementations, combined Figure 5 and Figure 7 The display panel includes a data line Data for transmitting data signals, and a pixel circuit includes a data receiving terminal DD. A data writing transistor M1 is connected to the data receiving terminal DD. The data receiving terminal DD and the active layer of the first transistor are located on the same layer, that is, the data receiving terminal DD is located on the first semiconductor layer O1. The data receiving terminal DD and the data line Data are connected through a first via V1.

[0045] The second transistor includes a second sub-transistor, which includes a conductive structure TGg; the second gate line 2X includes a wire-wound gate line, which is electrically connected to the conductive structure TGg of the second sub-transistor. Figure 5 The diagram illustrates that gate reset transistor M3 is the second sub-transistor in the second transistor, and the first sub-gated line 2Xa in the second gated line 2X is a wire-wound gated line 2Xr, which is electrically connected to the first conductive structure 1TGg of gate reset transistor M3. Specifically, the wire-wound gated line 2Xr is partially wound around the first via V1 on one side.

[0046] Depend on Figure 7 As can be seen, the data receiver DD is located on the first semiconductor layer 01, and the data line Data is located on the second metal layer 05. Multiple conductive layers separate the data line Data from the data receiver DD. The insulating layer between the data line Data and the data receiver DD is relatively thick, resulting in a larger drilling depth for the first via V1. To ensure the connection performance between the data line Data and the data receiver DD, the area of ​​the first via V1 needs to meet certain requirements. A winding selector line 2Xr is set to wind around the first via V1. The shape of the winding selector line 2Xr is designed to adapt to the position of the first via V1, which is beneficial for the compactness of the wiring arrangement in the pixel circuit 10 and can save wiring space.

[0047] In some implementations... Figure 9 This is a schematic diagram of a pixel circuit in a display panel provided as an embodiment of the present invention. Figure 9 As shown, the pixel circuit 10 includes a bias transistor M7, which is used to adjust the bias state of the driving transistor Tm. The bias transistor M7 is connected to the second node N2. The gate of the bias transistor M7 receives the scan signal Sp3, the first terminal of the bias transistor M7 receives the bias signal Dvh, and the second terminal of the bias transistor M7 is connected to the second node N2. The bias transistor M7 is a p-type transistor. This can be combined with... Figure 2 right Figure 9 To understand the implementation examples, Figure 9 In this embodiment, the gate reset transistor M3 and the threshold compensation transistor M4 are n-type transistors, while the remaining transistors are p-type. The bias transistor M7 can adjust the bias state of the driving transistor Tm, improve the threshold drift problem of the driving transistor Tm, and enhance the display effect.

[0048] In some other embodiments, the bias transistor M7 is connected to the third node N3, which is not illustrated in the accompanying drawings.

[0049] In some implementations, the bias transistor M7 includes a conductive structure, i.e., the first transistor includes the bias transistor M7. Figure 10This is a schematic diagram of another display panel provided in an embodiment of the present invention. Figure 10 The diagram illustrates some signal lines in the display panel and a pixel circuit 10 in the i-th pixel circuit row. The transistors in the pixel circuit 10 and their interconnections can be found above. Figure 9 The examples are used for understanding. Figure 10 As shown, the display panel includes a scan line Sp3_i extending along a first direction a and a bias signal line Dvh (the bias signal line Dvh and the bias signal Dvh are referred to by the same reference numerals). The bias signal line Dvh provides a bias signal Dvh to the bias transistor M7. The bias transistor M7 includes a conductive structure TGg, which is electrically connected to the gate line X through a via. Combined with... Figure 8 The embodiment illustrates the film layer structure for understanding. The active layer of the bias transistor M7 is located in the first semiconductor layer 01, the conductive structure TGg of the bias transistor M7 is located in the gate metal layer 02, and the selection line X, electrically connected to the conductive structure TGg of the bias transistor M7, is located in the first metal layer 04. The sheet resistance of the first metal layer 04 is less than the sheet resistance of the gate metal layer 02. This embodiment includes a bias transistor M7, which can adjust the bias state of the driving transistor Tm, improving the threshold drift problem of the driving transistor Tm and enhancing the display effect. Simultaneously, the bias transistor M7 includes a conductive structure TGg, and the sheet resistance of the film layer containing the scan line Sp3_i is set to be less than the sheet resistance of the film layer containing the conductive structure TGg, reducing the resistance of the scan line Sp3_i and thus reducing the voltage drop of the transmitted signal. This embodiment ensures the characteristic performance of the bias transistor M7 while also reducing the voltage drop of the transmitted signal of the scan line Sp3_i and improving display uniformity.

[0050] In other embodiments, the gate of the bias transistor M7 and the gate of the electrode reset transistor M2 in the same pixel circuit 10 receive the same signal. Figure 11 This is another schematic diagram of a display panel provided in an embodiment of the present invention, such as... Figure 11 As shown, the functional transistor TG includes a bias transistor M7 and an electrode reset transistor M2; the gates of both the bias transistor M7 and the electrode reset transistor M2 receive the scan signal provided by the scan line Sp3, and the conductive structure of the bias transistor M7 ( Figure 11 (Not shown in the text) and the conductive structure of electrode reset transistor M2 ( Figure 11 (Not shown) are connected to the same gate line X. This configuration reduces the number of gate lines X that need to be placed in the display panel, thereby saving wiring space in the display panel.

[0051] In other implementations, Figure 12 This is a schematic diagram of another display panel provided in an embodiment of the present invention. Figure 12The diagram illustrates three pixel circuits 10 arranged in the first direction a within the i-th pixel circuit row. (Example...) Figure 12 As shown, the functional transistor TG includes a bias transistor M7 and an electrode reset transistor M2; the conductive structure TGg of the bias transistor M7 and the conductive structure TGg of the electrode reset transistor M2 are connected to the same gate line X. In a pixel circuit 10, the conductive structures TGg of the bias transistor M7 and the electrode reset transistor M2 are integrated. In other words, the bias transistor M7 and the electrode reset transistor M2 in a pixel circuit 10 share a single conductive structure TGg. Figure 12 It can be seen that the conductive structure TGg shared by the bias transistor M7 and the electrode reset transistor M2 in the adjacent pixel circuit 10 is isolated and discontinuous, and signals are provided to the conductive structure TGg in each pixel circuit 10 through the gating line X.

[0052] In some implementations, such as Figure 12 As shown, the conductive structure TGg shared by the bias transistor M7 and the electrode reset transistor M2 is electrically connected to the gate line X through a via. This arrangement reduces the number of holes in the display panel, thus saving wiring space.

[0053] In other embodiments, the display panel includes reset signal lines and auxiliary signal lines that intersect in their extending directions. The pixel circuit 10 is connected to the reset signal lines, and the auxiliary signal lines are electrically connected to the reset signal lines. The film layer containing the reset signal lines is located on the side of the film layer containing the auxiliary signal lines closer to the substrate 00, and the film layer containing the auxiliary signal lines is located on the side of the film layer containing the gate line X farther from the substrate 00. The display panel is provided with reset signal lines, which are used to provide reset signals to the pixel circuit 10. The auxiliary signal lines intersect and are electrically connected to the reset signal lines. Multiple reset signal lines and multiple auxiliary signal lines intersect in the display panel to form a grid-like trace, which can reduce the voltage drop of the transmitted reset signal and improve the uniformity of the in-plane reset signal, thereby improving the display uniformity. Furthermore, by setting the auxiliary signal line film layer to be located on the side of the gating line X film layer away from the substrate 00, the distance between the gating line X film layer and the substrate 00 is reduced, which in turn reduces the distance between the gating line X film layer and the conductive structure TGg film layer. This ensures that the drilling depth and area of ​​the via connecting the conductive structure TGg and the gating line X are not too large, which helps to ensure the yield of the via connection between the conductive structure TGg and the gating line X, and also reduces the area occupied by the via, thus avoiding affecting the wiring space in the display panel.

[0054] In this embodiment of the invention, both the reset signal line and the auxiliary signal line are made of metal film. Compared with semiconductor materials, metal materials have lower resistivity. Using metal materials to make the reset signal line and the auxiliary signal line can reduce the voltage drop of the reset signal, which is beneficial to improving the uniformity of the display.

[0055] In some implementations, the sheet resistance of the film layer containing the auxiliary signal line is less than that of the film layer containing the reset signal line. This configuration can significantly reduce the voltage drop of the transmitted reset signal, thereby improving display uniformity.

[0056] In some embodiments, the display panel is provided with a reset signal line and an auxiliary signal line, and the electrode reset transistor M2 and the gate reset transistor M3 in the pixel circuit 10 receive the same reset signal. Figure 13 This is a schematic diagram of another display panel provided in an embodiment of the present invention. Figure 13 The intermediate pixel circuit 10 can be combined with the above Figure 1 To understand the implementation examples, Figure 13 Not all transistors are shown in the diagram. Figure 13 The diagram illustrates two pixel circuits 10 in the i-th pixel circuit row and two pixel circuits 10 in the (i+1)-th pixel circuit row. The pixel circuits 10 in the i-th pixel circuit row are connected to scan lines S1_i, S2_i, and Emit_i (light emission control line), while the pixel circuits 10 in the (i+1)-th pixel circuit row are connected to scan lines S1_i+1, S2_i+1, and Emit_i+1 (light emission control line). Figure 13 As shown, the display panel includes a reset signal line Ref extending along a first direction a and an auxiliary signal line F extending along a second direction b, where the second direction b intersects the first direction a; the auxiliary signal line F is electrically connected to the reset signal line Ref. Figure 13 The diagram illustrates the via O3 connecting the two transistors. Both electrode reset transistor M2 and gate reset transistor M3 are connected to the reset signal line Ref. The film layer containing the reset signal line Ref is located on the side of the film layer containing the auxiliary signal line F closer to the substrate 00, while the film layer containing the auxiliary signal line F is located on the side of the film layer containing the gate line X farther from the substrate 00.

[0057] In combination with the above Figure 4From the illustrated display panel film structure in the embodiment, the display panel includes a first semiconductor layer 01, a gate metal layer 02, a capacitor metal layer 03, a first metal layer 04, and a second metal layer 05 located on one side of the substrate 00. Optionally, the gate metal layer 02 and the capacitor metal layer 03 are made of the same material, and the material of the gate metal layer 02 and the capacitor metal layer 03 includes molybdenum. The materials of the first metal layer 04 and the second metal layer 05 include titanium and aluminum. The sheet resistance of the gate metal layer 02 and the capacitor metal layer 03 is greater than the sheet resistance of the first metal layer 04 and the second metal layer 05. The first electrode of the storage capacitor Cst and the gate of the driving transistor Tm are located on the same layer, both located on the gate metal layer 02. The second electrode of the storage capacitor Cst is located on the side of the gate of the driving transistor Tm away from the substrate 00. Figure 13 In this embodiment, the reset signal line Ref and the second plate of the storage capacitor Cst are located on the same layer, and the second plate of the reset signal line Ref and the storage capacitor Cst are located on the capacitor metal layer 03. The auxiliary signal line F, the data line Data, and the positive power line are all located on the second metal layer 05.

[0058] In the display panel, multiple pixel circuits 10 are arranged in a pixel circuit column in the second direction b. Figure 13 The diagram illustrates two pixel circuit columns, with one auxiliary signal line F corresponding to each pixel circuit column. In other embodiments, one auxiliary signal line F is provided for every two or more pixel circuit columns, which are not illustrated in the diagram here.

[0059] In other embodiments, the display panel is provided with a reset signal line and an auxiliary signal line, and the electrode reset transistor M2 and the gate reset transistor M3 in the pixel circuit 10 receive different reset signals. Figure 14 This is a schematic diagram of another display panel provided in an embodiment of the present invention. Figure 14 The intermediate pixel circuit 10 can be combined with the above Figure 2 To understand the implementation examples, Figure 14 The diagram illustrates two pixel circuits 10 in the i-th pixel circuit row and two pixel circuits 10 in the (i+1)-th pixel circuit row. The pixel circuits 10 in the i-th pixel circuit row are connected to scan lines Sn1_i, Sn2_i, Sp1_i, Sp2_i and the emission control line Emit_i. The pixel circuits 10 in the (i+1)-th pixel circuit row are connected to scan lines Sn1_i+1, Sn2_i+1, Sp1_i+1, Sp2_i+1 and the emission control line Emit_i+1.

[0060] like Figure 14As shown, the reset signal line Ref includes a first reset signal line Ref1 and a second reset signal line Ref2. The gate reset transistor is connected to the first reset signal line Ref1, and the electrode reset transistor is connected to the second reset signal line Ref2. The auxiliary signal line F includes a first auxiliary signal line F1 and a second auxiliary signal line F2. The first auxiliary signal line F1 is electrically connected to the first reset signal line Ref1, and the second auxiliary signal line F2 is electrically connected to the second reset signal line Ref2.

[0061] In combination with the above Figure 8 From the schematic diagram of the display panel's film layer structure, the display panel includes a first semiconductor layer 01, a gate metal layer 02, a capacitor metal layer 03, a second semiconductor layer 06, a second gate metal layer 07, a first metal layer 04, and a second metal layer 05 located on one side of the substrate 00. Optionally, the gate metal layer 02, capacitor metal layer 03, and second gate metal layer 07 are made of molybdenum. The first metal layer 04 and second metal layer 05 are made of titanium and aluminum. The sheet resistance of the gate metal layer 02, capacitor metal layer 03, and second gate metal layer 07 is greater than the sheet resistance of the first metal layer 04 and second metal layer 05. Figure 14 In this embodiment, the first plate of the storage capacitor Cst and the gate of the driving transistor Tm are located on the same layer, both on the gate metal layer 02. The second plate of the storage capacitor Cst is located on the side of the gate of the driving transistor Tm away from the substrate 00, and is located on the capacitor metal layer 03. One of the first reset signal line Ref1 and the second reset signal line Ref2 is located on the same layer as the gate of the driving transistor Tm, and the other is located on the same layer as the second plate of the storage capacitor Cst. Figure 14 The diagram illustrates that the first reset signal line Ref1 is located on the gate metal layer 02, and the second reset signal line Ref2 is located on the capacitor metal layer 03. The first auxiliary signal line F1 and the second auxiliary signal line F2 are located on the second metal layer 05, and are on the same layer as the data line Data and the positive power supply line Pvdd.

[0062] Figure 14In this embodiment, a first reset signal line Ref1 and a second reset signal line Ref2 are provided. Electrode reset transistor M2 and gate reset transistor M3 receive different reset signals. The voltage of the first reset signal transmitted via the first reset signal line Ref1 is greater than the voltage of the second reset signal transmitted via the second reset signal line Ref2. Providing a higher reset voltage to the control terminal of the driving transistor Tm via the first reset signal line Ref1 enables faster threshold capture at the control terminal of the driving transistor Tm. This results in a shorter threshold capture time for high-frequency or low-brightness (or grayscale) displays. Faster threshold capture leads to more accurate threshold capture, thus reducing display unevenness. Simultaneously, providing a lower reset voltage to the electrode of the light-emitting device PD via the second reset signal line Ref2 reduces PD bleed-through and improves low grayscale display performance. The first reset signal line Ref1 and the second reset signal line Ref2 extend in the same direction and are located in different layers, avoiding the arrangement of multiple signal lines in one film layer and thus minimizing the overall space occupied by the pixel circuit 10. In addition, the embodiments of the present invention also include a first auxiliary signal line F1 and a second auxiliary signal line F2. The auxiliary signal line F can reduce the voltage drop of the transmitted reset signal, thereby reducing the power consumption of the display panel and improving the display uniformity.

[0063] In the display panel, multiple pixel circuits 10 are arranged in a pixel circuit column in the second direction b. Figure 14 The diagram illustrates two pixel circuit columns, with one first auxiliary signal line F1 and one second auxiliary signal line F2 corresponding to each pixel circuit column. This arrangement results in a larger number of first auxiliary signal lines F1 and second auxiliary signal lines F2 in the display panel, which can significantly reduce the voltage drop when transmitting the first reset signal and the second reset signal. This reduces the power consumption of the display panel while also improving display uniformity.

[0064] In other implementations, Figure 15 This is another schematic diagram of a display panel provided in an embodiment of the present invention, such as... Figure 15 As shown, multiple pixel circuits 10 are arranged in a pixel circuit column in the second direction b. Figure 15(Not shown in the image), one auxiliary signal line F is provided for each pixel circuit column, and the first auxiliary signal line F1 and the second auxiliary signal line F2 are alternately arranged along the first direction a. In this embodiment, the first auxiliary signal line F1 is arranged to cross and be electrically connected to the first reset signal line Ref1, and the second auxiliary signal line F2 is arranged to cross and be electrically connected to the second reset signal line Ref2. This can reduce the voltage drop when transmitting the first reset signal and the second reset signal, and improve the uniformity of the display. In addition, one auxiliary signal line F is provided for each pixel circuit column. The number of auxiliary signal lines F is relatively small, which allows the auxiliary signal line F, the positive power line Pvdd, and the data line Data to be located on the same layer, simplifying the manufacturing process and ensuring that different signal lines are isolated from each other.

[0065] In some implementations, such as Figure 5 As shown, the display panel includes a power line P extending along a second direction b, which intersects with a first direction a; the pixel circuit 10 is electrically connected to the power line P, and the power line P includes a positive power line Pvdd. Figure 7 The power line P is located on the side of the film layer furthest from the substrate 00, where the gate line X is located. Specifically, the power line P is located in the second metal layer 05, and the gate line X is located in the first metal layer 04. The pixel circuit 10 includes a second transistor, the active layer of which comprises metal oxide. The second transistor includes a threshold compensation transistor M4 and a gate reset transistor M3. Figure 5 As can be seen, the power line P covers the second transistor in the plane perpendicular to the substrate 00. The power line P has a certain ability to block light. By using the power line P to cover the threshold compensation transistor M4 and the gate reset transistor M3, the light is blocked from shining on the threshold compensation transistor M4 and the gate reset transistor M3, which can ensure the stability of the characteristics of the threshold compensation transistor M4 and the gate reset transistor M3, thereby ensuring the stability of the gate potential of the driving transistor Tm.

[0066] In some implementations, combined Figure 5 , Figure 7 and Figure 8 The display panel also includes a cover portion 20, which is located on the side of the driving transistor Tm away from the substrate 00; in the plane direction e perpendicular to the substrate 00, the cover portion 20 overlaps with the active layer w of the driving transistor Tm. Figure 7 The diagram illustrates that the active layer w of the driving transistor Tm is located in the first semiconductor layer 01, and is composed of... Figure 7It can be seen that the cover portion 20 and the gate line X are located on the same layer. In this embodiment, the cover portion 20 overlaps and covers the active layer w of the driving transistor Tm. The cover portion 20 is made of metal, which has a certain ability to block light. The cover portion 20 can block light from hitting the active layer w of the driving transistor Tm, thereby ensuring the stability of the characteristics of the driving transistor Tm and ensuring the display effect. In addition, setting the cover portion 20 and the gate line X to be on the same layer and fabricated in the same process allows for reasonable utilization of the film layer where the gate line X is located, and also simplifies the process.

[0067] In some implementations, combined Figure 7 and Figure 8 The cover portion 20 and the gate line X are located in the first metal layer 04, the power line P is located in the second metal layer 05, and the first electrode C1 of the storage capacitor Cst is located in the gate metal layer 02, and the second electrode C2 is located in the capacitor metal layer 03. In the plane e perpendicular to the substrate 00, the film layer containing the cover portion 20 is located between the film layer containing the power line P and the film layer containing the second electrode C2 of the storage capacitor Cst. The cover portion 20 is coupled to the power line P. Specifically, the power line P overlaps with the cover portion 20 and is electrically connected through the second via V2, and the cover portion 20 overlaps with the second electrode C2 of the storage capacitor Cst and is electrically connected through the third via V3. In this embodiment, setting the cover portion 20 and the gate line X to be on the same layer can simplify the process. By connecting the cover portion 20 between the power line P and the second plate C2 of the storage capacitor Cst, the drilling depth of the second via V2 and the third via V3 is shallow, which can improve the yield of via connection. At the same time, it can also avoid the large area size of the hole affecting the wiring space.

[0068] Furthermore, considering the above embodiment of setting the auxiliary signal line F, the auxiliary signal line F extending along the second direction b can be located in the same layer as the power line P. When the auxiliary signal line F and the power line P are located in the same layer, there are more traces arranged in the film layer where the power line P is located. The second electrode plate C2 of the storage capacitor Cst is connected to the power line P by means of the cover portion 20, which can also reduce the space occupied by the power line P in its film layer, thereby reserving space for setting the auxiliary signal line F.

[0069] In some implementations, combined Figure 5 and Figure 7The display panel includes a node connection line 30. One end of the threshold compensation transistor M4 and one end of the gate reset transistor M3 are both connected to the node connection line 30. The node connection line 30 is connected to the gate Tmg of the driving transistor Tm. The node connection line 30 connects the threshold compensation transistor M4 and the gate reset transistor M3 to the gate Tmg of the driving transistor Tm, thereby providing a voltage signal to the gate Tmg of the driving transistor Tm. One end of the threshold compensation transistor M4 and one end of the gate reset transistor M3 are both led out from the film layer containing the active layer of the transistor. Figure 5 In this embodiment, the active layers of the threshold compensation transistor M4 and the gate reset transistor M3 are both located on the second semiconductor layer 06. The node connection line 30 is connected to the second semiconductor layer 06 through vias in the insulating layer. In this embodiment, the node connection line 30 intersects with at least one gate line X insulated manner. The gate line X intersecting with the node connection line 30 is located on the first metal layer 04, meaning that the gate line X and the gate Tmg of the driving transistor Tm are located on different layers, while the node connection line 30 and the gate Tmg of the driving transistor Tm are located on the same layer. This allows the node connection line 30 to be directly connected to the gate Tmg of the driving transistor Tm, thus eliminating the need for an opening in the second electrode C2 on the side of the gate Tmg of the driving transistor Tm away from the substrate 00.

[0070] In existing technology, the node connection line and the gate of the driving transistor are located on different layers. The film layer containing the node connection line is located on the side of the film layer containing the second electrode of the storage capacitor away from the gate of the driving transistor. The node connection line needs to pass through an opening in the second electrode of the storage capacitor to connect to the gate of the driving transistor. After making an opening in the second electrode of the storage capacitor, the overlap area between the second electrode and the first electrode (the gate of the driving transistor is reused as the first electrode) becomes smaller. However, in order to ensure that the capacitance value of the storage capacitor meets the requirements, it may be necessary to increase the area size of the second electrode with the opening. This results in the storage capacitor occupying a larger area space, affecting the wiring space of the display panel.

[0071] In this embodiment of the invention, a gate line X is provided. The conductive structure TGg is electrically connected to the gate line X through a via. The sheet resistance of the film layer where the gate line X is located is less than the sheet resistance of the film layer where the conductive structure TGg is located, which can reduce the resistance of the gate line X, thereby reducing the voltage drop of the signal transmitted by the gate line X. Since the gate line X and the gate of the driving transistor Tm are located on different layers, the node connection line 30 overlapping with the gate line X can be set to be on the same layer as the gate Tmg of the driving transistor Tm. The second electrode plate C2 on the side of the gate Tmg of the driving transistor Tm away from the substrate 00 does not need to be opened. When the capacitance value of the storage capacitor Cst meets the requirements, it is beneficial to reduce the area space occupied by the storage capacitor Cst, thereby saving the wiring space of the display panel.

[0072] In addition, by Figure 3 As can also be seen from the embodiment, node connection line 30 is insulated from a gate line X and crosses it. Node connection line 30 is on the same layer as the gate Tmg of the driving transistor Tm and is directly connected.

[0073] In some implementations, combined Figure 5 and Figure 7 As can be seen, the active layer M4w of the threshold compensation transistor M4 is located on one side of the node connection line 30 in the first direction a; the conductive structure TGg of the threshold compensation transistor M4 is electrically connected to the gate line X through the third via V3. Figure 5 In the embodiment, the conductive structure TGg of the threshold compensation transistor M4 includes a first gate 1TGg and a second gate 2TGg. The first gate 1TGg is electrically connected to the first sub-gated line 2Xa through via O1, and the second gate 2TGg is electrically connected to the second sub-gated line 2Xb through via O2. That is, the fourth via V4 includes via O1 and via O2. Figure 5 It can be seen that the active layer of the threshold compensation transistor M4 and the fourth via V4 are located on both sides of the node connection line 30. This arrangement makes the node connection line 30 shorter, with lower resistance and voltage drop.

[0074] In other implementations, Figure 16 This is a schematic diagram of another display panel provided in an embodiment of the present invention. Figure 16 The diagram illustrates a pixel circuit 10 in the i-th pixel circuit row. For example... Figure 16 As shown, the threshold compensation transistor M4 is located on one side of the node connection line 30 in the first direction a, and therefore the active layer of the threshold compensation transistor M4 is also located on one side of the node connection line 30 in the first direction a; the conductive structure TGg of the threshold compensation transistor M4 (see reference) Figure 7 (As illustrated in the diagram) It is electrically connected to the gate line X through the fourth via V4. The conductive structure TGg of the threshold compensation transistor M4 and the fourth via V4 are located on the same side of the node connection line 30. This arrangement ensures that the node connection line 30 and the conductive structure TGg do not overlap, avoiding a large coupling capacitance on the node connection line 30 that could affect the gate potential stability of the driving transistor Tm.

[0075] In some implementations, the display panel is also provided with repair lines and pixel repair circuits, the repair lines being used to repair defects in pixels within the display area. Figure 17 This is a simplified schematic diagram of another display panel provided in an embodiment of the present invention, as shown below. Figure 17 As shown, the display panel includes a repair line 40, which is connected to a repair pixel circuit 50 located in the non-display area NA. The repair pixel circuit 50 has the same structure as the pixel circuit 10 in the display area AA. Figure 17The diagram illustrates that a pixel repair circuit 50 is set up for each row of pixel circuits arranged in the first direction a. When a pixel circuit 10 has a defect, it is connected to the corresponding light-emitting device through a repair line 40, so that the light-emitting device can be driven by the repair pixel circuit 50. The repair pixel circuit 50 replaces the defective pixel circuit 10 to drive the light-emitting device to emit light normally.

[0076] Figure 18 This is a schematic diagram of another display panel provided in an embodiment of the present invention. Figure 19 for Figure 18 A schematic diagram of a cross-section at the position of the tangent CC′. Figure 18 The embodiment illustrates the repair line 40 in the display panel. Figure 18 The pixel circuit 10 shown in the diagram can be combined with the above. Figure 9 and Figure 10 The examples are explained below. Figure 18 The schematic pixel circuit 10 includes a first transistor and a second transistor. The active layer of the first transistor is silicon, and the active layer of the second transistor is metal oxide. The first transistor includes a driving transistor Tm, a data writing transistor M1, an electrode reset transistor M2, a bias adjustment transistor M7, a first light-emitting control transistor M5, and a second light-emitting control transistor M6. The second transistor includes a gate reset transistor M3 and a threshold compensation transistor M4.

[0077] like Figure 18 As shown, the display panel is equipped with a connecting electrode 60 and a light-emitting device ( Figure 18 (Not shown) is coupled to the pixel circuit 10 via a connecting electrode 60. The display panel also includes a repair line 40 extending along the first direction a. Figure 19 As can be seen, in the direction e perpendicular to the plane where the substrate 00 is located, the repair line 40 overlaps with the connecting electrode 60.

[0078] Figure 19 The diagram illustrates the film structure of the display panel, which includes a first semiconductor layer 01, a gate metal layer 02, a capacitor metal layer 03, a first metal layer 04, a second metal layer 05, a second semiconductor layer 06, and a second gate metal layer 07 located on a substrate 00.

[0079] Figure 19The diagram illustrates the threshold compensation transistor M4 in the second transistor. The threshold compensation transistor M4 includes a first conductive structure 1TGg and a second conductive structure 2TGg. The first conductive structure 1TGg is located on the side of the active layer of the threshold compensation transistor M4 away from the substrate 00. The film layer containing the gate line X is also located on the side of the active layer of the threshold compensation transistor M4 away from the substrate 00. Specifically, the active layer of the threshold compensation transistor M4 is located in the second semiconductor layer 06, the first conductive structure 1TGg is located in the second gate metal layer 07, the second conductive structure 2TGg is located in the capacitor metal layer 03, the gate line X is located in the first metal layer 04, the repair line 40 is located in the same layer as the first conductive structure 1TGg (i.e., the repair line 40 is in the same layer as the first gate of the second transistor), and the connecting electrode 60 is in the same layer as the gate line X. When repairing defective pixels in the display panel, a laser is used to fuse the overlap between the repair line 40 and the connecting electrode 60, electrically connecting the repair line 40 and the connecting electrode 60. This allows the pixel repair circuit 50 to drive the light-emitting device connected to the connecting electrode 60. In this embodiment of the invention, the repair line 40 is disposed in the second gate metal layer 07, and the connecting electrode 60 is disposed in the first metal layer 04. The repair line 40 and the connecting electrode 60 are close together in the direction perpendicular to the plane of the substrate 00, and the film thickness between them is small. This makes it easier to achieve a connection between the repair line 40 and the connecting electrode 60 during laser welding, thereby increasing the repair success rate.

[0080] In other implementations, Figure 20 This is another schematic diagram of a display panel provided in an embodiment of the present invention, such as... Figure 20 As shown, the display panel also includes auxiliary repair lines 70. Figure 20 This is a top view of the display panel. The top view direction of the display panel is parallel to the direction perpendicular to the plane containing the substrate 00. Figure 20 It can be seen that, in the direction perpendicular to the plane where the substrate 00 is located, the auxiliary repair line 70 overlaps with the connecting electrode 60. Figure 18 In the embodiment, the storage capacitor Cst ( Figure 18 The two electrode layers (not marked in the text) are located in the membrane layer mentioned above. Figure 5 and Figure 7The same applies to the embodiments. Specifically, the first electrode of the storage capacitor Cst is located on the same layer as the gate of the driving transistor Tm, and the second electrode of the storage capacitor Cst is located on the side of the gate of the driving transistor Tm away from the substrate 00. The first electrode of the storage capacitor Cst is located on the gate metal layer 02, and the second electrode of the storage capacitor Cst is located on the capacitor metal layer 03. Optionally, the auxiliary repair line 70 is located on the same layer as the second electrode of the storage capacitor Cst. The auxiliary repair line 70 is electrically connected to the repair pixel circuit in the non-display area, enabling the repair of defective pixels in the display area. In this embodiment, the inclusion of the repair line 40 and the auxiliary repair line 70 increases the repair probability. Furthermore, the parallel connection of the repair line 40 and the auxiliary repair line 70 reduces resistance, thereby reducing voltage drop and improving the brightness accuracy of driving the light-emitting device using the repair pixel circuit.

[0081] In some implementations, such as Figure 20 As shown, along a direction perpendicular to the plane of substrate 00, the repair line 40 and the auxiliary repair line 70 at least partially overlap. The repair line 40 and the auxiliary repair line 70 are located in different film layers. This partial overlap saves wiring space in the display panel. Furthermore, they can be connected at appropriate locations via vias in the insulating layer, thereby reducing voltage drop on the repair line and improving the brightness accuracy of driving the light-emitting device using the repair pixel circuit.

[0082] Based on the same inventive concept, embodiments of the present invention also provide a display device. Figure 21 This is a schematic diagram of a display device provided in an embodiment of the present invention, such as... Figure 21 As shown, the display device includes the display panel 100 provided in any embodiment of the present invention. The structure of the display panel 100 has been described in the above embodiments and will not be repeated here. The display device may be, for example, a mobile phone, tablet, laptop, television, or smart wearable product, etc.

[0083] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

[0084] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized in that, The display panel includes a substrate, a gate line located on one side of the substrate, and pixels. Each pixel includes a pixel circuit. The gate line extends along a first direction. The pixel circuit includes a functional transistor, which includes a patterned conductive structure, and the gate of the functional transistor is located within the conductive structure. The conductive structure is electrically connected to the gate line through a via, and the sheet resistance of the film layer where the gate line is located is less than the sheet resistance of the film layer where the conductive structure is located. The pixel circuit includes a first transistor and a second transistor. The active layer of the first transistor comprises silicon, and the functional transistor includes at least one of the first transistors. The active layer of the second transistor comprises metal oxide, and the functional transistor includes at least one of the second transistors. The gate line includes a first gate line, and the conductive structure of the first transistor is electrically connected to the first gate line through a via; the gate line also includes a second gate line, and the conductive structure of the second transistor is electrically connected to the second gate line through a via. The first gate line and the second gate line are located on the same layer.

2. The display panel according to claim 1, characterized in that, In a plane perpendicular to the substrate, the gate of the functional transistor at least partially overlaps with the gate line.

3. The display panel according to claim 1, characterized in that, The materials of the gate line include aluminum and titanium, and the materials of the conductive structure include molybdenum.

4. The display panel according to claim 1, characterized in that, The conductive structure of the second transistor includes a first conductive structure and a second conductive structure; the first gate of the second transistor is located in the first conductive structure, and the second gate of the second transistor is located in the second conductive structure; Along a plane perpendicular to the substrate, the first conductive structure and the second conductive structure are located on opposite sides of the active layer of the second transistor. The second gate line includes a first sub-gate line and a second sub-gate line. The first conductive structure is electrically connected to the first sub-gate line through a via, and the second conductive structure is electrically connected to the second sub-gate line through a via.

5. The display panel according to claim 4, characterized in that, The via between the first conductive structure and the first sub-gated line, and the via between the second conductive structure and the second sub-gated line, are located on the same side of the active layer of the second transistor.

6. The display panel according to claim 4, characterized in that, The pixel circuit includes a driving transistor and a storage capacitor. The first plate of the storage capacitor is located on the same layer as the gate of the driving transistor, and the second plate of the storage capacitor is located on the side of the first plate away from the substrate. The first conductive structure is located on the side of the second plate away from the substrate, and the second conductive structure is located on the same layer as the second plate. The second transistor includes a first sub-transistor; Regarding the first conductive structure and the second conductive structure of the first sub-transistor: in the second direction, the first conductive structure is located between the second conductive structure and the second electrode, the second direction intersects the first direction, and the second direction is parallel to the plane of the substrate.

7. The display panel according to claim 6, characterized in that, The display panel further includes a cover portion located on the side of the driving transistor away from the substrate; in a direction perpendicular to the plane of the substrate, the cover portion overlaps with the active layer of the driving transistor; In the second direction, the cover portion is adjacent to the first sub-gated line; the end of the cover portion near the first sub-gated line has a notch, the notch portion surrounding the via between the first conductive structure and the first sub-gated line.

8. The display panel according to claim 1, characterized in that, The display panel includes a data line that transmits data signals; the pixel circuit includes a data receiving end that is located on the same layer as the active layer of the first transistor; the data receiving end is connected to the data line through a first via. The second transistor includes a second sub-transistor, the second sub-transistor including the conductive structure; the second gate line includes a wire-wound gate line, the wire-wound gate line being electrically connected to the conductive structure of the second sub-transistor; The winding selection line is arranged to partially surround the first through hole on one side of the first through hole.

9. The display panel according to claim 1, characterized in that, The pixel circuit includes a driving transistor, a data writing transistor, a gate reset transistor, a threshold compensation transistor, a first light-emitting control transistor, and a second light-emitting control transistor. The driving transistor is connected in series between the first light-emitting control transistor and the second light-emitting control transistor. The gate of the driving transistor is connected to a first node, the first electrode of the driving transistor is connected to a second node, and the second electrode of the driving transistor is connected to a third node. The gate reset transistor is connected to the first node. The data writing transistor and the first light-emitting control transistor are connected to the second node. The threshold compensation transistor is connected in series between the first node and the third node. The first electrode of the second light-emitting control transistor is connected to the third node, and the second electrode of the second light-emitting control transistor is connected to a fourth node. The first transistor includes the data write transistor; The second transistor includes the gate reset transistor and the threshold compensation transistor.

10. The display panel according to claim 9, characterized in that, The pixel circuit also includes an electrode reset transistor connected to the fourth node; The first transistor includes the electrode reset transistor.

11. The display panel according to claim 9, characterized in that, The pixel circuit further includes a bias transistor, which is connected to the second node or the third node; The first transistor includes the bias transistor.

12. The display panel according to claim 9, characterized in that, The pixel circuit also includes an electrode reset transistor connected to the fourth node; The pixel circuit further includes a bias transistor, which is connected to the second node or the third node; The functional transistor includes the bias transistor and the electrode reset transistor; In one of the pixel circuits, the conductive structure of the bias transistor and the conductive structure of the electrode reset transistor are integrated into one unit.

13. The display panel according to claim 9, characterized in that, The pixel circuit also includes an electrode reset transistor connected to the fourth node; The pixel circuit further includes a bias transistor, which is connected to the second node or the third node; The functional transistor includes the bias transistor and the electrode reset transistor; In one of the pixel circuits: the conductive structure of the bias transistor and the conductive structure of the electrode reset transistor are connected to the same first gate line.

14. The display panel according to claim 1, characterized in that, The display panel further includes a reset signal line extending along the first direction and an auxiliary signal line extending along the second direction, the second direction intersecting the first direction; the pixel circuit is connected to the reset signal line, and the auxiliary signal line is electrically connected to the reset signal line at an intersection. The film layer containing the reset signal line is at least partially located on the side of the film layer containing the auxiliary signal line that is closer to the substrate, and the film layer containing the auxiliary signal line is located on the side of the film layer containing the gate line that is farther away from the substrate.

15. The display panel according to claim 14, characterized in that, The pixel circuit includes a gate reset transistor and an electrode reset transistor, both of which are connected to the reset signal line. The pixel circuit also includes a storage capacitor, wherein the first plate of the storage capacitor is located on the same layer as the gate of the driving transistor, and the second plate of the storage capacitor is located on the side of the gate of the driving transistor away from the substrate. The reset signal line and the second plate of the storage capacitor are located on the same layer.

16. The display panel according to claim 14, characterized in that, The pixel circuit includes a driving transistor, a gate reset transistor, and an electrode reset transistor. The reset signal line includes a first reset signal line and a second reset signal line. The gate reset transistor is connected to the first reset signal line, and the electrode reset transistor is connected to the second reset signal line. The auxiliary signal line includes a first auxiliary signal line, which is electrically connected to the first reset signal line; and / or, the auxiliary signal line includes a second auxiliary signal line, which is electrically connected to the second reset signal line. The pixel circuit also includes a storage capacitor, wherein the first plate of the storage capacitor is located on the same layer as the gate of the driving transistor, and the second plate of the storage capacitor is located on the side of the gate of the driving transistor away from the substrate. One of the first reset signal line and the second reset signal line is located on the same layer as the gate of the driving transistor, and the other is located on the same layer as the second electrode plate.

17. The display panel according to claim 16, characterized in that, The plurality of pixel circuits are arranged in a pixel circuit column in the second direction, and one pixel circuit column is provided with one first auxiliary signal line and one second auxiliary signal line.

18. The display panel according to claim 16, characterized in that, The plurality of pixel circuits are arranged in a pixel circuit column in the second direction, and one auxiliary signal line is provided for each pixel circuit column, and the first auxiliary signal line and the second auxiliary signal line are alternately arranged along the first direction.

19. The display panel according to claim 14, characterized in that, The pixel circuit further includes a data line and a power line extending along the second direction, and the pixel circuit is connected to the data line and the power line; The auxiliary signal line, the data line, and the power line are located on the same metal layer.

20. The display panel according to claim 1, characterized in that, The display panel further includes a power line extending along a second direction, which intersects the first direction; the pixel circuit is electrically connected to the power line, and the film layer where the power line is located is located on the side of the film layer where the gate line is located away from the substrate; The power line covers the second transistor in a direction perpendicular to the plane of the substrate.

21. The display panel according to claim 20, characterized in that, The pixel circuit includes a driving transistor; The display panel further includes a cover portion located on the side of the driving transistor away from the substrate; in a direction perpendicular to the plane of the substrate, the cover portion overlaps with the active layer of the driving transistor; The covering portion and the gate line are located on the same layer.

22. The display panel according to claim 21, characterized in that, The pixel circuit includes a driving transistor and a storage capacitor. The first plate of the storage capacitor is located on the same layer as the gate of the driving transistor, and the second plate of the storage capacitor is located on the side of the gate of the driving transistor away from the substrate. The membrane layer containing the covering portion is located between the membrane layer containing the second electrode plate and the membrane layer containing the power line; The power line overlaps with the cover portion, and the two are electrically connected through a second through-hole. The cover overlaps with the second electrode plate, and the two are electrically connected through a third via.

23. The display panel according to claim 1, characterized in that, The pixel circuit includes a driving transistor; The display panel includes node connection lines that are connected to the gate of the driving transistor; The node connection line is located on the same layer as the gate of the driving transistor.

24. The display panel according to claim 23, characterized in that, The node connection line and at least one of the gate lines are insulated from each other.

25. The display panel according to claim 23, characterized in that, The pixel circuit includes a threshold compensation transistor, the active layer of which is located on one side of the node connection line in the first direction. The functional transistor includes the threshold compensation transistor, and the conductive structure of the threshold compensation transistor is electrically connected to the gate line through a fourth via. The active layer of the threshold compensation transistor and the fourth via are located on both sides of the node connection line, respectively.

26. The display panel according to claim 23, characterized in that, The pixel circuit includes a threshold compensation transistor, the active layer of which is located on one side of the node connection line in the first direction. The functional transistor includes the threshold compensation transistor, and the conductive structure of the threshold compensation transistor is electrically connected to the gate line through a fourth via. The conductive structure of the threshold compensation transistor and the fourth via are located on the same side of the node connection line.

27. The display panel according to claim 1, characterized in that, The pixel includes a light-emitting device, which is coupled to the pixel circuit via a connecting electrode; The display panel further includes a repair line extending along the first direction, the repair line being used to repair defects in the pixel; in a direction perpendicular to the plane of the substrate, the repair line overlaps with the connecting electrode; The pixel circuit includes a second transistor, the active layer of the second transistor comprising a metal oxide, and the second transistor including a first gate; the first gate is located on the side of the active layer of the second transistor away from the substrate, and the film layer containing the gate line is located on the side of the active layer of the second transistor away from the substrate; The repair line is located on the same layer as the first gate, and the connection electrode is located on the same layer as the gate line.

28. The display panel according to claim 27, characterized in that, The display panel also includes auxiliary repair lines, which overlap with the connecting electrodes in a direction perpendicular to the plane of the substrate. The pixel circuit includes a driving transistor and a storage capacitor. The first plate of the storage capacitor is located on the same layer as the gate of the driving transistor, and the second plate of the storage capacitor is located on the side of the gate of the driving transistor away from the substrate. The auxiliary repair line is located in the same layer as the second electrode.

29. The display panel according to claim 28, characterized in that, Along a direction perpendicular to the plane containing the substrate, the repair line and the auxiliary repair line at least partially overlap.

30. A display panel, characterized in that, The display panel includes a substrate, a gate line located on one side of the substrate, and pixels. Each pixel includes a pixel circuit. The gate line extends along a first direction. The pixel circuit includes a functional transistor, which includes a patterned conductive structure, and the gate of the functional transistor is located within the conductive structure. The conductive structure is electrically connected to the gate line through a via, and the sheet resistance of the film layer where the gate line is located is less than the sheet resistance of the film layer where the conductive structure is located. The pixel circuit includes a second transistor, the active layer of the second transistor comprising a metal oxide, and the functional transistor includes at least one of the second transistors. The gate line includes a second gate line, and the conductive structure of the second transistor is electrically connected to the second gate line through a via; The conductive structure of the second transistor includes a first conductive structure and a second conductive structure; the first gate of the second transistor is located in the first conductive structure, and the second gate of the second transistor is located in the second conductive structure; Along a plane perpendicular to the substrate, the first conductive structure and the second conductive structure are located on opposite sides of the active layer of the second transistor. The second gate line includes a first sub-gate line and a second sub-gate line. The first conductive structure is electrically connected to the first sub-gate line through a via, and the second conductive structure is electrically connected to the second sub-gate line through a via.

31. The display panel according to claim 30, characterized in that, The via between the first conductive structure and the first sub-gated line, and the via between the second conductive structure and the second sub-gated line, are located on the same side of the active layer of the second transistor.

32. The display panel according to claim 30, characterized in that, The pixel circuit includes a driving transistor and a storage capacitor. The first plate of the storage capacitor is located on the same layer as the gate of the driving transistor, and the second plate of the storage capacitor is located on the side of the first plate away from the substrate. The first conductive structure is located on the side of the second plate away from the substrate, and the second conductive structure is located on the same layer as the second plate. The second transistor includes a first sub-transistor; Regarding the first conductive structure and the second conductive structure of the first sub-transistor: in the second direction, the first conductive structure is located between the second conductive structure and the second electrode, the second direction intersects the first direction, and the second direction is parallel to the plane of the substrate.

33. The display panel according to claim 32, characterized in that, The display panel further includes a cover portion located on the side of the driving transistor away from the substrate; in a direction perpendicular to the plane of the substrate, the cover portion overlaps with the active layer of the driving transistor; In the second direction, the cover portion is adjacent to the first sub-gated line; the end of the cover portion near the first sub-gated line has a notch, the notch portion surrounding the via between the first conductive structure and the first sub-gated line.

34. The display panel according to claim 30, characterized in that, In the plan view, the first sub-gated line and the second sub-gated line are arranged side by side along the second direction, and the second direction intersects the first direction.

35. The display panel according to claim 30, characterized in that, In the plan view, the gate of the functional transistor at least partially overlaps with the gate line.

36. The display panel according to claim 30, characterized in that, The materials of the gate line include aluminum and titanium, and the materials of the conductive structure include molybdenum.

37. The display panel according to claim 30, characterized in that, The pixel circuit includes a driving transistor, a data writing transistor, a gate reset transistor, a threshold compensation transistor, a first light-emitting control transistor, and a second light-emitting control transistor. The driving transistor is connected in series between the first light-emitting control transistor and the second light-emitting control transistor. The gate of the driving transistor is connected to a first node, the first electrode of the driving transistor is connected to a second node, and the second electrode of the driving transistor is connected to a third node. The gate reset transistor is connected to the first node. The data writing transistor and the first light-emitting control transistor are connected to the second node. The threshold compensation transistor is connected in series between the first node and the third node. The first electrode of the second light-emitting control transistor is connected to the third node, and the second electrode of the second light-emitting control transistor is connected to a fourth node. The second transistor includes the gate reset transistor and the threshold compensation transistor.

38. The display panel according to claim 30, characterized in that, The pixel circuit includes a driving transistor; The display panel includes node connection lines that are connected to the gate of the driving transistor; The node connection line is located on the same layer as the gate of the driving transistor.

39. The display panel according to claim 30, characterized in that, The node connection line and at least one of the gate lines are insulated from each other.

40. The display panel according to claim 39, characterized in that, The pixel circuit includes a threshold compensation transistor, the active layer of which is located on one side of the node connection line in the first direction. The functional transistor includes the threshold compensation transistor, and the conductive structure of the threshold compensation transistor is electrically connected to the gate line through a fourth via. The active layer of the threshold compensation transistor and the fourth via are located on both sides of the node connection line, respectively.

41. The display panel according to claim 39, characterized in that, The pixel circuit includes a threshold compensation transistor, the active layer of which is located on one side of the node connection line in the first direction. The functional transistor includes the threshold compensation transistor, and the conductive structure of the threshold compensation transistor is electrically connected to the gate line through a fourth via. The conductive structure of the threshold compensation transistor and the fourth via are located on the same side of the node connection line.

42. The display panel according to claim 30, characterized in that, The pixel includes a light-emitting device, which is coupled to the pixel circuit via a connecting electrode; The display panel further includes a repair line extending along the first direction, the repair line being used to repair defects in the pixel; in a direction perpendicular to the plane of the substrate, the repair line overlaps with the connecting electrode; The first gate of the second transistor is located on the side of the active layer of the second transistor away from the substrate, and the film layer in which the gate line is located is located on the side of the active layer of the second transistor away from the substrate; The repair line is located on the same layer as the first gate, and the connection electrode is located on the same layer as the gate line.

43. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 42.

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