Watch clock management for improving security of low-power processing systems

Abstract

A processing system includes a peripheral device configured to store security information and having a clock input to receive a gated clock; a watch clock generator configured to generate a watch clock having a reduced duty cycle relative to the system clock; and clock control circuitry configured to select the system clock as a gated clock during normal operation of the peripheral device and select the watch clock as a gated clock during a low power mode of the peripheral device. The watch clock generator may include a counter that counts system clock cycles and a clock pulse selector, such as a mode circuit, configured to select the cycles of the system clock to generate a watch clock. For multiple peripherals, the delay circuitry may skew a watch clock between two or more peripherals. A plurality of watch clocks having different delayed duty cycles may be generated, each for a corresponding group of a plurality of groups of peripherals.

Description

Technical Field

[0001] This disclosure generally relates to secure processing systems, and more specifically, to watch clock management for preventing attacks on blocks containing security information in low-power processing systems. Background Technology

[0002] Modern security systems require both security and low power consumption, such as the Secure Element (SE) used in watch applications. Conventional systems typically only stop the clock signal supplied to unused or suspended peripherals to reduce power consumption. However, unused peripherals often store secure information. The security challenge is that these unclock-managed peripherals may contain sensitive security information vulnerable to attack during low-power mode, such as one or more security keys, security tokens, passwords, authorization or authentication information, etc. Each peripheral containing secure information can be protected from bit-flip attacks using a corresponding Error Detection Code (EDC). EDC errors are typically latched in triggers or latches that initiate error responses. However, when one or more peripherals in a system are placed into low-power mode by temporarily stopping the clock signal supplied to them, no errors from these peripherals are captured or detected until the clock is reactivated. Assuming the clock is deactivated for a sufficiently long time, an attacker could have enough time to flip multiple bits of keys or other secure information within one or more peripherals to gain access. Furthermore, suspending the clock can disable other security mechanisms that might otherwise prevent attacks.

[0003] Furthermore, when a security attack is detected, multiple clocks may be needed to propagate the error to the system's security exception handler. If the peripheral clocks are not restarted, the security attack on the peripheral device may not be detected. Although the security risk can be reduced or minimized by maintaining the system clock to each peripheral device containing security information, the competing benefit of reduced power consumption is also reduced or minimized. Summary of the Invention

[0004] According to a first aspect of the present invention, a processing system is provided, comprising:

[0005] Peripheral devices, which are configured to store security information and have a clock input that receives a gated clock;

[0006] A watch clock generator configured to generate a watch clock with a reduced duty cycle relative to the system clock; and

[0007] A clock control circuit system configured to select the system clock as the gated clock during normal operation of the peripheral device, and to select the watch clock as the gated clock during low-power mode of the peripheral device.

[0008] In one or more embodiments, the watch clock generator includes:

[0009] A counter, configured to count cycles of the system clock and provide a count value indicating the cycle; and

[0010] A clock pulse selector, configured to provide a pulse on the watch clock after each occurrence of a selected number of cycles of the system clock, as indicated by the count value.

[0011] In one or more embodiments, the clock pulse selector is configured to select every 2 seconds of the system clock. M A pulse provides pulses on the watch clock, where M is the watch clock factor.

[0012] In one or more embodiments, the clock pulse selector includes an analog circuit system configured to, whenever the count value is divided by 2 M When the value is zero, a pulse is provided on the watch clock, where M is the watch clock factor.

[0013] In one or more embodiments, the clock control circuitry is configured to select the system clock as the gated clock when the system clock is enabled, and to select the watch clock as the gated clock when the watch clock is enabled and the system clock is disabled.

[0014] In one or more embodiments, the clock control circuitry is configured to select the system clock as the gated clock when the system clock is enabled or when a clock request signal from the peripheral device is asserted, and to select the watch clock as the gated clock when the watch clock is enabled and the system clock is disabled and when the clock request signal from the peripheral device is denied.

[0015] In one or more embodiments, the processing system further includes:

[0016] The second peripheral device is configured to store security information and has a clock input to receive a second gating clock.

[0017] A delay circuit system, configured to delay the watch clock and provide a delayed watch clock; and

[0018] The clock control circuitry is configured to select the system clock as the second gated clock during normal operation of the second peripheral device, and to select the delayed watch clock as the second gated clock during low-power mode of the second peripheral device.

[0019] In one or more embodiments, the delay circuit system includes a shift register.

[0020] In one or more embodiments, the processing system further includes:

[0021] The peripheral device includes one of a plurality of peripheral devices, each peripheral device being configured to store security information and each peripheral device having a clock input that receives a corresponding gated clock from a plurality of gated clocks;

[0022] A delay circuit system, configured to delay the watch clock and provide multiple delayed watch clocks offset from each other; and

[0023] The clock control circuitry is configured to select the system clock as the gate clock for the corresponding peripheral device during normal operation of the plurality of peripheral devices, and to select the corresponding delayed watch clock as the gate clock during the low-power mode of the corresponding peripheral device.

[0024] In one or more embodiments, the processing system further includes:

[0025] The peripheral device includes one of a plurality of peripheral devices, each peripheral device being configured to store security information and each peripheral device having a clock input that receives a corresponding gated clock from a plurality of gated clocks, wherein the plurality of peripheral devices are subdivided into a plurality of groups;

[0026] The watch clock generator includes one of a plurality of watch clock generators, each watch clock generator being configured to generate a corresponding master watch clock among a plurality of master watch clocks, each master watch clock having a corresponding duty cycle among a plurality of different duty cycles reduced relative to the system clock, wherein each of the plurality of watch clock generators generates a corresponding master watch clock for a corresponding group among the plurality of groups;

[0027] A delay circuit system configured to delay each of the plurality of master watch clocks and provide each of the plurality of groups with a plurality of delayed watch clocks offset from each other; and

[0028] The clock control circuitry is configured to select the system clock as the gate clock for the corresponding peripheral device during normal operation of the plurality of peripheral devices, and to select either the corresponding master watch clock or the corresponding delay watch clock among the plurality of master watch clocks as the gate clock during the low-power mode of the corresponding peripheral device.

[0029] According to a second aspect of the invention, a method is provided, comprising:

[0030] In a processing system that includes peripheral devices configured to store security information and having clock inputs that receive gated clocks:

[0031] Generate a watch clock with a reduced duty cycle relative to the system clock; and

[0032] The system clock is selected as the gated clock during normal operation of the peripheral device, and the watch clock is selected as the gated clock during the low-power mode of the peripheral device.

[0033] In one or more embodiments, generating a watch clock includes:

[0034] Counting the cycles of the system clock and providing a count value indicating the cycles; and

[0035] A pulse is provided on the watch clock after each occurrence of a selected number of cycles of the system clock, as indicated by the count value.

[0036] In one or more embodiments, the provision includes every 2 for the system clock. M A pulse provides pulses on the watch clock, where M is the watch clock factor.

[0037] In one or more embodiments, the provision includes whenever the count value is divided by 2 M When the value is zero, a pulse is provided on the watch clock, where M is the watch clock factor.

[0038] In one or more embodiments, the selection includes selecting the system clock as the gated clock when the system clock is enabled, and selecting the watch clock as the gated clock when the watch clock is enabled and the system clock is disabled.

[0039] In one or more embodiments, the selection includes selecting the system clock as the gated clock when the system clock is enabled or when a clock request signal from the peripheral device is asserted, and selecting the watch clock as the gated clock when the watch clock is enabled and the system clock is disabled and when the clock request signal from the peripheral device is denied.

[0040] In one or more embodiments, the processing system includes a second peripheral device configured to store security information and having a clock input for receiving a second gated clock, the method further comprising:

[0041] Delay the watch clock and provide a delayed watch clock; and

[0042] The system clock is selected as the second gated clock during normal operation of the second peripheral device, and the delayed watch clock is selected as the second gated clock during low-power mode of the second peripheral device.

[0043] In one or more embodiments, the delay includes shifting the watch clock via a shift register clocked by the system clock, and providing at least one delayed watch clock.

[0044] In one or more embodiments, the peripheral device includes one of a plurality of peripheral devices, each peripheral device being configured to store security information and each peripheral device having a clock input that receives a corresponding gated clock from a plurality of gated clocks, the method further comprising:

[0045] Delaying the watch clock and providing multiple delayed watch clocks that are offset from each other; and

[0046] During normal operation of the corresponding peripheral device among the plurality of peripheral devices, the system clock is selected as the gated clock of the corresponding peripheral device, and during the low-power mode of the corresponding peripheral device, the corresponding delayed watch clock among the plurality of delayed watch clocks is selected as the gated clock.

[0047] In one or more embodiments, the peripheral device includes one of a plurality of peripheral devices, each peripheral device being configured to store security information and each peripheral device having a clock input that receives a corresponding gated clock from a plurality of gated clocks, wherein the plurality of peripheral devices are subdivided into a plurality of groups, and the method further includes:

[0048] Generate a corresponding master watch clock among a plurality of master watch clocks for each of the plurality of groups, each of the plurality of master watch clocks having a corresponding duty cycle among a plurality of different duty cycles that are reduced relative to the system clock;

[0049] Delaying each of the plurality of master watch clocks and providing each of the plurality of groups with a plurality of delayed watch clocks offset from each other; and

[0050] During normal operation of the corresponding peripheral device among the plurality of peripheral devices, the system clock is selected as the gated clock of the corresponding peripheral device, and during the low-power mode of the corresponding peripheral device, the corresponding master watch clock among the plurality of master watch clocks or the corresponding delay watch clock among the plurality of delay watch clocks is selected as the gated clock.

[0051] These and other aspects of the invention will become apparent from the embodiments described below, and will be illustrated with reference to these embodiments. Attached Figure Description

[0052] Embodiments of the invention are illustrated by way of example and are not limited to the drawings. Similar reference numerals in the drawings may indicate similar elements. Elements in the drawings are shown for simplicity and clarity and are not necessarily drawn to scale.

[0053] Figure 1 This is a simplified block diagram of a selected portion of a processing system for managing a watch clock, implemented according to one embodiment.

[0054] Figure 2 These are simplified schematic diagrams and block diagrams of an exemplary peripheral block implemented according to one embodiment, which can be used to implement... Figure 1 One or more until all outer blocks.

[0055] Figure 3 It can be used as Figure 1 A simplified schematic and block diagram of a clock and reset generator (CRG) implemented according to one embodiment.

[0056] Figure 4 This illustrates an embodiment of the case when targeting a peripheral block PER. <1> When enabled, it performs watch clock management. Figure 1 The timing diagram of the operation of the clock control circuit.

[0057] Figure 5 It can be used as Figure 1 A simplified schematic and block diagram of another clock and reset generator (CRG) implemented according to another embodiment, wherein... Figure 1 The peripheral blocks are separated into one or more different groups for use with different programmable watch clocks.

[0058] Figure 6This is a simplified schematic diagram of a delay circuit implemented according to one embodiment, which can be used as any delay circuit for any CRG. Detailed Implementation

[0059] The watch clock system described herein avoids the security risks of conventional low-power processing system configurations, where peripheral devices containing security information (referred to herein as "security peripherals") remain unclocked for extended periods during low-power mode. Instead, the watch clock system clocks peripherals during low-power mode with a significantly reduced programmable duty cycle (e.g., reduced by 100 times or more). As used herein, the term "peripheral device" refers to any functional circuitry block or module that performs a corresponding function, including the security functions of the processing system. The watch clock system ensures that errors are cascaded up to the highest system level via clock management, while adding only minimal additional power. When the processing system includes multiple security peripherals, a separate watch clock signal can be provided to each peripheral, or the peripherals can be subdivided into groups, each group receiving a corresponding watch clock signal from among multiple watch clock signals.

[0060] A watch clock system can be configured to offset the watch clock by reducing the duty cycle supplied to multiple peripherals. A drawback of uniformly or uniformly reducing the clock is that it can cause power spikes during the clock rise time to multiple peripherals, such as when multiple triggers are fired simultaneously. Synchronous clock management also creates a potential physical attack surface because it allows an attacker to synchronize their attack with the synchronous clock management, which would otherwise be visible in the power distribution. Alternatively, synchronization attacks can be prevented by offsetting the watch clocks of different peripherals via simple shift registers or similar methods.

[0061] Furthermore, the watch clock process can be externally applied to any conventional peripheral device, including security information, without requiring internal modifications. Therefore, the watch clock system can be installed with low complexity in otherwise complex systems. By adding features such as duty cycle configuration registers, the security software programmer can easily balance error response speed with power consumption. The watch clock can be further extended by including simple circuitry or logic that automatically detects when peripheral devices are not in use, allowing clock management to switch from an active clock policy to a watch clock policy imposed by the watch clock system.

[0062] In summary, secure low-power processing systems can achieve power reduction with low complexity while maintaining the security of peripheral devices storing secure information. The watch clock system can be applied to traditional or external systems because it requires no internal modifications. Therefore, the watch clock system is easy to install and configure in any system, including complex systems with multiple secure peripheral devices. The watch clock system can be installed externally to the peripheral device without requiring internal changes or modifications.

[0063] Figure 1 This is a simplified block diagram of a selected portion of a processing system 100 that manages a watch clock according to one embodiment. The processing system 100 includes components individually labeled PER. <1> PER <2> PER <3> ... PER <n>The system comprises N peripheral blocks 102 and a clock and reset generator (CRG) 104. Although four peripheral blocks 102 (1, 2, 3, ..., N) are shown, it should be understood that N can be less than 4 and can even be 1, which includes only one peripheral block 102. Additional components and devices may be included, but are not shown, such as one or more processing devices including one or more of a processor, microprocessor, microcontroller, etc., and any other supporting circuitry systems. Additional components may implement the highest-level system (not shown), including security exception handlers for detecting security attacks or other security issues that may need to be addressed. The processing system 100 may be implemented as discrete components or according to a system-on-a-chip (SoC) configuration, etc.

[0064] Each of the N outer blocks 102 may include security information (SEC) 106 individually labeled SEC1, SEC2, SEC3, ..., SECN, wherein each instance of security information 106 includes sensitive information such as one or more security keys, security tokens, passwords, authorization or authentication information, etc. Although each of the outer blocks 102 is shown to include the corresponding security information 106 for illustrative purposes, it should be understood that other outer blocks (not shown) or even one or more of the shown outer blocks 102 may not include security information 106.

[0065] Each of the peripheral blocks 102 includes a clock input that receives a corresponding gated clock (CG) signal from CRG 104. As shown, the gated clock signal CG... <1> Provided to PER <1> CG gate clock signal <2> Provided to PER <2> CG gate clock signal <3> Provided to PER <3> Wait until the gated clock signal CG is turned on. <n>Provided to PER <n>Each of the peripheral blocks 102 may also have an output that provides a corresponding clock request (CLK_REQ) signal to the CRG 104, the CLK_REQ signal being separately referred to as CLK_REQ. <1> CLK_REQ <2> CLK_REQ <3> ... CLK_REQ <n>The CRG 104 receives the host oscillator (HOSC) and generates the system clock CLK_SYS, where each of the CG signals may be a copy of CLK_SYS or otherwise derived from CLK_SYS, as further described herein.

[0066] Processing system 100 is configured to operate in a low-power mode to save power. In a normal configuration, when any of the peripheral blocks 102 is not in use, the corresponding clock signal provided to the corresponding peripheral module 102 is disabled or otherwise turned off. Therefore, when one or more of the peripheral blocks 102 are not in use, power can be significantly reduced by stopping the clock on each of the unused and unclocked peripheral blocks 102. However, one or more of the unclocked peripheral blocks 102 may be, or otherwise may include, secure peripherals incorporating security information 106, which may be protected against bit-flip attacks by error detection codes (EDCs). EDC errors are typically latched in triggers that initiate error responses. The problem with the normal configuration is that when a peripheral block incorporating security information is unclocked for a considerable period of time, errors are no longer captured / detected until the clock is reactivated. Assuming the clock is activated for a sufficiently long time, this gives an attacker the opportunity to flip multiple bits of the corresponding security information 106 to gain access to the security information 106. Additionally, when the clock is stopped, any other security mechanisms that can be incorporated can be deactivated.

[0067] CRG 104 is configured to clock one through all peripheral blocks 102 using a watch clock signal that operates with a significantly reduced duty cycle during watch clock management operation in low-power mode. This ensures that any detected errors will be propagated cascaded up to the highest system level at the cost of minimal additional power for clock management. Additionally, multiple watch clock signals can be generated, each programmed with a different frequency or cycle time suitable for one or more selected peripheral blocks 102. Thus, the selected peripheral blocks 102 can be grouped, with each group receiving a corresponding watch clock signal from among multiple watch clock signals. In practice, a separate programmable watch clock generator can be provided for each peripheral block 102. Furthermore, the selected peripheral blocks 102 in each group do not necessarily need to be clocked simultaneously during watch clock management operation; instead, the watch clock signals in each group can be interleaved or offset from one peripheral to the next using delay circuitry systems, etc., to minimize visibility in the power distribution.

[0068] Figure 2 This is a simplified schematic and block diagram of an exemplary peripheral block 202 implemented according to one embodiment, which can be used to implement one or more, up to all, peripheral blocks 102. Peripheral block 202 includes a peripheral module 204 and a clock gating circuit (CGC) 206. Peripheral module 204 is denoted as PER. <x>This represents a peripheral circuit system incorporating any one of the peripheral blocks 102 containing security information represented as SECX, where "X" is a number from 1 to N. Peripheral module 204 includes a receiver for a gated clock signal CG. <x>The clock input (CLK_IN), the gated clock signal CG <x>This represents the corresponding one in the gated clock CG. Peripheral module 204 has a set of P inputs that receive a corresponding one of P slave interface signals SI1, SI2, ..., SIP, where P is a number 1 or greater. Peripheral module 204 includes a BUSY output, which is asserted high when active and low when inactive.

[0069] Peripheral module 204 can be a conventional module copied unmodified or otherwise instantiated into processing system 100. CGC 206 is added to detect activity on any one or more of the interface signals SI1-SIP, and the assertion is indicated as CLK_REQ. <x>The corresponding clock request signal is provided. CGC 206 includes a slave interface (I / F) 208, a Q-input Boolean OR gate 210, a 2-input Boolean OR gate 212, a D-type flip-flop (DFF) 214, and a 2-input Boolean AND gate 216. P slave interface signals SI1-SIP are provided to the corresponding inputs of the slave I / F 208, causing Q outputs to provide Q corresponding request signals REQ1, REQ2, ..., REQQ to the Q inputs of OR gate 210. It should be noted that, depending on the implementation, P and Q can be the same number or can be different numbers. The output of OR gate 210 is provided to one input of OR gate 212, causing its other input to be coupled to the output of AND gate 216 and causing the output to provide the clock request signal CLK_REQ. <x>Set the CLK_REQ output of OR gate 212. <x>The D input of DFF 214 is provided to enable the clock input to receive CLK_SYS and to couple the non-inverting Q output to one input of AND gate 216. The BUSY output of peripheral module 204 is coupled to the other input of AND gate 216.

[0070] It should be noted that each DFF shown in the figure and referenced herein can typically be configured as any type of bistable multivibrator or "latch" having at least two stable digital states capable of storing information. Each DFF or latch is configured to change its state by adjusting its input and applying one or more control inputs (e.g., set, reset, clear, clock, etc.). In the illustrated embodiment, each DFF latches its input to its output in response to a clock signal transition; however, alternative configurations are possible and contemplated.

[0071] During the operation of peripheral block 202, when peripheral module 204 is inactive and assuming that the interface signal SI1-SIP is also inactive, BUSY is low and CLK_REQ is high. <x>For low and CG <x>Currently inactive. Activity on any one or more of the interface signals SI1-SIP is detected by the slave I / F 208, which asserts one or more corresponding request signals among the request signals REQ1-REQQ. In response, OR gate 210 asserts its output is high, causing OR gate 212 to assert the CLK_REQ input provided to the corresponding input of CRG 104. <x>High. CRG 104 activates the corresponding gated clock CG. <x>This wakes up peripheral module 204, which becomes active and asserts BUSY as high. Due to CLK_REQ... <x>Both BUSY and AND gate 216 are high, therefore AND gate 216 asserts that its output is high to maintain CLK_REQ while peripheral module 204 is active. <x>When peripheral module 204 completes its task, it becomes inactive, returns to a low-power state, and asserts BUSY low. AND gate 216 asserts its output low, and assuming that interface signals SI1-SIP are also inactive, then CLK_REQ... <x>It was asserted that the clock would drop, and CRG104 deactivated the corresponding gated clock CG. <x>For use in low power mode.

[0072] Since peripheral block 202 is shown to include security information SECX, CRG 104 is configured to provide a watch clock signal as CG with a significantly reduced duty cycle when peripheral block 202 is in low-power mode. <x>In this way, peripheral block 202 can achieve substantial power reduction while maintaining the security of the security information SECX, instead of remaining clockless indefinitely during low-power operation.

[0073] Figure 3 This is a simplified schematic and block diagram of a clock and reset generator (CRG) 300 implemented according to one embodiment, which can be used as CRG 104. The host oscillator signal HOSC is provided as input to a system clock generator 302, which outputs the system clock signal CLK_SYS. CLK_SYS is provided as input to a watch clock generator 304, which outputs a first watch clock gate (WCG1) signal to the peripheral block PER. <1> The clock control circuit 306 receives input from the external block PER. <1> Receive clock request signal CLK_REQ <1> And the gate clock signal CG <1> Output to peripheral block PER <1> WCG1 is also provided as an input to delay circuit 308, which delays WCG1 by a first delay value DEL1 to provide a second watch clock gate (WCG2) signal, where WCG2 is a delayed version of WCG1. WCG2 is then provided to the peripheral block PER. <2> The clock control circuit 310 receives input from the peripheral block PER. <2> Receive clock request signal CLK_REQ <2> And the gate clock signal CG <2> Output to peripheral block PER <2> WCG2 is also provided as an input to delay circuit 312, which delays WCG2 by a second delay value DEL2 to provide a third watch clock gate (WCG3) signal, where WCG3 is a delayed version of WCG2. WCG3 is then provided to the peripheral block PER. <3> The clock control circuit 314 receives input from the peripheral block PER. <3> Receive clock request signal CLK_REQ <3> And the gate clock signal CG <3> Output to peripheral block PER <3> Additional clock control circuitry and delay circuitry can be included in a similar manner to provide a gated clock signal for each peripheral block 102.

[0074] In one embodiment, the watch clock generator 304 includes a counter 320 and a modulo-dial (MOD) circuit 322. The counter 320 counts cycles of CLK_SYS and provides the count value CNT to the input of the MOD circuit 322, which provides the WCG1 signal. A programmable register 324 stores the watch clock management factor M provided to another input of the MOD circuit 322. As further described herein, this factor is for every 2 cycles of CLK_SYS. M One clock pulse provides one watch clock pulse. Counter 320 can be configured as an R-bit cyclic counter that provides CNT as an R-bit value (where R is an integer), the R-bit cyclic counter for CNT=0 to CNT=2. R The counting loop is set to -1, wraps back to 0, and repeats in consecutive loops. For example, for R=8, CNT counts up from CNT=00000000b (where the appended "b" indicates a binary value) to CNT=11111111b, wraps back to 00000000b in the next CLK_SYS loop, and repeats. The MOD circuit 322 counts at CNT / 2... M When CNT = 0, WCG1 is asserted as high; otherwise, it is pulled low. For example, for M = 3, WCG1 goes high when CNT = 00000000b, 00001000b, 00010000b, 00011000b, and so on. In other words, when the least significant bit (LSB) of CNT = 000b, WCG1 is asserted as high within one CLK_SYS loop.

[0075] It should be noted that the programmable register 324 shown in the figure and referenced herein, and other programmable registers (e.g., Figure 3 Programmable registers 330 and 332 in the middle, and Figure 5 The programmable registers 502, 510, 512, 524, 526, 530, 538, 540, 554 and 556 in the memory can each be implemented in an alternative manner, such as any other suitable type of programmable memory or storage component.

[0076] The clock control circuit 306 includes Boolean logic 2-input OR gates 334 and 338, a Boolean logic 2-input AND gate 336, and a first clock gate (CG1) 340. CG1 340 includes a DFF 342 and another 2-input AND gate 344. Register 330 stores the CLK_SYS enable value and outputs the corresponding system clock enable signal SCE1 to one input of OR gate 334. Register 332 stores the peripheral block PER. <1> The watch clock (WC) enable value is set, and the corresponding watch clock enable signal WCE1 is output to one input of AND gate 336. CLK_REQ is then set to... <1> Provide another input to OR gate 334, causing its output to be coupled to one input of OR gate 338. Provide WCG1 to another input of AND gate 336, causing its output to be coupled to another input of OR gate 338. The output of AND gate 338 is coupled to the D input of DFF 342. Provide CLK_SYS to one input of AND gate 344 and the inverting clock input of DFF 342, causing its non-inverting Q output to provide the clock enable signal CE1 to another input of AND gate 344. The output of AND gate 344 provides the gated clock signal CG. <1> Although not specifically described, each of the other clock control circuits 310, 314, etc., is configured in substantially the same manner as clock control circuit 306, including additional programmable registers for storing the corresponding CLK_SYS and watch clock enable signals in a manner similar to registers 330 and 332. Each of the other clock control circuits 310, 314, etc., receives a corresponding clock request, an enable signal, and a delayed watch clock gate signal, and provides a corresponding gated clock signal CG. <2> CG <3> wait.

[0077] The clock control circuit 306 operates as follows. When register 330 is programmed to enable peripheral device PER... <1> When CLK_SYS is active (e.g., by storing a logic "1" in register 300), SCE1 is high, causing the outputs of OR gates 334 and 338 to be asserted high, thus pulling the D input of the DFF high. After one cycle of CLK_SYS (e.g., after CLK_SYS is subsequently asserted low), the DFF 342 asserts CE1 high as long as register 330 is programmed for PER. <1> With CLK_SYS enabled, CE1 remains high. In this case, AND gate 344 asserts CG. <1> This is to follow CLK_SYS in subsequent loops. Therefore, when CLK_SYS is enabled in this way, CLK_SYS serves as the gated clock signal CG. <1> Effectively provide PER to peripheral devices <1> Clock input.

[0078] Register 330 can be programmed to disable the peripheral device PER. <1> CLK_SYS (e.g., by storing logic "0" in register 300) makes SCE1 low, for example, during low-power mode. (Return to reference) Figure 2 If PER <1> Configured in a similar manner to peripheral block 202, which includes CGC 206, and if CLK_REQ <x>=CLK_REQ <1> In response to a signal being asserted high, CE1 is asserted high (via OR gates 334 and 338 and DFF 342) as long as the clock request signal remains asserted high. In this case, in response to the corresponding clock request signal CLK_REQ... <1> The asserted operation is similar to the case where SCE1 is high, causing CLK_SYS to act as the gated clock signal CG. <1> Effectively provide PER to peripheral devices <1> The clock input, as long as CLK_REQ <1> Keep it at a high level.

[0079] Register 332 can be programmed to enable peripheral device PER. <1> The watch clock management (e.g., by storing a logic "1" in register 332) causes WCE1 to be pulled high. In this way, when register 330 is programmed to disable CLK_SYS, SCE1 is low and CLK_REQ is low during low-power mode. <1> When kept low, WCE1 keeps one input of the AND gate 336 high to enable the peripheral device PER. <1> The watch clock is managed in this way. In this case, when WCE1 is high, whenever WCG1 goes high within one cycle of CLK_SYS, the gated clock signal CG... <1> The watch outputs one clock pulse from CLK_SYS. The watch clock management factor M determines the rate of the watch clock pulse relative to CLK_SYS, where for every 2 CLK_SYS... M One clock pulse generates one watch clock pulse.

[0080] Figure 4 This illustrates an embodiment of the case when targeting a peripheral block PER. <1> Timing diagram of the operation of clock control circuit 306, which performs watch clock management when enabled. WCE1, CLK_SYS, WCG1, CE1, and CG are plotted relative to time. <1> In this case, assuming PER <1> CLK_SYS is disabled (SCE1 is low) and CLK_REQ <1> Keep it low because any of these conditions is managed by the overclock watch clock. For the purpose of simplifying illustration and explanation, logic or other circuit system delays are ignored in the timing diagram. At the initial time t0, WCE1 is shown as asserted high to enable PER. <1> The watch clock is managed by the watch clock generator 304. At a subsequent time t1, the watch clock generator 304 asserts WCG1 high, coinciding with the rising edge of CLK_SYS. At the next falling edge of CLK_SYS at time t2, the DFF 342 asserts CE1 high. At the next rising edge of CLK_SYS at time t3, CG1... <1> It was asserted as high, and both CE1 and CLK_SYS were high. Furthermore, WCG1 went low again around time t3. At the next falling edge of CLK_SYS at time t4, CLK_SYS went low, causing CG... <1> It was also pulled back down. (CG) <1> It remains low until the watch clock generator 304 asserts WCG1 as high the next time.

[0081] In this situation, due to the operation of the watch clock generator 304, each time WCG1 is asserted high within one cycle of CLK_SYS, only one pulse of CLK_SYS is gated to CG. <1> The watch clock management factor M determines the number of CLK_SYS cycles counted before WCG1 is next asserted high. As shown in the diagram, for example, later at time t5, WCG1 is asserted high again within a CLK_SYS cycle, causing CE1 to go high within a CLK_SYS cycle starting at time t6, thus causing CE1 to go high between times t7 and t8. <1> Another clock pulse is generated. According to the watch clock management operation, this operation is repeated in this manner for subsequent assertions of WCG1.

[0082] Return to reference Figure 3 The value of M determines CG <1> The number of CLK_SYS cycles between clock pulse assertions. For M=3, every 2 clock pulses in CLK_SYS... 3 =After 8 cycles, in CG <1> The assertion clock pulse, for M=4, occurs every 2 in CLK_SYS. 4 =After 16 cycles in CG <1> The assertion clock pulse, for M=5, occurs every 2 in CLK_SYS. 5 =32 cycles in CG <1> The assertion clock pulse is repeated, and so on. For an 8-bit counter 320, for M=8, CG <1> The maximum delay between clock pulses is 2 of CLK_SYS. 8 =256 cycles. The size of the counter 320 (e.g., the number of bits) can be increased to achieve a larger watch clock management pulse delay. For example, a 10-bit counter can be used to implement CLK_SYS 2 if needed. 10 =Maximum delay of 1024 cycles (i.e., M=10).

[0083] The operation of each of the clock control circuits 310 and 314, and any additional clock control circuits, is substantially the same. However, if each clock control circuit responds to the same watch clock gate signal WCG1, each peripheral block 102 will clock manage simultaneously during watch clock management operations, resulting in simultaneous peaks of power consumption visible in the power distribution. This synchronized watch clock management operation can create a potential physical attack surface because it allows an attacker to synchronize their attack with the visible power consumption peaks in the power distribution. Alternatively, subsequent watch clock gate signals can be offset relative to WCG1. Delay circuit 308 delays WCG2 by a delay amount DEL1, causing clock control circuit 310 to be offset from WCG1. <2> Watch clock management relative to CG <1> Offset by DEL1. Similarly, delay circuit 312 delays WCG3 by a delay amount DEL2, causing clock control circuit 314 to adjust CG... <3> Watch clock management relative to CG <2> Offset DEL2, and so on.

[0084] The delays DEL1, DEL2, etc., of delay circuits 308, 312, etc., can be equal, so that the watch clock offset among clock control circuits 306, 310, 314, etc., is evenly distributed if needed. Alternatively, the delays can be different, for example, randomly or pseudo-randomly distributed, to potentially achieve a more uniform power consumption distribution when needed. Each of the delay circuits 308, 312, etc., can be implemented as one or more shift registers, etc., as further described herein.

[0085] The CRG 300 shown is illustrated with only one watch clock generator 304, which, if needed, generates watch clock pulses based on watch clock factors M for one or more up to all N peripheral blocks 102. If only one watch clock management gate is provided or otherwise used, the watch clock management of each gated clock signal has the same frequency, even at offsets. In an alternative embodiment, the peripheral blocks 102 may be subdivided into different watch clock management groups, and a separate watch clock management gate (each similar to watch clock generator 304) may be provided for each group. In this case, the different watch clock management gates include separate programmable registers, similar to programmable register 324, for storing different watch clock factors among multiple watch clock factors (e.g., M1, M2, M3, etc.).

[0086] Although not shown, enable values ​​can be programmed into enable registers (e.g., registers 330, 332, 502, 510, 512, 524, 526, 530, 538, 540, 554, 556, etc.) by an externally coupled power controller, located within processing system 100 or within CRG 104, to control the power operation mode and watch clock management operation of each peripheral block 102. For example, the power controller programs register 330 to enable or disable the power supply provided to the peripheral block PER. <1> The system clock is used to switch between normal operating mode and low-power operating mode. Furthermore, the power controller programs register 332 to enable or disable the peripheral block PER during low-power mode. <1> The watch's clock management operations. In this way, when targeting the peripheral block PER... <1> When watch clock management is enabled, watch clock management operations are overridden by the system clock when enabled (e.g., during normal operation), and when the system clock is disabled (e.g., in peripheral block PER). <1> It operates automatically during low-power mode. Watch clock management can be disabled for any of the peripheral blocks 102 that do not include security information to minimize power consumption.

[0087] Figure 5 This is a simplified schematic and block diagram of another clock and reset generator (CRG) 500 implemented according to another embodiment, which can be used as CRG 104, wherein the peripheral block 102 is divided into one or more different groups for operation with different programmable watch clocks. It includes a system clock generator 302 that receives HOSC and provides a system clock signal CLK_SYS. A programmable register 502 stores the watch clock factor M_G1 for a group referred to as group 1. M_G1 and CLK_SYS are provided to a watch clock generator 504, which provides a watch clock gate signal WC for group 1.<G1_1> It should be noted that the value G1_1 maps to the N outer blocks PER assigned to group 1. <1> -PER <n>Any one of them, where the mapped outer block can be called PER.<G1_1> The watch clock generator 504 can be configured in a similar manner to the watch clock generator 304 previously described.

[0088] WC<G1_1> Inputs are provided to clock control circuit 506 and delay circuit 508, the delay circuit 508 having a delay DEL.<G1_1> It also features a delayed watch clock gate signal (WC).<G1_2> The output. Programmable register 510 stores the system clock enable value SCE_G1_1 and programmable register 512 stores the watch clock enable value WCE_G1_1. SCE_G1_1, WCE_G1_1, and the corresponding clock request signal CLK_REQ are then used.<G1_1> A corresponding input is provided to the clock selection (CSEL) circuit 514 of the clock control circuit 506 for the first peripheral block (G1_1) of group 1. The CSEL circuit 514 has outputs that provide selection inputs to the multiplexer (MUX) 516 of the clock control circuit 506, wherein the MUX 516 receives CLK_SYS, WC, and CLK_SYS at the corresponding inputs.<G1_1> And the digital zero value "0" and the corresponding gated clock signal CG<G1_1> Provide PER for outer blocks of group 1<G1_1> Clock input.

[0089] The operation of clock control circuit 506 is now described. Again, the power controller programs enable values ​​into enable registers 502, 510, 512, 524, 526, 530, 538, 540, 554, 556, etc., to control the power operation mode and watch clock management operation of each peripheral block 102. This is achieved when the system clock enable value SCE_G1_1 is logic value "1" or when CLK_REQ...<G1_1> When asserted as high, the CSEL circuit 514 then asserts its output, causing the MUX 516 to select CLK_SYS as the CG.<G1_1> In either case, the outer block PER<G1_1> It receives CLK_SYS and operates normally.

[0090] When the system clock enable value SCE_G1_1 is logic "0" and when CLK_REQ<G1_1> When kept low, and if the watch clock enable value WCE_G1_1 is also logic "0" to disable watch clock management, the CSEL circuit 514 asserts its output, causing the MUX 516 to select logic "0" as CG.<G1_1> To effectively disable the corresponding outer block PER<G1_1> The clock. In this case, the peripheral block PER is effectively disabled.<G1_1> This configuration is suitable for low-power operation. It is ideal for minimizing power consumption for low-power operation of peripheral devices in the absence of safety information. However, if the peripheral block PER...<G1_1> Including corresponding security information (e.g., SEC)<G1_1> If this is the case, then security information may still be vulnerable to attack during low-power mode.

[0091] It should be noted that the MUX 516 can be simplified and configured without a logic "0" input, allowing selection of only CLK_SYS or the corresponding watch clock signal (e.g., WC).<G1_1> In one embodiment, peripheral blocks 102 that only include security information are assigned to one of a different group for operation with the corresponding programmable watch clock. The remaining peripheral blocks 102 that do not include security information are excluded because watch clock management is not required or otherwise not used.

[0092] When the system clock enable value SCE_G1_1 is logic "0" and when CLK_REQ<G1_1> When held low, and if the watch clock enable value WCE_G1_1 is logic "1" to enable watch clock management, the CSEL circuit 514 asserts its output, causing the MUX 516 to select the watch clock signal WC.<G1_1> As CG<G1_1> In this case, the outer block PER<G1_1> Clock management is based on the watch clock factor M-G1 with a significantly reduced duty cycle, ensuring that errors are propagated cascaded through the clock management hierarchy to the highest system level while adding only minimal extra power. Therefore, the highest-level system detects interference with the peripheral block PER.<G1_1> Any attack.

[0093] The delayed watch clock signal WC<G1_2> Inputs are provided to clock control circuit 520 and delay circuit 522, the delay circuit 522 having a delay DEL.<G1_2> It also has the function of providing another delayed watch clock gate signal WC<G1_3> The output. The value G1_2 is mapped to the N peripheral blocks PER assigned to group 1. <1> -PER <n>Any of the other ones, where the mapped outer block is called PER.<G1_2> Programmable register 524 stores the system clock enable value SCE_G1_2, and register 526 stores the watch clock enable value WCE_G1_2. SCE_G1_2, WCE_G1_2, and the corresponding clock request signal CLK_REQ are then used.<G1_2> A corresponding input is provided to the clock control circuit 520 for the second peripheral block (G1_2) of group 1. The clock control circuit 520 is configured in substantially the same manner as the clock control circuit 506, which includes a CSEL circuit and a MUX (not shown) for selecting CLK_SYS, WC...<G1_2> Or no clock as the outer block PER to group 1<G1_2> The corresponding gated clock signal CG of the clock input<G1_2> .

[0094] The operation of clock control circuit 520 is essentially the same as that of clock control circuit 506 previously described. The SCE_G1_2 value stored in register 524 can be used to enable or disable the supply to peripheral block PER.<G1_2> CLK_SYS. If configured this way, the outer block PER<G1_2> It can be asserted that CLK_REQ<G1_2> The request provides CLK_SYS. The WCE_G1_2 value stored in register 526 can be used to enable or disable provisioning to the peripheral block PER.<G1_2> watch clock WC<G1_2> When watch clock management is enabled (i.e., when WCE_G1_2 = logic "1") and when the SCE_G1_2 value is disabled for CLK_SYS and when CLK_REQ<G1_2> When not asserted, the watch clock signal WC<G1_2> As a gated clock signal CG<G1_2> Provided to the outer block PER<G1_2> .

[0095] Programmable register 530 stores another watch clock factor M_G2 for another group, referred to as group 2. M_G2 can be different from M_G1, thus providing watch clock pulses at different rates for group 2. M_G2 and CLK_SYS are provided to another watch clock generator 532, which provides another watch clock gate signal WC for group 2.<G2_1> Again, the value G2_1 maps to the N outer blocks PER assigned to group 2. <1> -PER <n>Any one of them, where the mapped outer block can be called PER.<G2_1> The watch clock generator 532 can be configured in a similar manner to the watch clock generator 304 previously described.

[0096] WC<G2_1> It provides input to another clock control circuit 534 and input to a delay circuit 536, the delay circuit 536 having a delay DEL.<G2_1> It also features a delayed watch clock gate signal (WC).<G2_2> The output. Programmable register 538 stores the system clock enable value SCE_G2_1 and programmable register 540 stores the watch clock enable value WCE_G2_1. SCE_G2_1, WCE_G2_1, and the corresponding clock request signal CLK_REQ are then used.<G2_1> The clock selection (CSEL) circuit 542 is provided with corresponding inputs to the clock control circuit 534 for the peripheral block (G2_1) of group 2. The CSEL circuit 542 has outputs that provide selection inputs to the MUX 544 of the clock control circuit 534, wherein the MUX 544 receives CLK_SYS and WC at the corresponding inputs.<G2_1> And the corresponding gated clock signal CG<G2_1> Provide PER for outer blocks of group 2<G2_1> The clock input. In this case, the MUX 544 is simplified and configured without a logic "0" input. It should be noted that peripherals without security information can be excluded from the watch clock management group and receive clock signals that can be turned off indefinitely without watch clock management operation.

[0097] The delayed watch clock signal WC<G2_2> An input is provided to a clock control circuit 550 and an input is provided to a delay circuit 552, the delay circuit 552 having a delay DEL.<G2_2> It also has the function of providing another delayed watch clock gate signal WC<G2_3> The output. The value G2_2 is mapped to the N outer blocks PER assigned to group 2. <1> -PER <n>Any of the other ones, where the mapped outer block is called PER.<G2_2> Programmable register 554 stores the system clock enable value SCE_G2_2, and register 556 stores the watch clock enable value WCE_G2_2. SCE_G2_2, WCE_G2_2, and the corresponding clock request signal CLK_REQ are then used.<G2_2> A corresponding input is provided to the clock control circuit 550 for the second peripheral block (G2_2) of group 2. The clock control circuit 550 is configured in substantially the same manner as the clock control circuit 534, which includes a CSEL circuit and a MUX (not shown) for selecting CLK_SYS or WC.<G2_2> As an outer block PER to group 2<G2_2> The corresponding gated clock signal CG of the clock input<G2_2> .

[0098] The operation of clock control circuit 534 will not be described further, but it is essentially similar to the previously described clock control circuit 506, except that MUX 544 does not include a logic "0" input. Furthermore, the rate of the watch clock pulses can vary based on the watch clock factor M_G2. The operation of clock control circuit 550 will not be described further, but it is essentially similar to clock control circuit 534 and similar to the previously described clock control circuit 506.

[0099] Figure 6 This is a simplified schematic diagram of a delay circuit 600 implemented according to one embodiment, which can be used as any of the previously described delay circuits, such as delay circuits 308, 312, 508, 522, 536, and 552. Depending on the desired amount of delay, the shown delay circuit 600 is configured as a shift register including one or more DFFs 602, 604, 606, etc. Although three DFFs are shown, it should be understood that more or fewer DFFs may be included, such as a single DFF, a pair of consecutive DFFs, an array of more than three DFFs, etc. Each of the DFFs includes a clock input that receives an appropriate clock signal, such as CLK_SYS as shown. An input watch clock signal WCI is provided to the D input of a first DFF 602, which outputs a first delayed watch clock signal WCO1. If an additional delay is required, WCO1 is provided to the input of a second DFF 604, which outputs a second delayed watch clock signal WCO2. If additional delay is required, WCO2 is provided as input to the third DFF 606, which outputs a third delayed watch clock signal WCO3, and so on. In this case, each subsequent watch clock signal is delayed from the previous watch clock signal by one or more cycles of CLK_SYS. As previously mentioned, the subsequent sequentially delayed watch clock signals can be relative to the first or master watch clock signal (e.g., WCG1, WC...).<G1_1> WC<G2_1> (etc.) offset to avoid peaks in the power distribution, thereby preventing synchronization attacks on the peripheral block 102 containing security information.

[0100] Each delay in any given group can be the same for a uniform offset, or different for a non-uniform offset from one peripheral device to the next. In one embodiment, each delay circuit can be fixed or hardwired to implement a preselected or predetermined delay. In an alternative embodiment, a power controller or other clock controller (not shown) can be configured to program registers, etc., to control the corresponding delay of one or more delay circuits, for example by selecting one of the delayed watch clock signals WCO1, WCO2, WCO3, etc., for each delay circuit.

[0101] Although the invention has been described in conjunction with several embodiments, it is not intended that the invention be limited to the specific forms set forth herein. Rather, it is intended to encompass such alternatives, modifications, and equivalents that can be reasonably included within the scope of the invention as defined by the appended claims. For example, in various embodiments where the invention is not limited to specific circuit system polarity, device type, or voltage or error level, variations of positive or negative circuit systems may be used. For instance, circuit system states such as circuit system low and circuit system high may be inverted depending on whether a pin or signal is implemented in a positive or negative circuit system, etc. In some cases, the circuit system states may be programmable, wherein the circuit system states can be inverted for a given circuit system function.

[0102] As used herein, the terms "a" or "an" are defined as one or more. Furthermore, the use of introductory phrases such as "at least one" and "one or more" in the claims should not be construed as implying that another claim element introduced by the indefinite article "a" or "an" limits any particular claim containing such an introductory claim element to an invention containing only one such element, even when the same claim includes the introductory phrase "one or more" or "at least one" and an indefinite article such as "a" or "an". The foregoing applies to the use of definite articles. Unless otherwise stated, terms such as "first" and "second" are used to arbitrarily distinguish the elements described by these terms. Therefore, these terms are not necessarily intended to indicate a temporal or other priority order of such elements.< / n> < / n> < / n> < / n> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / n> < / n> < / n> < / n>

Claims

1. A processing system, characterized in that, include: Peripheral devices, which are configured to store security information and have a clock input that receives a gated clock; A watch clock generator configured to generate a watch clock with a reduced duty cycle relative to the system clock; as well as A clock control circuit system configured to select the system clock as the gated clock during normal operation of the peripheral device, and to select the watch clock as the gated clock during low-power mode of the peripheral device.

2. The processing system according to claim 1, characterized in that, The watch clock generator includes: A counter, configured to count cycles of the system clock and provide a count value indicating the cycle; and A clock pulse selector, configured to provide a pulse on the watch clock after each occurrence of a selected number of cycles of the system clock, as indicated by the count value.

3. The processing system according to claim 2, characterized in that, The clock pulse selector is configured to select every 2 seconds of the system clock. M A pulse provides pulses on the watch clock, where M is the watch clock factor.

4. The processing system according to claim 2, characterized in that, The clock pulse selector includes an analog circuit system configured to, whenever the count value is divided by 2 M When the value is zero, a pulse is provided on the watch clock, where M is the watch clock factor.

5. The processing system according to claim 1, characterized in that, The clock control circuit system is configured to select the system clock as the gated clock when the system clock is enabled, and to select the watch clock as the gated clock when the watch clock is enabled and the system clock is disabled.

6. The processing system according to claim 1, characterized in that, The clock control circuitry is configured to select the system clock as the gated clock when the system clock is enabled or when a clock request signal from the peripheral device is asserted, and to select the watch clock as the gated clock when the watch clock is enabled and the system clock is disabled and when the clock request signal from the peripheral device is denied.

7. The processing system according to claim 1, characterized in that, In addition, including: The second peripheral device is configured to store security information and has a clock input to receive a second gating clock. A delay circuit system configured to delay the watch clock and provide a delayed watch clock; and The clock control circuitry is configured to select the system clock as the second gated clock during normal operation of the second peripheral device, and to select the delayed watch clock as the second gated clock during low-power mode of the second peripheral device.

8. The processing system according to claim 1, characterized in that, In addition, including: The peripheral device includes one of a plurality of peripheral devices, each peripheral device being configured to store security information and each peripheral device having a clock input that receives a corresponding gated clock from a plurality of gated clocks; A delay circuit system configured to delay the watch clock and provide multiple delayed watch clocks that are offset from each other; and The clock control circuitry is configured to select the system clock as the gate clock for the corresponding peripheral device during normal operation of the plurality of peripheral devices, and to select the corresponding delayed watch clock as the gate clock during the low-power mode of the corresponding peripheral device.

9. The processing system according to claim 1, characterized in that, In addition, including: The peripheral device includes one of a plurality of peripheral devices, each peripheral device being configured to store security information and each peripheral device having a clock input that receives a corresponding gated clock from a plurality of gated clocks, wherein the plurality of peripheral devices are subdivided into a plurality of groups; The watch clock generator includes one of a plurality of watch clock generators, each watch clock generator being configured to generate a corresponding master watch clock among a plurality of master watch clocks, each master watch clock having a corresponding duty cycle among a plurality of different duty cycles reduced relative to the system clock, wherein each of the plurality of watch clock generators generates a corresponding master watch clock for a corresponding group among the plurality of groups; A delay circuit system configured to delay each of the plurality of master watch clocks and provide each of the plurality of groups of delayed watch clocks that are offset from each other; and The clock control circuitry is configured to select the system clock as the gate clock for the corresponding peripheral device during normal operation of the plurality of peripheral devices, and to select either the corresponding master watch clock or the corresponding delay watch clock among the plurality of master watch clocks as the gate clock during the low-power mode of the corresponding peripheral device.

10. A method, characterized in that, include: In a processing system that includes peripheral devices configured to store security information and having clock inputs that receive gated clocks: Generate a watch clock with a reduced duty cycle relative to the system clock; as well as The system clock is selected as the gated clock during normal operation of the peripheral device, and the watch clock is selected as the gated clock during the low-power mode of the peripheral device.

Images