Pixel, display device including same, and electronic device including same

Abstract

Disclosed are a pixel, a display device including the pixel, and an electronic device including the display device, in which each of an addressing scan period and a self-scan period includes a data initialization period and an anode initialization period, and a voltage of an anode electrode is initialized in the data initialization period and the anode initialization period. That is, the voltage of the anode electrode can be initialized multiple times.

Description

Technical Field

[0001] Some aspects of embodiments of this disclosure relate to a pixel, a display device including the pixel, and an electronic device including the display device. Background Technology

[0002] Typically, a display device includes a display panel and a display panel driver. The display panel includes gate lines, data lines, emitter lines, and pixels. The display panel driver includes a gate driver for providing gate signals to the gate lines, a data driver for providing data voltages to the data lines, an emitter driver for providing emitter signals to the emitter lines, and a drive controller for controlling the gate driver, data driver, and emitter driver.

[0003] The display device can support a variable drive frequency, and the frame period for each pixel can include an addressing scan period and a self-scanning period. An anode initialization operation can be performed in each of the addressing scan period and the self-scanning period to initialize the voltage of the anode electrode of the light-emitting element included in each pixel.

[0004] A light-emitting element can emit light based on the voltage of its anode electrode and cathode electrode. Typically, since the voltage of the cathode electrode is fixed at a constant voltage, the brightness of the light-emitting element can be determined based on the voltage of the anode electrode.

[0005] To maintain consistent brightness across the same grayscale level, the voltage of the anode electrode must be exactly the same in both the addressing scan period and the self-scanning period. Display quality can only be guaranteed when these conditions are maintained consistently. For this purpose, anode initialization is crucial.

[0006] The information disclosed in this background section is only intended to enhance the understanding of the background art, and therefore the information discussed in this background section does not necessarily constitute prior art. Summary of the Invention

[0007] Some aspects of embodiments of this disclosure relate to a pixel, a display device including the pixel, and an electronic device including the display device. For example, some aspects of embodiments of this disclosure relate to a pixel for relatively improving display quality, a display device including the pixel, and an electronic device including the display device.

[0008] Some aspects of embodiments of this disclosure include a pixel for performing an anode initialization operation to maintain the same conditions in each of the addressing scan period and the self-scan period.

[0009] Some embodiments of this disclosure include a display device that includes the pixel.

[0010] Some aspects of embodiments of this disclosure include an electronic device that includes the display device.

[0011] According to some embodiments of this disclosure, a pixel can be driven based on a frame period including an addressing scan period and a self-scanning period. The pixel includes: a data write transistor configured to output a data voltage in response to a data write gate signal; a driving transistor configured to generate a driving current based on the data voltage; a light-emitting element including a cathode electrode and an anode electrode to which the driving current is applied; a data initialization transistor configured to apply a data initialization voltage to the driving transistor in response to a data initialization gate signal; and an anode initialization transistor configured to apply an anode initialization voltage to the anode electrode in response to an anode initialization gate signal. Each of the addressing scan period and the self-scanning period includes a non-emission period in which the light-emitting element does not emit light and an emission period in which the light-emitting element emits light, and the non-emission period includes a data initialization period and an anode initialization period following the data initialization period. The voltage of the anode electrode is initialized to a data initialization voltage during the data initialization period and to an anode initialization voltage during the anode initialization period.

[0012] According to some embodiments, the driving transistor may be a PMOS transistor.

[0013] According to some embodiments, when the difference between the voltage of the anode electrode and the anode initialization voltage is less than a threshold, the current flowing from the anode electrode to the anode initialization voltage line that transmits the anode initialization voltage can be reduced.

[0014] According to some embodiments, the data initialization voltage can be greater than the anode initialization voltage.

[0015] According to some embodiments, the difference between the data initialization voltage and the anode initialization voltage can be less than the difference between the voltage of the anode electrode during the emission period and the anode initialization voltage.

[0016] According to some embodiments, the address scan period may further include a data write period between the data initialization period and the anode initialization period. During the data write period, the data write transistor may be configured to apply a data voltage to the drive transistor in response to a data write gate signal.

[0017] According to some embodiments, the pixel may further include: an emitter transistor configured to connect a data initialization transistor and an anode electrode in response to an emitter signal. The emitter transistor can be turned on during a data initialization period to connect the data initialization transistor and the anode electrode, and can be turned off during an anode initialization period to electrically separate the data initialization transistor and the anode electrode.

[0018] According to some embodiments, the driving transistor may include a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; the data writing transistor may include a gate electrode to which a data writing gate signal is applied, a first electrode connected to a data line transmitting a data voltage, and a second electrode connected to a second node; the data initialization transistor may include a gate electrode to which a data initialization gate signal is applied, a first electrode to which a data initialization voltage is applied, and a second electrode connected to a third node; the emitting transistor may include a gate electrode to which an emitting signal is applied, a first electrode connected to a third node, and a second electrode connected to a fourth node; the anode initialization transistor may include a gate electrode to which an anode initialization gate signal is applied, a first electrode to which an anode initialization voltage is applied, and a second electrode connected to a fourth node; and the light-emitting element may include an anode electrode connected to a fourth node and a cathode electrode to which a low power supply voltage is applied.

[0019] According to some embodiments, the pixel may further include: a compensation transistor configured to diode-connect a driving transistor in response to a compensation gate signal; a second emitter transistor configured to connect a high power supply voltage line transmitting a high power supply voltage and a first electrode of the driving transistor in response to a second emitter signal; a bias transistor configured to apply a bias voltage to the first electrode of the driving transistor in response to an anode initialization gate signal; and a storage capacitor configured to store a data voltage. The compensation transistor may include a gate electrode to which the compensation gate signal is applied, a first electrode connected to a first node, and a second electrode connected to a third node; the second emitter transistor may include a gate electrode to which the second emitter signal is applied, a first electrode to which a high power supply voltage is applied, and a second electrode connected to a second node; the bias transistor may include a gate electrode to which the anode initialization gate signal is applied, a first electrode to which a bias voltage is applied, and a second electrode connected to a second node; and the storage capacitor may include a first electrode to which a high power supply voltage is applied and a second electrode connected to a first node.

[0020] According to some embodiments, the driving transistor may include a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; the data writing transistor may include a gate electrode to which a data writing gate signal is applied, a first electrode connected to a data line transmitting a data voltage, and a second electrode connected to a fourth node; the data initialization transistor may include a gate electrode to which a data initialization gate signal is applied, a first electrode to which a data initialization voltage is applied, and a second electrode connected to a third node; the anode initialization transistor may include a gate electrode to which an anode initialization gate signal is applied, a first electrode to which an anode initialization voltage is applied, and a second electrode connected to a fifth node; the emitting transistor may include a gate electrode to which an emitting signal is applied, a first electrode connected to a third node, and a second electrode connected to a fifth node; and the light-emitting element may include an anode electrode connected to the fifth node and a cathode electrode to which a low power supply voltage is applied.

[0021] According to some embodiments, the pixel may further include: a compensation transistor configured to diode-connect a driving transistor in response to a compensation gate signal; a second emitter transistor configured to connect a high power supply voltage line transmitting a high power supply voltage and a first electrode of the driving transistor in response to a second emitter signal; a bias transistor applying a bias voltage to the first electrode of the driving transistor in response to an anode initialization gate signal; a second compensation transistor configured to connect a high power supply voltage line and a second electrode of a data write transistor in response to a compensation gate signal; a storage capacitor configured to store a data voltage; and a boost capacitor configured to boost the voltage of the first node. The compensation transistor may include a gate electrode to which the compensation gate signal is applied, a first electrode connected to the first node, and a second electrode connected to a third node; the second emitter transistor may include a gate electrode to which the second emitter signal is applied, a first electrode to which a high power supply voltage is applied, and a second electrode connected to a second node; the bias transistor may include a gate electrode to which the anode initialization gate signal is applied, a first electrode to which a bias voltage is applied, and a second electrode connected to the second node; the storage capacitor may include a first electrode to which a high power supply voltage is applied and a second electrode connected to a fourth node; and the boost capacitor may include a first electrode connected to the fourth node and a second electrode connected to the first node.

[0022] According to some embodiments, the pixel may further include: a first emitting transistor configured to connect a high power supply voltage line transmitting a high power supply voltage and a first electrode of a driving transistor in response to an emitting signal; and a second emitting transistor configured to connect a data initialization transistor and an anode electrode in response to an emitting signal. The driving transistor may include a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; the data writing transistor may include a gate electrode to which a data writing gate signal is applied, a first electrode connected to a data line transmitting a data voltage, and a second electrode connected to a second node; the data initialization transistor may include a gate electrode to which a data initialization gate signal is applied, a first electrode to which a data initialization voltage is applied, and a second electrode connected to a third node; the first emitting transistor may include a gate electrode to which an emitting signal is applied, a first electrode to which a high power supply voltage is applied, and a second electrode connected to a second node; the second emitting transistor may include a gate electrode to which an emitting signal is applied, a first electrode connected to a third node, and a second electrode connected to a fourth node; the anode initialization transistor may include a gate electrode to which an anode initialization gate signal is applied, a first electrode to which an anode initialization voltage is applied, and a second electrode connected to a fourth node; and the light-emitting element may include an anode electrode connected to a fourth node and a cathode electrode to which a low power supply voltage is applied.

[0023] According to some embodiments, the pixel may further include: a compensation transistor configured to diode-connect a driving transistor in response to a compensation gate signal; a bias transistor configured to apply a bias voltage to a first electrode of the driving transistor in response to an anode initialization gate signal; a second data initialization transistor configured to apply a data initialization voltage to an anode electrode in response to a data initialization gate signal; and a storage capacitor configured to store a data voltage. The compensation transistor may include a gate electrode to which the compensation gate signal is applied, a first electrode connected to a first node, and a second electrode connected to a third node; the bias transistor may include a gate electrode to which the anode initialization gate signal is applied, a first electrode to which the bias voltage is applied, and a second electrode connected to a second node; and the second data initialization transistor may include a gate electrode to which the data initialization gate signal is applied, a first electrode to which the data initialization voltage is applied, and a second electrode connected to a fourth node.

[0024] In a display device according to some embodiments of the present disclosure, the display device includes: a display panel including pixels driven based on a frame period including an addressing scan period and a self-scanning period; and a display panel driver configured to drive the display panel. Each pixel includes: a data write transistor configured to output a data voltage in response to a data write gate signal; a drive transistor configured to generate a drive current based on the data voltage; a light-emitting element including a cathode electrode and an anode electrode to which the drive current is applied; a data initialization transistor configured to apply a data initialization voltage to the drive transistor in response to a data initialization gate signal; and an anode initialization transistor configured to apply an anode initialization voltage to the anode electrode in response to an anode initialization gate signal. Each of the addressing scan period and the self-scanning period includes a non-emission period in which the light-emitting element does not emit light and an emission period in which the light-emitting element emits light, and the non-emission period includes a data initialization period and an anode initialization period following the data initialization period. The voltage of the anode electrode is initialized to a data initialization voltage during the data initialization period and to an anode initialization voltage during the anode initialization period.

[0025] According to some embodiments, the driving transistor may be a PMOS transistor.

[0026] According to some embodiments, when the difference between the voltage of the anode electrode and the anode initialization voltage is less than a threshold, the current flowing from the anode electrode to the anode initialization voltage line that transmits the anode initialization voltage can be reduced.

[0027] According to some embodiments, the data initialization voltage can be greater than the anode initialization voltage.

[0028] According to some embodiments, the difference between the data initialization voltage and the anode initialization voltage can be less than the difference between the voltage of the anode electrode during the emission period and the anode initialization voltage.

[0029] According to some embodiments, the address scan period may further include a data write period between the data initialization period and the anode initialization period. During the data write period, the data write transistor may be configured to apply a data voltage to the drive transistor in response to a data write gate signal.

[0030] In an electronic device according to some embodiments of the present disclosure, the electronic device includes: a display panel including pixels driven based on a frame period including an addressing scan period and a self-scanning period; a display panel driver configured to drive the display panel; and a power supply configured to supply power to the display panel and the display panel driver. Each pixel includes: a data write transistor configured to output a data voltage in response to a data write gate signal; a drive transistor configured to generate a drive current based on the data voltage; a light-emitting element including a cathode electrode and an anode electrode to which the drive current is applied; a data initialization transistor configured to apply a data initialization voltage to the drive transistor in response to a data initialization gate signal; and an anode initialization transistor configured to apply an anode initialization voltage to the anode electrode in response to an anode initialization gate signal. Each of the addressing scan period and the self-scanning period includes a non-emission period in which the light-emitting element does not emit light and an emission period in which the light-emitting element emits light, and the non-emission period includes a data initialization period and an anode initialization period following the data initialization period. The voltage of the anode electrode is initialized to a data initialization voltage during the data initialization period and to an anode initialization voltage during the anode initialization period.

[0031] Depending on the pixels, display device, and electronic device, each of the addressing scan period and the self-scanning period may include a data initialization period and an anode initialization period, and the voltage of the anode electrode can be initialized during both the data initialization period and the anode initialization period. That is, the voltage of the anode electrode can be initialized multiple times and can be consistently maintained. Therefore, display quality can be guaranteed or relatively improved. Attached Figure Description

[0032] The above and other features of the present disclosure will become more apparent from the detailed description of specific embodiments of the present disclosure with reference to the accompanying drawings, in which: Figure 1 This is a block diagram illustrating a display device according to some embodiments of the present disclosure; Figure 2 It is shown Figure 1 A circuit diagram of an example pixel; Figure 3 It shows the driver Figure 2 A timing diagram of examples of pixels; Figure 4 It is shown in Figure 3 During the data initialization period, the driver Figure 2 A timing diagram of examples of pixels; Figure 5 It is shown in Figure 3 Data is written to the compensation period drive Figure 2 A timing diagram of examples of pixels; Figure 6 It is shown in Figure 3 During the anode initialization period, drive Figure 2 A timing diagram of examples of pixels; Figure 7 It is shown in Figure 3 During the launch period Figure 2 A timing diagram of examples of pixels; Figure 8 It is shown in Figure 3 During the anode initialization period Figure 2 A circuit diagram showing the anodic current flowing within a pixel; Figure 9 It shows the basis Figure 3 The graph shows the voltage curves of the anode electrode during the data initialization period and the anode initialization period, representing the anode initialization operation. Figure 10 It is shown Figure 1 A conceptual diagram of the driving frequency of the display panel; Figure 11 This indicates that when the transmission frequency is 480Hz... Figure 2 A timing diagram of the signals of the pixels; Figure 12 This indicates that when the transmission frequency is 240Hz... Figure 2 A timing diagram of the signals of the pixels; Figure 13 It is shown Figure 1 A circuit diagram of an example pixel; Figure 14 It shows the driver Figure 13 A timing diagram of examples of pixels; Figure 15 It is shown Figure 1 A circuit diagram of an example pixel; Figure 16 It is a block diagram showing an electronic device; and Figure 17 It is shown that Figure 16 The diagram shows an embodiment of an electronic device implemented as a smartphone. Detailed Implementation

[0033] In the following, aspects of some embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings.

[0034] Figure 1 This is a block diagram illustrating a display device 10 according to some embodiments of the present disclosure.

[0035] Reference Figure 1The display device 10 may include a display panel 100 and a display panel driver. The display panel driver may include a drive controller 200, a gate driver 300, a gamma reference voltage generator 400, a data driver 500, and a transmit driver 600.

[0036] The display panel 100 may include a display area for displaying images and a peripheral area located adjacent to the display area.

[0037] The display panel 100 may include a gate line GL, a data line DL, an emitter line EML, and pixels PX electrically connected to the gate line GL, the data line DL, and the emitter line EML. The gate line GL may extend in a first direction, the data line DL may extend in a second direction intersecting the first direction, and the emitter line EML may extend in the first direction.

[0038] The drive controller 200 can receive input image data IMG and input control signals CONT from an external device. For example, the input image data IMG may include red image data, green image data, and blue image data. The input image data IMG may also include white image data. The input image data IMG may also include magenta image data, yellow image data, and cyan image data. The input control signal CONT may include a master clock signal and a data enable signal. The input control signal CONT may also include a vertical synchronization signal and a horizontal synchronization signal.

[0039] The drive controller 200 can generate a first control signal CONT1, a second control signal CONT2, a third control signal CONT3, a fourth control signal CONT4, and a data signal DATA based on the input image data IMG and the input control signal CONT.

[0040] The drive controller 200 can generate a first control signal CONT1 for controlling the operation of the gate driver 300 based on the input control signal CONT, and output the first control signal CONT1 to the gate driver 300. The first control signal CONT1 may include a vertical start signal and a gate clock signal.

[0041] The drive controller 200 can generate a second control signal CONT2 for controlling the operation of the data driver 500 based on the input control signal CONT, and output the second control signal CONT2 to the data driver 500. The second control signal CONT2 may include a horizontal start signal and a load signal.

[0042] The drive controller 200 can generate a data signal DATA based on the input image data IMG. The drive controller 200 can output the data signal DATA to the data driver 500.

[0043] The drive controller 200 can generate a third control signal CONT3 based on the input control signal CONT for controlling the operation of the gamma reference voltage generator 400, and output the third control signal CONT3 to the gamma reference voltage generator 400.

[0044] The drive controller 200 can generate a fourth control signal CONT4 for controlling the operation of the transmitter driver 600 based on the input control signal CONT, and output the fourth control signal CONT4 to the transmitter driver 600.

[0045] The gate driver 300 can generate a gate signal for driving the gate line GL in response to a first control signal CONT1 received from the drive controller 200. The gate driver 300 can output the gate signal to the gate line GL.

[0046] The gamma reference voltage generator 400 can generate a gamma reference voltage VGREF in response to a third control signal CONT3 received from the drive controller 200. The gamma reference voltage generator 400 can provide the gamma reference voltage VGREF to the data driver 500. The gamma reference voltage VGREF can have a value corresponding to each data signal DATA.

[0047] For example, the gamma reference voltage generator 400 may be located within the drive controller 200 or within the data driver 500.

[0048] The data driver 500 can receive a second control signal CONT2 and a data signal DATA from the drive controller 200, and a gamma reference voltage VGREF from the gamma reference voltage generator 400. The data driver 500 can use the gamma reference voltage VGREF to convert the data signal DATA into a data voltage of analog type. The data driver 500 can output the data voltage to the data line DL.

[0049] The transmit driver 600 can generate a transmit signal for driving the transmit line EML in response to a fourth control signal CONT4 received from the drive controller 200. The transmit driver 600 can output the transmit signal to the transmit line EML.

[0050] exist Figure 1In this illustration, for ease of explanation, the gate driver 300 may be located on a first side of the display panel 100, and the emitter driver 600 may be located on a second side of the display panel 100. However, this disclosure is not limited thereto. For example, both the gate driver 300 and the emitter driver 600 may be located on the first side of the display panel 100. For example, both the gate driver 300 and the emitter driver 600 may be located on opposite sides of the display panel 100. For example, the gate driver 300 and the emitter driver 600 may be integrally formed.

[0051] Figure 2 It is shown Figure 1 A circuit diagram of an example pixel PX. Although Figure 2 Various components in a pixel according to some embodiments are shown, but the embodiments of this disclosure are not limited thereto, and according to various embodiments, a pixel may include additional components or fewer components without departing from the spirit and scope of the embodiments of this disclosure.

[0052] Figure 3 It shows the driver Figure 2 A timing diagram of an example of pixel PX.

[0053] Reference Figures 1 to 3 The display panel 100 may include pixels PX. Each of the pixels PX may include a first transistor T1 to an eighth transistor T8, a storage capacitor CST, and a light-emitting element EL. However, this disclosure is not limited to... Figure 2 The pixel PX. This disclosure can be applied to various embodiments.

[0054] The first transistor T1 may include a gate electrode connected to a first node N1, a first electrode connected to a second node N2, and a second electrode connected to a third node N3. According to some embodiments, the first transistor T1 may be a PMOS transistor. The first transistor T1 may generate a drive current based on the voltage of the first node N1 and the voltage of the second node N2. The first transistor T1 may be referred to as a drive transistor.

[0055] The second transistor T2 may include a gate electrode to which a data write gate signal GW is applied, a first electrode connected to a data line DL for transmitting data voltage VDATA, and a second electrode connected to a second node N2. According to some embodiments, the second transistor T2 may be a PMOS transistor. The second transistor T2 may apply the data voltage VDATA to the second node N2 in response to the data write gate signal GW. The second transistor T2 may be referred to as a data write transistor.

[0056] The third transistor T3 may include a gate electrode to which a compensation gate signal GC is applied, a first electrode connected to the first node N1, and a second electrode connected to the third node N3. According to some embodiments, the third transistor T3 may be an NMOS transistor. The third transistor T3 may be diode-connected to the first transistor T1 in response to the compensation gate signal GC. The third transistor T3 may be referred to as a compensation transistor.

[0057] The fourth transistor T4 may include a gate electrode to which a data initialization gate signal GI is applied, a first electrode to which a data initialization voltage VINT is applied, and a second electrode connected to the third node N3. According to some embodiments, the fourth transistor T4 may be a PMOS transistor. The fourth transistor T4 may apply the data initialization voltage VINT to the first transistor T1 in response to the data initialization gate signal GI. The fourth transistor T4 may be referred to as a data initialization transistor.

[0058] The fifth transistor T5 may include a gate electrode to which an emitter signal EM(N) is applied, a first electrode to which a high supply voltage ELVDD is applied, and a second electrode connected to the second node N2. According to some embodiments, the fifth transistor T5 may be a PMOS transistor. The fifth transistor T5 may connect to the high supply voltage line transmitting the high supply voltage ELVDD and the second node N2 in response to the emitter signal EM(N). The fifth transistor T5 may be referred to as the first emitter transistor.

[0059] The sixth transistor T6 may include a gate electrode to which the next emitter signal EM(N+2) is applied, a first electrode connected to the third node N3, and a second electrode connected to the fourth node N4. According to some embodiments, the sixth transistor T6 may be a PMOS transistor. The sixth transistor T6 may connect the third node N3 and the fourth node N4 in response to the next emitter signal EM(N+2). The sixth transistor T6 may be referred to as the second emitter transistor.

[0060] The transmitted signal EM(N) can be the Nth transmitted signal, and the next transmitted signal EM(N+2) can be the (N+2)th transmitted signal. Here, N can be a positive integer greater than or equal to 1. However, in Figure 2 In a pixel PX, the next transmitted signal is not limited to the (N+2)th transmitted signal. For example, the next transmitted signal could be the (N+1)th transmitted signal.

[0061] The seventh transistor T7 may include a gate electrode to which an anode initialization gate signal GB is applied, a first electrode to which an anode initialization voltage VAINT is applied, and a second electrode connected to the fourth node N4. According to some embodiments, the seventh transistor T7 may be a PMOS transistor. The seventh transistor T7 may apply the anode initialization voltage VAINT to the fourth node N4 in response to the anode initialization gate signal GB. According to some embodiments, the data initialization voltage VINT may be greater than the anode initialization voltage VAINT. The seventh transistor T7 may be referred to as an anode initialization transistor.

[0062] The eighth transistor T8 may include a gate electrode to which an anode initialization gate signal GB is applied, a first electrode to which a bias voltage VOBS is applied, and a second electrode connected to the second node N2. According to some embodiments, the eighth transistor T8 may be a PMOS transistor. The eighth transistor T8 may apply the bias voltage VOBS to the second node N2 in response to the anode initialization gate signal GB. The eighth transistor T8 may be referred to as a bias transistor.

[0063] The storage capacitor CST may include a first electrode to which a high supply voltage ELVDD is applied and a second electrode connected to a first node N1. The storage capacitor CST can store the data voltage VDATA.

[0064] The light-emitting element EL may include an anode electrode connected to the fourth node N4 and a cathode electrode to which a low supply voltage ELVSS is applied. A drive current may be applied to the anode electrode, the voltage of the anode electrode may be determined based on the drive current, and the brightness of the light-emitting element EL may be determined based on the voltage of the anode electrode.

[0065] The frame period of a pixel PX can include a non-emission period (NEP) and an emission period (EP). The non-emission period (NEP) can be the period during which the light-emitting element (EL) does not emit light, and the emission period (EP) can be the period during which the light-emitting element (EL) emits light.

[0066] The non-emission period (NEP) can include a data initialization period (DIP), a data write compensation period (DWCP) following the data initialization period (DIP), and an anode initialization period (AIP) following the data write compensation period (DWCP). Here, the signals EM(N), EM(N+2), GI, GC, GW, and GB applied to the pixel PX can have an active level L_ACT and an inactive level L_INACT. The active level L_ACT is the level at which the transistor is turned on when the signals EM(N), EM(N+2), GI, GC, GW, and GB are applied to the gate electrode of the transistor. The inactive level L_INACT is the level at which the transistor is turned off when the signals EM(N), EM(N+2), GI, GC, GW, and GB are applied to the gate electrode of the transistor.

[0067] During the data initialization period (DIP), the transmit signal EM(N) can have an invalid level L_INACT, the next transmit signal EM(N+2) can have an active level L_ACT, the data initialization gate signal GI can have an active level L_ACT, the compensation gate signal GC can have an active level L_ACT, the data write gate signal GW can have an invalid level L_INACT, and the anode initialization gate signal GB can have an invalid level L_INACT.

[0068] During the data write compensation period (DWCP), the transmit signal EM(N) can have an invalid level L_INACT, the next transmit signal EM(N+2) can have an invalid level L_INACT, the data initialization gate signal GI can have an invalid level L_INACT, the compensation gate signal GC can have an active level L_ACT, the data write gate signal GW can have an active level L_ACT, and the anode initialization gate signal GB can have an invalid level L_INACT.

[0069] During the anode initialization period (AIP), the transmit signal EM(N) can have an invalid level L_INACT, the next transmit signal EM(N+2) can have an invalid level L_INACT, the data initialization gate signal GI can have an invalid level L_INACT, the compensation gate signal GC can have an invalid level L_INACT, the data write gate signal GW can have an invalid level L_INACT, and the anode initialization gate signal GB can have an active level L_ACT.

[0070] During the transmit period EP, the transmit signal EM(N) can have an active level L_ACT, the next transmit signal EM(N+2) can have an active level L_ACT, the data initialization gate signal GI can have an inactive level L_INACT, the compensation gate signal GC can have an inactive level L_INACT, the data write gate signal GW can have an inactive level L_INACT, and the anode initialization gate signal GB can have an inactive level L_INACT.

[0071] Figure 4 It is shown in Figure 3 Data initialization period DIP driver Figure 2 A timing diagram of an example of pixel PX. Figure 5 It is shown in Figure 3 Data is written to the DWCP driver during the compensation period. Figure 2 A timing diagram of an example of pixel PX. Figure 6 It is shown in Figure 3 Anode initialization period in AIP drive Figure 2 A timing diagram of an example of pixel PX. Figure 7 It is shown in Figure 3 During the launch period, drive in EP Figure 2 A timing diagram of an example of pixel PX.

[0072] Reference Figure 3 and Figure 4 During the data initialization period DIP, the second transistor T2 can be turned off in response to the data write gate signal GW with an invalid level L_INACT, the fifth transistor T5 can be turned off in response to the transmit signal EM(N) with an invalid level L_INACT, the seventh transistor T7 can be turned off in response to the anode initialization gate signal GB with an invalid level L_INACT, and the eighth transistor T8 can be turned off in response to the anode initialization gate signal GB with an invalid level L_INACT.

[0073] The fourth transistor T4 can be turned on in response to the data initialization gate signal GI with an active level L_ACT, so as to apply the data initialization voltage VINT to the third node N3. Therefore, the voltage of the third node N3 can have the data initialization voltage VINT.

[0074] The third transistor T3 can be turned on in response to a compensation gate signal GC with an effective level L_ACT, so as to apply the voltage of the third node N3 (i.e., the data initialization voltage VINT) to the first node N1. Therefore, the voltage of the first node N1 can have the data initialization voltage VINT.

[0075] The sixth transistor T6 can be turned on in response to the next transmit signal EM(N+2) with an effective level L_ACT, to apply the voltage of the third node N3 (i.e., the data initialization voltage VINT) to the fourth node N4. Therefore, the voltage of the fourth node N4 can be changed from the voltage VANO_EP of the anode electrode during the transmit period EP of the previous frame period to the data initialization voltage VINT. In other words, the voltage of the anode electrode can be initialized to the data initialization voltage VINT.

[0076] Thus, during the data initialization period (DIP), a data initialization operation can be performed to initialize the data voltage VDATA stored in the storage capacitor CST in the previous frame period, and an anode initialization operation can be performed to initialize the voltage of the anode electrode.

[0077] Reference Figure 3 and Figure 5During the data write compensation period (DWCP), the fourth transistor T4 can be turned off in response to the data initialization gate signal GI with an invalid level L_INACT, the fifth transistor T5 can be turned off in response to the transmit signal EM(N) with an invalid level L_INACT, the sixth transistor T6 can be turned off in response to the next transmit signal EM(N+2) with an invalid level L_INACT, the seventh transistor T7 can be turned off in response to the anode initialization gate signal GB with an invalid level L_INACT, and the eighth transistor T8 can be turned off in response to the anode initialization gate signal GB with an invalid level L_INACT.

[0078] The second transistor T2 can be turned on in response to a data write gate signal GW with an active level L_ACT, so as to apply the data voltage VDATA to the second node N2. Therefore, the voltage of the second node N2 can have the data voltage VDATA.

[0079] The first transistor T1 can be turned on in response to the voltage of the first node N1 (i.e., the data initialization voltage VINT) and the voltage of the second node N2 (i.e., the data voltage VDATA) to apply the voltage of the second node N2 to the third node N3. The third transistor T3 can be turned on in response to the compensation gate signal GC with an effective level L_ACT, and is connected to the first transistor T1 as a diode. Therefore, the threshold voltage of the first transistor T1 can be compensated, and the storage capacitor CST can store the data voltage VDATA of the first transistor T1 whose threshold voltage has been compensated.

[0080] Thus, during the data write compensation period (DWCP), a data write operation to apply the data voltage VDATA to the pixel PX and a compensation operation to compensate for the threshold voltage of the first transistor T1 can be performed.

[0081] Reference Figure 3 and Figure 6 During the anode initialization period (AIP), the second transistor T2 can be turned off in response to the data write gate signal GW with an invalid level L_INACT, the third transistor T3 can be turned off in response to the compensation gate signal GC with an invalid level L_INACT, the fourth transistor T4 can be turned off in response to the data initialization gate signal GI with an invalid level L_INACT, the fifth transistor T5 can be turned off in response to the emit signal EM(N) with an invalid level L_INACT, and the sixth transistor T6 can be turned off in response to the next emit signal EM(N+2) with an invalid level L_INACT.

[0082] The seventh transistor T7 can be turned on in response to the anode initialization gate signal GB with an effective level L_ACT, so as to apply the anode initialization voltage VAINT to the fourth node N4. Therefore, the voltage of the fourth node N4 can change from the data initialization voltage VINT to the anode initialization voltage VAINT. That is, the voltage of the anode electrode can be initialized to the anode initialization voltage VAINT. In this case, since the sixth transistor T6 is turned off, the sixth transistor T6 can electrically disconnect the fourth transistor T4 and the fourth node N4, and the anode initialization voltage VAINT can be omitted from the application to the third node N3 without affecting the voltage of the third node N3.

[0083] The eighth transistor T8 can be turned on in response to the anode initialization gate signal GB with an effective level L_ACT, so as to apply the bias voltage VOBS to the second node N2. Therefore, the hysteresis characteristics of the first transistor T1 can be relatively improved.

[0084] In this way, the anode initialization operation can be performed during the anode initialization period (AIP).

[0085] Reference Figure 3 and Figure 7 During the transmit phase EP, the second transistor T2 can be turned off in response to the data write gate signal GW with an invalid level L_INACT, the third transistor T3 can be turned off in response to the compensation gate signal GC with an invalid level L_INACT, the fourth transistor T4 can be turned off in response to the data initialization gate signal GI with an invalid level L_INACT, the seventh transistor T7 can be turned off in response to the anode initialization gate signal GB with an invalid level L_INACT, and the eighth transistor T8 can be turned off in response to the anode initialization gate signal GB with an invalid level L_INACT.

[0086] The fifth transistor T5 can be turned on in response to the transmit signal EM(N) with an effective level L_ACT to connect the high power supply voltage line and the second node N2, and the sixth transistor T6 can be turned on in response to the next transmit signal EM(N+2) with an effective level L_ACT to connect the third node N3 and the fourth node N4.

[0087] The first transistor T1 can generate a drive current based on the voltage of the first node N1 and the voltage of the second node N2. The drive current can be applied to the anode electrode along the path of the fifth transistor T5, the first transistor T1, and the sixth transistor T6. Therefore, the voltage of the fourth node N4 can change from the anode initialization voltage VAINT to the anode electrode voltage VANO_EP during the emitter period EP.

[0088] The light-emitting element EL can emit light based on the voltage VANO_EP of the anode electrode.

[0089] In this way, during the emission period EP, the emission operation of the light-emitting element EL can be performed.

[0090] Figure 8 It is shown in Figure 3 During the anode initialization period (AIP) Figure 2 The circuit diagram of the anodic current IANO_AIP flowing in the pixel PX. Figure 9 It shows the basis Figure 3 The graph shows the voltage VANO of the anode electrode during the anode initialization operation in the data initialization period DIP and the anode initialization period AIP.

[0091] Reference Figures 1 to 9 The anode initialization operation can be performed not only in the anode initialization period (AIP) but also in the data initialization period (DIP).

[0092] During the data initialization period (DIP), the fourth transistor T4 can apply the data initialization voltage VINT to the anode electrode in response to the data initialization gate signal GI with an active level L_ACT. Therefore, the voltage VANO at the anode electrode can be changed from the voltage VANO_EP at the anode electrode during the transmit period (EP) of the previous frame period to the data initialization voltage VINT. In other words, the voltage at the anode electrode can be initialized to the data initialization voltage VINT.

[0093] During the anode initialization period (AIP), the seventh transistor T7 can apply the anode initialization voltage VAINT to the anode electrode in response to the anode initialization gate signal GB with an effective level L_ACT. Therefore, the anode electrode voltage VANO can be changed from the data initialization voltage VINT to the anode initialization voltage VAINT. In other words, the anode electrode voltage can be initialized to the anode initialization voltage VAINT.

[0094] In this way, the voltage VANO at the anode electrode can be initialized multiple times.

[0095] During the anode initialization period (AIP), when the difference between the anode electrode voltage VANO_AIP and the anode initialization voltage VAINT is small (e.g., below a threshold or a set or predetermined threshold), the drain-source voltage of the seventh transistor T7 (e.g., the anode initialization transistor) can decrease. Therefore, the anode current IANO_AIP, which is the current flowing from the anode electrode to the anode initialization voltage line carrying the anode initialization voltage VAINT, can decrease. During the anode initialization period (AIP), when the anode current IANO_AIP is small (e.g., below a threshold or a set or predetermined threshold), the anode electrode voltage VANO can remain consistent and have a constant value.

[0096] The difference V1 between the data initialization voltage VINT and the anode initialization voltage VAINT can be less than the difference V2 between the anode electrode voltage VANO_EP and the anode initialization voltage VAINT during the transmission period EP. Therefore, during the data initialization period DIP, when no anode initialization operation is performed, the anode electrode voltage VANO can change from VANO_EP in the previous frame period's transmission period EP to the anode initialization voltage VAINT, and the anode current IANO_AIP can be relatively large. Consequently, the anode electrode voltage VANO may not remain consistent. In this case, a stain may be detected on the display panel 100. This stain can be referred to as a mura. In low grayscale, since the anode electrode voltage VANO in the previous frame period's transmission period EP is relatively small, the mura is more easily detected in low grayscale.

[0097] On the other hand, during the data initialization period (DIP), when the anode initialization operation is performed, the anode electrode voltage VANO can change from the data initialization voltage VINT to the anode initialization voltage VAINT, and the anode current IANO_AIP can be relatively small. Therefore, the anode electrode voltage VANO can remain consistent.

[0098] In this way, when the voltage VANO of the anode electrode is initialized multiple times, the voltage VANO of the anode electrode can remain consistent, and the display quality can be guaranteed.

[0099] Figure 10 It is shown Figure 1 A conceptual diagram of the driving frequency of the display panel 100.

[0100] Reference Figures 1 to 10The display panel 100 can be driven at a variable driving frequency. A first frame FR1 having a first driving frequency may include a first active period AC1 and a first blanking period BL1. A second frame FR2 having a second driving frequency different from the first driving frequency may include a second active period AC2 and a second blanking period BL2. A third frame FR3 having a third driving frequency different from the first and second driving frequencies may include a third active period AC3 and a third blanking period BL3.

[0101] The first effective time period AC1 can have the same length as the second effective time period AC2, and the first blanking time period BL1 can have a different length than the second blanking time period BL2.

[0102] The second effective time period AC2 can have the same length as the third effective time period AC3, and the second blanking time period BL2 can have a different length than the third blanking time period BL3.

[0103] The frame period of the display panel 100 driven by the variable drive frequency may include an addressing scan period in which data writing operations are performed and a self-scan period in which only transmission operations are performed without data writing operations. The addressing scan period may be arranged within the active periods AC1, AC2, and AC3. The self-scan period may be arranged within the blanking periods BL1, BL2, and BL3.

[0104] Figure 11 This indicates that when the transmission frequency is 480Hz... Figure 2 Timing diagram of the signals EM, GI, GB, and GW of pixel PX. Figure 12 This indicates that when the transmission frequency is 240Hz... Figure 2 Timing diagram of the signals EM, GI, GB, and GW of pixel PX.

[0105] Reference Figures 1 to 12 The display panel 100 can be driven at a variable driving frequency. According to some embodiments, the display panel 100 driven at a variable driving frequency can be driven in a cycle manner. Cyclic manner means performing the emission operation at a constant period. Therefore, in a display panel 100 driven in a cycle manner, non-uniformity can be identified based on the frequency of the emission operation.

[0106] The frame cycle of the display panel 100 driven in a cyclic manner may include an addressing scan period and a self-scanning period following the addressing scan period. Each of the addressing scan period and the self-scanning period may include a non-emission period NEP during which the light-emitting element EL does not emit light and an emission period EP during which the light-emitting element EL emits light.

[0107] As described above, the addressing scan period can be a period in which data write operations are performed, and the self-scan period can be a period in which no data write operations are performed and only transmit operations are performed. Therefore, data initialization operations, data write operations, and anode initialization operations can be performed in the non-transmit period NEP of the addressing scan period, and data initialization operations and anode initialization operations can be performed in the non-transmit period NEP of the self-scan period.

[0108] For example, refer to Figure 11 The display panel 100 can be driven at a maximum of 240Hz. When the display panel 100 is driven at a maximum of 240Hz, a transmission operation based on the transmission signal EM can be performed at 480Hz, an anode initialization operation based on the data initialization gate signal GI can be performed at 480Hz, and an anode initialization operation based on the anode initialization gate signal GB can be performed at 480Hz.

[0109] When the display panel 100 is driven at 240Hz, the data write gate signal GW can have an effective level L_ACT during the first duration DU1, the third duration DU3, the fifth duration DU5, and the seventh duration DU7, and a data write operation can be performed. Therefore, the first duration DU1, the third duration DU3, the fifth duration DU5, and the seventh duration DU7 can be addressing scan periods, and the second duration DU2, the fourth duration DU4, the sixth duration DU6, and the eighth duration DU8 can be self-scanning periods. Here, when the display panel 100 is driven at 240Hz and a transmit operation is performed at 480Hz, it can be said that the display panel 100 operates in two cycles.

[0110] When the display panel 100 is driven at 120Hz, the data write gate signal GW can have an active level L_ACT during the first duration DU1 and the fifth duration DU5, and a data write operation can be performed. Therefore, the first duration DU1 and the fifth duration DU5 can be address scan periods, and the second duration DU2 to the fourth duration DU4 and the sixth duration DU6 to the eighth duration DU8 can be self-scan periods. Here, when the display panel 100 is driven at 120Hz and the transmit operation is performed at 480Hz, it can be said that the display panel 100 operates in 4 cycles.

[0111] For example, refer to Figure 12The display panel 100 can be driven at a maximum of 120Hz. When the display panel 100 is driven at a maximum of 120Hz, a transmission operation based on the transmission signal EM can be performed at 240Hz, an anode initialization operation based on the data initialization gate signal GI can be performed at 240Hz, and an anode initialization operation based on the anode initialization gate signal GB can be performed at 240Hz.

[0112] Figure 13 It is shown Figure 1 A circuit diagram of an example pixel PX (pixel PX'). Although Figure 13 Various components in a pixel according to some embodiments are shown, but the embodiments of this disclosure are not limited thereto, and according to various embodiments, a pixel may include additional components or fewer components without departing from the spirit and scope of the embodiments of this disclosure.

[0113] Figure 14 It shows the driver Figure 13 A timing diagram of an example of pixel PX'.

[0114] Reference Figures 1 to 13 The display panel 100 may include pixels PX'. Each of the pixels PX' may include a first transistor T1 to a ninth transistor T9, a storage capacitor CST, a boost capacitor CBST, and a light-emitting element EL. However, this disclosure is not limited to... Figure 13 The pixel PX'. This disclosure can be applied to various embodiments.

[0115] The first transistor T1 may include a gate electrode connected to a first node N1, a first electrode connected to a second node N2, and a second electrode connected to a third node N3. According to some embodiments, the first transistor T1 may be a PMOS transistor. The first transistor T1 may generate a drive current based on the voltage of the first node N1 and the voltage of the second node N2. The first transistor T1 may be referred to as a drive transistor.

[0116] The second transistor T2 may include a gate electrode to which a data write gate signal GW is applied, a first electrode connected to a data line DL for transmitting data voltage VDATA, and a second electrode connected to a fourth node N4. According to some embodiments, the second transistor T2 may be a PMOS transistor. The second transistor T2 may apply the data voltage VDATA to the fourth node N4 in response to the data write gate signal GW. The second transistor T2 may be referred to as a data write transistor.

[0117] The third transistor T3 may include a gate electrode to which a compensation gate signal GC is applied, a first electrode connected to the first node N1, and a second electrode connected to the third node N3. According to some embodiments, the third transistor T3 may be a PMOS transistor. The third transistor T3 may be diode-connected to the first transistor T1 in response to the compensation gate signal GC. The third transistor T3 may be referred to as a compensation transistor.

[0118] The fourth transistor T4 may include a gate electrode to which a data initialization gate signal GI is applied, a first electrode to which a data initialization voltage VINT is applied, and a second electrode connected to the third node N3. According to some embodiments, the fourth transistor T4 may be a PMOS transistor. The fourth transistor T4 may apply the data initialization voltage VINT to the first transistor T1 in response to the data initialization gate signal GI. The fourth transistor T4 may be referred to as a data initialization transistor.

[0119] The fifth transistor T5 may include a gate electrode to which a first emitter signal EM1 is applied, a first electrode to which a high supply voltage ELVDD is applied, and a second electrode connected to a second node N2. According to some embodiments, the fifth transistor T5 may be a PMOS transistor. The fifth transistor T5 may be connected to a high supply voltage line transmitting the high supply voltage ELVDD and a second node N2 in response to the first emitter signal EM1. The fifth transistor T5 may be referred to as the first emitter transistor.

[0120] The sixth transistor T6 may include a gate electrode to which the second emitter signal EM2 is applied, a first electrode connected to the third node N3, and a second electrode connected to the fifth node N5. According to some embodiments, the sixth transistor T6 may be a PMOS transistor. The sixth transistor T6 may connect the third node N3 and the fifth node N5 in response to the second emitter signal EM2. The sixth transistor T6 may be referred to as the second emitter transistor.

[0121] The seventh transistor T7 may include a gate electrode to which an anode initialization gate signal GB is applied, a first electrode to which an anode initialization voltage VAINT is applied, and a second electrode connected to the fifth node N5. According to some embodiments, the seventh transistor T7 may be a PMOS transistor. The seventh transistor T7 may apply the anode initialization voltage VAINT to the fifth node N5 in response to the anode initialization gate signal GB. According to some embodiments, the data initialization voltage VINT may be greater than the anode initialization voltage VAINT. The seventh transistor T7 may be referred to as an anode initialization transistor.

[0122] The eighth transistor T8 may include a gate electrode to which an anode initialization gate signal GB is applied, a first electrode to which a bias voltage VOBS is applied, and a second electrode connected to the second node N2. According to some embodiments, the eighth transistor T8 may be a PMOS transistor. The eighth transistor T8 may apply the bias voltage VOBS to the second node N2 in response to the anode initialization gate signal GB. The eighth transistor T8 may be referred to as a bias transistor.

[0123] The ninth transistor T9 may include a gate electrode to which a compensation gate signal GC is applied, a first electrode to which a high supply voltage ELVDD is applied, and a second electrode connected to the fourth node N4. According to some embodiments, the ninth transistor T9 may be a PMOS transistor. The ninth transistor T9 may connect to the high supply voltage line transmitting the high supply voltage ELVDD and the fourth node N4 in response to the compensation gate signal GC. The ninth transistor T9 may be referred to as the second compensation transistor.

[0124] The storage capacitor CST may include a first electrode to which a high supply voltage ELVDD is applied and a second electrode connected to a fourth node N4. The storage capacitor CST can store the data voltage VDATA.

[0125] The boost capacitor CBST may include a first electrode connected to the fourth node N4 and a second electrode connected to the first node N1. The boost capacitor CBST can boost the voltage of the first node N1 to transmit the data voltage VDATA to the first node N1.

[0126] The light-emitting element EL may include an anode electrode connected to the fifth node N5 and a cathode electrode to which a low supply voltage ELVSS is applied. A drive current may be applied to the anode electrode, the voltage of the anode electrode may be determined based on the drive current, and the brightness of the light-emitting element EL may be determined based on the voltage of the anode electrode.

[0127] The frame period of a pixel PX can include a non-emission period (NEP) and an emission period (EP). The non-emission period (NEP) can be the period during which the light-emitting element (EL) does not emit light, and the emission period (EP) can be the period during which the light-emitting element (EL) emits light.

[0128] The non-emit phase (NEP) may include a data initialization phase (DIP), a data write compensation phase (DWCP) following the data initialization phase (DIP), and an anode initialization phase (AIP) following the data write compensation phase (DWCP). Here, the signals EM1, EM2, GI, GC, GW, and GB applied to pixel PX' may have an active level L_ACT and an inactive level L_INACT. The active level L_ACT is the level at which the transistor is turned on when signals EM1, EM2, GI, GC, GW, and GB are applied to the gate electrode of the transistor. The inactive level L_INACT is the level at which the transistor is turned off when signals EM1, EM2, GI, GC, GW, and GB are applied to the gate electrode of the transistor.

[0129] During the data initialization period (DIP), the first transmit signal EM1 can have an invalid level L_INACT, the second transmit signal EM2 can have an active level L_ACT, the data initialization gate signal GI can have an active level L_ACT, the compensation gate signal GC can have an active level L_ACT, the data write gate signal GW can have an invalid level L_INACT, and the anode initialization gate signal GB can have an invalid level L_INACT.

[0130] During the data write compensation period (DWCP), the first transmit signal EM1 can have an active level L_ACT, the second transmit signal EM2 can have an inactive level L_INACT, the data initialization gate signal GI can have an inactive level L_INACT, the compensation gate signal GC can have an active level L_ACT, the data write gate signal GW can have an active level L_ACT, and the anode initialization gate signal GB can have an inactive level L_INACT.

[0131] During the anode initialization period (AIP), the first transmit signal EM1 can have an invalid level L_INACT, the second transmit signal EM2 can have an invalid level L_INACT, the data initialization gate signal GI can have an invalid level L_INACT, the compensation gate signal GC can have an invalid level L_INACT, the data write gate signal GW can have an invalid level L_INACT, and the anode initialization gate signal GB can have an active level L_ACT.

[0132] During the transmit period EP, the first transmit signal EM1 can have an active level L_ACT, the second transmit signal EM2 can have an active level L_ACT, the data initialization gate signal GI can have an inactive level L_INACT, the compensation gate signal GC can have an inactive level L_INACT, the data write gate signal GW can have an inactive level L_INACT, and the anode initialization gate signal GB can have an inactive level L_INACT.

[0133] The voltage of the anode electrode can be initialized multiple times. Specifically, an anode initialization operation to initialize the voltage of the anode electrode can be performed during the data initialization period (DIP) and the anode initialization period (AIP). During the DIP, the anode initialization operation is performed so that the voltage of the anode electrode changes from the voltage of the anode electrode during the transmit period of the previous frame period to the data initialization voltage VINT. During the AIP, the anode initialization operation is performed so that the voltage of the anode electrode changes from the data initialization voltage VINT to the anode initialization voltage VAINT. Therefore, the voltage of the anode electrode can remain consistent.

[0134] In this way, when the voltage of the anode electrode is initialized multiple times, the voltage of the anode electrode can remain consistent, and the display quality can be guaranteed.

[0135] Figure 15 It is shown Figure 1 A circuit diagram of an example pixel PX (pixel PX''). Although Figure 15 Various components in a pixel according to some embodiments are shown, but the embodiments of this disclosure are not limited thereto, and according to various embodiments, a pixel may include additional components or fewer components without departing from the spirit and scope of the embodiments of this disclosure.

[0136] Reference Figures 1 to 15 The display panel 100 may include pixels PX''. Each of the pixels PX'' may include a first transistor T1 to a ninth transistor T9, a storage capacitor CST, and a light-emitting element EL. However, this disclosure is not limited to... Figure 15 The pixel PX''. This disclosure can be applied to various embodiments.

[0137] The first transistor T1 may include a gate electrode connected to a first node N1, a first electrode connected to a second node N2, and a second electrode connected to a third node N3. According to some embodiments, the first transistor T1 may be a PMOS transistor. The first transistor T1 may generate a drive current based on the voltage of the first node N1 and the voltage of the second node N2. The first transistor T1 may be referred to as a drive transistor.

[0138] The second transistor T2 may include a gate electrode to which a data write gate signal GW is applied, a first electrode connected to a data line DL for transmitting data voltage VDATA, and a second electrode connected to a second node N2. According to some embodiments, the second transistor T2 may be a PMOS transistor. The second transistor T2 may apply the data voltage VDATA to the second node N2 in response to the data write gate signal GW. The second transistor T2 may be referred to as a data write transistor.

[0139] The third transistor T3 may include a gate electrode to which a compensation gate signal GC is applied, a first electrode connected to the first node N1, and a second electrode connected to the third node N3. According to some embodiments, the third transistor T3 may be an NMOS transistor. The third transistor T3 may be diode-connected to the first transistor T1 in response to the compensation gate signal GC. The third transistor T3 may be referred to as a compensation transistor.

[0140] The fourth transistor T4 may include a gate electrode to which a data initialization gate signal GI is applied, a first electrode to which a data initialization voltage VINT is applied, and a second electrode connected to the third node N3. According to some embodiments, the fourth transistor T4 may be a PMOS transistor. The fourth transistor T4 may apply the data initialization voltage VINT to the first transistor T1 in response to the data initialization gate signal GI. The fourth transistor T4 may be referred to as a data initialization transistor.

[0141] The fifth transistor T5 may include a gate electrode to which an emitter signal EM(N) is applied, a first electrode to which a high supply voltage ELVDD is applied, and a second electrode connected to the second node N2. According to some embodiments, the fifth transistor T5 may be a PMOS transistor. The fifth transistor T5 may connect to the high supply voltage line transmitting the high supply voltage ELVDD and the second node N2 in response to the emitter signal EM(N). The fifth transistor T5 may be referred to as the first emitter transistor.

[0142] The sixth transistor T6 may include a gate electrode to which an emission signal EM(N) is applied, a first electrode connected to the third node N3, and a second electrode connected to the fourth node N4. According to some embodiments, the sixth transistor T6 may be a PMOS transistor. The sixth transistor T6 may connect the third node N3 and the fourth node N4 in response to the emission signal EM(N). The sixth transistor T6 may be referred to as the second emitter transistor.

[0143] The seventh transistor T7 may include a gate electrode to which an anode initialization gate signal GB is applied, a first electrode to which an anode initialization voltage VAINT is applied, and a second electrode connected to the fourth node N4. According to some embodiments, the seventh transistor T7 may be a PMOS transistor. The seventh transistor T7 may apply the anode initialization voltage VAINT to the fourth node N4 in response to the anode initialization gate signal GB. According to some embodiments, the data initialization voltage VINT may be greater than the anode initialization voltage VAINT. The seventh transistor T7 may be referred to as an anode initialization transistor.

[0144] The eighth transistor T8 may include a gate electrode to which an anode initialization gate signal GB is applied, a first electrode to which a bias voltage VOBS is applied, and a second electrode connected to the second node N2. According to some embodiments, the eighth transistor T8 may be a PMOS transistor. The eighth transistor T8 may apply the bias voltage VOBS to the second node N2 in response to the anode initialization gate signal GB. The eighth transistor T8 may be referred to as a bias transistor.

[0145] The ninth transistor T9 may include a gate electrode to which a data initialization gate signal GI is applied, a first electrode to which a data initialization voltage VINT is applied, and a second electrode connected to the fourth node N4. According to some embodiments, the ninth transistor T9 may be a PMOS transistor. The ninth transistor T9 may apply the data initialization voltage VINT to the fourth node N4 in response to the data initialization gate signal GI. The ninth transistor T9 may be referred to as the second data initialization transistor.

[0146] The storage capacitor CST may include a first electrode to which a high supply voltage ELVDD is applied and a second electrode connected to a first node N1. The storage capacitor CST can store the data voltage VDATA.

[0147] The light-emitting element EL may include an anode electrode connected to the fourth node N4 and a cathode electrode to which a low supply voltage ELVSS is applied. A drive current may be applied to the anode electrode, the voltage of the anode electrode may be determined based on the drive current, and the brightness of the light-emitting element EL may be determined based on the voltage of the anode electrode.

[0148] In addition to the fifth transistor T5 and the sixth transistor T6 turning on in response to the same emitter signal EM, a ninth transistor T9 has also been added. Figure 15 The pixel PX'' is similar in configuration and operation to Figure 2 The pixel values ​​PX are basically the same. Therefore, the description of repeated operations is omitted.

[0149] exist Figure 15In pixel PX'', during the data initialization period, the ninth transistor T9 can be turned on in response to a data initialization gate signal GI with an effective level, so as to apply the data initialization voltage VINT to the fourth node N4. Therefore, during the data initialization period, the voltage of the fourth node N4 can be initialized from the voltage of the anode electrode of the light-emitting element EL during the emission period of the previous frame period to the data initialization voltage VINT.

[0150] During the anode initialization period, the seventh transistor T7 can be turned on in response to the anode initialization gate signal GB with an active level, so as to apply the anode initialization voltage VAINT to the fourth node N4. Therefore, the voltage of the fourth node N4 can change from the data initialization voltage VINT to the anode initialization voltage VAINT. In this case, the sixth transistor T6 is turned off in response to the transmit signal EM with an inactive level L_INACT, so that the anode initialization voltage VAINT is not applied to the third node N3 and does not affect the voltage of the third node N3.

[0151] In this way, when the voltage of the anode electrode is initialized multiple times, the voltage of the anode electrode can remain consistent, and the display quality can be guaranteed.

[0152] Figure 16 This is a block diagram showing the electronic device 1000. Figure 17 It is shown Figure 16 The diagram shows an embodiment of the electronic device 1000 implemented as a smartphone.

[0153] Reference Figure 16 and Figure 17 The electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output (I / O) device 1040, a power supply 1050, and a display device 1060. The display device 1060 may be... Figure 1 The display device 10. In addition, the electronic device 1000 may also include multiple ports for communicating with video cards, sound cards, memory cards, universal serial bus (USB) devices, other electronic devices, etc.

[0154] According to some embodiments, such as Figure 17 As shown, the electronic device 1000 can be implemented as a smartphone. However, the electronic device 1000 is not limited to this. For example, the electronic device 1000 can be implemented as a cellular phone, video phone, smart tablet, smartwatch, tablet PC, car navigation system, computer monitor, laptop computer, head-mounted display (HMD) device, etc.

[0155] Processor 1010 can perform various computing functions. Processor 1010 can be a microprocessor, central processing unit (CPU), application processor (AP), etc. Processor 1010 can be connected to other components via address bus, control bus, data bus, etc. In addition, processor 1010 can be connected to an expansion bus (such as a peripheral component interconnect (PCI) bus).

[0156] The memory device 1020 can store data for the operation of the electronic device 1000. For example, the memory device 1020 may include at least one non-volatile memory device (such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase-change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano-floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, a ferroelectric random access memory (FRAM) device, etc.) and / or at least one volatile memory device (such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a mobile DRAM device, etc.).

[0157] Storage device 1030 may include solid-state drive (SSD) devices, hard disk drive (HDD) devices, CD-ROM devices, etc.

[0158] I / O device 1040 may include input devices such as a keyboard, keypad, mouse, touchpad, touchscreen, etc., and output devices such as a printer, speaker, etc. In some embodiments, I / O device 1040 may include display device 1060.

[0159] Power supply 1050 can provide power for the operation of electronic device 1000.

[0160] The display device 1060 can be connected to other components via a bus or other communication link.

[0161] The embodiments of this disclosure can be applied to any display device and any electronic device, including a touch panel. For example, the embodiments of this disclosure can be applied to mobile phones, smartphones, tablet computers, digital televisions (TVs), 3D TVs, personal computers (PCs), home appliances, laptop computers, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, music players, portable game consoles, navigation devices, etc.

[0162] The foregoing is illustrative of some embodiments of this disclosure and should not be construed as limiting it. Although some aspects of embodiments of this disclosure have been described, it will be readily understood by those skilled in the art that many modifications may be made to the embodiments without substantially departing from the novel teachings and advantages of this disclosure. Therefore, all such modifications are intended to be included within the scope of this disclosure as defined in the claims. In the claims, the device plus function clause is intended to cover not only structural equivalents but also equivalent structures as described herein. Therefore, it will be understood that the foregoing is illustrative of this disclosure and should not be construed as limiting it to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims. This disclosure is defined by the appended claims and their equivalents included therein.

Claims

1. A pixel driven based on a frame period including an addressing scan period and a self-scanning period, wherein, The pixels include: The data write transistor is configured to output a data voltage in response to a data write gate signal; A driving transistor is configured to generate a driving current based on the data voltage; The light-emitting element includes a cathode electrode and an anode electrode configured to receive the driving current; A data initialization transistor is configured to apply a data initialization voltage to the drive transistor in response to a data initialization gate signal; and An anode initialization transistor is configured to apply an anode initialization voltage to the anode electrode in response to an anode initialization gate signal. Each of the addressing scan period and the self-scanning period includes a non-emission period during which the light-emitting element does not emit light and an emission period during which the light-emitting element emits light. The non-emission period includes a data initialization period and an anode initialization period following the data initialization period. The voltage of the anode electrode is initialized to the data initialization voltage during the data initialization period, and is also initialized to the anode initialization voltage during the anode initialization period.

2. The pixel according to claim 1, wherein, The driving transistor is a PMOS transistor.

3. The pixel according to claim 1, wherein, When the difference between the voltage of the anode electrode and the anode initialization voltage is less than a threshold, the current flowing from the anode electrode to the anode initialization voltage line configured to transmit the anode initialization voltage decreases.

4. The pixel according to claim 3, wherein, The data initialization voltage is greater than the anode initialization voltage.

5. The pixel according to claim 4, wherein, The difference between the data initialization voltage and the anode initialization voltage is less than the difference between the voltage of the anode electrode during the emission period and the anode initialization voltage.

6. The pixel according to claim 1, wherein, The addressing scan period also includes a data writing period between the data initialization period and the anode initialization period, and During the data writing period, the data writing transistor is configured to apply the data voltage to the driving transistor in response to the data writing gate signal.

7. The pixel according to claim 1, wherein, The pixel further includes: an emitting transistor configured to connect the data initialization transistor and the anode electrode in response to an emitting signal, and The emitter transistor is turned on during the data initialization period to connect the data initialization transistor and the anode electrode, and is turned off during the anode initialization period to electrically disconnect the data initialization transistor and the anode electrode.

8. The pixel according to claim 7, wherein, The driving transistor includes a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node. The data write transistor includes a gate electrode to which the data write gate signal is applied, a first electrode connected to a data line transmitting the data voltage, and a second electrode connected to the second node. The data initialization transistor includes a gate electrode to which the data initialization gate signal is applied, a first electrode to which the data initialization voltage is applied, and a second electrode connected to the third node. The emitter transistor includes a gate electrode to which the emitter signal is applied, a first electrode connected to the third node, and a second electrode connected to the fourth node. The anode initialization transistor includes a gate electrode to which the anode initialization gate signal is applied, a first electrode to which the anode initialization voltage is applied, and a second electrode connected to the fourth node. The light-emitting element includes the anode electrode connected to the fourth node and the cathode electrode to which a low power supply voltage is applied.

9. The pixel according to claim 8, wherein, The pixels also include: A compensation transistor is configured such that a diode is connected to the driving transistor in response to a compensation gate signal; The second transmitting transistor is configured to connect the high power supply voltage line transmitting the high power supply voltage and the first electrode of the driving transistor in response to the second transmitting signal; A bias transistor, configured to apply a bias voltage to the first electrode of the driving transistor in response to the anode initialization gate signal; and A storage capacitor is configured to store the data voltage, and The compensation transistor includes a gate electrode to which the compensation gate signal is applied, a first electrode connected to the first node, and a second electrode connected to the third node. The second emitter transistor includes a gate electrode configured to receive the second emitter signal, a first electrode configured to receive the high power supply voltage, and a second electrode connected to the second node. The bias transistor includes a gate electrode configured to receive the anode initialization gate signal, a first electrode configured to receive the bias voltage, and a second electrode connected to the second node. The storage capacitor includes a first electrode configured to receive the high power supply voltage and a second electrode connected to the first node.

10. The pixel according to claim 7, wherein, The driving transistor includes a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node. The data write transistor includes a gate electrode configured to receive the data write gate signal, a first electrode connected to a data line configured to transmit the data voltage, and a second electrode connected to a fourth node. The data initialization transistor includes a gate electrode configured to receive the data initialization gate signal, a first electrode configured to receive the data initialization voltage, and a second electrode connected to the third node. The anode initialization transistor includes a gate electrode configured to receive the anode initialization gate signal, a first electrode configured to receive the anode initialization voltage, and a second electrode connected to the fifth node. The transmitting transistor includes a gate electrode configured to receive the transmitted signal, a first electrode connected to the third node, and a second electrode connected to the fifth node. The light-emitting element includes the anode electrode connected to the fifth node and the cathode electrode configured to receive a low power supply voltage.

11. The pixel according to claim 10, wherein, The pixels also include: A compensation transistor is configured such that a diode is connected to the driving transistor in response to a compensation gate signal; The second transmitting transistor is configured to connect, in response to a second transmitting signal, a high power supply voltage line configured to transmit a high power supply voltage and the first electrode of the driving transistor; A bias transistor is configured to apply a bias voltage to the first electrode of the drive transistor in response to the anode initialization gate signal; The second compensation transistor is configured to connect the high power supply voltage line and the second electrode of the data write transistor in response to the compensation gate signal; A storage capacitor is configured to store the data voltage; and A boost capacitor is configured to boost the voltage of the first node, and The compensation transistor includes a gate electrode configured to receive the compensation gate signal, a first electrode connected to the first node, and a second electrode connected to the third node. The second emitter transistor includes a gate electrode configured to receive the second emitter signal, a first electrode configured to receive the high power supply voltage, and a second electrode connected to the second node. The bias transistor includes a gate electrode configured to receive the anode initialization gate signal, a first electrode configured to receive the bias voltage, and a second electrode connected to the second node. The storage capacitor includes a first electrode configured to receive the high power supply voltage and a second electrode connected to the fourth node, and The boost capacitor includes a first electrode connected to the fourth node and a second electrode connected to the first node.

12. The pixel according to claim 1, wherein, The pixels also include: A first transmitting transistor is configured to connect, in response to a transmitting signal, a high power supply voltage line configured to transmit a high power supply voltage and a first electrode of the driving transistor; and The second emitter transistor is configured to connect the data initialization transistor and the anode electrode in response to the emitter signal, and The driving transistor includes a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node. The data write transistor includes a gate electrode to which the data write gate signal is applied, a first electrode connected to a data line configured to transmit the data voltage, and a second electrode connected to the second node. The data initialization transistor includes a gate electrode configured to receive the data initialization gate signal, a first electrode configured to receive the data initialization voltage, and a second electrode connected to the third node. The first emitter transistor includes a gate electrode configured to receive the emitted signal, a first electrode configured to receive the high power supply voltage, and a second electrode connected to the second node. The second transmitting transistor includes a gate electrode configured to receive the transmitted signal, a first electrode connected to the third node, and a second electrode connected to the fourth node. The anode initialization transistor includes a gate electrode configured to receive the anode initialization gate signal, a first electrode configured to receive the anode initialization voltage, and a second electrode connected to the fourth node. The light-emitting element includes the anode electrode connected to the fourth node and the cathode electrode configured to receive a low power supply voltage.

13. The pixel according to claim 12, wherein, The pixels also include: A compensation transistor is configured such that a diode is connected to the driving transistor in response to a compensation gate signal; A bias transistor is configured to apply a bias voltage to the first electrode of the drive transistor in response to the anode initialization gate signal; A second data initialization transistor is configured to apply the data initialization voltage to the anode electrode in response to the data initialization gate signal; and A storage capacitor is configured to store the data voltage, and The compensation transistor includes a gate electrode configured to receive the compensation gate signal, a first electrode connected to the first node, and a second electrode connected to the third node. The bias transistor includes a gate electrode configured to receive the anode initialization gate signal, a first electrode configured to receive the bias voltage, and a second electrode connected to the second node. The second data initialization transistor includes a gate electrode configured to receive the data initialization gate signal, a first electrode configured to receive the data initialization voltage, and a second electrode connected to the fourth node.

14. A display device, the display device comprising: The display panel includes pixels configured to be driven based on a frame period including an addressing scan period and a self-scan period; as well as A display panel driver is configured to drive the display panel. The pixels include: The data write transistor is configured to output a data voltage in response to a data write gate signal; A driving transistor is configured to generate a driving current based on the data voltage; The light-emitting element includes a cathode electrode and an anode electrode configured to receive the driving current; A data initialization transistor is configured to apply a data initialization voltage to the drive transistor in response to a data initialization gate signal; and An anode initialization transistor is configured to apply an anode initialization voltage to the anode electrode in response to an anode initialization gate signal. Each of the addressing scan period and the self-scanning period includes a non-emission period during which the light-emitting element does not emit light and an emission period during which the light-emitting element emits light. The non-emission period includes a data initialization period and an anode initialization period following the data initialization period. The voltage of the anode electrode is initialized to the data initialization voltage during the data initialization period, and is also initialized to the anode initialization voltage during the anode initialization period.

15. The display device according to claim 14, wherein, The driving transistor is a PMOS transistor.

16. The display device according to claim 14, wherein, When the difference between the voltage of the anode electrode and the anode initialization voltage is less than a threshold, the current flowing from the anode electrode to the anode initialization voltage line that transmits the anode initialization voltage decreases.

17. The display device according to claim 16, wherein, The data initialization voltage is greater than the anode initialization voltage.

18. The display device according to claim 17, wherein, The difference between the data initialization voltage and the anode initialization voltage is less than the difference between the voltage of the anode electrode during the emission period and the anode initialization voltage.

19. The display device according to claim 14, wherein, The addressing scan period also includes a data writing period between the data initialization period and the anode initialization period, and During the data writing period, the data writing transistor is configured to apply the data voltage to the driving transistor in response to the data writing gate signal.

20. An electronic device, the electronic device comprising: The display panel includes pixels configured to be driven based on a frame period including an addressing scan period and a self-scan period; A display panel driver is configured to drive the display panel; as well as The power supply is configured to supply power to the display panel and the display panel driver. The pixels include: The data write transistor is configured to output a data voltage in response to a data write gate signal; A driving transistor is configured to generate a driving current based on the data voltage; The light-emitting element includes a cathode electrode and an anode electrode to which the driving current is applied; A data initialization transistor is configured to apply a data initialization voltage to the drive transistor in response to a data initialization gate signal; and An anode initialization transistor is configured to apply an anode initialization voltage to the anode electrode in response to an anode initialization gate signal. Each of the addressing scan period and the self-scanning period includes a non-emission period during which the light-emitting element does not emit light and an emission period during which the light-emitting element emits light. The non-emission period includes a data initialization period and an anode initialization period following the data initialization period. The voltage of the anode electrode is initialized to the data initialization voltage during the data initialization period, and is also initialized to the anode initialization voltage during the anode initialization period.

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