Display panel and display device

Abstract

The invention relates to the technical field of display, and provides a display panel and a display device.The display panel comprises a display area, and the display area comprises a first pixel driving circuit integration area, a first gate driving circuit integration area and a second pixel driving circuit integration area which are sequentially distributed in the first direction; the display panel further comprises a substrate, a plurality of pixel driving circuits, data lines and one or more gate driving circuits. At least part of the pixel driving circuits are located in the first pixel driving circuit integration area and the second pixel driving circuit integration area; orthographic projections of the data lines on the substrate extend along a second direction, and the second direction intersects with the first direction; the gate drive circuit is used for providing gate drive signals for the pixel drive circuit, the one or more gate drive circuits comprise a first gate drive circuit, and the first gate drive circuit is located in the first gate drive circuit integration area. The display panel provided by the invention can realize a narrow frame design.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0002] In related technologies, gate driving circuits need to be set at the left and right bezel positions of the display panel, making it difficult to achieve a narrow bezel design.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] According to one aspect of this disclosure, a display panel is provided, wherein the display panel includes a display area, the display area including a first pixel driving circuit integration area, a first gate driving circuit integration area, and a second pixel driving circuit integration area, the first pixel driving circuit integration area, the first gate driving circuit integration area, and the second pixel driving circuit integration area are sequentially distributed in a first direction.

[0005] The display panel also includes:

[0006] Substrate;

[0007] A plurality of pixel driving circuits, at least some of which are located in the first pixel driving circuit integration area and at least some of which are located in the second pixel driving circuit integration area;

[0008] A data line is used to provide data signals to the pixel driving circuit. The orthographic projection of the data line on the substrate extends along a second direction, which intersects with the first direction.

[0009] One or more gate driving circuits, the gate driving circuits being used to provide gate driving signals to the pixel driving circuits, the one or more gate driving circuits including a first gate driving circuit, the first gate driving circuit being located in the first gate driving circuit integration area.

[0010] In one exemplary embodiment of this disclosure, the display area includes a corner area located at the corner of the display area, the corner area having an arc-shaped edge, and the first gate driving circuit integration area located outside the corner area.

[0011] In one exemplary embodiment of this disclosure, the display area further includes a first gate line bridging area and a second gate line bridging area, wherein the first gate line bridging area is located between the first pixel driving circuit integrated area and the first gate driving circuit integrated area, and the second gate line bridging area is located between the second pixel driving circuit integrated area and the first gate driving circuit integrated area.

[0012] The display panel also includes:

[0013] Multiple gate lines are provided, the orthographic projections of which on the substrate extend along the first direction and are spaced apart along the second direction. Each gate line includes a first gate line segment and a second gate line segment. The first gate line segment is at least partially located in the first pixel driving circuit integration area and is used to provide a gate driving signal to the pixel driving circuit in the first pixel driving circuit integration area. The second gate line segment is at least partially located in the second pixel driving circuit integration area and is used to provide a gate driving signal to the pixel driving circuit in the second pixel driving circuit integration area.

[0014] The first grid line bridging portion is located in the first grid line bridging area, and the first grid line bridging portion connects one or more identical first grid line segments distributed along the second direction.

[0015] The second grid line bridging part is located in the second grid line bridging area, and the second grid line bridging part connects one or more identical second grid line segments distributed along the second direction;

[0016] A bridging wire extends along the first direction on the substrate through its orthogonal projection. The bridging wire is at least partially located in the first gate drive circuit integration area. The bridging wire connects the first gate line bridging portion and the second gate line bridging portion to connect the first gate line segment and the second gate line segment in the same gate line. The bridging wire is also connected to the signal output terminal of the first gate drive circuit.

[0017] In one exemplary embodiment of this disclosure, the pixel driving circuit includes a plurality of transistors, and the display panel further includes:

[0018] A first source / drain layer is located on one side of the substrate. The first source / drain layer includes a circuit bridging portion, which is connected to different transistors through vias.

[0019] The first gate line bridging portion and the second gate line bridging portion are located in the first source / drain layer.

[0020] In one exemplary embodiment of this disclosure, the display panel further includes:

[0021] The second source / drain layer is located on the side of the first source / drain layer away from the substrate. The bridging wire is located in the second source / drain layer and is connected to the first gate line bridging portion and the second gate line bridging portion through vias.

[0022] In one exemplary embodiment of this disclosure, the display panel includes a plurality of first gate line bridging portions and a plurality of second gate line bridging portions;

[0023] At least a portion of the first gate line bridging portions have their orthographic projections on the substrate disposed opposite each other in the first direction, and the orthographic projections of the plurality of first gate line bridging portions disposed opposite each other in the first direction are distributed at intervals along the first direction.

[0024] At least a portion of the second gate line bridging portions have their orthographic projections on the substrate disposed opposite each other in the first direction, and the orthographic projections of the plurality of second gate line bridging portions disposed opposite each other in the first direction are distributed at intervals along the first direction.

[0025] In one exemplary embodiment of this disclosure, the display panel further includes:

[0026] A first signal line extends along a second direction from its orthogonal projection onto the substrate. The first signal line is used to provide a clock signal or a power signal to the first gate driving circuit. The first signal line is located in the integrated area of ​​the first gate driving circuit.

[0027] In one exemplary embodiment of this disclosure, the pixel driving circuit includes driving transistors, the first gate driving circuit includes a plurality of transistors, the display area further includes a first wiring area located between the first pixel driving circuit integration area and the second pixel driving circuit integration area, and the display panel further includes:

[0028] A first signal line is used to provide a clock signal or a power signal to the first gate drive circuit, and the first signal line is located in the first trace area.

[0029] A shielding layer is located on one side of the substrate. The shielding layer includes a plurality of first shielding portions and a second shielding portion, and the plurality of first shielding portions are arrayed in the first direction and the second direction.

[0030] The first blocking portion is provided in the first pixel driving circuit integration area, the second pixel driving circuit integration area, and the first wiring area. The orthographic projection of the first blocking portion in the first pixel driving circuit integration area and the second pixel driving circuit integration area on the substrate and the orthographic projection of the channel area of ​​the driving transistor in the pixel driving circuit on the substrate at least partially overlap.

[0031] The second shielding portion is located in the first gate drive circuit integration area, and the orthographic projection of the second shielding portion on the substrate and the orthographic projection of the channel region of at least a portion of the transistors in the first gate drive circuit on the substrate at least partially overlap.

[0032] In one exemplary embodiment of this disclosure, the orthographic projection of the second shielding portion on the substrate extends along the second direction, and a plurality of first shielding portions and second shielding portions are interconnected.

[0033] In one exemplary embodiment of this disclosure, the display panel further includes:

[0034] A plurality of light-emitting units, at least some of which are located in the first pixel driving circuit integration area and the second pixel driving circuit integration area respectively, and at least some of which are located in the first gate driving circuit integration area;

[0035] An electrical connection layer is located on one side of the substrate. The electrical connection layer includes electrical connection lines. The light-emitting unit located in the first gate driving circuit integration area is connected to the pixel driving circuit located in the first pixel driving circuit integration area and / or the second pixel driving circuit integration area through the electrical connection lines.

[0036] In an exemplary embodiment of this disclosure, the second direction is a column direction, and the display panel further includes a virtual pixel driving circuit group, which includes one or more columns of virtual pixel driving circuits. The virtual pixel driving circuit does not drive the light-emitting unit to emit light.

[0037] The virtual pixel driving circuit group is located in the first pixel driving circuit integration area and / or the second pixel driving circuit integration area;

[0038] The display panel also includes:

[0039] Multiple light-emitting units, at least some of which are located in the first pixel driving circuit integration area and the second pixel driving circuit integration area respectively;

[0040] An electrical connection layer is located on one side of the substrate, and the electrical connection layer includes electrical connection lines;

[0041] The light-emitting unit located in the area where the virtual pixel driving circuit group is located is connected to the pixel driving circuit located in the first pixel driving circuit integration area and / or the second pixel driving circuit integration area through the electrical connection line.

[0042] In one exemplary embodiment of this disclosure, the display panel further includes:

[0043] The third source / drain layer is located on one side of the substrate. The third source / drain layer includes multiple data lines and multiple first power lines. The first power lines are used to provide power signals to the pixel driving circuit.

[0044] Wherein, at least a portion of the data lines and the first power line are located in the first pixel driving circuit integration area and the second pixel driving circuit integration area, and at least a portion of the data lines and the first power line are located in the first gate driving circuit integration area.

[0045] In one exemplary embodiment of this disclosure, the display panel further includes:

[0046] An electrical connection layer is located on one side of the substrate, and the electrical connection layer includes multiple electrical connection lines;

[0047] An electrode layer is located on the side of the electrical connection layer opposite to the substrate. The electrode layer includes a plurality of electrode portions, which are used to form the first electrode of the light-emitting unit. The electrode portions are connected to the pixel driving circuit through the electrical connection line.

[0048] Wherein, the first pixel driving circuit integration area and the second pixel driving circuit integration area form a pixel driving circuit integration area, and the extension length of the electrical connection line connected to the electrode portion located in the first gate driving circuit integration area is greater than the extension length of the electrical connection line connected to the electrode portion located in the pixel driving circuit integration area.

[0049] The area of ​​the electrode portion located in the first gate driving circuit integration area projected onto the substrate is smaller than the area of ​​the electrode portion located in the pixel driving circuit integration area projected onto the substrate.

[0050] In one exemplary embodiment of this disclosure, the first gate driving circuit includes a plurality of shift register units, which are distributed along the second direction.

[0051] According to one aspect of this disclosure, a display device is provided, wherein the display device includes the display panel described above.

[0052] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0053] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0054] Figure 1 This is a schematic diagram of the structure of an exemplary embodiment of the display panel disclosed herein;

[0055] Figure 2 This is a partial structural schematic diagram of a display panel in an exemplary embodiment of the present disclosure;

[0056] Figure 3 This is an equivalent circuit diagram of the pixel driving circuit in the display panel of this disclosure;

[0057] Figure 4 for Figure 3 The timing diagram of some nodes in an exemplary embodiment of the pixel driving circuit shown is as follows;

[0058] Figure 5 This is a schematic diagram of the shift register unit in the gate drive circuit of this disclosure;

[0059] Figure 6 This is a structural layout diagram of an exemplary embodiment of the display panel disclosed herein;

[0060] Figure 7 for Figure 6 Structural layout of the middle shielding layer;

[0061] Figure 8 for Figure 6 Structural layout of the first active layer;

[0062] Figure 9 for Figure 6 The structural layout of the first gate layer;

[0063] Figure 10 for Figure 6 The structural layout of the second gate layer;

[0064] Figure 11 for Figure 6 Structural layout of the second active layer;

[0065] Figure 12 for Figure 6 The structural layout of the third gate layer;

[0066] Figure 13 for Figure 6Structural layout of the first source / drain layer;

[0067] Figure 14 for Figure 6 Structural layout of the second source / drain layer;

[0068] Figure 15 for Figure 6 Structural layout of the third source / drain layer;

[0069] Figure 16 for Figure 6 Structural layout of the electrical interconnect layer;

[0070] Figure 17 for Figure 6 Structural layout of the middle electrode layer;

[0071] Figure 18 for Figure 6 Structural layout of the middle shielding layer and the first active layer;

[0072] Figure 19 for Figure 6 The structural layout of the middle shielding layer, the first active layer, and the first gate layer;

[0073] Figure 20 for Figure 6 The structural layout of the middle shielding layer, the first active layer, the first gate layer, and the second gate layer;

[0074] Figure 21 for Figure 6 The structural layout of the middle shielding layer, the first active layer, the first gate layer, the second gate layer, and the second active layer;

[0075] Figure 22 for Figure 6 The structural layout of the middle shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, and the third gate layer;

[0076] Figure 23 for Figure 6 The structural layout of the middle shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, and the first source / drain layer;

[0077] Figure 24 for Figure 6 The structural layout of the middle shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, the first source / drain layer, and the second source / drain layer;

[0078] Figure 25 for Figure 6 The structural layout of the middle shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, the first source / drain layer, the second source / drain layer, and the third source / drain layer;

[0079] Figure 26 for Figure 6 The structural layout of the middle shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, the first source / drain layer, the second source / drain layer, the third source / drain layer, and the electrical connection layer;

[0080] Figure 27 for Figure 6 The image shown is a magnified view of a portion of the display panel, BB.

[0081] Figure 28 for Figure 27 Structural layout of the middle shielding layer;

[0082] Figure 29 for Figure 27 Structural layout of the first active layer;

[0083] Figure 30 for Figure 27 The structural layout of the first gate layer;

[0084] Figure 31 for Figure 27 The structural layout of the second gate layer;

[0085] Figure 32 for Figure 27 Structural layout of the second active layer;

[0086] Figure 33 for Figure 27 The structural layout of the third gate layer;

[0087] Figure 34 for Figure 27 Structural layout of the first source / drain layer;

[0088] Figure 35 for Figure 27 Structural layout of the second source / drain layer;

[0089] Figure 36 for Figure 27 Structural layout of the third source / drain layer;

[0090] Figure 37 for Figure 27 Structural layout of the electrical interconnect layer;

[0091] Figure 38 for Figure 27 Structural layout of the middle electrode layer;

[0092] Figure 39 for Figure 27 Structural layout of the middle shielding layer and the first active layer;

[0093] Figure 40 for Figure 27 The structural layout of the middle shielding layer, the first active layer, and the first gate layer;

[0094] Figure 41 for Figure 27 The structural layout of the middle shielding layer, the first active layer, the first gate layer, and the second gate layer;

[0095] Figure 42 for Figure 27 The structural layout of the middle shielding layer, the first active layer, the first gate layer, the second gate layer, and the second active layer;

[0096] Figure 43 for Figure 27 The structural layout of the middle shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, and the third gate layer;

[0097] Figure 44 for Figure 27 The structural layout of the middle shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, and the first source / drain layer;

[0098] Figure 45 for Figure 27 The structural layout of the middle shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, the first source / drain layer, and the second source / drain layer;

[0099] Figure 46 for Figure 27 The structural layout of the middle shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, the first source / drain layer, the second source / drain layer, and the third source / drain layer;

[0100] Figure 47 for Figure 27 The structural layout of the middle shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, the first source / drain layer, the second source / drain layer, the third source / drain layer, and the electrical connection layer;

[0101] Figure 48 for Figure 27 The image shows a partial sectional view of the display panel cut along the dashed line DD.

[0102] Figure 49 This is a structural layout of the electrical connection layer and electrode layer in another exemplary embodiment of the display panel disclosed herein;

[0103] Figure 50 This is a schematic diagram of another exemplary embodiment of the display panel disclosed herein. Detailed Implementation

[0104] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore their detailed description will be omitted.

[0105] The terms “a,” “one,” and “the” are used to indicate the existence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended meaning of inclusion and that there may be other elements / components / etc. in addition to the listed elements / components / etc.

[0106] This exemplary embodiment provides a display panel, such as Figure 1 The diagram shown is a schematic representation of an exemplary embodiment of the display panel disclosed herein. The display panel includes a display area AA, which comprises a first pixel driving circuit integration area AA1, a first gate driving circuit integration area AA2, and a second pixel driving circuit integration area AA3, sequentially distributed along a first direction X. The display panel also includes a substrate, a plurality of pixel driving circuits Pix, a data line Da, and one or more gate driving circuits GOA. At least some of the pixel driving circuits Pix are located in the first pixel driving circuit integration area AA1, and at least some of the pixel driving circuits Pix are located in the second pixel driving circuit integration area AA3. The data line Da is used to provide data signals to the pixel driving circuits Pix. The orthogonal projection of the data line Da onto the substrate extends along a second direction Y, which intersects with the first direction X. For example, the first direction X can be a row direction, and the second direction can be a column direction. The gate driving circuit GOA is used to provide gate driving signals to the pixel driving circuits Pix. One or more gate driving circuits GOA include a first gate driving circuit GOA1, which is located in the first gate driving circuit integration area AA2.

[0107] This exemplary embodiment can compress the pixel driving circuit in the first direction X, thereby reserving a first gate driving circuit integration area AA2 in the display area for integrating the first gate driving circuit. Meanwhile, the first gate driving circuit integration area AA2 still contains light-emitting units, which can be connected to the pixel driving circuits in the first pixel driving circuit integration area AA1 and / or the second pixel driving circuit integration area AA3. This configuration enables an extremely narrow bezel design for the display panel.

[0108] like Figure 2 The diagram shown is a partial structural schematic of a display panel in an exemplary embodiment of this disclosure. Figure 2The area shown is the display area. In this exemplary embodiment, multiple columns of pixel driving circuits Pix form a pixel driving circuit group Pixz. This exemplary embodiment can compress the pixel driving circuit group Pixz as a unit in the first direction X. The space formed by the compression of part of the pixel driving circuit group Pixz is used to integrate the first gate driving circuit, and the space formed by the compression of part of the pixel driving circuit group Pixz can be used to integrate the virtual pixel driving circuit Pid. The virtual pixel driving circuit Pid is not connected to the light-emitting unit. This setting can control the distance between the pixel driving circuit and the light-emitting unit within a certain range. The virtual pixel driving circuit Pid can be used to adjust the transmittance and uniformity of the electric field environment at different positions of the display panel. One or more columns of virtual pixel driving circuits Pid can be set in the pixel driving circuit group Pixz.

[0109] In this exemplary embodiment, as Figure 2 As shown, the space created by compressing the pixel driving circuit group Pixz is located at the middle position of the pixel driving circuit group Pixz in the first direction. It should be understood that, in other exemplary embodiments, the space created by compressing the pixel driving circuit group Pixz may also be located at either side of the pixel driving circuit group Pixz in the first direction. Furthermore, in other exemplary embodiments, the space formed by partially compressing the pixel driving circuit group Pixz may also be used to integrate a virtual first gate driving circuit, which does not provide gate driving signals to the pixel driving circuit.

[0110] In this exemplary embodiment, as Figure 2 As shown, the pixel driving circuit group Pixz may include 8 columns of pixel driving circuits, which compress the space corresponding to two columns of pixel driving circuits. It should be understood that in other exemplary embodiments, the pixel driving circuit group Pixz may include other numbers of columns of pixel driving circuits, and the pixel driving circuit group Pixz may also compress the space corresponding to other numbers of columns of pixel driving circuits.

[0111] In this exemplary embodiment, as Figure 1 As shown, the first gate driving circuit integration area AA2 integrates two first gate driving circuits GOA1, and the different first gate driving circuits are used to provide gate driving signals to different transistors in the pixel driving circuit. It should be understood that in other exemplary embodiments, the first gate driving circuit integration area AA2 may also integrate other numbers of first gate driving circuits, for example, the number of first gate driving circuits integrated in the first gate driving circuit integration area AA2 may also be 1, 3, 4, 5, etc.

[0112] In this exemplary embodiment, as Figure 1As shown, the display area AA may further include a second gate driving circuit integration area AA4 and a third pixel driving circuit integration area AA5. At least a portion of the pixel driving circuit Pix is ​​located in the third pixel driving circuit integration area AA5. The second gate driving circuit integration area AA4 can also be obtained by compressing the pixel driving circuit in the first direction, and light-emitting units can also be disposed on the second gate driving circuit integration area AA4. One or more gate driving circuits include a second gate driving circuit GOA2, which is located in the second gate driving circuit integration area AA4. The second gate driving circuit GOA2 and the first gate driving circuit GOA1 are correspondingly arranged, and the second gate driving circuit GOA2 and its corresponding first gate driving circuit GOA1 can provide gate driving signals to the same transistor in the pixel driving circuit. This arrangement provides gate driving signals to the same transistor in the pixel driving circuit through multiple gate driving circuits, which can improve the driving capability of the gate driving signal and improve the uniformity of the gate driving signal driving capability of the display panel at different positions in the first direction X.

[0113] In this exemplary embodiment, as Figure 1 As shown, the display area AA includes a corner area AD, which is located at the corner of the display area and has a curved edge. The display area used to house the gate drive circuit is located outside the corner area AD. This arrangement facilitates the configuration of the gate drive circuit.

[0114] In this exemplary embodiment, as Figure 1 As shown, the gate drive circuit includes multiple cascaded shift register units UT, and the orthographic projections of the multiple shift register units UT in the same gate drive circuit onto the substrate are distributed along the second direction.

[0115] In this exemplary embodiment, as Figure 3 , 4 As shown, Figure 3 This is an equivalent circuit diagram of the pixel driving circuit in the display panel of this disclosure. Figure 4 for Figure 3 The timing diagram of some nodes in an exemplary embodiment of the pixel driving circuit shown is illustrated.

[0116] The pixel driving circuit may include: a driving transistor T3, a first transistor T1, a second transistor T2, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a fourth capacitor C4. Specifically, the first terminal of the fourth transistor T4 is connected to the data signal terminal Da, the second terminal of the fourth transistor T4 is connected to the first terminal of the driving transistor T3, and the gate of the fourth transistor T4 is connected to the second gate driving signal terminal G2. The first terminal of the fifth transistor T5 is connected to the first power supply terminal VDD, the second terminal of the fifth transistor T5 is connected to the first terminal of the driving transistor T3, and the gate of the fifth transistor T5 is connected to the enable signal terminal EM. The gate of the driving transistor T3 is connected to node N. The first terminal of the second transistor T2 is connected to node N, the second terminal of the second transistor T2 is connected to the second terminal of the driving transistor T3, and the gate of the second transistor T2 is connected to the first gate driving signal terminal G1. The first terminal of the sixth transistor T6 is connected to the second terminal of the driving transistor T3, and the second terminal of the sixth transistor T6 is connected to the seventh transistor T8. The second electrode of transistor T7 is connected to the enable signal terminal EM via the gate of the sixth transistor T6. The first electrode of the seventh transistor T7 is connected to the second initial signal terminal Vinit2, and its gate is connected to the second reset signal terminal Re2. The first electrode of the first transistor T1 is connected to the first initial signal terminal Vinit1, and its second electrode is connected to the second electrode of the driving transistor T3, with its gate connected to the first reset signal terminal Re1. The first electrode of the eighth transistor T8 is connected to the third initial signal terminal Vinit3, and its second electrode is connected to the first electrode of the driving transistor T3, with its gate connected to the second reset signal terminal Re2. The first electrode of the fourth capacitor C4 is connected to node N, and its second electrode is connected to the first power supply terminal VDD. This pixel driving circuit can be used to drive a light-emitting unit (OLED). The first electrode of the OLED can be connected to the second electrode of the sixth transistor T6, and its second electrode can be connected to the second power supply terminal VSS. The first electrode of the OLED can be the anode, and the second electrode can be the cathode. The second transistor T2 can be an N-type transistor, for example, an N-type metal-oxide transistor. N-type transistors have a smaller leakage current, which can avoid the light-emitting stage, where node N leaks current through the second transistor T2.Meanwhile, the first transistor T1, driving transistor T3, fourth transistor T4, fifth transistor T5, sixth transistor T6, seventh transistor T7, and eighth transistor T8 can be P-type transistors. For example, driving transistor T3, fourth transistor T4, fifth transistor T5, sixth transistor T6, seventh transistor T7, and eighth transistor T8 can be P-type transistors, such as P-type low-temperature polycrystalline silicon transistors. P-type transistors have higher carrier mobility, which is beneficial for realizing display panels with high resolution, high response speed, high pixel density, and high aperture ratio. The first initial signal terminal, second initial signal terminal, and third initial signal terminal can output the same or different voltage signals according to actual conditions.

[0117] like Figure 4 As shown, G1 represents the timing of the first gate drive signal terminal G1, G2 represents the timing of the second gate drive signal terminal G2, Re2 represents the timing of the second reset signal terminal Re2, Re1 represents the timing of the first reset signal terminal Re1, and EM represents the timing of the enable signal terminal EM. One driving cycle of this pixel driving circuit may include a first reset phase t1, a second reset phase t2, a data writing phase t3, a third reset phase t4, and a light emission phase t5.

[0118] In the first reset phase t1: the second reset signal terminal Re2 outputs a low-level signal, the seventh transistor T7 and the eighth transistor T8 are turned on, the second initial signal terminal Vinit2 inputs a second initial signal to the first electrode of the OLED light-emitting unit, and the third initial signal terminal Vinit3 inputs a third initial signal to the first electrode of the driving transistor T3 to improve the hysteresis problem of the driving transistor T3. In the second reset phase t2: the first gate drive signal terminal G1 outputs a high-level signal, the first reset signal terminal Re1 outputs a low-level signal, the first transistor T1 and the second transistor T2 are turned on, and the first initial signal terminal Vinit1 inputs a first initial signal to node N through the first transistor T1 and the second transistor T2. In the data writing phase t3: the second gate drive signal terminal G2 outputs a low-level signal, the first gate drive signal terminal G1 outputs a high-level signal, the fourth transistor T4 and the second transistor T2 are turned on, and the data signal terminal Da writes a compensation voltage Vdata+Vth to node N through the fourth transistor T4 and the second transistor T2, where Vdata is the voltage of the data signal on the data signal terminal, and Vth is the threshold voltage of the driving transistor T3. In the third reset phase t4: the second reset signal terminal RE2 outputs a low-level signal, the seventh transistor T7 and the eighth transistor T8 are turned on, the second initial signal terminal Vinit2 inputs the second initial signal to the first electrode of the OLED light-emitting unit, and the third initial signal terminal Vinit3 inputs the third initial signal to the first electrode of the driving transistor T3. In the light-emitting phase t5: the enable signal terminal EM outputs a low-level signal, the sixth transistor T6 and the fifth transistor T5 are turned on, and the driving transistor T3 drives the light-emitting unit to emit light under the action of the compensation voltage Vdata+Vth stored in the fourth capacitor C4. The formula for the output current of the driving transistor is as follows:

[0119] I = (μWCox / 2L)(Vgs-Vth) 2

[0120] Where I is the output current of the driving transistor; μ is the carrier mobility; Cox is the gate capacitance per unit area; W is the width of the driving transistor channel; L is the length of the driving transistor channel; Vgs is the gate-source voltage difference of the driving transistor; and Vth is the threshold voltage of the driving transistor. In the pixel driving circuit described above, the output current of the driving transistor I = (μWCox / 2L)(Vdata + Vth - Vdd - Vth) 2 This pixel driving circuit can avoid the influence of the driving transistor threshold on its output current.

[0121] like Figure 5The diagram shown is a schematic representation of the shift register unit in the gate drive circuit of this disclosure. The shift register unit may include a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, a sixteenth transistor T16, a seventeenth transistor T17, an eighteenth transistor T18, a nineteenth transistor T19, a first capacitor C1, a second capacitor C2, and a third capacitor C3. The ninth transistor T9 has its first terminal connected to the input terminal IN, its second terminal connected to the first node N1, and its gate connected to the first clock signal terminal CK; the tenth transistor T10 has its first terminal connected to the first clock signal terminal CK, its second terminal connected to the second node N2, and its gate connected to the first node N1; the eleventh transistor T11 has its first terminal connected to the third power supply terminal VGL, its second terminal connected to the second node N2, and its gate connected to the first clock signal terminal CK; the twelfth transistor T12 has its second terminal connected to the first node N1, and its gate connected to the second clock signal terminal CB; the thirteenth transistor T13 has its first terminal connected to the fourth power supply terminal VGH, its second terminal connected to the first terminal of the twelfth transistor T12, and its gate connected to the second node N2; the fourteenth transistor T14 has its first terminal connected to the second clock signal terminal CB, its second terminal connected to the third node N3, and its gate connected to the second node N2; the fifteenth transistor T15 has its first terminal connected to the third... Node N3, its second terminal is connected to the fourth node N4, and its gate is connected to the second clock signal terminal CB; the sixteenth transistor T16, its first terminal is connected to the third power supply terminal VGL, its second terminal is connected to the fourth node N4, and its gate is connected to the first node N1; the seventeenth transistor T17, its first terminal is connected to the fourth power supply terminal VGH, its second terminal is connected to the output terminal OUT, and its gate is connected to the fourth node N4; the eighteenth transistor T18, its first terminal is connected to the third power supply terminal VGL, its second terminal is connected to the output terminal OUT, and its gate is connected to the fifth node N5; the nineteenth transistor T19, its first terminal is connected to the first node N1, its second terminal is connected to the fifth node N5, and its gate is connected to the third power supply terminal VGL; the first capacitor C1 is connected between the second node N2 and the third node N3; the second capacitor C2 is connected between the fifth node N5 and the second clock signal terminal CB; the third capacitor C3 is connected between the fourth node and the fourth power supply terminal VGH.

[0122] The gate drive circuit includes multiple Figure 5 The shift register unit shown is configured by cascading multiple shift register units. For example, the output terminal OUT of this shift register unit can be connected to the input terminal IN of the adjacent next-level shift register unit.

[0123] This exemplary embodiment also provides a display panel, which may include a substrate, a shielding layer, a first active layer, a first gate layer, a second gate layer, a second active layer, a third gate layer, a first source / drain layer, a second source / drain layer, a third source / drain layer, an electrical connection layer, and an electrode layer, which are sequentially stacked. An insulating layer may be disposed between adjacent layers. Figure 6-26 As shown, Figure 6 This is a structural layout diagram of an exemplary embodiment of the display panel disclosed herein. Figure 7 for Figure 6 Structural layout of the middle shading layer, Figure 8 for Figure 6 The structural layout of the first active layer in the middle, Figure 9 for Figure 6 The structural layout of the first gate layer in the middle, Figure 10 for Figure 6 The structural layout of the second gate layer in the middle. Figure 11 for Figure 6 The structural layout of the second active layer in the middle. Figure 12 for Figure 6 The structural layout of the third gate layer in the middle, Figure 13 for Figure 6 The structural layout of the first source / drain layer in the middle. Figure 14 for Figure 6 Structural layout of the second source / drain layer. Figure 15 for Figure 6 Structural layout of the third source / drain layer in the middle. Figure 16 for Figure 6 The structural layout of the intermediate electrical connection layer, Figure 17 for Figure 6 Structural layout of the middle electrode layer, Figure 18 for Figure 6 The structural layout of the middle shielding layer and the first active layer. Figure 19 for Figure 6 The structural layout of the middle shielding layer, the first active layer, and the first gate layer. Figure 20 for Figure 6 The structural layout of the middle shielding layer, the first active layer, the first gate layer, and the second gate layer. Figure 21 for Figure 6 The structural layout of the middle shielding layer, the first active layer, the first gate layer, the second gate layer, and the second active layer. Figure 22 for Figure 6 The structural layout of the middle shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, and the third gate layer. Figure 23 for Figure 6 The structural layout of the middle shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, and the first source / drain layer. Figure 24 for Figure 6The structural layout of the middle shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, the first source / drain layer, and the second source / drain layer. Figure 25 for Figure 6 The structural layout of the middle shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, the first source / drain layer, the second source / drain layer, and the third source / drain layer. Figure 26 for Figure 6 The structural layout of the middle shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, the first source / drain layer, the second source / drain layer, the third source / drain layer, and the electrical connection layer. This display panel may include multiple... Figure 3 The pixel driving circuit shown and Figure 5 The gate drive circuit shown.

[0124] like Figure 27-47 As shown, Figure 27 for Figure 6 The image shown is a magnified view of a portion BB of the display panel. Figure 28 for Figure 27 Structural layout of the middle shading layer, Figure 29 for Figure 27 The structural layout of the first active layer in the middle, Figure 30 for Figure 27 The structural layout of the first gate layer in the middle, Figure 31 for Figure 27 The structural layout of the second gate layer in the middle. Figure 32 for Figure 27 The structural layout of the second active layer in the middle. Figure 33 for Figure 27 The structural layout of the third gate layer in the middle, Figure 34 for Figure 27 The structural layout of the first source / drain layer in the middle. Figure 35 for Figure 27 Structural layout of the second source / drain layer. Figure 36 for Figure 27 Structural layout of the third source / drain layer in the middle. Figure 37 for Figure 27 The structural layout of the intermediate electrical connection layer, Figure 38 for Figure 27 Structural layout of the middle electrode layer, Figure 39 for Figure 27 The structural layout of the middle shielding layer and the first active layer. Figure 40 for Figure 27 The structural layout of the middle shielding layer, the first active layer, and the first gate layer. Figure 41 for Figure 27 The structural layout of the middle shielding layer, the first active layer, the first gate layer, and the second gate layer. Figure 42 for Figure 27The structural layout of the middle shielding layer, the first active layer, the first gate layer, the second gate layer, and the second active layer. Figure 43 for Figure 27 The structural layout of the middle shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, and the third gate layer. Figure 44 for Figure 27 The structural layout of the middle shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, and the first source / drain layer. Figure 45 for Figure 27 The structural layout of the middle shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, the first source / drain layer, and the second source / drain layer. Figure 46 for Figure 27 The structural layout of the middle shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, the first source / drain layer, the second source / drain layer, and the third source / drain layer. Figure 47 for Figure 27 The structural layout of the middle shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, the first source / drain layer, the second source / drain layer, the third source / drain layer, and the electrical connection layer.

[0125] like Figure 23 As shown, two first gate drive circuits GOA1 can be disposed in the first gate drive circuit integration area AA2. The two first gate drive circuits GOA1 form a first sub-gate drive circuit GOA11 and a second sub-gate drive circuit GOA12 respectively. The orthogonal projections of the first sub-gate drive circuit GOA11 and the second sub-gate drive circuit GOA12 on the substrate can be distributed in the first direction X.

[0126] like Figure 23 As shown, the display area further includes a first gate line bridging area AJ1 and a second gate line bridging area AJ2. The first gate line bridging area AJ1 is located between the first pixel driving circuit integrated area AA1 and the first gate driving circuit integrated area AA2, and the second gate line bridging area AJ2 is located between the second pixel driving circuit integrated area AA3 and the first gate driving circuit integrated area AA2.

[0127] The display panel may include a plurality of pixel units distributed in a first direction X and a second direction Y. Each pixel unit may include two pixel driving circuits Pix that are adjacently distributed in the first direction X. The orthogonal projections of the two pixel driving circuits in the same pixel unit onto the substrate may be at least partially mirror-symmetrical.

[0128] like Figure 6 , 7As shown in 18, 27, 28, and 39, the shielding layer includes a plurality of first shielding portions 81 and second shielding portions 82 distributed in an array along a first direction X and a second direction Y. The orthographic projection of the second shielding portion 82 on the substrate extends along the second direction, and the first shielding portions 81 and the second shielding portions 82 are interconnected.

[0129] like Figure 6 , 8As shown in 18, 19, 27, 29, 39, and 40, the first active layer may include: a first active section 71, a third active section 73, a fourth active section 74, a fifth active section 75, a sixth active section 76, a seventh active section 77, an eighth active section 78, a ninth active section 79, a tenth active section 710, an eleventh active section 711, a twelfth active section 712, a thirteenth active section 713, a fourteenth active section 714, a fifteenth active section 715, a sixteenth active section 716, a seventeenth active section 717, an eighteenth active section 718, and a nineteenth active section 719. The first active portion 71 is used to form the channel region of the first transistor T1; the third active portion 73 can be used to form the channel region of the driving transistor T3; the fourth active portion 74 can be used to form the channel region of the fourth transistor T4; the fifth active portion 75 can be used to form the channel region of the fifth transistor T5; the sixth active portion 76 can be used to form the channel region of the sixth transistor T6; the seventh active portion 77 can be used to form the channel region of the seventh transistor T7; the eighth active portion 78 can be used to form the channel region of the eighth transistor T8; the ninth active portion 79 can be used to form the channel region of the ninth transistor T9; the tenth active portion 710 can be used to form the channel region of the tenth transistor T10; the eleventh active portion 711 can be used to form the eleventh... The channel region of transistor T11; the twelfth active part 712 can be used to form the channel region of the twelfth transistor T12; the thirteenth active part 713 can be used to form the channel region of the thirteenth transistor T13; the fourteenth active part 714 can be used to form the channel region of the fourteenth transistor T14; the fifteenth active part 715 can be used to form the channel region of the fifteenth transistor T15; the sixteenth active part 716 can be used to form the channel region of the sixteenth transistor T16; the seventeenth active part 717 can be used to form the channel region of the seventeenth transistor T17; the eighteenth active part 718 can be used to form the channel region of the eighteenth transistor T18; and the nineteenth active part 719 can be used to form the channel region of the nineteenth transistor T19. The first active layer can be formed of polycrystalline silicon material. Correspondingly, the first transistor T1, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, the eleventh transistor T11, the twelfth transistor T12, the thirteenth transistor T13, the fourteenth transistor T14, the fifteenth transistor T15, the sixteenth transistor T16, the seventeenth transistor T17, the eighteenth transistor T18, and the nineteenth transistor T19 can be P-type low-temperature polycrystalline silicon thin-film transistors.

[0130] The orthogonal projection of the first shielding part 81 on the substrate can cover the orthogonal projection of the third active part 73 on the substrate. The first shielding part 81 can shield the third active part 73 from light to improve the stability of the output characteristics of the driving transistor. The orthogonal projection of the second shielding part 82 onto the substrate covers the orthogonal projections of the ninth active part 79, the tenth active part 710, the eleventh active part 711, the twelfth active part 712, the thirteenth active part 713, the fourteenth active part 714, the fifteenth active part 715, the sixteenth active part 716, the seventeenth active part 717, the eighteenth active part 718, and the nineteenth active part 719 onto the substrate. The second shielding part 82 can shield the ninth active part 79, the tenth active part 710, the eleventh active part 711, the twelfth active part 712, the thirteenth active part 713, the fourteenth active part 714, the fifteenth active part 715, the sixteenth active part 716, the seventeenth active part 717, the eighteenth active part 718, and the nineteenth active part 719 from light to improve the stability of the output characteristics of the corresponding transistors. The shielding layer can be a conductive structure, can be connected to a stable voltage source, and can shield the pixel driving circuit and the gate driving circuit from signals.

[0131] like Figure 6 , 9 As shown in Figures 19, 27, 30, and 40, the first gate layer may include: a first conductive portion 11, a second gate line G2, an enable signal line EM, a first reset signal line Re1, and a second reset signal line Re2. The second gate line G2 can be used to provide... Figure 3 The second gate drive signal terminal; the enable signal line EM can be used to provide Figure 3 The enable signal terminal; the first reset signal line Re1 can be used to provide Figure 3 The first reset signal terminal; the second reset signal line Re2 can be used to provide Figure 3The second reset signal terminal is shown in the diagram. The orthographic projections of the second gate line G2, the enable signal line EM, the first reset signal line Re1, and the second reset signal line Re2 on the substrate can all extend along the first direction X. The orthographic projection of the second gate line G2 on the substrate covers the orthographic projection of the fourth active portion 74 on the substrate, and a portion of the structure of the second gate line G2 is used to form the gate of the fourth transistor. The orthographic projection of the enable signal line EM on the substrate covers the orthographic projections of the fifth active portion 75 and the sixth active portion 76 on the substrate, and a portion of the structure of the enable signal line EM can be used to form the gates of the fifth transistor T5 and the sixth transistor T6, respectively. The orthographic projection of the first reset signal line Re1 on the substrate can cover the orthographic projection of the first active portion 71 on the substrate, and a portion of the structure of the first reset signal line Re1 is used to form the gate of the first transistor T1. The orthographic projection of the second reset signal line Re2 on the substrate can cover the orthographic projections of the seventh active part 77 and the eighth active part 78 on the substrate. A portion of the structure of the first reset signal line Re1 can be used to form the gates of the seventh transistor T7 and the eighth transistor T8, respectively. The orthographic projection of the first conductive part 11 on the substrate covers the orthographic projection of the third active part 73 on the substrate. The first conductive part 11 can be used to form the gate of the driving transistor T3 and the first electrode of the fourth capacitor C4.

[0132] like Figure 6 , 9As shown in 19, 27, 30, and 40, the first gate layer may further include: a third conductive portion 13, a fourth conductive portion 14, a fifth conductive portion 15, a sixth conductive portion 16, a seventh conductive portion 17, an eighth conductive portion 18, a ninth conductive portion 19, and a tenth conductive portion 110. The orthogonal projection of the third conductive portion 13 onto the substrate covers the orthogonal projections of the ninth active portion 79 and the eleventh active portion 711 onto the substrate. A portion of the structure of the third conductive portion 13 is used to form the gate of the ninth transistor T9, and a portion is used to form the gate of the eleventh transistor T11. The orthogonal projection of the fourth conductive portion 14 onto the substrate covers the orthogonal projections of the tenth active portion 710 and the sixteenth active portion 716 onto the substrate. A portion of the structure of the fourth conductive portion 14 is used to form the gate of the tenth transistor T10, and a portion is used to form the gate of the sixteenth transistor T16. The orthogonal projection of the fifth conductive portion 15 onto the substrate covers the orthogonal projection of the twelfth active portion onto the substrate. A portion of the structure of the fifth conductive portion 15 is used to form the gate of the twelfth transistor T12. The orthographic projection of the sixth conductive portion 16 onto the substrate covers the orthographic projections of the thirteenth active portion 713 and the fourteenth active portion 714 onto the substrate. A portion of the structure of the sixth conductive portion 16 is used to form the gate of the thirteenth transistor T13, and a portion of the structure is used to form the gate of the fourteenth transistor T14. The orthographic projection of the seventh conductive portion 17 onto the substrate covers the orthographic projection of the fifteenth active portion 715 onto the substrate. A portion of the structure of the seventh conductive portion 17 is used to form the gate of the fifteenth transistor T15. The orthographic projection of the eighth conductive portion 18 onto the substrate covers the orthographic projection of the seventeenth active portion 717 onto the substrate. A portion of the structure of the eighth conductive portion 18 is used to form the gate of the seventeenth transistor T17. The orthographic projection of the ninth conductive portion 19 onto the substrate covers the orthographic projection of the eighteenth active portion 718 onto the substrate. A portion of the structure of the ninth conductive portion 19 is used to form the gate of the eighteenth transistor T18. The orthogonal projection of the tenth conductive part 110 on the substrate covers the orthogonal projection of the nineteenth active part 719 on the substrate, and part of the structure of the tenth conductive part 110 is used to form the gate of the nineteenth transistor T19.

[0133] The display panel can use the first gate layer as a mask to conduct the first active layer, that is, the area of ​​the first active layer covered by the first gate layer can form the channel region of the transistor, and the area of ​​the first active layer not covered by the first gate layer forms a conductor structure.

[0134] like Figure 6 , 9As shown in 19, 27, 30, and 40, the second gate layer may include: a third gate line 2G1, a second conductive portion 22, a first connection portion 23, an eleventh conductive portion 211, a twelfth conductive portion 212, a thirteenth conductive portion 213, and a fourteenth conductive portion 214. The orthogonal projection of the third gate line 2G1 onto the substrate extends along the first direction X. The third gate line 2G1 can be used to provide... Figure 3 The first gate drive signal terminal is located in the substrate. The orthographic projection of the second conductive portion 22 on the substrate can at least partially overlap with the orthographic projection of the first conductive portion 11 on the substrate. The second conductive portion 22 is used to form the second electrode of the fourth capacitor C4. The first connecting portion 23 is connected between two adjacent second conductive portions 22 in the first direction X. The orthographic projection of the eleventh conductive portion 211 on the substrate and the orthographic projection of the sixth conductive portion 16 on the substrate at least partially overlap. A portion of the structure of the sixth conductive portion 16 is used to form the first electrode of the first capacitor C1, and the eleventh conductive portion 211 is used to form the second electrode of the first capacitor C1. The orthographic projection of the thirteenth conductive portion 213 on the substrate and the orthographic projection of the eighth conductive portion 18 on the substrate at least partially overlap. A portion of the structure of the eighth conductive portion 18 is used to form the first electrode of the third capacitor C3, and the thirteenth conductive portion 213 is used to form the second electrode of the third capacitor C3. The orthographic projection of the twelfth conductive portion 212 on the substrate and the orthographic projection of the ninth conductive portion 19 on the substrate at least partially overlap. A portion of the structure of the ninth conductive portion 19 is used to form the first electrode of the second capacitor C2, and the twelfth conductive portion 212 is used to form the second electrode of the second capacitor C2. The orthographic projection of the fourteenth conductive portion 214 on the substrate extends along the second direction Y.

[0135] like Figure 6 , 10 As shown in Figures 20, 27, 31, and 41, the second active layer may include an active portion 9, which may include a second active portion 92. The second active portion 92 is used to form the channel region of the second transistor T2. The second active layer may be formed of indium gallium zinc oxide, and correspondingly, the second transistor T2 may be an N-type metal-oxide-slim transistor. The orthogonal projection of the third gate line 2G1 onto the substrate may cover the orthogonal projection of the second active portion 92 onto the substrate, and a portion of the structure of the third gate line 2G1 may be used to form the bottom gate of the second transistor T2.

[0136] like Figure 6 , 11As shown in Figures 21, 27, 32, and 42, the third gate layer may include a first gate line 3G1, a first initial signal line Vinit1, a second initial signal line Vinit2, and a third initial signal line Vinit3. The orthographic projections of the first gate line 3G1, the first initial signal line Vinit1, the second initial signal line Vinit2, and the third initial signal line Vinit3 onto the substrate can all extend along a first direction X. The first gate line 3G1 can be used to provide... Figure 3 The first gate drive signal terminal, the orthogonal projection of the first gate line 3G1 on the substrate can cover the orthogonal projection of the second active part 92 on the substrate. A portion of the structure of the first gate line 3G1 can be used to form the top gate of the second transistor T2. Simultaneously, the first gate line 3G1 can be connected to the third gate line 2G1 via a via. The first initial signal line Vinit1 can be used to provide... Figure 3 The first initial signal terminal and the second initial signal line Vinit2 can be used to provide... Figure 3 The second initial signal terminal and the third initial signal line Vinit3 can be used to provide Figure 3 The third initial signal terminal in the display panel. The orthographic projection of the first initial signal line Vinit1 on the substrate can at least partially coincide with the orthographic projection of the second reset signal line Re2 in the adjacent previous row pixel driving circuit on the substrate. The orthographic projection of the second initial signal line Vinit2 on the substrate can at least partially coincide with the orthographic projection of the first reset signal line Re1 in the adjacent next row pixel driving circuit on the substrate. The orthographic projection of the third initial signal line Vinit3 on the substrate can at least partially coincide with the orthographic projection of the enable signal line EM in the current row pixel driving circuit on the substrate. This arrangement can improve the light transmittance and integration of the display panel. In addition, the display panel can use the third gate layer as a mask to perform conductor processing on the second active layer. That is, the area of ​​the second active layer covered by the third gate layer can form the channel region of the transistor, and the area of ​​the second active layer not covered by the third gate layer forms a conductor structure.

[0137] It should be noted that in other exemplary embodiments, the first initial signal line Vinit1, the second initial signal line Vinit2, and the third initial signal line Vinit3 may also be located in other conductive layers. For example, the first initial signal line Vinit1, the second initial signal line Vinit2, and the third initial signal line Vinit3 may also be located in the second gate layer, the first source / drain layer, etc.

[0138] like Figure 9 , 10As shown in Figures 1 and 12, the first gate line 3G1, the third gate line 2G1, the second gate line G2, the first reset signal line Re1, the second reset signal line Re2, and the enable signal line EM are all gate lines. Each of the above gate lines includes a first gate line segment G11 and a second gate line segment G12. The first gate line segment is at least partially located in the first pixel driving circuit integration area and is used to provide a gate driving signal to the pixel driving circuit in the first pixel driving circuit integration area. The second gate line segment is at least partially located in the second pixel driving circuit integration area and is used to provide a gate driving signal to the pixel driving circuit in the second pixel driving circuit integration area.

[0139] like Figure 6 , 12 As shown in Figures 22, 27, 33, and 43, the first source / drain layer may include a first bridging section 41, a second bridging section 42, a third bridging section 43, a fourth bridging section 44, a fifth bridging section 45, a sixth bridging section 46, a seventh bridging section 47, an eighth bridging section 48, a ninth bridging section 49, and a tenth bridging section 410. The first bridging section 41 connects to the second terminal of the eighth transistor T8 and the first terminal of the driving transistor T3 via vias. The second bridging section 42 connects to the second terminals of the first transistor T1, the second transistor T2, and the driving transistor T3 via vias. The third bridging section 43 connects to the first initial signal line Vinit1 and the first terminal of the first transistor T1 via vias. The fourth bridging section 44 connects to the first terminal of the seventh transistor T7 and the second initial signal line Vinit2 via vias. The fifth bridging section 45 connects to the first terminal of the fourth transistor T4 via vias. The sixth bridging section 46 connects to the third initial signal line and the first terminal of the eighth transistor T8 via vias. The seventh bridging section 47 is connected to the first connecting section 21 and the first terminal of the fifth transistor T5 via vias. The eighth bridging section 48 is connected to the second terminal of the sixth transistor T6 via vias. The ninth bridging section 49 is connected to the first terminal of the second transistor T2 and the first conductive section 11 via vias. The tenth bridging section 410 is connected to the second terminal of the fourth transistor T4 via vias.

[0140] like Figure 6 , 12 As shown in Figures 22, 27, 33, and 43, the first source / drain layer may further include an eleventh bridging section 411, a twelfth bridging section 412, a thirteenth bridging section 413, a fourteenth bridging section 414, a fifteenth bridging section 415, a sixteenth bridging section 416, a seventeenth bridging section 417, an eighteenth bridging section 418, a nineteenth bridging section 419, a twentieth bridging section 420, a twenty-first bridging section 421, a twenty-second bridging section 422, a twenty-third bridging section 423, a twenty-fourth bridging section 424, a twenty-fifth bridging section 425, and a twenty-sixth bridging section 426. It also includes a first clock signal line CK, a second clock signal line CB, a third power supply line VGL, and a fourth power supply line VGH.

[0141] The twenty-third bridging portion 423, the twenty-fourth bridging portion 424, the twenty-fifth bridging portion 425, and the twenty-sixth bridging portion 426 can form gate line bridging portions. The gate line bridging portion located in the first gate line bridging region forms a first gate line bridging portion, and the gate line bridging portion located in the second gate line bridging region forms a second gate line bridging portion. At least a portion of the orthographic projections of the first gate line bridging portions on the substrate are arranged opposite each other in the first direction, and the orthographic projections of the plurality of first gate line bridging portions arranged opposite each other in the first direction are spaced apart along the first direction. At least a portion of the orthographic projections of the second gate line bridging portions on the substrate are arranged opposite each other in the first direction, and the orthographic projections of the plurality of second gate line bridging portions arranged opposite each other in the first direction are spaced apart along the first direction. Structure A and structure B are arranged opposite each other in the first direction, which can be understood as meaning that the region traversed by structure A extending infinitely along the first direction and the region traversed by structure B extending infinitely along the first direction at least partially intersect each other.

[0142] The orthographic projections of the first clock signal line CK, the second clock signal line CB, the third power supply line VGL, and the fourth power supply line VGH onto the substrate extend along the second direction Y. The first clock signal line CK is used to provide... Figure 5 The first clock signal terminal and the second clock signal line CB are used to provide... Figure 5 The second clock signal terminal and the third power supply line VGL are used to provide... Figure 5 The third power signal terminal and the fourth power line VGH are used to provide power. Figure 5 The fourth power supply terminal is located in the capacitor C3. The first clock signal line CK is connected to the third conductive part 13 via a via, the second clock signal line CB is connected to the fifth conductive part 15 via a via, the third power supply line VGL is connected to the fourteenth bridge part 414 on the same layer, and the third power supply line VGL is connected to the tenth conductive part 110 via a via, and the fourth power supply line VGH is connected to the thirteenth conductive part 213 via a via, thus connecting the second electrode of the third capacitor C3 and the fourth power supply terminal. The first clock signal line CK, the second clock signal line CB, the third power supply line VGL, and the fourth power supply line VGH form the first signal line.

[0143] The eleventh bridging section 411 connects to the first active layer and the fourth conductive section 14 at one end of the nineteenth active section 719 via vias, thereby connecting the first terminal of the nineteenth transistor T19 and the second terminal of the ninth transistor T9. The twelfth bridging section 412 connects to the first active layer and the ninth conductive section 19 at the other end of the nineteenth active section 719 via vias, thereby connecting the second terminal of the nineteenth transistor T19 and the gate of the eighteenth transistor T18. The thirteenth bridging section 413 connects to the first active layer at one end of the ninth active section 79 in this stage shift register unit, the first active layer at one end of the seventeenth active section 717 in the previous stage shift register unit, and the fourteenth conductive section 214 via vias, thereby connecting the first terminal of the first transistor T1 in this stage shift register unit and the second terminal of the ninth transistor T9 in the previous stage shift register unit. The fourteenth bridging section 414 is connected via vias to the first active layer at one end of the eleventh active section 711 and the first active layer at one end of the eighteenth active section 718, and is also connected to the third power line VGL on the same layer, thereby connecting the first terminal of the eleventh transistor T11, the first terminal of the eighteenth transistor T18, and the third power line VGL. The fifteenth bridging section 415 is connected via vias to the first active layer at the other end of the ninth active section 79, the fourth conductive section 14, and the first active layer at one end of the twelfth active section 712, thereby connecting the second terminal of the ninth transistor T9, the second terminal of the twelfth transistor T12, and the gate of the tenth transistor T10. The sixteenth bridging section 416 is connected via vias to the first active layer at the other end of the eleventh active section 711, the first active layer on the side of the tenth active section 710 away from the ninth active section 79, and the sixth conductive section 16, thereby connecting the second terminal of the eleventh transistor T11, the second terminal of the tenth transistor T10, and the gate of the thirteenth transistor T13. The seventeenth bridging section 417 connects vias to the fifth conductive section 15, the first active layer at one end of the fourteenth active section 714, and the thirteenth conductive section 213, respectively, to connect the gate of the twelfth transistor T12, the first electrode of the fourteenth transistor T14, the second electrode of the second capacitor C2, and the second clock signal line CB. The eighteenth bridging section 418 connects vias to the first active layer at one end of the fifteenth active section, the eleventh conductive section 211, and the first active layer at the other end of the fourteenth active section 714, respectively, to connect the first electrode of the fifteenth transistor, the second electrode of the first capacitor C1, and the second electrode of the fourteenth transistor T14. The nineteenth bridging section 419 connects vias to the first active layer at the other end of the fifteenth active section 715, the first active layer at one end of the sixteenth active section 716, and the eighth conductive section 18, respectively, to connect the second electrode of the fifteenth transistor T15, the first electrode of the third capacitor C3, and the second electrode of the sixteenth transistor T16.The twentieth bridging section 420 connects vias to the first active layer at one end of the thirteenth conductive section 213, the first active layer at the seventeenth active section 717, and the first active layer at the other end of the sixteenth active section 716, respectively, to connect the second electrode of the third capacitor C3, the first electrode of the seventeenth transistor T17, and the first electrode of the sixteenth transistor T16. The twenty-first bridging section 421 connects vias to the first active layer at the other end of the eighteenth active section 718 and the fourteenth conductive section 214, respectively, to connect the second electrode of the eighteenth transistor T18 and the second electrode of the seventeenth transistor T17. The twenty-second bridging section 422 connects vias to the first active layer at the other end of the third conductive section 13 and the tenth active section 710, respectively, to connect the gate of the ninth transistor T9, the first electrode of the tenth transistor T10, and the first clock signal terminal. The orthographic projections of the twenty-third bridging section 423, the twenty-fourth bridging section 424, and the twenty-sixth bridging section 426 on the substrate extend along the second direction Y. The twenty-third bridging section 423 is connected via vias to adjacent second reset signal lines Re2 in the second direction Y. The twenty-fourth bridging section 424 is connected via vias to two adjacent third gate lines 2G1 in the second direction, and / or the twenty-fourth bridging section 424 is connected via vias to two adjacent first gate lines 3G1 in the second direction. The twenty-fifth bridging section 425 is connected via vias to the second gate line G2. The twenty-sixth bridging section 426 is connected via vias to two adjacent first reset signal lines Re1 in the second direction.

[0144] like Figure 6 , 13 As shown in Figures 23, 27, 34, and 44, the second source / drain layer may include: a fifteenth conductive portion 515, a twenty-seventh bridging portion 527, a twenty-eighth bridging portion 528, and a first fan-out line FIPH. The orthographic projection of the first fan-out line FIPH onto the substrate can extend along a first direction X, and the first fan-out line FIPH can serve as a row-direction fan-out line connecting data lines within a FIP (Fanout In Pixel). The fifteenth conductive portion 515 can be connected to the seventh bridging portion 47 via a via to connect to the first terminal of the fifth transistor T5. The twenty-seventh bridging portion 527 can be connected to the fifth bridging portion 45 via a via to connect to the first terminal of the fourth transistor. The twenty-eighth bridging portion 528 can be connected to the eighth bridging portion 48 via a via to connect to the second terminal of the sixth transistor T6.

[0145] like Figure 6 , 13As shown in Figures 23, 27, 34, and 44, the second source / drain layer may further include: a first bridge connection 51, a second bridge connection 52, a third bridge connection 53, and a fourth bridge connection 54. The orthogonal projections of the first bridge connection 51, the second bridge connection 52, the third bridge connection 53, and the fourth bridge connection 54 on the substrate can all extend along the first direction X. The first bridge connection 51 can be connected via vias to the twenty-third bridge portion 423 located on both sides of the first gate drive circuit integration area AA2 in the first direction X. At the same time, the first bridge connection 51 can be connected via vias to the thirteenth bridge portion 413 in the first sub-gate drive circuit GOA11, so that the output terminal of the shift register unit in the first sub-gate drive circuit GOA11 is connected to the second reset signal line Re2. The second bridge connection 52 can be connected via vias to the twenty-sixth bridge portion 426 located on both sides of the first gate drive circuit integrated area AA2 in the first direction X. Simultaneously, the second bridge connection 52 can be connected via vias to the twenty-first bridge portion 421 in the second sub-gate drive circuit GOA12, so that the output terminal of the shift register unit in the second sub-gate drive circuit GOA12 is connected to the first reset signal line Re1. The third bridge connection 53 can be connected via vias to the twenty-fifth bridge portion 425 located on both sides of the first gate drive circuit integrated area AA2 in the first direction X, so as to connect the second gate line G2 located on both sides of the first gate drive circuit integrated area AA2 in the first direction X. The fourth bridge connection 54 can be connected via vias to the twenty-fourth bridge portion 424 located on both sides of the first gate drive circuit integrated area AA2 in the first direction X, so as to connect the first gate line 3G1 located on both sides of the first gate drive circuit integrated area AA2 in the first direction X.

[0146] The first bridge connection 51, the second bridge connection 52, the third bridge connection 53, and the fourth bridge connection 54 can form a bridge connection.

[0147] like Figure 6 , 14 As shown in Figures 24, 27, 35, and 45, the third source / drain layer may include: a data line Da, a first power line VDD, a second fan-out line FIPV, and a twenty-ninth bridging portion 629. The orthogonal projections of the data line Da, the first power line VDD, and the second fan-out line FIPV onto the substrate can extend along the second direction Y. The data line Da is used to provide... Figure 3 The data signal terminal in the middle, the first power line VDD is used to provide Figure 3The first power supply terminal is located in the first power supply section. The data line Da can be connected to the twenty-seventh bridge section 527 via a via to connect the data signal terminal and the first terminal of the fourth transistor. The first power supply line VDD can be connected to the fifteenth conductive section 515, which intersects with its orthographic projection onto the substrate, via a via. The second fan-out line FIPV can serve as a column-direction fan-out line connecting the data lines in the FIP (Fanout InPixel). The twenty-ninth bridge section 629 can be connected to the twenty-eighth bridge section 528 via a via.

[0148] At least a portion of the data line Da and the first power line VDD are located in the first pixel driving circuit integration area and the second pixel driving circuit integration area, and at least a portion of the data line Da and the first power line VDD are located in the first gate driving circuit integration area AA2, the first gate line bridging area, and the second gate line bridging area. This arrangement can unify the metal load under the electrode layer, thereby improving the uniformity of the flatness of the electrode parts at different locations. This arrangement can also shield the coupling interference of the underlying metal trace signals to the electrode layer.

[0149] like Figure 6 , 15 As shown in Figures 25, 27, 36, and 46, the electrical connection layer may include multiple electrical connection lines DL. The orthographic projection of the electrical connection lines DL onto the substrate may extend along a first direction. The electrical connection lines DL may connect the twenty-ninth bridging portion 629 and the light-emitting unit through vias, respectively. This arrangement allows the pixel driving circuit in the first pixel driving circuit integration area AA1 / the second pixel driving circuit integration area AA3 to connect with the light-emitting unit in the first gate driving circuit integration area AA2.

[0150] like Figure 6 , 16 As shown in Figures 27 and 37, the electrode layer may include multiple electrode sections: these multiple electrode sections include a first electrode section R, a second electrode section B, and a third electrode section G. Each electrode section can be connected to an electrical connection line DL via a via to connect to the second electrode of the sixth transistor. Among the multiple electrode sections connected to the same row of pixel driving circuits, the first electrode section R, the third electrode section G, the second electrode section B, and the third electrode section G are alternately distributed in the row direction. In two adjacent columns of pixel driving circuits, multiple first electrode sections R and multiple second electrode sections B are connected to the same column of pixel driving circuits, and the first electrode sections R and second electrode sections B connected to the same column of pixel driving circuits are alternately distributed in the column direction. Multiple third electrode sections G are connected to another column of pixel driving circuits. The third electrode section G can serve as the first electrode of a green light-emitting unit, the first electrode section R can serve as the first electrode of a red light-emitting unit, and the second electrode section B can serve as the first electrode of a blue light-emitting unit.

[0151] It should be noted that the pixel driving circuit in this exemplary embodiment can also have other structures, and correspondingly, the display panel can also have other layout structures.

[0152] like Figure 48 As shown, Figure 27 The diagram shows a partial cross-sectional view of the display panel taken along the dashed line FF. The display panel may further include a buffer layer 101, a second insulating layer 102, a third insulating layer 103, a fourth insulating layer 104, a fifth insulating layer 105, a first dielectric layer 106, a passivation layer 107, a first planarization layer 108, a second planarization layer 109, a third planarization layer 1010, and a fourth planarization layer 1011. The substrate 100, shielding layer, buffer layer 101, first active layer, second insulating layer 102, first gate layer, third insulating layer 103, second gate layer, fourth insulating layer 104, second active layer, fifth insulating layer 105, third gate layer, first dielectric layer 106, first source / drain layer, passivation layer 107, first planarization layer 108, second source / drain layer, second planarization layer 109, third source / drain layer, third planarization layer 1010, electrical connection layer, and fourth planarization layer 1011 electrode layer are sequentially stacked. The buffer layer 101, the second insulating layer 102, the third insulating layer 103, the fourth insulating layer 104, and the fifth insulating layer 105 can be single-layer or multi-layer structures, and the materials of the buffer layer 101, the second insulating layer 102, the third insulating layer 103, the fourth insulating layer 104, and the fifth insulating layer 105 can be at least one of silicon nitride, silicon oxide, and silicon oxynitride; the first dielectric layer 106 can be a silicon nitride layer; the materials of the first planarization layer 108, the second planarization layer 109, the third planarization layer 1010, and the fourth planarization layer 1011 can be organic materials, such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), silicon-glass bonded structure (SOG), etc. The passivation layer 97 can be a silicon oxide layer. The substrate 90 can include a glass substrate, a barrier layer, and a polyimide layer stacked sequentially, and the barrier layer can be an inorganic material. The materials of the first gate layer, second gate layer, and third gate layer can be molybdenum, aluminum, copper, titanium, niobium, or alloys thereof, or molybdenum / titanium alloys or stacked conductive layers. The materials of the first source / drain layer, second source / drain layer, and third source / drain layer can include metallic materials, for example, molybdenum, aluminum, copper, titanium, niobium, or alloys thereof, or molybdenum / titanium alloys or stacked layers, or titanium / aluminum / titanium stacked conductive layers. The sheet resistance of any one of the first, second, and third source / drain layers can be less than the sheet resistance of any one of the first, second, and third gate layers. The material of the electrical connection layer can include one or more of ITO, MO, and TiAlTi.

[0153] like Figure 49The diagram shows a structural layout of the electrical connection layer and electrode layer in another exemplary embodiment of the display panel of this disclosure. The first pixel driving circuit integration area AA1 and the second pixel driving circuit integration area AA3 form a pixel driving circuit integration area. The extension length of the electrical connection line DL connected to the electrode portion of the first gate driving circuit integration area AA2 is greater than the extension length of the electrical connection line DL connected to the electrode portion of the pixel driving circuit integration area. The area of ​​the orthographic projection of the electrode portion of the first gate driving circuit integration area AA2 onto the substrate is smaller than the area of ​​the orthographic projection of the electrode portion of the pixel driving circuit integration area onto the substrate. This arrangement can make the capacitive load of each electrode portion uniform, thereby improving the uniformity of the display panel.

[0154] like Figure 50 The diagram shown is a structural schematic of another exemplary embodiment of the display panel of this disclosure, wherein, in the first direction X, a portion of the gate driving circuit GOA may be located between the pixel driving circuit integration areas, and a portion of the gate driving circuit GOA may be located on both sides of the display area AA in the first direction X.

[0155] It should be noted that the scale of the accompanying drawings in this disclosure can be used as a reference in actual processes, but is not limited thereto. For example, the aspect ratio of the channels, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The accompanying drawings described in this disclosure are only schematic diagrams of the structure. In addition, the terms "first," "second," etc., are only used to define different structural names and do not have a specific order meaning. The same structural layer can be formed by the same patterning process. In this exemplary embodiment, the orthographic projection of a certain structure on the substrate extends along a certain direction, which can be understood as the orthographic projection of the structure on the substrate extending in a straight line or bending along that direction.

[0156] In this exemplary embodiment, the black squares drawn on the side of the first source / drain layer facing away from the substrate represent vias connecting the first source / drain layer to other layers facing the substrate; the black squares drawn on the side of the second source / drain layer facing away from the substrate represent vias connecting the second source / drain layer to other layers facing the substrate; the black squares drawn on the side of the third source / drain layer facing away from the substrate represent vias connecting the third source / drain layer to other layers facing the substrate; the black squares drawn on the side of the electrical connection layer facing away from the substrate represent vias connecting the electrical connection layer to other layers facing the substrate; and the black squares drawn on the side of the electrode layer facing away from the substrate represent vias connecting the electrode layer to other layers facing the substrate. Different vias represented by black squares at different locations can penetrate different insulating layers.

[0157] This exemplary embodiment also provides a display device, which includes the display panel described above. The display device can be a mobile phone, tablet computer, television, or other display device.

[0158] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

[0159] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

[0160] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is defined only by the appended claims.

Claims

1. A display panel, wherein, The display panel includes a display area, which includes a first pixel driving circuit integration area, a first gate driving circuit integration area, and a second pixel driving circuit integration area. The first pixel driving circuit integration area, the first gate driving circuit integration area, and the second pixel driving circuit integration area are distributed sequentially in a first direction. The display panel also includes: Substrate; A plurality of pixel driving circuits, at least some of which are located in the first pixel driving circuit integration area and at least some of which are located in the second pixel driving circuit integration area; A data line is used to provide data signals to the pixel driving circuit. The orthographic projection of the data line on the substrate extends along a second direction, which intersects with the first direction. One or more gate driving circuits, the gate driving circuits being used to provide gate driving signals to the pixel driving circuits, the one or more gate driving circuits including a first gate driving circuit, the first gate driving circuit being located in the first gate driving circuit integration area.

2. The display panel according to claim 1, wherein, The display area includes a corner area, which is located at the corner of the display area and has an arc-shaped edge. The first gate drive circuit integration area is located outside the corner area.

3. The display panel according to claim 1, wherein, The display area further includes a first gate line bridging area and a second gate line bridging area. The first gate line bridging area is located between the first pixel driving circuit integrated area and the first gate driving circuit integrated area, and the second gate line bridging area is located between the second pixel driving circuit integrated area and the first gate driving circuit integrated area. The display panel also includes: Multiple gate lines are provided, the orthographic projections of which on the substrate extend along the first direction and are spaced apart along the second direction. Each gate line includes a first gate line segment and a second gate line segment. The first gate line segment is at least partially located in the first pixel driving circuit integration area and is used to provide a gate driving signal to the pixel driving circuit in the first pixel driving circuit integration area. The second gate line segment is at least partially located in the second pixel driving circuit integration area and is used to provide a gate driving signal to the pixel driving circuit in the second pixel driving circuit integration area. The first grid line bridging portion is located in the first grid line bridging area, and the first grid line bridging portion connects one or more identical first grid line segments distributed along the second direction. The second grid line bridging part is located in the second grid line bridging area, and the second grid line bridging part connects one or more identical second grid line segments distributed along the second direction; A bridging wire extends along the first direction on the substrate through its orthogonal projection. The bridging wire is at least partially located in the first gate drive circuit integration area. The bridging wire connects the first gate line bridging portion and the second gate line bridging portion to connect the first gate line segment and the second gate line segment in the same gate line. The bridging wire is also connected to the signal output terminal of the first gate drive circuit.

4. The display panel according to claim 3, wherein, The pixel driving circuit includes multiple transistors, and the display panel further includes: A first source / drain layer is located on one side of the substrate. The first source / drain layer includes a circuit bridging portion, which is connected to different transistors through vias. The first gate line bridging portion and the second gate line bridging portion are located in the first source / drain layer.

5. The display panel according to claim 4, wherein, The display panel also includes: The second source / drain layer is located on the side of the first source / drain layer away from the substrate. The bridging wire is located in the second source / drain layer and is connected to the first gate line bridging portion and the second gate line bridging portion through vias.

6. The display panel according to claim 3, wherein, The display panel includes a plurality of first grid line bridging portions and a plurality of second grid line bridging portions; At least a portion of the first gate line bridging portions have their orthographic projections on the substrate disposed opposite each other in the first direction, and the orthographic projections of the plurality of first gate line bridging portions disposed opposite each other in the first direction are distributed at intervals along the first direction. At least a portion of the second gate line bridging portions have their orthographic projections on the substrate disposed opposite each other in the first direction, and the orthographic projections of the plurality of second gate line bridging portions disposed opposite each other in the first direction are distributed at intervals along the first direction.

7. The display panel according to claim 3, wherein, The display panel also includes: A first signal line extends along a second direction from its orthogonal projection onto the substrate. The first signal line is used to provide a clock signal or a power signal to the first gate driving circuit. The first signal line is located in the integrated area of ​​the first gate driving circuit.

8. The display panel according to claim 1, wherein, The pixel driving circuit includes driving transistors, the first gate driving circuit includes multiple transistors, the display area further includes a first wiring area located between the first pixel driving circuit integration area and the second pixel driving circuit integration area, and the display panel further includes: A first signal line is used to provide a clock signal or a power signal to the first gate drive circuit, and the first signal line is located in the first trace area. A shielding layer is located on one side of the substrate. The shielding layer includes a plurality of first shielding portions and a second shielding portion, and the plurality of first shielding portions are arrayed in the first direction and the second direction. The first blocking portion is provided in the first pixel driving circuit integration area, the second pixel driving circuit integration area, and the first wiring area. The orthographic projection of the first blocking portion in the first pixel driving circuit integration area and the second pixel driving circuit integration area on the substrate and the orthographic projection of the channel area of ​​the driving transistor in the pixel driving circuit on the substrate at least partially overlap. The second shielding portion is located in the first gate drive circuit integration area, and the orthographic projection of the second shielding portion on the substrate and the orthographic projection of the channel region of at least a portion of the transistors in the first gate drive circuit on the substrate at least partially overlap.

9. The display panel according to claim 8, wherein, The second shielding portion extends along the second direction in the orthographic projection on the substrate, and the plurality of first shielding portions and second shielding portions are interconnected.

10. The display panel according to claim 1, wherein, The display panel also includes: A plurality of light-emitting units, at least some of which are located in the first pixel driving circuit integration area and the second pixel driving circuit integration area respectively, and at least some of which are located in the first gate driving circuit integration area; An electrical connection layer is located on one side of the substrate. The electrical connection layer includes electrical connection lines. The light-emitting unit located in the first gate driving circuit integration area is connected to the pixel driving circuit located in the first pixel driving circuit integration area and / or the second pixel driving circuit integration area through the electrical connection lines.

11. The display panel according to claim 1, wherein, The second direction is the column direction. The display panel also includes a virtual pixel driving circuit group, which includes one or more columns of virtual pixel driving circuits. The virtual pixel driving circuit does not drive the light-emitting unit to emit light. The virtual pixel driving circuit group is located in the first pixel driving circuit integration area and / or the second pixel driving circuit integration area; The display panel also includes: Multiple light-emitting units, at least some of which are located in the first pixel driving circuit integration area and the second pixel driving circuit integration area respectively; An electrical connection layer is located on one side of the substrate, and the electrical connection layer includes electrical connection lines; The light-emitting unit located in the area where the virtual pixel driving circuit group is located is connected to the pixel driving circuit located in the first pixel driving circuit integration area and / or the second pixel driving circuit integration area through the electrical connection line.

12. The display panel according to claim 1, wherein, The display panel also includes: The third source / drain layer is located on one side of the substrate. The third source / drain layer includes multiple data lines and multiple first power lines. The first power lines are used to provide power signals to the pixel driving circuit. Wherein, at least a portion of the data lines and the first power line are located in the first pixel driving circuit integration area and the second pixel driving circuit integration area, and at least a portion of the data lines and the first power line are located in the first gate driving circuit integration area.

13. The display panel according to claim 1, wherein, The display panel also includes: An electrical connection layer is located on one side of the substrate, and the electrical connection layer includes multiple electrical connection lines; An electrode layer is located on the side of the electrical connection layer opposite to the substrate. The electrode layer includes a plurality of electrode portions, which are used to form the first electrode of the light-emitting unit. The electrode portions are connected to the pixel driving circuit through the electrical connection line. Wherein, the first pixel driving circuit integration area and the second pixel driving circuit integration area form a pixel driving circuit integration area, and the extension length of the electrical connection line connected to the electrode portion located in the first gate driving circuit integration area is greater than the extension length of the electrical connection line connected to the electrode portion located in the pixel driving circuit integration area. The area of ​​the electrode portion located in the first gate driving circuit integration area projected onto the substrate is smaller than the area of ​​the electrode portion located in the pixel driving circuit integration area projected onto the substrate.

14. The display panel according to claim 1, wherein, The first gate drive circuit includes a plurality of shift register units, which are distributed along the second direction.

15. A display device, wherein, The display device includes the display panel as described in any one of claims 1-14.

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