Electronic device

Abstract

The present disclosure relates to an electronic device. An electronic device includes a logic gate coupled to a first node to which a reference voltage is applied, a random voltage generator configured to generate a random voltage at a second node, and a first diode having a cathode coupled to the second node and an anode coupled to the first node.

Description

Priority requirements

[0001] This application claims priority to French patent application number FR 2412655, filed on November 19, 2024, the contents of which are incorporated herein by reference in their entirety to the fullest extent permitted by law. Technical Field

[0002] This disclosure relates generally to electronic devices, and more specifically, to electronic devices for preventing laser scanning attacks. Background Technology

[0003] There are many hacking techniques that allow individuals to access information contained on a chip. For example, an individual could manage to determine the binary information contained in the logic circuitry of an electronic chip. One such hacking technique is laser scanning.

[0004] There is a need to protect the chip from laser scanning.

[0005] It is necessary to overcome all or part of the known shortcomings of electronic devices regarding hacking techniques. Summary of the Invention

[0006] One embodiment provides an electronic device comprising: a logic gate coupled to a first node to which a reference voltage is applied; a random voltage generator configured to generate a random voltage at a second node; and a first diode having an anode coupled to the first node and a cathode coupled to the second node.

[0007] Another embodiment provides a method of using an electronic device including a logic gate coupled to a first node, a random voltage generator, and a first diode having a cathode and an anode connected to the first node, the method including applying a random voltage to the cathode using the random voltage generator; and applying a reference voltage to the anode.

[0008] According to one embodiment, a logic gate is a logic circuit that includes one of the following: an inverter, a logical AND gate, a logical NAND gate, an OR gate, a NOR gate, an XOR gate, or an XOR NOT gate.

[0009] According to one embodiment, the device includes a first region, which includes a plurality of logic gates and a plurality of first diodes.

[0010] According to one embodiment, in the first region, the density of the first diodes is greater than 5 per square millimeter.

[0011] According to one embodiment, at least two first diodes have different sizes.

[0012] According to one embodiment, at least two first diodes have different structures.

[0013] According to one embodiment, at least one first diode includes a PN junction formed between a first well of a first conductivity type and a substrate of a device of a second conductivity type, the second conductivity type being opposite to the first conductivity type.

[0014] According to one embodiment, at least one first diode includes a PN junction formed between a first well of a first conductivity type and a second well of a second conductivity type, the second conductivity type being opposite to the first conductivity type, and the second well being located within the first well.

[0015] According to one embodiment, the random voltage generator is configured to generate at least two different random voltages, each of which is applied to the cathode of at least one first diode.

[0016] According to one embodiment, the random voltage generator includes: an input coupled to a node to which a clock signal is applied; and at least one circuit module configured to receive a random number as input and modify the clock signal according to the random number.

[0017] According to one embodiment, the random voltage generator includes a circuit module configured to modify the amplitude of a clock signal based on a random number.

[0018] According to an embodiment, the random voltage generator includes a circuit module configured to divide a clock signal.

[0019] According to one embodiment, the random voltage generator includes at least one random switching circuit module.

[0020] According to one embodiment, the random voltage generator includes a circuit module configured to add a delay to a clock signal. Attached Figure Description

[0021] The foregoing features and advantages, as well as other features and advantages, will be described in detail in the remainder of the disclosure of specific embodiments given by way of illustration and not limitation, with reference to the accompanying drawings, wherein:

[0022] Figure 1A , Figure 1B and Figure 1C The principle of laser scanning is illustrated;

[0023] Figure 2 An embodiment of an electronic device for preventing laser scanning is shown;

[0024] Figure 3 An embodiment of a device for preventing laser scanning is illustrated schematically;

[0025] Figure 4 An embodiment of a device for preventing laser scanning is illustrated schematically;

[0026] Figure 5 A top view schematically illustrates an embodiment of a device for preventing laser scanning;

[0027] Figure 6 An embodiment of an electronic device including a random voltage generator is shown; and

[0028] Figure 7 It shows Figure 6 The operation of the random voltage generator. Detailed Implementation

[0029] In the various figures, similar features have been designated by similar reference numerals. In particular, common structural and / or functional features in the various embodiments may have the same reference numerals and may have the same structure, dimensions, and material properties.

[0030] For clarity, only those steps and elements useful for understanding the embodiments are shown and described in detail.

[0031] Unless otherwise indicated, when referring to two elements connected together, it means that there is no direct connection between them except for the conductor, and when referring to two elements coupled together, it means that the two elements can be connected or they can be connected via one or more other elements.

[0032] In the following description, when absolute positional qualifiers such as “front,” “back,” “up,” “down,” “left,” “right,” etc., or relative positional qualifiers such as “upper side,” “lower side,” “upper part,” “lower part,” etc., or orientation qualifiers such as “horizontal,” “vertical,” etc. are mentioned, the orientation of the drawings is indicated unless otherwise specified.

[0033] Unless otherwise specified, the expressions “about,” “approximately,” “basically,” and “roughly” indicate addition or subtraction of 10% or 10°, preferably 5% or 5°.

[0034] Furthermore, the embodiments described below are particularly suitable for any type of industrial market requiring logic circuitry, preferably secure logic circuitry. More specifically, such logic circuitry can be intended for use in: the automotive industry, such as in the field of automotive electrification or in the field of advanced driver assistance systems (ADAS); industrial sectors, such as in the fields of green energy, infrastructure electrification, the Internet of Things (IoT), and smart homes, where power and energy consumption and data exchange are key elements; the personal electronics industry, such as in the fields of mobile phones and the Internet of Things (IoT), and in the field of high-speed interfaces; and the communication equipment, computer, and peripheral equipment industry, such as in the fields of infrastructure and data centers, and in the field of low Earth orbit (LEO) satellites.

[0035] The term "logic gate" is used to specify an electronic circuit that performs logical (Boolean) operations on a sequence of bits. This sequence is given by a square-wave modulated input signal, precisely timed by a clock circuit or quartz. Logic gates include inverter (INV) gates, AND gates, NAND gates, OR gates, NOR gates, XOR gates, and XNOR gates.

[0036] Figure 1A , Figure 1B and Figure 1C The principle of laser scanning is illustrated. More specifically, Figure 1A The logic circuit in its first state is shown, on which laser scanning is performed. Figure 1B The same logic circuit is shown in the second state, on which laser scanning is performed. Figure 1C It shows Figure 1A and Figure 1B The reference current IGND of the logic circuit in the circuit.

[0037] Figure 1A and Figure 1B An inverter (INV) gate circuit 10 is shown. Circuit 10 includes two transistors 12 and 14. Transistors 12 and 14 are, for example, CMOS transistors. Transistor 12 is, for example, a PMOS transistor. Transistor 14 is, for example, an NMOS transistor. Transistors 12 and 14 are coupled in series between a power supply voltage node 16 and a reference voltage node 18. More specifically, at the source of transistor 12, the first power supply node of the logic circuit inverter 10 is coupled, for example, to, preferably connected to node 16 (to receive a power supply voltage (e.g., VDD)), and the drain of transistor 12 is coupled, for example, to, preferably connected to output node 20, generating an output voltage Vout at output node 20. At the source of transistor 14, the second power supply node of the logic circuit inverter 10 is coupled, for example, to, preferably connected to node 18 (to receive a reference power supply voltage (e.g., ground)), and the drain of transistor 14 is coupled, for example, to, preferably connected to output node 20. The control nodes of transistors 12 and 14 are coupled to each other, preferably connected to each other, and connected to input node 22 to which an input voltage Vin is applied. Circuit 10 also includes a capacitor 23 coupled between node 20 and node 18.

[0038] exist Figure 1A In this circuit, circuit 10 receives the binary value "1" as input and outputs the binary value "0". Figure 1B In the circuit, circuit 10 receives the binary value "0" as input and outputs the binary value "1".

[0039] During laser scanning, a laser beam is directed to (i.e., applied to) circuit 10, such as the drain of transistor 14. The application of the laser beam induces electron-hole pairs at node 20, and thus generates a current Iph in circuit 10. Current Iph in Figure 1A and Figure 1B The current source 24 represents the current Iph. The location of the current source 24 depends on the state of the logic circuit.

[0040] exist Figure 1A In the case where the output of circuit 10 corresponds to the binary value "0", transistor 14 is turned on and transistor 12 is turned off. Therefore, source 24, representing current Iph, is located between node 16 and node 20.

[0041] exist Figure 1B In the case where the output of circuit 10 delivers a signal corresponding to the binary value "1", transistor 14 is turned off and transistor 12 is turned on. Therefore, the source 24 representing the current Iph is located between node 18 and node 20.

[0042] Figure 1C The reference current IGND, which varies with time, is shown; that is, the current flowing through node 18, i.e., the total current seen on the ground. Figure 1C Including corresponding to Figure 1A The current curve IGND in circuit 10, and the curve 26 corresponding to it. Figure 1B The current curve IGND in circuit 10 is shown in curve 28.

[0043] Between times t1 and t2, a laser beam is applied to node 20, for example, to the drain of transistor 14. Therefore, it is possible to... Figure 1C The effect of the state of circuit 10 on the current IGND was observed. More precisely, between times t1 and t2, the current IGND corresponding to curve 26 is lower than the current IGND corresponding to curve 28. This difference is due to... Figure 1B In the case of rather than in Figure 1A This is caused by the current Iph flowing through node 18 under certain conditions.

[0044] The significant difference between curves 26 and 28 makes it possible to determine the state of circuit 10 by measuring the current IGND and by applying a laser beam to circuit 10.

[0045] Figure 2 An embodiment of an electronic device for preventing laser scanning is shown. More specifically, Figure 2 The circuit 30 is shown with protection against laser scanning attacks.

[0046] Circuit 30 includes logic gate 31. The logic gate includes an input having a voltage Vin applied thereto corresponding to the input binary value. Logic gate 31 includes an output having an output voltage Vout applied thereto corresponding to the output binary value.

[0047] Logic gate 31 includes a first power node coupled to, and preferably connected to, node 16 to which a power supply voltage (e.g., VDD) is applied. Logic gate 31 also includes a second power node coupled to, and preferably connected to, node 18 to which a reference power supply voltage (e.g., ground) is applied.

[0048] exist Figure 2 In the example, the logic gate is an inverter (INV) gate. Therefore, circuit 30 includes elements of the aforementioned circuit 10. Therefore, logic gate 31 includes elements as combined with... Figure 1A and Figure 1B The arrangement and coupling of transistors 12 and 14, and capacitor 23.

[0049] Circuit 30 also includes a diode 32 coupled between node 34 and node 18. More specifically, the cathode of diode 32 is coupled to, preferably connected to, node 34 and the anode of diode is coupled to, preferably connected to, node 18.

[0050] Node 34 is the node to which a random voltage VRAND is applied, i.e., a voltage with random values ​​and varying durations. Therefore, the voltage VRAND is independent of the voltage Vout at node 20, independent of the voltage Vin at node 22, and independent of the supply voltage at node 16. The voltage VRAND is not a constant voltage. The voltage VRAND is, for example, a periodic voltage whose amplitude and period vary randomly.

[0051] Applying a laser beam to the circuit causes a current to form through diode 32. Therefore, this current has a constant value, preferably zero, in the absence of a laser beam, and has a variable value depending on the voltage VRAND when a laser beam is applied.

[0052] The random current flowing through diode 32 increases to Figure 1C The reference current is shown. Adding a random component to the reference current ensures that it is no longer possible to identify a significant difference between the reference current when the output of circuit 10 is in the first binary state and the reference current when the output of circuit 10 is in the second binary state.

[0053] The diode is preferably dedicated to providing laser scanning protection. Therefore, the cathode of diode 32 does not receive any voltage other than the voltage VRAND.

[0054] Figure 3An embodiment of a device for preventing laser scanning is illustrated schematically. More specifically, Figure 3 schematically shown Figure 2 Implementation of diode 32.

[0055] Figure 3 An electronic device 36 is shown. Device 36 is, for example, an electronic chip. Device 36 includes a semiconductor substrate 38 of a first conductivity type. Substrate 38 is, for example, a p-type doped substrate.

[0056] Device 36 includes, for example, one or more logic circuit regions 40. A logic circuit region refers to a circuit region in which components of logic circuits or gates are formed, such as a circuit region of transistor components. For example, transistors 12 and 14 of circuit 30 may be formed in region 40. Region 40 includes, for example, a semiconductor well, such as a well of at least a second conductivity type, such as an N-type well. Region 40 preferably includes at least one more heavily doped region 42 coupled to, preferably connected to, a ground node 18.

[0057] Device 36 includes a well 44. The well 44 is made of a doped semiconductor material of a second conductivity type, the opposite of the first conductivity type. The well 44 is, for example, N-type doped. A diode 32 is formed at the interface between the well 44 and the substrate 38.

[0058] For example, well 44 includes a more heavily doped region 46 of the same conductivity type as well 44. Region 46 is coupled to, and preferably connected to, the output of a random voltage source circuit. Thus, region 46 receives a random voltage VRAND.

[0059] Substrate 38 includes, for example, a more heavily doped region 48 of the same conductivity type as substrate 38. Region 48 is coupled to, preferably connected to, region 42. Region 48 is coupled to, for example, preferably connected to a reference voltage source.

[0060] Figure 4 An embodiment of a device for preventing laser scanning is illustrated schematically. More specifically, Figure 3 schematically shown Figure 2 Another embodiment of diode 32.

[0061] Figure 4 An electronic device 50 is shown. Device 50 is, for example, an electronic chip. Device 50 includes a semiconductor substrate 52 of a first conductivity type. Substrate 52 is, for example, a p-type doped substrate.

[0062] Device 50 includes, for example, one or more logic circuit regions 54, which are combined with Figure 3 The logic circuit region 40 is the same. The logic circuit region includes, for example, combinations with... Figure 3 The same semiconductor well 56 as well 42.

[0063] Device 50 includes a well 58 located in substrate 52. The well 58 is made of a doped semiconductor material of a second conductivity type. The well 58 is, for example, N-type doped.

[0064] Device 50 includes another well 60. Well 60 is made of a doped semiconductor material of a first conductivity type, namely the conductivity type of substrate 52. Well 60 is, for example, p-type doped. Well 60 is located in well 58.

[0065] Diode 32 is formed at the interface between well 58 and well 60.

[0066] Well 58 includes, for example, a more heavily doped region 62 of the same conductivity type as well 58. Region 62 is coupled to, and preferably connected to, the output of a random voltage source. Thus, region 62 receives a random voltage VRAND.

[0067] For example, well 60 includes a more heavily doped region 64 of the same conductivity type as well 60. Region 64 is coupled to, and preferably connected to, region 56. Region 64 is coupled to, and preferably connected to, a reference voltage source, for example.

[0068] Figure 5 A top view schematically illustrates an embodiment of a device 66 for preventing laser scanning. Device 66 is, for example, an electronic chip. Device 66 includes, for example, logic circuitry. Figure 5 A portion of device 66, which includes logic circuitry, is shown.

[0069] Device 66 includes a substrate 68. Substrate 68 is made of a semiconductor material. Substrate 68 is doped with a first conductivity type, such as p-type.

[0070] Device 66 also includes at least one well 70, for example, at least two wells 70, for example, at least ten wells 70. The wells 70 are located in the substrate 68. The wells 70 are made of a semiconductor material, for example, the same material as the substrate 68. The wells 70 are doped with a second conductivity type, that is, a type opposite to the conductivity type of the substrate 68. For example, the wells 70 are N-type doped.

[0071] The well 70 is preferably flush with the surface of the substrate 68. The wells 70 form a row extending along the X-axis. The wells 70 preferably extend in directions parallel to each other. Preferably, each well 70 has a substantially constant dimension along the Y-axis.

[0072] The wells 70 are separated from each other by regions 71 of the substrate 68. The regions 71 of the substrate 68 separating the wells 70 preferably extend over the entire height of the wells 70. The regions 71 of the substrate 68 located between the wells 70 have, for example, substantially constant dimensions along the Y-axis.

[0073] Therefore, device 66 includes a region 71 of well 70 and substrate 68 alternating along the Y-axis at the substrate surface.

[0074] For example, wells 70 may be located in the same row along the X-axis. Wells 70 are then aligned along the X-axis. Wells 70 in the same row are separated from each other by region 71 of substrate 68.

[0075] Device 66 includes rows 72 of cells 74. These rows preferably extend along the X-axis. Therefore, rows 72 are preferably parallel to each other. Each row 72 preferably includes at least two cells 74, for example, at least ten cells.

[0076] Each cell 74 includes a portion of a well 70 and a portion of a region 71 of the substrate 68. Therefore, each cell 74 includes a portion of a well 70 and a portion of a region 71 on the surface of the substrate 68. Each cell 74 thus includes a PN interface. Preferably, each cell 74 includes a PN interface on the surface of the substrate 68.

[0077] Each unit 74 is surrounded, for example, by an insulating wall 76.

[0078] Preferably, all cells 74 in the same row 72 have the same dimension along the Y-axis. Preferably, except for cell 74a, all cells 74 in the same row 72 have the same dimension along the Y-axis. The dimension of each cell 74a along the Y-axis is substantially equal to the sum of the dimensions of its row along the Y-axis. Figure 5 Two units 74a are shown in the figure. Figure 5 The dimensions of the two units 74a along the Y-axis are equal to the sum of the dimensions of the two rows 72. Therefore, Figure 5 Unit 74a extends over two rows 72.

[0079] Preferably, each unit 74 includes at least one electronic component. An electronic component is an active or passive element designed to be assembled with other components to perform one or more electronic functions. For example, the component may be a transistor, resistor, diode, capacitor, or inductor.

[0080] Device 66 includes unit 74b, which includes diode 32, as described above, capable of protecting the circuit from laser scanning attacks. Preferably, each unit 74b includes a single diode 32. Preferably, each unit 74b includes only diode 32.

[0081] Furthermore, device 66 includes unit 74c. Each unit 74c includes an electron tube and a diode 32. This component is, for example, a transistor. The diode 32 is, for example, located in a well 78 within unit 74c.

[0082] The cathodes of all diodes 32 are coupled, for example, to, preferably connected to, node 18 (not shown) where a reference voltage is applied, for example, to ground.

[0083] The anode of each diode 32 is coupled to, preferably connected to, a source of random voltage. Device 66 thus includes a random voltage generator. Preferably, the random voltage generator is configured to generate at least two different random voltages. Diodes 32 preferably do not all receive the same random voltage. Preferably, diodes 32 receive a random voltage from at least two random voltages generated by the random voltage generator.

[0084] According to one embodiment, the anode of each diode 32 receives a random voltage that is different from the random voltage received by the other diodes 32. The random voltage generator is then configured to generate at least as many random voltages as the diodes 32 and device 66.

[0085] According to another embodiment, at least two diodes 32 receive the same random voltage. Preferably, the same random voltage is not delivered to diodes in the same row. Therefore, diodes 32 in the same row preferably all receive different random voltages.

[0086] Diodes 32 are preferably distributed in device 66, preferably distributed over the entire area including logic circuit elements. Preferably, each row 72 includes at least one diode 32, for example, at least two diodes 32. Preferably, the density of diodes 32 in row 72 is at least five diodes 32 per 100 square micrometers, preferably at least ten diodes 32 per 100 square micrometers.

[0087] Preferably, device 66 does not include two adjacent diodes 32. In other words, each diode 32 is isolated from other diodes 32 by at least one unit 72 that does not include diode 32.

[0088] Preferably, device 66 includes at least two types of diodes 32. For example, device 66 includes at least one diode 32, such as in combination with... Figure 3 The diode, and at least one diode, for example, in combination Figure 4 The aforementioned diode.

[0089] For example, device 66 includes at least two diodes with different sizes. For example, device 66 includes at least two diodes with a PN interface, i.e., contact surfaces with different sizes between the cathode and anode.

[0090] For example, device 66 includes at least two diodes 32 with different doping values.

[0091] Figure 6 An embodiment of a random voltage generator 100 is shown. The generator 100 is configured, for example, to generate multiple random voltages. Figure 6In this configuration, generator 100 is configured to generate N random voltages (VRAND1, VRAND2, VRAND3…, VRANDN), where N is greater than 3. Generator 100 therefore includes N outputs, each generating a random voltage. Each output is coupled to, and preferably connected to, the cathode of at least one diode 32. Figure 6 In the example, each output of generator 100 is coupled to, preferably connected to, the cathode of three diodes 32.

[0092] Generator 100 includes a first input 102. The generator is configured to receive a clock signal CLK at input 102, i.e., a periodic oscillating voltage with a constant period, such as a square wave signal.

[0093] Generator 100 includes at least one second input, not shown. The second input is configured to receive random values. Each second input is coupled to, and preferably connected to, the output of a random number generator. The random number generator is, for example, a physical random number generator. The random number generator generates random numbers, for example, for data encryption and / or decryption. The value of the random number provided to the output of the random number generator is variable. Therefore, the value of the random number provided to the output of the random number generator changes in each cycle of a clock signal, for example, each cycle of the clock signal CLK.

[0094] The generator 100 includes at least one circuit module configured to modify a clock signal to obtain a random voltage. Each circuit module depends on at least one random value received at a second input. Figure 6 The diagram illustrates several types of circuit modules arranged in a certain order. A generator can have any number of circuit modules arranged in any order, and certain types of circuit modules can appear multiple times. The generator may also include other types of circuit modules capable of modifying the clock signal to obtain random voltages.

[0095] exist Figure 6 In the example, generator 100 includes circuit module 104 configured to divide a clock signal by a random value. Circuit module 104 includes a first input configured to receive a clock signal CLK and a second input configured to receive a random value RAND-DIV. The first input of circuit module 104 is coupled to, and preferably connected to, a first input 102 of generator 100. The second input of circuit module 104 is coupled to, and preferably connected to, a second input of generator 100. Circuit module 104 includes an output that generates a CLK-DIV signal thereon. The signal CLK-DIV is equal to the signal CLK having a frequency divided by the random value RAND-DIV.

[0096] exist Figure 6In the example, generator 100 includes circuit module 106. Circuit module 106 is configured to add delays, preferably different from each other, to each signal received as input. Figure 6 In the example, circuit module 106 includes m first inputs configured to receive voltages. Figure 6 In the example, the m first inputs are coupled to, and preferably connected to, the output of circuit module 104. Therefore, all of these first inputs receive the same voltage CLK-DIV. The value of the number m is greater than or equal to 1, preferably greater than or equal to 3. Circuit module 106 also includes m second inputs, each configured to receive a random number (RAND-D1, RAND-D2, RAND-D3, RAND-Dm), preferably different from other random numbers received on the other second inputs of circuit module 106. These second inputs are coupled to, and preferably connected to, the output of a random number generator, preferably a different output.

[0097] exist Figure 6 In the example, circuit module 106 includes m elements 107 (D1, D2, D3, ..., Dm). Each element 107 includes a first input configured to receive a voltage and a second input configured to receive a random number. Each first input is coupled to, preferably connected to, a first input of circuit module 106, and therefore coupled to, preferably connected to, an output of circuit module 104.

[0098] Each circuit module 107 is configured to add a delay to the signal received at the first input of the element. The delay added by each element 107 depends on the random value received by the element 107.

[0099] exist Figure 6 In the example, generator 100 includes a random switching circuit module 108. Circuit module 108 includes m first inputs, each coupled to, and preferably connected to, the output of element 107. Therefore, the output of each element 107 is coupled to, and preferably connected to, the first input of circuit module 108. Circuit module 108 includes a second input configured to receive a random value RAND-A1 generated by a random value generator. The second input of circuit module 108 is, for example, coupled to, and preferably connected to, the output of a random number generator.

[0100] Circuit module 108 includes outputs. For example, circuit module 108 includes an even number of outputs. Circuit module 108 includes, for example, a number different from, for example, greater than, the number of inputs. Each output of circuit module 108 is coupled to, preferably connected to, a first input of circuit module 108. The first input coupled to, preferably connected to, each output depends on a random value RAND-A1. Each output of circuit module 108 may be coupled to, preferably connected to, any first input of circuit module 108. Multiple outputs may be coupled to the same first input. For some random values ​​RAND-A1, some first inputs may not be coupled to the outputs of circuit module 108, preferably not for all possible values ​​of RAND-A1. When the random value received at the second input changes, the connection between the first input and the output changes so that it depends on the new value RAND-A1.

[0101] exist Figure 6 In the example, generator 100 includes circuit module 110. Circuit module 110 is configured to apply an OR function to a voltage derived from the output of a previous circuit module, namely, circuit module 108. Circuit module 110 includes OR logic gates 111. Circuit module 110 includes, for example, at least three gates 111. Circuit module 110 includes, for example, half the number of gates 111 as circuit module 108. Each gate 111 includes two inputs coupled to, preferably connected to, an output of circuit module 108. Preferably, each output of circuit module 108 is coupled to, preferably connected to, one, preferably a single input of gate 111.

[0102] According to another embodiment, gate 111 can be a logic gate other than an OR gate. For example, gate 111 can be an AND gate, a NAND gate, or an XOR gate.

[0103] exist Figure 6 In the example, generator 100 includes a random switching circuit module 112. Circuit module 112 includes a first input and a second input. Circuit module 112 includes, for example, as many first inputs as gates 111 included in circuit module 110. Each first input is, for example, coupled to, preferably connected to the output of gate 111. For example, each output of gate 111 is coupled to, preferably connected to, the first input of circuit module 112. The second input of circuit module 112 is configured to receive a random value RAND-A2 generated by a random value generator. The second input of circuit module 112 is, for example, coupled to, preferably connected to the output of a random number generator.

[0104] Circuit module 112 includes outputs. Circuit module 112 includes, for example, outputs in a number different from, for example, greater than, the number of inputs. Each output of circuit module 112 is coupled to, preferably connected to, a first input of circuit module 112. The first input coupled to, preferably connected to, each output depends on a random value RAND-A2. Each output of circuit module 112 may be coupled to, preferably connected to, any first input of circuit module 112. Multiple outputs may be coupled to the same first input. For some random values ​​RAND-A2, some first inputs may not be coupled to the outputs of circuit module 112, preferably not for all possible values ​​of RAND-A2. When a random value received at a second input is modified, the connection between the first input and the output is changed to depend on the new value RAND-A2.

[0105] Generator 100 includes a random voltage conversion (“level converter”) circuit module 114. Circuit module 114 is configured to modify the voltage amplitude of an input signal based on random values. More specifically, circuit module 114 includes elements 115, each element being a voltage conversion circuit configured to modify the voltage amplitude based on random values. Circuit module 114 includes p elements 115, where p is preferably greater than or equal to 3. Circuit module 114 preferably includes as many elements 115 as circuit module 112 has outputs. Each element 115 has a first input, for example coupled to, and preferably connected to, the output of circuit module 112, and a second input configured to receive random values ​​(RAND-LS1, RAND-LS2, RAND-LS3, RAND-LSp). Each element 115 is configured to add a voltage, positive or negative, to the voltage received at the first input, the value of which depends on the random value received at the second input.

[0106] exist Figure 6 In the example, generator 100 includes circuit module 116. Circuit module 116 includes a first input and a second input. Circuit module 116 includes as many first inputs as circuit module 115 includes elements 115. Each first input of circuit module 116 is coupled to, and preferably connected to, the output of circuit module 114, i.e., the output of element 115. Circuit module 116 includes, for example, as many second inputs as the first inputs. The second inputs are configured to receive different random numbers (RAND-C1, RAND-C2, ..., RAND-Cp). Therefore, the first inputs are preferably coupled to, and preferably connected to, the output of the random number generator.

[0107] Circuit module 116 includes outputs. Circuit module 116 preferably includes as many outputs as the first inputs. Each output of circuit module 116 is coupled to, preferably connected to, one, preferably a single first input of circuit module 116. Each first input of circuit module 116 is coupled to, preferably connected to, one, preferably a single output of circuit module 116. Circuit module 116 includes elements 117, for example, as many elements 117 as the outputs of circuit module 116. Each output of circuit module 116 is coupled to a reference node 117a, for example, ground, via element 117.

[0108] Each element 117 receives a random number. More precisely, each element 117 includes a first input coupled to, preferably connected to, the output of circuit module 116, and a second input coupled to, preferably connected to, a second input of circuit module 116, thereby receiving a random number (RAND-C1, RAND-C2, ..., RAND-Cp). Element 117 is a capacitive element. The capacitance of each element 117 depends on the random number received by that element 117. For example, each element 117 includes multiple branches comprising switches and capacitors coupled in series, the control of which switches depends on the random number provided to element 117. Thus, the random number received at the input of element 117 determines which switches are on and which are off, and thus determines the total capacitance value of element 117.

[0109] In one example, components 117 are identical to each other. In another example, components 117 are different from each other. For example, the number of capacitors and the capacitance of the capacitors are different.

[0110] exist Figure 6 In the example, generator 100 includes a random switching circuit module 118. Circuit module 118 includes a first input and a second input. Circuit module 118 includes, for example, as many first inputs as circuit module 116 includes. Each first input is coupled to, for example, preferably connected to an output of circuit module 116. Each output of circuit module 116 is coupled to, for example, preferably connected to a first input of circuit module 118. The second input of circuit module 118 is configured to receive a random value RAND-A3 generated by a random value generator. The second input of circuit module 118 is coupled to, for example, preferably connected to an output of a random number generator.

[0111] Circuit module 118 includes outputs. Circuit module 118 includes, for example, outputs in a number different from, for example, greater than, the number of inputs. Preferably, circuit module 118 includes N outputs. Each output of circuit module 118 is coupled to, preferably connected to, a first input of circuit module 118. The first input to which each output is coupled, preferably connected, depends on a random value RAND-A3. Each output of circuit module 118 may be coupled to, preferably connected to, any first input of circuit module 112. Multiple outputs may be coupled to the same first input. For some random values ​​RAND-A3, some first inputs may not be coupled to the outputs of circuit module 112, preferably not for all possible values ​​of RAND-A3. When a random value received at a second input changes, the connection between the first input and the output changes so that it depends on the new value RAND-A3.

[0112] The output of circuit module 118 is coupled to, and preferably connected to, the output of generator 100. Therefore, voltages VRAND1, VRAND2, VRAND3, ... VRANDN are generated on the output of circuit module 118.

[0113] All random values ​​RAND-DIV, RAND-D1, RAND-D2, RAND-D3…RAND-Dm, RAND-A1, RAND-A2, RAND-A3, RAND-LS1, RAND-LS2…RAND-LSp, RAND-C1, RAND-C2…RAND-Cp are preferably different. Therefore, although two random values ​​may be equal at a given time, they are preferably different at another time. Alternatively, random values ​​of different circuit modules may be equal to each other. Preferably, random values ​​of the same circuit module are different.

[0114] Figure 7 It shows Figure 6 The operation of the generator. More precisely, Figure 7 This is a timing diagram, which includes: curve 120, showing the change of clock signal CLK; curve 122, showing the change of signal CLK-DIV due to applying signal CLK to the input of circuit module 104; curve 124, showing the change of signal CLK-D1 due to applying signal CLK-DIV to the input of component 107; curve 126, showing the change of voltage V1 due to applying the signal shown in curve 124 to the input of component 115; curve 128, showing the change of voltage VRAND due to applying the signal shown in curve 126 to the input of component 117; curve 130, showing the current IL generated by the laser beam; and curve 132, showing the current Iph.

[0115] Curve 120 illustrates the clock signal CLK. Signal CLK is a periodic square wave signal with a constant period P.

[0116] Curve 122 illustrates the signal CLK-DIV, which corresponds to the signal CLK after frequency division depending on a variable random number. Therefore, between times t0 and t1, the frequency of signal CLK-DIV is equal to half the frequency of signal CLK. Between times t1 and t2, the frequency of signal CLK-DIV is equal to the frequency of signal CLK divided by 1. After time t2, the frequency of signal CLK-DIV is equal to the frequency of signal CLK divided by 5.

[0117] Curve 124 illustrates the signal generated by applying signal CLK-DIV to the input of element 107, i.e., the element causing the random delay. Therefore, the rising edge of signal CLK-DIV at time t0 is delayed by a delay D1 determined by the random number received by element 107, and is thus placed at time t3. The rising edge of signal CLK-DIV at time t1 is delayed by D2, which is shorter than delay D1, the random number has changed, and is thus placed at time t4. The rising edge of signal CLK-DIV at time t2 is delayed by a delay D3, which is longer than delay D2, the random number has changed, and is thus placed at time t5.

[0118] Curve 126 illustrates the change in signal V1 caused by applying signal CLK-D1 to the input of voltage conversion element 115. Therefore, at the rising edge of time t3, voltage V1 takes a first value depending on the random number received by element 115, for example, equal to 0.3V. At the rising edge of time t4, voltage V1 takes a second value different from the first value; the random number has changed, for example, equal to 0.2V. At the rising edge of time t5, voltage V1 takes a third value different from the second value; the random number has changed, for example, equal to 0.1V.

[0119] Curve 128 illustrates the change in voltage VRAND caused by voltage V1 applied to the input of capacitor element 117. At times t3, t4, and t5, the capacitor of element 117 charges. Therefore, voltage VRAND gradually increases to reach the value of voltage V1. Similarly, at times t6 and t7, corresponding to the falling edge of voltage V1, the capacitor of element 117 discharges. Therefore, voltage VRAND gradually decreases to reach the value of voltage V1. The charging and discharging times depend on the value of the random number received by element 117 and are therefore different from each other.

[0120] At time t8, the laser beam is applied near the logic gate that prevents laser scanning, such as a combination... Figure 2The laser beam is removed at time t9. Therefore, before time t8, the current IL is equal to a low value I0, such as zero. At time t8, the current IL gradually increases to reach a high value I1. The high value depends on the state of the logic gate. At time t9, the current IL gradually decreases to reach a low value I0.

[0121] The current Iph corresponds to the current flowing through diode 32 when voltage VRAND is applied to the cathode of diode 32. Before time t8, current Iph has a low value, such as zero. From time t8 onwards, the value of current Iph increases and decreases in a manner determined by the change in voltage VRAND, and is therefore determined by random values ​​from generator 100.

[0122] The current IGND, measured during a laser scanning attack, is the sum of currents IL and Iph. Therefore, the changes caused by current Iph make it difficult to determine high values ​​based on the state of the logic gates.

[0123] The advantage of the described embodiments is that it is more difficult for an individual to determine the values ​​contained in the logic circuit by performing a laser scan.

[0124] Another advantage of this embodiment is that different Iph currents are generated on different diodes 32 associated with different logic gates. Therefore, it is not possible to use the values ​​obtained on different logic gates to determine the current values ​​corresponding to different logic states.

[0125] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations can be combined, and other variations will occur to those skilled in the art.

[0126] Finally, based on the functional indications given above, the actual implementation of the described embodiments and variations is within the capabilities of those skilled in the art.

Claims

1. An electronic device, comprising: A logic gate having a power supply node coupled to a first node to which a power supply reference voltage is applied; A random voltage generator is configured to generate a random voltage at the second node; The first diode has a cathode coupled to the second node and an anode coupled to the first node.

2. The device of claim 1, wherein the logic gate has another power node coupled to receive a power supply voltage.

3. The device according to claim 1, wherein the logic gate is a circuit including one of the following: a logic inverter gate, a logic AND gate, a logic NAND gate, an OR gate, a NOR gate, an XOR gate, or an XOR gate.

4. The device according to claim 1, wherein the device includes a first region, the first region including a plurality of logic gates and a plurality of first diodes.

5. The device according to claim 4, wherein in the first region, the density of the first diodes is greater than 5 per square millimeter.

6. The device of claim 4, wherein the plurality of first diodes comprises at least two first diodes having different sizes.

7. The device of claim 6, wherein the at least two first diodes have different structures.

8. The device of claim 4, wherein at least one first diode includes a PN junction formed between a first well of a first conductivity type and a substrate of the device of a second conductivity type, the second conductivity type being opposite to the first conductivity type.

9. The device of claim 4, wherein at least one first diode includes a PN junction formed between a first well of a first conductivity type and a second well of a second conductivity type, the second conductivity type being opposite to the first conductivity type, and the second well being located in the first well.

10. The device of claim 1, wherein the random voltage generator is configured to generate at least two different random voltages, each of which is applied to the cathode of at least one first diode.

11. The device of claim 10, wherein the random voltage generator comprises: The input is coupled to the node where the clock signal is applied; as well as At least one circuit module is configured to receive a random number as input and modify the clock signal based on the random number.

12. The device of claim 10, wherein the random voltage generator comprises: The input is coupled to the node where the clock signal is applied; as well as The circuit module is configured to modify the amplitude of the clock signal based on a random number.

13. The device of claim 10, wherein the random voltage generator comprises: The input is coupled to the node where the clock signal is applied; as well as The circuit module is configured to divide the clock signal.

14. The device of claim 10, wherein the random voltage generator comprises at least one random switching circuit module.

15. The device of claim 10, wherein the random voltage generator comprises: The input is coupled to the node where the clock signal is applied; as well as The circuit module is configured to add a delay to the clock signal.

16. A method of using an electronic device, said electronic device comprising a logic gate, a random voltage generator, and a first diode; said logic gate having a first power supply node to which a power supply reference voltage is applied, and the first diode having a cathode and an anode connected to the first power supply node, the method comprising: A random voltage is applied to the cathode of the first diode using the random voltage generator; as well as The power supply reference voltage is applied to the anode of the first diode.

17. The method of claim 16, wherein the logic gate is a circuit comprising one of the following: a logic inverter gate, a logic AND gate, a logic NAND gate, an OR gate, a NOR gate, an XOR gate, or an XNOR gate.

18. The method of claim 16, further comprising using the random voltage generator to generate a random voltage by: Receive clock signal; and Receive random numbers; and The clock signal is modified based on a random number.

19. The method of claim 18, wherein the modification includes either frequency division or adding a delay.

20. The method of claim 16, further comprising generating a random voltage using a random voltage generator by: Receive clock signal; Receive random numbers; and The amplitude of the clock signal is modified according to the random number.

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