Wireless communication method, device and equipment

Abstract

The invention discloses a wireless communication method, device and equipment, and belongs to the field of communication, and the wireless communication method comprises the steps that the communication equipment encodes a first information bit according to a target check matrix, and / or the communication equipment decodes a second information bit according to the target check matrix; wherein the target check matrix is obtained by performing M-time hashing on a basis matrix, an object of the first-time hashing in the M-time hashing is the basis matrix, an object of the ith-time hashing in the M-time hashing is a hash check matrix obtained by performing (i-1) th-time hashing, M is a positive integer, i is a positive integer, M is greater than or equal to 2, and i is greater than or equal to 2 and less than or equal to M.

Description

Technical Field

[0001] This application belongs to the field of communication technology, specifically relating to a wireless communication method, apparatus, and device. Background Technology

[0002] With the evolution of communication technologies, mobile communication systems will support ultra-high throughput data transmission exceeding 100Gbps, requiring the further utilization of higher frequency bands to obtain greater bandwidth. This increase in data throughput places higher demands on the design of channel coding schemes; therefore, improving channel coding performance is a problem that needs to be solved. Summary of the Invention

[0003] This application provides a wireless communication method, apparatus, and device that can solve the problem of insufficient channel coding performance.

[0004] Firstly, a wireless communication method is provided, comprising:

[0005] The communication device encodes the first information bit according to the target parity check matrix, and / or the communication device decodes the second information bit according to the target parity check matrix;

[0006] The target verification matrix is ​​obtained by hashing the base matrix M times. The object of the first hash in the M hashing is the base matrix, and the object of the i-th hash in the M hashing is the hash verification matrix obtained by hashing the (i-1)-th hash. M is a positive integer, i is a positive integer, and M≥2, 2≤i≤M.

[0007] In a second aspect, a wireless communication device is provided, comprising: a processing module;

[0008] The processing module is used to encode the first information bit according to the target parity check matrix, and / or the processing module is used to decode the second information bit according to the target parity check matrix;

[0009] The target verification matrix is ​​obtained by hashing the base matrix M times. The object of the first hash in the M hashing is the base matrix, and the object of the i-th hash in the M hashing is the hash verification matrix obtained by hashing the (i-1)-th hash. M is a positive integer, i is a positive integer, and M≥2, 2≤i≤M.

[0010] Thirdly, a wireless communication device is provided, the device being configured to perform the steps of the wireless communication method as described in the first aspect.

[0011] Fourthly, a communication device is provided, comprising a processor and a memory, the memory storing a program or instructions executable on the processor, the program or instructions, when executed by the processor, implementing the steps of the wireless communication method as described in the first aspect.

[0012] Fifthly, a communication device is provided, including a processor and a communication interface;

[0013] Wherein, the processor is used to encode the first information bit according to the target parity check matrix, and / or, the processor is used to decode the second information bit according to the target parity check matrix;

[0014] The target verification matrix is ​​obtained by hashing the base matrix M times. The object of the first hash in the M hashing is the base matrix, and the object of the i-th hash in the M hashing is the hash verification matrix obtained by hashing the (i-1)-th hash. M is a positive integer, i is a positive integer, and M≥2, 2≤i≤M.

[0015] In a sixth aspect, a terminal is provided, the terminal including a processor and a memory, the memory storing a program or instructions executable on the processor, the program or instructions, when executed by the processor, implementing the steps of the method as described in the first aspect.

[0016] In a seventh aspect, a network-side device is provided, the network-side device including a processor and a memory, the memory storing a program or instructions executable on the processor, the program or instructions, when executed by the processor, implementing the steps of the method as described in the first aspect.

[0017] In an eighth aspect, a readable storage medium is provided, on which a program or instructions are stored, which, when executed by a processor, implement the steps of the wireless communication method as described in the first aspect.

[0018] A ninth aspect provides a wireless communication system, comprising: a terminal and a network-side device, wherein the terminal is configured to perform the steps of the wireless communication method as described in the first aspect, or the network-side device is configured to perform the steps of the wireless communication method as described in the first aspect.

[0019] In a tenth aspect, a chip is provided, the chip including a processor and a communication interface, the communication interface being coupled to the processor, the processor being used to run programs or instructions to implement the wireless communication method as described in the first aspect.

[0020] Eleventhly, a computer program / program product is provided, which is stored in a storage medium and executed by at least one processor to implement the steps of the wireless communication method as described in the first aspect.

[0021] In this embodiment, the communication device encodes the first information bit according to the target parity check matrix, and / or decodes the second information bit according to the target parity check matrix. The target parity check matrix is ​​obtained by hashing the base matrix M times. The object of the first hash in the M hashing is the base matrix, and the object of the i-th hash in the M hashing is the hash parity check matrix obtained after the (i-1)-th hashing. M is a positive integer, i is a positive integer, and M≥2, 2≤i≤M. Specifically, obtaining the target parity check matrix through M (M≥2) hashing can improve the coding parallelism of the target parity check matrix and increase the length of the corresponding coding block. The communication device encodes the first information bit according to the target parity check matrix, and / or decodes the second information bit according to the target parity check matrix. Higher coding parallelism and longer coding blocks can better meet the peak throughput requirements, thereby improving data transmission throughput and channel coding performance. Furthermore, the embodiments of this application are compatible with the NR LDPC code processing flow, without the need to redesign the base matrix and cyclic shift matrix, thus simplifying the design of the LDPC code parity check matrix while meeting the requirements for higher peak throughput. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of a communication system architecture provided in an embodiment of this application.

[0023] Figure 2 This is a schematic diagram of a quasi-cyclic matrix provided in this application.

[0024] Figure 3 This is a schematic diagram of a basic graph matrix (BG1 and BG2) provided in this application.

[0025] Figure 4 This is a schematic diagram of a basic diagram provided in this application.

[0026] Figure 5 This is a schematic flowchart of an NR LDPC encoding and decoding method provided in this application.

[0027] Figure 6 This is a schematic flowchart of a wireless communication method provided according to an embodiment of this application.

[0028] Figure 7 This is a schematic block diagram of a wireless communication device provided according to an embodiment of this application.

[0029] Figure 8 This is a schematic block diagram of a communication device provided according to an embodiment of this application.

[0030] Figure 9 This is a schematic diagram of the hardware structure of a terminal according to an embodiment of this application.

[0031] Figure 10 This is a schematic block diagram of a network-side device provided according to an embodiment of this application. Detailed Implementation

[0032] The technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.

[0033] The terms "first," "second," etc., used in this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first" and "second" are generally of the same class, not limited in number; for example, the first object can be one or more. Furthermore, "or" in this application indicates at least one of the connected objects. For example, the scope of protection for "A or B" covers at least three scenarios: Scenario 1: including A but not B; Scenario 2: including B but not A; Scenario 3: including both A and B. In addition, the terms "A and / or B," "at least one of A and B," and "at least one of A or B" also cover at least the above three scenarios. The character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0034] The term "instruction" in this application can be either a direct instruction (or explicit instruction) or an indirect instruction (or implicit instruction). A direct instruction can be understood as one in which the sender explicitly informs the receiver of specific information, the operation to be performed, or the requested result, etc., in the instruction sent. An indirect instruction can be understood as one in which the receiver determines the corresponding information based on the instruction sent by the sender, or makes a judgment and determines the operation to be performed or the requested result, etc., based on the judgment result.

[0035] It is worth noting that the technologies described in this application are not limited to Long Term Evolution (LTE) / LTE-Advanced (LTE-A) systems, but can also be used in other wireless communication systems, such as Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Frequency Division Multiple Access (FDMA), Orthogonal Frequency Division Multiple Access (OFDMA), Single-carrier Frequency-Division Multiple Access (SC-FDMA), or other systems. The terms "system" and "network" in this application are often used interchangeably, and the described technologies can be used with the systems and radio technologies mentioned above, as well as with other systems and radio technologies. The following description describes New Radio (NR) systems for illustrative purposes, and the term NR is used in most of the following description; however, these technologies can also be applied to systems other than NR systems, such as 6th generation (6G) radio systems. th Generation 6G communication system.

[0036] Figure 1 This diagram illustrates a block diagram of a wireless communication system applicable to embodiments of this application. Specifically, the wireless communication system includes a terminal 11 and a network-side device 12. The communication device described in this application embodiment can be either the terminal 11 or the network-side device 12.

[0037] Terminal 11 can be a mobile phone, tablet computer, laptop computer, notebook computer, personal digital assistant (PDA), handheld computer, netbook, ultra-mobile personal computer (UMPC), mobile internet device (MID), augmented reality (AR), virtual reality (VR) device, robot, wearable device, flight vehicle, vehicle user equipment (VUE), shipboard equipment, pedestrian user equipment (PUE), smart home device (home device with wireless communication function, such as refrigerator, television, washing machine or furniture, etc.), game console, personal computer (PC), ATM or self-service machine, etc. Wearable devices include: smartwatches, smart bracelets, smart earphones, smart glasses, smart jewelry (smart bracelets, smart chains, smart rings, smart necklaces, smart anklets, smart anklets, etc.), smart wristbands, smart clothing, etc. Among these, in-vehicle devices can also be referred to as in-vehicle terminals, in-vehicle controllers, in-vehicle modules, in-vehicle components, in-vehicle chips, or in-vehicle units, etc. It should be noted that the specific type of terminal 11 is not limited in the embodiments of this application.

[0038] Among them, network-side equipment 12 may include access network equipment.

[0039] Alternatively, access network equipment may also be referred to as Radio Access Network (RAN) equipment, radio access network function, or radio access network unit. Access network equipment may include base stations, wireless local area network (WLAN) access points (APs), or wireless Fidelity (WiFi) nodes, etc. The term "base station" can be referred to as Node B (NB), Evolved Node B (eNB), Next Generation Node B (gNB), New Radio Node B (NRNode B), Access Point, Relay Base Station (RBS), Serving Base Station (SBS), Base Transceiver Station (BTS), Radio Base Station, Radio Transceiver, Basic Service Set (BSS), Extended Service Set (ESS), Home Node B (HNB), Home Evolved Node B, Transmit / Receive Point (TRP), or any other suitable term in the relevant field, as long as the same technical effect is achieved. The term "base station" is not limited to specific technical terms. It should be noted that this application embodiment only uses a base station in an NR system as an example for description and does not limit the specific type of base station.

[0040] To better understand the technical solution of this application, the channel coding scheme related to this application is explained below.

[0041] Future 6G mobile communication systems will support ultra-high throughput data transmission exceeding 100Gbps, requiring the further utilization of higher frequency bands to obtain greater bandwidth. This increase in data throughput places higher demands on the design of channel coding schemes.

[0042] Low-Density Parity-Check (LDPC) codes are a class of linear block codes that approximate channel capacity limits, and their parity-check matrix is ​​sparse. Compared to Turbo codes, LDPC codes have been shown to have several advantages:

[0043] (1) It does not require a complex interleaver, which reduces the complexity and latency of the system;

[0044] (2) It has better frame error rate (FER) performance, which meets the needs of modern digital communication;

[0045] (3) The error level is greatly reduced, meeting the requirements of communication systems with extremely low bit error rate;

[0046] (4) The decoding algorithm has linear complexity, the decoder consumes less power and has a higher data throughput.

[0047] 5G mobile communication systems use quasi-cyclic LDPC (QC-LDPC) codes as the channel coding scheme for data channels.

[0048] 1) Basic knowledge of linear block codes

[0049] The information sequence (bits) is divided into fixed-length message blocks, each containing k information bits, denoted as u = (u0, u1, ..., u...). k-1 ), which is encoded into a binary sequence of length n, c = (c0, c1, ..., cn), according to certain encoding rules. n-1 ), where n>k. The sequence c is called the codeword of the message sequence u. The binary digits in the codeword are called code bits. This encoding method is called block code.

[0050] A binary (n,k) linear block code It is a k-dimensional subspace of the vector space V consisting of all n-dimensional vectors over GF(2), and it contains 2 k Each code character. There exist k linearly independent codewords g0, g1, ..., g k-1 , making Each codeword c is a linear combination of these k linearly independent codewords, where u i ∈GF(2), that is

[0051] c = u0g0 + u1g1 + ... + u k-1 g k-1

[0052] Among them, k linearly independent codewords g0, g1, ..., g k-1 As a row vector of a k×n matrix over GF(2), the relationship between message u and codeword c can be expressed as: c = u·G. Therefore, the codeword c of message u is a linear combination of the row vectors of matrix G.

[0053] The matrix G is called an (n,k) linear block code. The generating matrix G. Typically, the generating matrix G can be transformed into the following systematic form through a linear transformation:

[0054]

[0055] Among them, I k P is a k×k identity matrix, and P is a k×(nk) matrix. i,j ∈GF(2).

[0056] An (n,k) linear block code It can also be fully defined by its parity-check matrix H. Assume the dimension of H is m, where m ≥ nk. The relationship between matrices G and H is:

[0057] GH T =0

[0058] If and only if c·H T When = 0 (nk-dimensional all-zero vector), the binary n-dimensional vector c ∈ V is The code words in the text, namely:

[0059]

[0060] H is called The verification matrix, This is called the null space of H.

[0061] A linear block code can be uniquely determined by two matrices: the generator matrix and the parity check matrix. LDPC codes are typically defined based on the parity check matrix, while Polar codes are defined based on the generator matrix.

[0062] If (n,k) is a linear block code If the generator matrix is ​​in systematic form, then the corresponding check matrix in systematic form is as follows:

[0063]

[0064] The H matrix of a typical binary linear block code is an (nk,n) matrix over GF(2):

[0065]

[0066] 2) LDPC code definition

[0067] A binary LDPC code with information bit length k and code length n is a special type of (n,k) linear block code, whose parity-check matrix H = h ij H is an m×n sparse matrix, meaning that H contains a majority of "0"s and a relatively small number of "1"s, where m≥nk.

[0068] If matrix H has a constant column weight d v and line weight d cThen the null space of matrix H over GF(2) gives a (d v ,d c Regular binary LDPC codes. If H is sparse, but its row weight or column weight is not fixed, then the LDPC code defined in this way is a non-regular LDPC code. Compared with regular LDPC codes, non-regular LDPC codes are likely to be closer to the capacity limit.

[0069] Typically, the parity-check matrix H of an LDPC code defined on GF(q) has the following structural properties: (a) Row-column constraint (RC-constraint): No two rows (or two columns) will have more than one non-zero element at the same position. (b) The density r of H (defined as the ratio of the number of non-zero elements in the matrix to the total number of elements) is very small (the smaller the value, the sparser H). (c) For structured LDPC codes, especially those with H having (quasi)cyclic structure properties, the hardware implementation of the encoder and decoder can be greatly simplified.

[0070] If the parity-check matrix of an LDPC code consists of a column of circulate matrices, then the LDPC code is called a cyclic LDPC code. If the parity-check matrix of an LDPC code is an array of circulate matrices, then the LDPC code is a quasi-cyclic LDPC (QC-LDPC) code.

[0071] QC-LDPC codes are a type of structured LDPC codes whose parity-check matrix enables efficient and fast encoding and is easy to implement in hardware. The superposition construction process involves designing a base matrix B and a cyclic shift matrix P sequentially. The elements in the cyclic shift matrix are then dispersed into a cyclic matrix Q or a zero matrix of the same size as Q, thus obtaining the parity-check matrix H of the QC-LDPC code. A commonly used cyclic matrix is ​​the cyclic permutation matrix (CPM).

[0072] The H matrix of a QC-LDPC code is typically represented as a cyclic array, as shown below:

[0073]

[0074] Where each matrix A i,j Both are Z×Z sparse cyclic matrices or all-zero matrices. Cyclic matrices with a weight of 1 (called cyclic permutation matrices) are very common, where the weight of each row and each column is equal to 1. QC-LDPC codes can be implemented using simple shift registers, and the decoder can also be simplified, thus they are widely used in engineering practice.

[0075] A 9×12 quasi-cyclic matrix is ​​as follows Figure 2 As shown, it is an array of 3×4 cyclic submatrices, each of which is 3×3 in size.

[0076] 3) NR LDPC code design

[0077] The NR standard's LDPC code is based on a compact basic graph (BG) design, supporting two basic graph matrices, where each element is either 0 or 1. For example... Figure 3 As shown, the first basic graph (BG1, 46*68) matrix is ​​relatively large, with K columns in the system. b The maximum is 22, the minimum mother code rate is 1 / 3, the kernel matrix rate is around 22 / 24, and the maximum supported code block length is 8448 bits; the second basic graph (BG2, 42*52) matrix is ​​slightly smaller, and the number of systematic columns K b The maximum value is 10, the minimum mother code rate is 1 / 5, the kernel matrix rate is around 5 / 6, and the maximum supported code block length is 3840 bits.

[0078] Each BG defines 8 sub-matrices, cyclic shift coefficient matrices P, meaning each group a defines one coefficient matrix. If an element in a cyclic shift matrix is ​​greater than or equal to 0, it is replaced with a cyclic matrix Q and its cyclic shift matrix; if an element is equal to -1, it is replaced with a zero matrix of the same size.

[0079] In the basic diagram, such as Figure 4 As shown, K b m represents the number of information bits in the basis matrix. b This indicates the number of parity bits. Regions A and B are the core coding regions. Region A is denser, region B has a double-diagonal structure and contains all zeros, region D is relatively sparse, and region E is an identity matrix. The first two columns of the basis matrix are two columns of punctured bits, which are not transmitted and offer better performance. K b The last column consists of shortened bits, used for fine-tuning the number of information bits, while the rightmost punched bits are used to adjust the number of parity bits.

[0080] The boost values ​​of LDPC codes in the NR standard all satisfy a×2 j That is, 2 raised to a positive integer power multiplied by a positive integer. The reason for this design is to take into account the complexity of cyclic shifting during hardware implementation.

[0081] This design enables decoding-friendly or parallelism-friendly decoding, i.e., for a maximum parallelism of PM=2. i The decoder can decode even if the required exponent i is less than j, using a×2 j The encoded LDPC codeword is decoded.

[0082] The key to achieving parallelism-friendly decoding lies in how to decompose a large cyclic shift into multiple smaller cyclic shifts. By using a hybrid shift network of Banyan+QSN, the decoding of arbitrary codewords can be achieved with low complexity.

[0083] 4) NR LDPC encoding and decoding process

[0084] The physical layer uplink and downlink data sharing channel transmits data in basic units of transmission blocks (TBs), which can be composed of resource elements (REs), transmission layer number, and modulation order (Q). m N is calculated from the bit rate (R). info Then, the actual transmission block size (TBS) is calculated.

[0085] like Figure 5 As shown, after the physical layer receives a transport block from the Media Access Control (MAC) layer, it first adds a (16-bit or 24-bit) Cyclic Redundancy Check (CRC). If the number of bits exceeds a certain value, it needs to be divided into two or more code blocks of the same length. Each code block then adds its own CRC and independently performs LDPC encoding, rate matching, Hybrid Automatic Repeat reQuest (HARQ) processing, and interleaving.

[0086] To better understand the technical solution of this application, the problems solved by this application are explained below.

[0087] The target peak rate for NR LDPC codes is 20Gbps, with future 6G systems aiming for peak rates of 100Gbps or even higher. Higher peak rates mean larger block lengths (TBs). NR supports a maximum block size of 8448 bits. When the TB length exceeds 1,000,000 bits, it needs to be divided into more than 120 code blocks (CBs). Too many CBs can affect the complexity of rate matching and HARQ feedback during retransmissions. Therefore, the CB length should also increase with the peak rate. Furthermore, LDPC performance improves with increasing code length.

[0088] Specifically, there are two ways to increase the length of the CB: one is to design a base matrix larger than BG1, but this requires redesigning a new BG matrix; the other is to increase the value of the boost factor Z, which also requires redesigning the value of the cyclic shift coefficient matrix. Both of these will increase the complexity of the protocol design and affect compatibility with the NR protocol.

[0089] To address the aforementioned technical issues, this application proposes a method for designing LDPC codes using M-fold hashing of the base matrix. Based on the base matrix B being hashed once by a lifting factor Z1, M-1 more hashing operations are performed to obtain a larger parity check matrix (i.e., the target parity check matrix). The parallelism of the entire target parity check matrix (the parity check matrix of the LDPC code) changes from Z1 to Z1*Z2*,…,*Z M On the one hand, with the increase in parallelism, even without designing a new BG matrix, the length of CB can be made to become the original Z2*,…,*Z. M The number of CBs also becomes 1 / (Z2*,…,*Z) of the original number. M On the other hand, with the development of chip technology and the improvement of algorithm design capabilities, higher hardware parallelism can better meet the requirements of peak throughput.

[0090] The embodiments of this application are compatible with the NR LDPC code processing flow, do not require redesigning the base matrix and cyclic shift matrix, and simplify the design of the LDPC code parity check matrix while meeting the requirements of higher peak throughput.

[0091] The wireless communication method provided in this application will be described in detail below with reference to the accompanying drawings and through some embodiments and application scenarios.

[0092] Figure 6 This is a schematic flowchart of a wireless communication method 200 according to an embodiment of this application, such as... Figure 6 As shown, the wireless communication method 200 may include at least some of the following:

[0093] S210, the communication device encodes the first information bit according to the target parity check matrix, and / or, the communication device decodes the second information bit according to the target parity check matrix;

[0094] The target verification matrix is ​​obtained by hashing the base matrix M times. The object of the first hash in the M hashing is the base matrix, and the object of the i-th hash in the M hashing is the hash verification matrix obtained by hashing the (i-1)-th hash. M is a positive integer, i is a positive integer, and M≥2, 2≤i≤M.

[0095] It should be understood that Figure 6 The steps or operations of the wireless communication method 200 are illustrated, but these steps or operations are merely examples, and other operations may be performed in this application. Figure 6 Variations of various operations within it.

[0096] The target parity check matrix described in the embodiments of this application can also be referred to as or replaced by the parity check matrix of LDPC code.

[0097] In some embodiments, the present application can be applied to, for example... Figure 5 The encoding / decoding process is shown.

[0098] In some embodiments, the communication device includes at least one of a terminal and a network-side device.

[0099] In this embodiment, the target parity check matrix is ​​obtained by hashing M (M≥2) times, which can improve the coding parallelism of the target parity check matrix and increase the length of the coding block corresponding to the target parity check matrix. The communication device encodes the first information bit according to the target parity check matrix, and / or the communication device decodes the second information bit according to the target parity check matrix. The higher coding parallelism and the longer coding block can better meet the peak throughput requirements, thereby improving the data transmission throughput and improving the channel coding performance.

[0100] The embodiments of this application are compatible with the NR LDPC code processing flow, do not require redesigning the base matrix and cyclic shift matrix, and simplify the design of the LDPC code parity check matrix while meeting the requirements of higher peak throughput.

[0101] In some embodiments, the lifting factors of the M hashes are Z1, Z2, ..., Zn. M Where Z1, Z2, ..., Z M All values ​​are positive integers. Optionally, the encoding parallelism of the target parity check matrix is ​​the product of the lifting factors of the M hashes. Specifically, for example, the encoding parallelism of the target parity check matrix is ​​Z, where Z = Z1 * Z2 * ..., * Z M .

[0102] In this embodiment, the encoding parallelism of the target parity-check matrix is ​​Z = Z1*Z2*,…,*Z M (That is, the product of the lifting factors of M hashes), compared to a single hash (with a lifting factor of Z1), can increase the coding parallelism of the target parity check matrix by Z2*,…,*Z M (The product of the lifting factors of the next M-1 hashes) times.

[0103] For example, the base matrix is ​​hashed first based on Z1 to obtain hash verification matrix H1; H1 is hashed second based on Z2 to obtain hash verification matrix H2; H2 is hashed third based on Z3 to obtain hash verification matrix H3; and so on, based on Z... MFor the hash check matrix H M-1 Perform the Mth hash operation to obtain the hash verification matrix H. M Among them, the hash verification matrix H M This is the target verification matrix.

[0104] In some embodiments, each element in the basis matrix takes the value 0 or 1.

[0105] In some embodiments, at least two base matrices can be defined or configured based on different scenario requirements and / or different technical indicators (such as protocol agreement or network-side configuration), and the base matrix used for this transmission can be selected according to parameters such as transport block size (TBS) and code rate R during each transmission.

[0106] For example, the base matrix can be defined or configured based on different terminal movement speeds.

[0107] For example, the basis matrix can be defined or configured based on different channel conditions or channel quality.

[0108] For example, the base matrix can be defined or configured separately based on different transmission rates.

[0109] For example, the base matrix can be defined or configured based on different interference levels.

[0110] For example, the base matrix can be defined or configured separately based on different latency requirements.

[0111] In some embodiments, the lifting factor Z of the i-th hash i Meet at least one of the following:

[0112] Z i =a i *2^b i , where a i and b i All are integers, and a i >0, b i ≥0;

[0113] Z i =Z1, or, Z i <Z1 (e.g., Z) i (where Z is any positive integer less than Z1);

[0114] Z i Related to the size of the first information bit, or, Z i It is related to the size of the second information bit.

[0115] In this embodiment, Z i =a i *2^b i Therefore, it is possible to base it on ai and b i Flexibly determine Z i .

[0116] In this embodiment, Z i =Z1, or, Z i <Z1, thus Z can be determined based on Z1. i .

[0117] In this embodiment, Z i Z is related to the size of the first information bit, thus Z can be determined based on the size of the first information bit. i Or, Z i Z can be determined based on the size of the second information bit, which is related to the size of the second information bit. i .

[0118] Optional, a i and / or b i It can be agreed upon by agreement, or, a i and / or b i It can be configured by the network side.

[0119] Optionally, the hash 'a' corresponding to different hashes can be the same or different. For example, the hash 'a2' corresponding to the second hash and the hash 'a3' corresponding to the third hash can be the same or different.

[0120] Optionally, the hash value b can be the same or different for different hashes. For example, the hash value b2 for the second hash and the hash value b3 for the third hash can be the same or different.

[0121] For example, the size of the first information bit (such as TBS) is in the range [(2^c)*200000, 2*(2^c)*200000], where c is an integer greater than or equal to 0, and Z i The value is 2^c. For example, if TBS is in the interval [200000, 400000], Z... i Z is 1; TBS is in the interval [400000, 800000] i The value is 2; TBS is in the interval [800000, 1600000], Z i The answer is 4; and so on.

[0122] In some embodiments, the hash verification matrix H obtained after the i-th hash is... i The number of rows is MB*Z1*,…,*Z i (i.e., hash check matrix H) i The number of rows is the value obtained by multiplying the number of rows of the base matrix by the lifting factor of the first i hashes, and the hash verification matrix H obtained after the i-th hash is... iThe number of columns is NB*Z1*,…,*Z i (i.e., hash check matrix H) i The column number is the value obtained by multiplying the column number of the base matrix by the lifting factor of the first i hashes;

[0123] Where MB is the number of rows in the base matrix, and NB is the number of columns in the base matrix.

[0124] In this embodiment, the target parity check matrix obtained after M hashing has MB*Z1*,…,*Z rows. M (That is, the number of rows in the target verification matrix is ​​the product of the number of rows in the base matrix and the lifting factor of the M hashes), and the number of columns is NB*Z1*,…,*Z M (That is, the number of columns in the target parity matrix is ​​the value obtained by multiplying the number of columns in the base matrix by the lifting factor of the Mth hash).

[0125] In some embodiments, in the i-th hash, the hash verification matrix H obtained by the (i-1)-th hash is... i-1 The element 0 in the Z is composed of a Z i *Z i The all-zero matrix substitution, the hash check matrix H obtained by the (i-1)th hash is... i-1 Element 1 in the Z is composed of a Z i *Z i The identity matrix is ​​replaced, or the hash verification matrix H obtained from the (i-1)th hash is... i-1 Element 1 in the Z is composed of a Z i *Z i Replacement with a cyclic shift matrix of the identity matrix;

[0126] Wherein, the Z i *Z i The cyclic shift coefficients of the cyclic shift matrix of the identity matrix are the cyclic shift coefficient matrix P corresponding to the i-th hash. i The element at the corresponding position in the middle modulus Z i The value after that.

[0127] In some embodiments, P i The size of the hash verification matrix H obtained by the (i-1)th hash is related to the hash value. i-1 They are the same size;

[0128] Among them, P i The elements in the array satisfy one of the following:

[0129] P i The elements in the array can take two values: -1 and k. i Where -1 corresponds to H i-1 The row index and column index have the same element 0,k i Corresponding to Hi-1 The row index and column index have the same element 1, k i greater than or equal to 0 and less than Z i Integers;

[0130] P i H in the middle i-1 Elements with the same row index and column index, where element 0 is -1, are represented by P. i H in the middle i-1 The value of element 1, whose row index and column index are the same, is determined by P. i The order of the row index followed by the column index is from 0, 1, ..., Z. i -1 traversal;

[0131] P i H in the middle i-1 Elements with the same row index and column index, where element 0 is -1, are represented by P. i H in the middle i-1 The value of element 1, where the row index and column index are the same, is based on P. i The circular shift value generated by the row index and column index;

[0132] P i H in the middle i-1 Elements with the same row index and column index, where element 0 is -1, are represented by P. i H in the middle i-1 The value of element 1, where the row index and column index are the same, is based on P. i-1 The elements are determined.

[0133] For example, P i H in the middle i-1 Elements with the same row index and column index, where element 0 is -1, are represented by P. i H in the middle i-1 The value of element 1, where the row index and column index are the same, is based on P. i The circular shift value generated by the row index and column index, for example, P i Input the row and column indices into a specific function to get P. i H in the middle i-1 The value of element 1, where the row index and column index are the same.

[0134] For example, P i H in the middle i-1 Elements with the same row index and column index, where element 0 is -1, are represented by P. i H in the middle i-1 The value of element 1, where the row index and column index are the same, is based on P. i-1 The elements are determined, for example, according to P. iReading the row and column indices of the sub-block containing the element P i-1 The coefficient value in the figure is considered as P. i The element value in; or, P i The cyclic shift coefficient is P i-1 The element at the corresponding position in the middle modulus Z i-1 The value after that.

[0135] In this embodiment, P i The elements in the array can take two values: -1 and k. i Where -1 corresponds to H i-1 The row index and column index have the same element 0,k i Corresponding to H i-1 The row index and column index have the same element 1, k i greater than or equal to 0 and less than Z i The integers are used to determine the cyclic shift coefficient matrix P. i .

[0136] In this embodiment, P i H in the middle i-1 Elements with the same row index and column index, where element 0 is -1, are represented by P. i H in the middle i-1 The value of element 1, whose row index and column index are the same, is determined by P. i The order of the row index followed by the column index is from 0, 1, ..., Z. i By iterating through -1, the cyclic shift coefficient matrix P can be determined. i .

[0137] In this embodiment, P i H in the middle i-1 Elements with the same row index and column index, where element 0 is -1, are represented by P. i H in the middle i-1 The value of element 1, where the row index and column index are the same, is based on P. i The cyclic shift values ​​generated by the row and column indices can be used to determine the cyclic shift coefficient matrix P. i .

[0138] In this embodiment, P i H in the middle i-1 Elements with the same row index and column index, where element 0 is -1, are represented by P. i H in the middle i-1 The value of element 1, where the row index and column index are the same, is based on P. i-1 The elements are determined, thus allowing the determination of the cyclic shift coefficient matrix P. i .

[0139] In some embodiments, the specific steps of the first hashing may be as follows:

[0140] a) Determine the lifting factor Z1 and the basis matrix B; wherein the basis matrix B has MB rows and NB columns;

[0141] b) Determine the values ​​of each element in the circular shift coefficient matrix P1 corresponding to the first hash. P1 is the same size as the base matrix B. The elements in P1 have two possible values: -1 and k1. -1 corresponds to the element 0 in the base matrix B with the same row and column indices. k1 corresponds to the element 1 in the base matrix B with the same row and column indices. Here, k1 is an integer greater than or equal to 0 and less than Z1.

[0142] c) First hashing process: Replace the element 0 in the base matrix B with a Z1*Z1 all-zero matrix; replace the element 1 in the base matrix B with a Z1*Z1 identity matrix; or replace the element 1 in the base matrix B with a cyclic shift matrix of a Z1*Z1 identity matrix (both cyclic right shift and cyclic left shift are acceptable, but the hashing process needs to remain consistent). The cyclic shift coefficient is the value of the element at the corresponding position in P1 modulo Z1.

[0143] d) After the above operations, the base matrix B completes the first hashing process and obtains the first hash check matrix H1. H1 has MB*Z1 rows and NB*Z1 columns.

[0144] In some embodiments, the specific steps of the i-th hash can be as follows:

[0145] a) Determine the enhancement factor Z i and hash check matrix H i-1 Among them, H i-1 The number of rows is MB*Z1*,…,*Z i-1 (i.e. H) i-1 The number of rows is the value obtained by multiplying the number of rows of the base matrix by the lifting factor of the first i-1 hashes, and the number of columns is NB*Z1*,…,*Z. i-1 (i.e. H) i-1 The column number is the value obtained by multiplying the column number of the base matrix by the lifting factor of the first i-1 hashes;

[0146] b) Determine the cyclic shift coefficient matrix P corresponding to the i-th hash. i The values ​​of each element in P i Size and H i-1 The same size; P i The elements in the array can take two values: -1 and k. i Where -1 corresponds to H i-1 The row index and column index have the same element 0,k i Corresponding to Hi-1 The row index and column index have the same element 1, k i greater than or equal to 0 and less than Z i An integer; or, P i H in the middle i-1 Elements with the same row index and column index, where element 0 is -1, are represented by P. i H in the middle i-1 The value of element 1, whose row index and column index are the same, is determined by P. i The order of the row index followed by the column index is from 0, 1, ..., Z. i -1 is traversed; or, P i H in the middle i-1 Elements with the same row index and column index, where element 0 is -1, are represented by P. i H in the middle i-1 The value of element 1, where the row index and column index are the same, is based on P. i The circular shift value generated by the row and column indexes; or, P i H in the middle i-1 Elements with the same row index and column index, where element 0 is -1, are represented by P. i H in the middle i-1 The value of element 1, where the row index and column index are the same, is based on P. i-1 The elements are determined;

[0147] c) The i-th hash process: H is hashed... i-1 The element 0 in the Z is represented by a Z. i *Z i Replace with an all-zero matrix; replace H i-1 Element 1 in the Z, using a Z i *Z i Replace it with the identity matrix; or, replace H with i-1 Element 1 in the Z, using a Z i *Z i Replace it with a circular shift matrix of the identity matrix (either circular right shift or circular left shift is acceptable, but the hashing process needs to remain consistent);

[0148] d) After the above operations, the i-th hashing process is completed, and the i-th hash verification matrix H is obtained. i H i The number of rows is MB*Z1*,…,*Z i (i.e. H) i The number of rows is the value obtained by multiplying the number of rows of the base matrix by the lifting factor of the first i hashes, and the number of columns is NB*Z1*,…,*Z. i (i.e. H) i The column number is the value obtained by multiplying the column number of the base matrix by the lifting factor of the first i hashes.

[0149] In some embodiments, the code block length corresponding to the first information bit is related to the coding parallelism Z; and / or,

[0150] The number of code blocks corresponding to the first information bit is related to the coding parallelism Z; and / or,

[0151] The padding bits corresponding to the first information bit are related to the encoding parallelism Z.

[0152] In this embodiment, the code block length corresponding to the first information bit can be determined based on the coding parallelism Z of the target parity-check matrix, and / or the number of code blocks corresponding to the first information bit can be determined based on the coding parallelism Z of the target parity-check matrix, and / or the padding bits corresponding to the first information bit can be determined based on the coding parallelism Z of the target parity-check matrix.

[0153] In some embodiments, the bit length of the first information bit before encoding is related to the encoding parallelism Z; and / or, the bit length of the first information bit after encoding is related to the encoding parallelism Z.

[0154] In this embodiment, the bit length of the first information bit before encoding can be determined based on the encoding parallelism Z of the target parity matrix, and / or the bit length of the first information bit after encoding can be determined based on the encoding parallelism Z of the target parity matrix.

[0155] In some embodiments, the rate matching parameter corresponding to the first information bit is related to the coding parallelism Z.

[0156] Optionally, the rate matching parameters include, but are not limited to, at least one of the following:

[0157] The length of the encoded bits after puncturing, the length of the bits placed in the circular buffer, and the starting point of each Redundancy Version (RV).

[0158] In this embodiment, the rate matching parameter corresponding to the first information bit can be determined based on the coding parallelism Z of the target parity matrix.

[0159] In some embodiments, the communication device is a terminal, and the wireless communication method 200 further includes:

[0160] The terminal receives instruction information from the network-side device;

[0161] The indication information is used to instruct the terminal to activate the first verification matrix determination method;

[0162] The method for determining the first verification matrix corresponds to at least two hashing processes.

[0163] For example, before performing S210 above, the terminal receives the indication information from the network-side device.

[0164] In some embodiments, the communication device is a network-side device, and the wireless communication method 200 further includes:

[0165] The network-side device sends instruction information to the terminal;

[0166] The indication information is used to instruct the terminal to activate the first verification matrix determination method;

[0167] The method for determining the first verification matrix corresponds to at least two hashing processes.

[0168] In this embodiment, the network-side device can instruct the terminal to activate the first check matrix determination method through the indication information, so that the terminal can obtain the target check matrix based on M hashes, and the terminal can encode the first information bits according to the target check matrix, and / or the terminal can decode the second information bits according to the target check matrix.

[0169] For example, if the network-side device does not indicate activation of the first parity check matrix determination method, or if the network-side device indicates deactivation of the first parity check matrix determination method, the terminal obtains the parity check matrix of the LDPC code based on a single hash.

[0170] Optionally, the indication information may be carried by at least one of the following: Radio Resource Control (RRC) signaling, Downlink Control Information (DCI), or Media Access Control Control Element (MAC CE).

[0171] In some embodiments, the communication device is a terminal, and the wireless communication method 200 further includes:

[0172] The terminal sends capability information to the network-side device;

[0173] The capability information is used to indicate that the terminal supports the first verification matrix determination method;

[0174] The method for determining the first verification matrix corresponds to at least two hashing processes.

[0175] For example, before executing S210 above, the terminal sends the capability information to the network-side device.

[0176] In some embodiments, the communication device is a network-side device, and the wireless communication method 200 further includes:

[0177] The network-side device receives capability information from the terminal;

[0178] The capability information is used to indicate that the terminal supports the first verification matrix determination method;

[0179] The method for determining the first verification matrix corresponds to at least two hashing processes.

[0180] In this embodiment, the terminal reports capability information, so that the network-side device can know that the terminal supports the first check matrix determination method. Consequently, the transmission between the terminal and the network-side device can be encoded based on the target check matrix.

[0181] Optionally, the capability information can be carried by at least one of the following: RRC signaling, Uplink Control Information (UCI), or MAC CE.

[0182] Therefore, in this embodiment, the communication device encodes the first information bit according to the target parity check matrix, and / or decodes the second information bit according to the target parity check matrix; wherein, the target parity check matrix is ​​obtained by hashing the base matrix M times, the object of the first hash in the M hashing is the base matrix, the object of the i-th hash in the M hashing is the hash parity check matrix obtained by the (i-1)-th hashing, M is a positive integer, i is a positive integer, and M≥2, 2≤i≤M. Specifically, obtaining the target parity check matrix through M (M≥2) hashing can improve the coding parallelism of the target parity check matrix and increase the length of the coding block corresponding to the target parity check matrix. The communication device encodes the first information bit according to the target parity check matrix, and / or decodes the second information bit according to the target parity check matrix. Higher coding parallelism and longer coding blocks can better meet the peak throughput requirements, thereby improving the data transmission throughput and channel coding performance. Furthermore, the embodiments of this application are compatible with the NR LDPC code processing flow, without the need to redesign the base matrix and cyclic shift matrix, thus simplifying the design of the LDPC code parity check matrix while meeting the requirements for higher peak throughput.

[0183] The technical solution of this application is described in detail below through specific embodiments.

[0184] Example 1: Taking the determination of the target parity check matrix (LDPC code) based on secondary hashing in an ultra-high throughput scenario as an example.

[0185] When the TBS is large, BG1 is typically used as the base matrix for LDPC codes, and one TBS is divided into several independently encoded CBs. Due to the limitations of the base matrix, one CB can carry a maximum of 8448 information bits (considering CB-CRC), and the parallelism of encoding and decoding is related to the lifting factor Z. When the number of information bits is 8448, the corresponding lifting factor Z is 384, meaning the maximum parallelism is 384. When the TBS exceeds 1,000,000 bits, at least 120 CBs are required. Limited by the lifting factor or parallelism, the number of CBs increases with the increase of TBS, which inevitably affects the peak decoding rate.

[0186] Based on the aforementioned technical issues, this embodiment takes M=2 as an example, meaning the target parity check matrix (LDPC code) is obtained by hashing the base matrix twice. The enhancement design for the ultra-large TBS scenario in this embodiment is as follows:

[0187] 1. The base matrix is ​​chosen as BG1, with 46 rows and 68 columns; the first lifting factor Z1 is chosen as 384, and the first cyclic shift coefficient matrix P1 is determined as the cyclic shift coefficient matrix corresponding to BG1 and a is 3.

[0188] 2. Perform a hash operation on BG1 to obtain the first parity check matrix H1. H1 has 17644 rows, 26112 columns, and 8448 information bits.

[0189] 3. Select the second lifting factor Z2 as 4, set the values ​​in the second circular shift coefficient matrix P2 that are at the same positions as the 1 element in H1 (same row index and column index) to 0, and set the rest to -1;

[0190] 4. Perform a second hash operation on H1 to obtain the second parity check matrix H2 (i.e., the target parity check matrix). H2 has 70,576 rows and 104,448 columns. The number of information bits corresponding to H2 is 33,792, and its parallelism is 1,536 (i.e., Z1*Z2).

[0191] It can be seen that by a simple double hash operation, the length of CB can be increased by 4 times (that is, the number of information bits corresponding to H2 is 4 times the number of information bits corresponding to H1), the parallelism of LDPC code is also increased by 4 times, and it is fully compatible with the BG basis matrix and cyclic shift coefficient matrix of NR protocol.

[0192] The double hashing scheme does not change the connectivity between nodes in the base matrix, therefore it does not degrade the performance of LDPC codes. By selecting appropriate second boosting factor Z2 and the values ​​of each element in the second cyclic shift coefficient matrix P2, the performance of long LDPC codes can be further improved.

[0193] Example 2 takes the correlation effect of the target parity check matrix (LDPC code) on the LDPC coding chain as an example.

[0194] This embodiment takes M=2 as an example, that is, the target parity check matrix (LDPC code) is obtained by hashing the base matrix twice, and the corresponding adaptations need to be made to each component of the NR LDPC coding chain.

[0195] 1. Segmentation

[0196] a) Let A be the transport block size and L be the TB-CRC check bit length. The length of the TB block after CRC check is B = A + L.

[0197] b) The first lifting factor is Z1, the second lifting factor is Z2, and the overall lifting factor Z of the quadratic hash scheme is Z1*Z2. Kcb is the maximum code block length. When the base matrix is ​​BG1, Kcb is 8448*Z2, and when the base matrix is ​​BG2, Kcb is 3840*Z2.

[0198] c) Calculation of the number of code blocks C:

[0199]

[0200] d) Calculation of code block length K:

[0201]

[0202] Table 1 below is the lifting factor table. Find the smallest Z1 in Table 1 such that K b ·Z1·Z2≥K ′ For BG1, K is 22*Z1*Z2; for BG2, K is 10*Z1*Z2.

[0203] Table 1

[0204] <![CDATA[ a ]]> <![CDATA[Boost factor Z1]]> 2 {2，4，8，16，32，64，128，256} 3 {3，6，12，24，48，96，192，384} 5 {5，10，20，40，80，160，320} 7 {7，14，28，56，112，225} 9 {9，18，36，72，144，288} 11 {11，22，44，88，176，352} 13 {13，26，52，104，208} 15 {15，30，60，120，240}

[0205] e) Calculation of the padding bits F:

[0206] F = KK ′

[0207] 2. Encoding

[0208] a) When the base matrix is ​​BG1, the length of the information bit to be encoded is 22*Z1*Z2, and the length of the encoded bit is 68*Z1*Z2.

[0209] b) When the base matrix is ​​BG2, the length of the information bit to be encoded is 10*Z1*Z2, and the length of the encoded bit is 52*Z1*Z2.

[0210] c) The parallelism of the encoding is Z1*Z2.

[0211] 3. Rate matching

[0212] a) N is the bit length after puncturing the encoded bits. When the base matrix is ​​BG1, N is 66*Z1*Z2; when the base matrix is ​​BG2, N is 50*Z1*Z2.

[0213] b) Ncb is the bit length placed in the circular buffer. If the parameter I-LBRM is 0, then Ncb equals N; otherwise, Ncb is min(N, Nref), where

[0214]

[0215] c) When the base matrix is ​​BG1, the starting point of each RV version is [0,17 / 66,33 / 66,56 / 66]*Ncb.

[0216] d) When the base matrix is ​​BG2, the starting point of each RV version is [0,13 / 50,25 / 50,43 / 50]*Ncb.

[0217] The wireless communication method provided in this application can be executed by a wireless communication device. This application uses an example of a wireless communication device executing the wireless communication method to illustrate the wireless communication device provided in this application.

[0218] This application provides a wireless communication device. As an example, the wireless communication device can be a communication equipment or a component within a communication equipment, such as a chip. The communication equipment can be a terminal, a network-side device, or a server, etc. Exemplarily, the terminal can be, but is not limited to, the type of terminal 11 listed above, and the network-side device can be, but is not limited to, the type of network-side device 12 listed above. This application does not impose specific limitations.

[0219] The wireless communication device includes a receiving module, a transmitting module, and a processing module. These modules can be implemented in software or hardware. When implemented in hardware, the processing module can be implemented by a processor. For example, the processor can include general-purpose processors, special-purpose processors, such as a Central Processing Unit (CPU), microprocessor, Digital Signal Processor (DSP), Artificial Intelligence (AI) processor, Graphics Processing Unit (GPU), Application Specific Integrated Circuit (ASIC), Network Processor (NP), Field Programmable Gate Array (FPGA), or other programmable logic devices, gate circuits, transistors, discrete hardware components, etc. The receiving and transmitting modules can be implemented by a communication interface, which can include one or more of the following: transceiver, pins, circuits, bus, radio frequency unit, etc.

[0220] See Figure 7 When the wireless communication device is a communication device or a component of a communication device, the wireless communication device 300 includes:

[0221] Processing module 301 is used to encode the first information bit according to the target parity check matrix, and / or to decode the second information bit according to the target parity check matrix;

[0222] The target verification matrix is ​​obtained by hashing the base matrix M times. The object of the first hash in the M hashing is the base matrix, and the object of the i-th hash in the M hashing is the hash verification matrix obtained by hashing the (i-1)-th hash. M is a positive integer, i is a positive integer, and M≥2, 2≤i≤M.

[0223] In some embodiments, the lifting factors of the M hashes are Z1, Z2, ..., Zn. M Where Z1, Z2, ..., Z M All are positive integers;

[0224] The encoding parallelism of the target parity check matrix is ​​Z, where Z = Z1*Z2*,…,*Z M .

[0225] In some embodiments, the lifting factor Z of the i-th hash i Meet at least one of the following:

[0226] Z i =a i *2^b i , where a i and b i All are integers, and a i >0, b i ≥0;

[0227] Z i =Z1, or, Z i <Z1;

[0228] Z i Related to the size of the first information bit, or, Z i It is related to the size of the second information bit.

[0229] In some embodiments, the hash verification matrix H obtained after the i-th hash is... i The number of rows is MB*Z1*,…,*Z i The hash verification matrix H obtained after the i-th hash is i The number of columns is NB*Z1*,…,*Z i ;

[0230] Where MB is the number of rows in the base matrix, and NB is the number of columns in the base matrix.

[0231] In some embodiments, in the i-th hash, the hash verification matrix H obtained by the (i-1)-th hash is... i-1 The element 0 in the Z is composed of a Z i *Z i The all-zero matrix substitution, the hash check matrix H obtained by the (i-1)th hash is... i-1 Element 1 in the Z is composed of a Z i *Z i The identity matrix is ​​replaced, or the hash verification matrix H obtained from the (i-1)th hash is... i-1 Element 1 in the Z is composed of a Z i *Z i Replacement with a cyclic shift matrix of the identity matrix;

[0232] Wherein, the Z i *Z i The cyclic shift coefficients of the cyclic shift matrix of the identity matrix are the cyclic shift coefficient matrix P corresponding to the i-th hash. i The element at the corresponding position in the middle modulus Z i The value after that.

[0233] In some embodiments, P i The size of the hash verification matrix H obtained by the (i-1)th hash is related to the hash value.i-1 They are the same size;

[0234] Among them, P i The elements in the array satisfy one of the following:

[0235] P i The elements in the array can take two values: -1 and k. i Where -1 corresponds to H i-1 The row index and column index have the same element 0,k i Corresponding to H i-1 The row index and column index have the same element 1, k i greater than or equal to 0 and less than Z i Integers;

[0236] P i H in the middle i-1 Elements with the same row index and column index, where element 0 is -1, are represented by P. i H in the middle i-1 The value of element 1, whose row index and column index are the same, is determined by P. i The order of the row index followed by the column index is from 0, 1, ..., Z. i -1 traversal;

[0237] P i H in the middle i-1 Elements with the same row index and column index, where element 0 is -1, are represented by P. i H in the middle i-1 The value of element 1, where the row index and column index are the same, is based on P. i The circular shift value generated by the row index and column index;

[0238] P i H in the middle i-1 Elements with the same row index and column index, where element 0 is -1, are represented by P. i H in the middle i-1 The value of element 1, where the row index and column index are the same, is based on P. i-1 The elements are determined.

[0239] In some embodiments, the code block length corresponding to the first information bit is related to the coding parallelism Z; and / or,

[0240] The number of code blocks corresponding to the first information bit is related to the coding parallelism Z; and / or,

[0241] The padding bits corresponding to the first information bit are related to the encoding parallelism Z; and / or,

[0242] The bit length of the first information bit before encoding is related to the encoding parallelism Z; and / or,

[0243] The length of the first information bit after encoding is related to the encoding parallelism Z; and / or,

[0244] The rate matching parameter corresponding to the first information bit is related to the coding parallelism Z.

[0245] In some embodiments, the rate matching parameters include at least one of the following:

[0246] The length of the encoded bits after puncturing, the length of the bits placed in the circular buffer, and the starting point of each redundant version (RV).

[0247] In some embodiments, the wireless communication device 300 includes at least one of a terminal and a network-side device.

[0248] In some embodiments, the wireless communication device 300 is a terminal, and the wireless communication device 300 further includes:

[0249] The receiving module 302 is used to receive indication information from the network-side device;

[0250] The indication information is used to instruct the wireless communication device 300 to activate the first verification matrix determination method;

[0251] The method for determining the first verification matrix corresponds to at least two hashing processes.

[0252] In some embodiments, the wireless communication device 300 is a terminal, and the wireless communication device 300 further includes:

[0253] The sending module 303 is used to send capability information to network-side devices;

[0254] The capability information is used to indicate that the wireless communication device 300 supports the first verification matrix determination method;

[0255] The method for determining the first verification matrix corresponds to at least two hashing processes.

[0256] In some embodiments, the wireless communication device 300 is a network-side device, and the wireless communication device 300 further includes:

[0257] The sending module 303 is used to send indication information to the terminal;

[0258] The indication information is used to instruct the terminal to activate the first verification matrix determination method;

[0259] The method for determining the first verification matrix corresponds to at least two hashing processes.

[0260] In some embodiments, the wireless communication device 300 is a network-side device, and the wireless communication device 300 further includes:

[0261] The receiving module 302 is used to receive capability information from the terminal;

[0262] The capability information is used to indicate that the terminal supports the first verification matrix determination method;

[0263] The method for determining the first verification matrix corresponds to at least two hashing processes.

[0264] Therefore, in this embodiment, the communication device encodes the first information bit according to the target parity check matrix, and / or decodes the second information bit according to the target parity check matrix; wherein, the target parity check matrix is ​​obtained by hashing the base matrix M times, the object of the first hash in the M hashing is the base matrix, the object of the i-th hash in the M hashing is the hash parity check matrix obtained by the (i-1)-th hashing, M is a positive integer, i is a positive integer, and M≥2, 2≤i≤M. Specifically, obtaining the target parity check matrix through M (M≥2) hashing can improve the coding parallelism of the target parity check matrix and increase the length of the coding block corresponding to the target parity check matrix. The communication device encodes the first information bit according to the target parity check matrix, and / or decodes the second information bit according to the target parity check matrix. Higher coding parallelism and longer coding blocks can better meet the peak throughput requirements, thereby improving the data transmission throughput and channel coding performance. Furthermore, the embodiments of this application are compatible with the NR LDPC code processing flow, without the need to redesign the base matrix and cyclic shift matrix, thus simplifying the design of the LDPC code parity check matrix while meeting the requirements for higher peak throughput.

[0265] The wireless communication device provided in this application embodiment can achieve... Figure 6 The various processes implemented in the method embodiments shown achieve the same technical effects, and will not be described again here to avoid repetition.

[0266] like Figure 8 As shown in the figure, this application embodiment also provides a communication device 400, including a processor 401 and a memory 402, wherein the memory 402 stores a program or instructions that can be run on the processor 401.

[0267] For example, when the communication device 400 is a terminal, the program or instruction executed by the processor 401 implements the various steps executed by the terminal in the above wireless communication method embodiment and can achieve the same technical effect. To avoid repetition, it will not be described again here.

[0268] For example, when the communication device 400 is a network-side device, the program or instruction executed by the processor 401 implements the various steps executed by the network-side device in the above wireless communication method embodiment and can achieve the same technical effect. To avoid repetition, it will not be described again here.

[0269] This application embodiment also provides a terminal, including a processor and a communication interface, wherein the communication interface is coupled to the processor, and the processor is used to run programs or instructions to implement, for example... Figure 6 The steps in the method embodiment shown are illustrated. This terminal embodiment corresponds to the method embodiment executed by the aforementioned communication device. All implementation processes and methods of the aforementioned method embodiments can be applied to this terminal embodiment and achieve the same technical effect. The terminal can be... Figure 7 The wireless communication device 300 shown.

[0270] Specifically, Figure 9 A schematic diagram of the hardware structure of a terminal to implement an embodiment of this application.

[0271] The terminal 500 includes, but is not limited to, at least some of the following components: radio frequency unit 501, network module 502, audio output unit 503, input unit 504, sensor 505, display unit 506, user input unit 507, interface unit 508, memory 509, and processor 510.

[0272] Those skilled in the art will understand that the terminal 500 may also include a power supply (such as a battery) for supplying power to various components. The power supply may be logically connected to the processor 510 through a power management system, thereby enabling functions such as managing charging, discharging, and power consumption through the power management system. Figure 9 The terminal structure shown does not constitute a limitation on the terminal. The terminal may include more or fewer components than shown, or combine certain components, or have different component arrangements, which will not be elaborated here.

[0273] It should be understood that, in this embodiment, the input unit 504 may include a graphics processor 5041 and a microphone 5042. The graphics processor 5041 processes image data of still images or videos obtained by an image capture device (such as a camera) in video capture mode or image capture mode. The display unit 506 may include a display panel 5061, which may be configured in the form of a liquid crystal display, an organic light-emitting diode, or the like. The user input unit 507 includes at least one of a touch panel 5071 and other input devices 5072. The touch panel 5071 is also called a touch screen. The touch panel 5071 may include two parts: a touch detection device and a touch controller. Other input devices 5072 may include, but are not limited to, physical keyboards, function keys (such as volume control buttons, power buttons, etc.), trackballs, mice, and joysticks, which will not be described in detail here.

[0274] In this embodiment, after receiving downlink data from the network-side device, the radio frequency unit 501 can transmit it to the processor 510 for processing; in addition, the radio frequency unit 501 can send uplink data to the network-side device. Typically, the radio frequency unit 501 includes, but is not limited to, antennas, amplifiers, transceivers, couplers, low-noise amplifiers, duplexers, etc.

[0275] The memory 509 can be used to store software programs or instructions, as well as various data. The memory 509 may primarily include a first storage area for storing programs or instructions and a second storage area for storing data. The first storage area may store the operating system, application programs or instructions required for at least one function (such as sound playback, image playback, etc.). Furthermore, the memory 509 may include volatile memory or non-volatile memory. The non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory can be random access memory (RAM), static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), and direct memory bus RAM (DRRAM). The memory 509 in this embodiment includes, but is not limited to, these and any other suitable types of memory.

[0276] Processor 510 may include one or more processing units; optionally, processor 510 integrates an application processor and a modem processor, wherein the application processor mainly handles operations involving the operating system, user interface, and applications, and the modem processor mainly handles wireless communication signals, such as a baseband processor. It is understood that the aforementioned modem processor may also not be integrated into processor 510.

[0277] In some embodiments, the processor 510 is configured to encode a first information bit according to a target parity check matrix, and / or the processor 510 is configured to decode a second information bit according to a target parity check matrix;

[0278] The target verification matrix is ​​obtained by hashing the base matrix M times. The object of the first hash in the M hashing is the base matrix, and the object of the i-th hash in the M hashing is the hash verification matrix obtained by hashing the (i-1)-th hash. M is a positive integer, i is a positive integer, and M≥2, 2≤i≤M.

[0279] Therefore, in this embodiment, the terminal encodes the first information bit according to the target parity check matrix, and / or decodes the second information bit according to the target parity check matrix; wherein, the target parity check matrix is ​​obtained by hashing the base matrix M times, the object of the first hash in the M hashing is the base matrix, the object of the i-th hash in the M hashing is the hash parity check matrix obtained by the (i-1)-th hashing, M is a positive integer, i is a positive integer, and M≥2, 2≤i≤M. Specifically, obtaining the target parity check matrix through M (M≥2) hashing can improve the coding parallelism of the target parity check matrix and increase the length of the coding block corresponding to the target parity check matrix. The terminal encodes the first information bit according to the target parity check matrix, and / or decodes the second information bit according to the target parity check matrix. Higher coding parallelism and longer coding blocks can better meet the peak throughput requirements, thereby improving the data transmission throughput and channel coding performance. Furthermore, the embodiments of this application are compatible with the NR LDPC code processing flow, without the need to redesign the base matrix and cyclic shift matrix, thus simplifying the design of the LDPC code parity check matrix while meeting the requirements for higher peak throughput.

[0280] It is understood that the implementation process of each implementation method mentioned in this embodiment can refer to the relevant description of the method embodiment and achieve the same or corresponding technical effect. To avoid repetition, it will not be described again here.

[0281] This application embodiment also provides a network-side device, including a processor and a communication interface, wherein the communication interface is coupled to the processor, and the processor is used to run programs or instructions to implement, for example... Figure 6 The steps of the method embodiment shown are illustrated. This network-side device embodiment corresponds to the method embodiment executed by the communication device described above. All implementation processes and methods of the above method embodiments can be applied to this network-side device embodiment and can achieve the same technical effect.

[0282] This application embodiment also provides a network-side device, which may be... Figure 7 The wireless communication device 300 shown. Specifically, as... Figure 10As shown, the network-side device 600 includes: an antenna 61, a radio frequency (RF) device 62, a baseband device 63, a processor 64, and a memory 65. The antenna 61 is connected to the RF device 62. In the uplink direction, the RF device 62 receives information through the antenna 61 and transmits the received information to the baseband device 63 for processing. In the downlink direction, the baseband device 63 processes the information to be transmitted and sends it to the RF device 62. The RF device 62 processes the received information and transmits it through the antenna 61.

[0283] The method executed by the communication device in the above embodiments can be implemented in the baseband device 63, which includes a baseband processor.

[0284] Baseband device 63 may include, for example, at least one baseband board on which multiple chips are disposed, such as Figure 10 As shown, one of the chips is, for example, a baseband processor, which is connected to the memory 65 via a bus interface to call the program in the memory 65 and execute the operation of the network-side device shown in the above method embodiment.

[0285] The network-side device may also include a network interface 66, such as a Common Public Radio Interface (CPRI).

[0286] Specifically, the network-side device 600 in this application embodiment further includes: instructions or programs stored in memory 65 and executable on processor 64, wherein processor 64 calls the instructions or programs in memory 65 to execute. Figure 7 The methods executed by each module shown achieve the same technical effect, and to avoid repetition, they will not be described in detail here.

[0287] In some embodiments, the processor 64 is configured to encode a first information bit according to a target parity check matrix, and / or the processor 64 is configured to decode a second information bit according to a target parity check matrix;

[0288] The target verification matrix is ​​obtained by hashing the base matrix M times. The object of the first hash in the M hashing is the base matrix, and the object of the i-th hash in the M hashing is the hash verification matrix obtained by hashing the (i-1)-th hash. M is a positive integer, i is a positive integer, and M≥2, 2≤i≤M.

[0289] Therefore, in this embodiment, the network-side device encodes the first information bit according to the target parity check matrix, and / or decodes the second information bit according to the target parity check matrix; wherein, the target parity check matrix is ​​obtained by hashing the base matrix M times, the object of the first hash in the M hashing is the base matrix, the object of the i-th hash in the M hashing is the hash parity check matrix obtained by the (i-1)-th hashing, M is a positive integer, i is a positive integer, and M≥2, 2≤i≤M. Specifically, obtaining the target parity check matrix through M (M≥2) hashing can improve the coding parallelism of the target parity check matrix and increase the length of the coding block corresponding to the target parity check matrix. The network-side device encodes the first information bit according to the target parity check matrix, and / or decodes the second information bit according to the target parity check matrix. Higher coding parallelism and longer coding blocks can better meet the peak throughput requirements, thereby improving the data transmission throughput and channel coding performance. Furthermore, the embodiments of this application are compatible with the NR LDPC code processing flow, without the need to redesign the base matrix and cyclic shift matrix, thus simplifying the design of the LDPC code parity check matrix while meeting the requirements for higher peak throughput.

[0290] This application also provides a readable storage medium storing a program or instructions. When the program or instructions are executed by a processor, they implement the various processes of the above-described wireless communication method embodiments and achieve the same technical effects. To avoid repetition, they will not be described again here.

[0291] The processor mentioned above is the processor in the terminal or network-side device described in the above embodiments. The readable storage medium includes computer-readable storage media, such as computer read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk. In some examples, the readable storage medium may be a non-transient readable storage medium.

[0292] This application embodiment also provides a chip, which includes a processor and a communication interface. The communication interface is coupled to the processor. The processor is used to run programs or instructions to implement the various processes of the above-described wireless communication method embodiments and can achieve the same technical effect. To avoid repetition, it will not be described again here.

[0293] It should be understood that the chip mentioned in the embodiments of this application may also be referred to as a system-on-a-chip, system chip, chip system, or system-on-a-chip, etc.

[0294] This application also provides a computer program / program product, which is stored in a storage medium and executed by at least one processor to implement the various processes of the above-described wireless communication method embodiments, and can achieve the same technical effect. To avoid repetition, it will not be described again here.

[0295] This application also provides a wireless communication system, including: a terminal and a network-side device. The terminal can be used to perform the steps performed by the terminal in the wireless communication method described above, and the network-side device can be used to perform the steps performed by the network-side device in the wireless communication method described above.

[0296] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of this application is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0297] From the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of computer software products plus necessary general-purpose hardware platforms, and of course, they can also be implemented by hardware. The computer software product is stored in a storage medium (such as ROM, RAM, magnetic disk, optical disk, etc.) and includes several instructions to cause the terminal or network-side device to execute the methods described in the various embodiments of this application.

[0298] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other implementations under the guidance of this application without departing from the spirit and scope of the claims. All of these implementations are within the protection scope of this application.

Claims

1. A wireless communication method, characterized in that, include: The communication device encodes the first information bit according to the target parity check matrix, and / or the communication device decodes the second information bit according to the target parity check matrix; The target verification matrix is ​​obtained by hashing the base matrix M times. The object of the first hash in the M hashing is the base matrix, and the object of the i-th hash in the M hashing is the hash verification matrix obtained by hashing the (i-1)-th hash. M is a positive integer, i is a positive integer, and M≥2, 2≤i≤M.

2. The method according to claim 1, characterized in that, The lifting factors for the M hashes are Z1, Z2, ..., Zn. M Where Z1, Z2, ..., Z M All are positive integers; The encoding parallelism of the target parity check matrix is ​​Z, where Z = Z1*Z2*,…,*Z M .

3. The method according to claim 2, characterized in that, The lifting factor Z of the i-th hash i Meet at least one of the following: Z i =a i *2^b i , where a i and b i All are integers, and a i >0, b i ≥0; Z i =Z1, or, Z i <Z1; Z i Related to the size of the first information bit, or, Z i It is related to the size of the second information bit.

4. The method according to claim 2 or 3, characterized in that, The hash verification matrix H obtained after the i-th hash is i The number of rows is MB*Z1*,…,*Z i The hash verification matrix H obtained after the i-th hash is i The number of columns is NB*Z1*,…,*Z i ; Where MB is the number of rows in the base matrix, and NB is the number of columns in the base matrix.

5. The method according to any one of claims 2 to 4, characterized in that, In the i-th hash, the hash verification matrix H obtained from the (i-1)-th hash is... i-1 The element 0 in the Z is composed of a Z i *Z i The all-zero matrix substitution, the hash check matrix H obtained by the (i-1)th hash is... i-1 Element 1 in the Z is composed of a Z i *Z i The identity matrix is ​​replaced, or the hash verification matrix H obtained from the (i-1)th hash is... i-1 Element 1 in the Z is composed of a Z i *Z i Replacement with a cyclic shift matrix of the identity matrix; Wherein, the Z i *Z i The cyclic shift coefficients of the cyclic shift matrix of the identity matrix are the cyclic shift coefficient matrix P corresponding to the i-th hash. i The element at the corresponding position in the middle modulus Z i The value after that.

6. The method according to claim 5, characterized in that, P i The size of the hash verification matrix H obtained by the (i-1)th hash is related to the hash value. i-1 They are the same size; Among them, P i The elements in the array satisfy one of the following: P i The elements in the array can take two values: -1 and k. i Where -1 corresponds to H i-1 The row index and column index have the same element 0,k i Corresponding to H i-1 The row index and column index have the same element 1, k i greater than or equal to 0 and less than Z i Integers; P i H in the middle i-1 Elements with the same row index and column index, where element 0 is -1, are represented by P. i H in the middle i-1 The value of element 1, whose row index and column index are the same, is determined by P. i The order of the row index followed by the column index is from 0, 1, ..., Z. i -1 traversal; P i H in the middle i-1 Elements with the same row index and column index, where element 0 is -1, are represented by P. i H in the middle i-1 The value of element 1, where the row index and column index are the same, is based on P. i The circular shift value generated by the row index and column index; P i H in the middle i-1 Elements with the same row index and column index, where element 0 is -1, are represented by P. i H in the middle i-1 The value of element 1, where the row index and column index are the same, is based on P. i-1 The elements are determined.

7. The method according to any one of claims 2 to 6, characterized in that, The length of the code block corresponding to the first information bit is related to the coding parallelism Z; and / or, The number of code blocks corresponding to the first information bit is related to the coding parallelism Z; and / or, The padding bits corresponding to the first information bit are related to the encoding parallelism Z; and / or, The bit length of the first information bit before encoding is related to the encoding parallelism Z; and / or, The length of the first information bit after encoding is related to the encoding parallelism Z; and / or, The rate matching parameter corresponding to the first information is related to the coding parallelism Z.

8. The method according to claim 7, characterized in that, The rate matching parameters include at least one of the following: The length of the encoded bits after puncturing, the length of the bits placed in the circular buffer, and the starting point of each redundant version (RV).

9. The method according to any one of claims 1 to 8, The communication equipment includes at least one of a terminal and a network-side device.

10. The method according to any one of claims 1 to 9, characterized in that, The communication device is a terminal, and the method further includes: The terminal receives instruction information from the network-side device; The indication information is used to instruct the terminal to activate the first verification matrix determination method; The method for determining the first verification matrix corresponds to at least two hashing processes.

11. The method according to any one of claims 1 to 10, characterized in that, The communication device is a terminal, and the method further includes: The terminal sends capability information to the network-side device; The capability information is used to indicate that the terminal supports the first verification matrix determination method; The method for determining the first verification matrix corresponds to at least two hashing processes.

12. The method according to any one of claims 1 to 9, characterized in that, The communication device is a network-side device, and the method further includes: The network-side device sends instruction information to the terminal; The indication information is used to instruct the terminal to activate the first verification matrix determination method; The method for determining the first verification matrix corresponds to at least two hashing processes.

13. The method according to any one of claims 1 to 9 or 12, characterized in that, The communication device is a network-side device, and the method further includes: The network-side device receives capability information from the terminal; The capability information is used to indicate that the terminal supports the first verification matrix determination method; The method for determining the first verification matrix corresponds to at least two hashing processes.

14. A wireless communication device, characterized in that, include: The processing module is used to encode the first information bit according to the target parity check matrix, and / or to decode the second information bit according to the target parity check matrix; The target verification matrix is ​​obtained by hashing the base matrix M times. The object of the first hash in the M hashing is the base matrix, and the object of the i-th hash in the M hashing is the hash verification matrix obtained by hashing the (i-1)-th hash. M is a positive integer, i is a positive integer, and M≥2, 2≤i≤M.

15. The apparatus according to claim 14, characterized in that, The lifting factors for the M hashes are Z1, Z2, ..., Zn. M Where Z1, Z2, ..., Z M All are positive integers; The encoding parallelism of the target parity check matrix is ​​Z, where Z = Z1*Z2*,…,*Z M .

16. The apparatus according to claim 15, characterized in that, The lifting factor Z of the i-th hash i Meet at least one of the following: Z i =a i *2^b i , where a i and b i All are integers, and a i >0, b i ≥0; Z i =Z1, or, Z i <Z1; Z i Related to the size of the first information bit, or, Z i It is related to the size of the second information bit.

17. The apparatus according to claim 15 or 16, characterized in that, In the i-th hash, the hash verification matrix H obtained from the (i-1)-th hash is... i-1 The element 0 in the Z is composed of a Z i *Z i The all-zero matrix substitution, the hash check matrix H obtained by the (i-1)th hash is... i-1 Element 1 in the Z is composed of a Z i *Z i The identity matrix is ​​replaced, or the hash verification matrix H obtained from the (i-1)th hash is... i-1 Element 1 in the Z is composed of a Z i *Z i Replacement with a cyclic shift matrix of the identity matrix; Wherein, the Z i *Z i The cyclic shift coefficients of the cyclic shift matrix of the identity matrix are the cyclic shift coefficient matrix P corresponding to the i-th hash. i The element at the corresponding position in the middle modulus Z i The value after that.

18. The apparatus according to claim 17, characterized in that, P i The size of the hash verification matrix H obtained by the (i-1)th hash is related to the hash value. i-1 They are the same size; Among them, P i The elements in the array satisfy one of the following: P i The elements in the array can take two values: -1 and k. i Where -1 corresponds to H i-1 The row index and column index have the same element 0,k i Corresponding to H i-1 The row index and column index have the same element 1, k i greater than or equal to 0 and less than Z i Integers; P i H in the middle i-1 Elements with the same row index and column index, where element 0 is -1, are represented by P. i H in the middle i-1 The value of element 1, whose row index and column index are the same, is determined by P. i The order of the row index followed by the column index is from 0, 1, ..., Z. i -1 traversal; P i H in the middle i-1 Elements with the same row index and column index, where element 0 is -1, are represented by P. i H in the middle i-1 The value of element 1, where the row index and column index are the same, is based on P. i The circular shift value generated by the row index and column index; P i H in the middle i-1 Elements with the same row index and column index, where element 0 is -1, are represented by P. i H in the middle i-1 The value of element 1, where the row index and column index are the same, is based on P. i-1 The elements are determined.

19. The apparatus according to any one of claims 14 to 18, characterized in that, The wireless communication device further includes: The receiving module is used to receive indication information from network-side devices; The indication information is used to instruct the wireless communication device to activate the first verification matrix determination method; The method for determining the first verification matrix corresponds to at least two hashing processes.

20. The apparatus according to any one of claims 14 to 19, characterized in that, The wireless communication device further includes: The sending module is used to send capability information to network-side devices; The capability information is used to indicate that the wireless communication device supports the first verification matrix determination method; The method for determining the first verification matrix corresponds to at least two hashing processes.

21. The apparatus according to any one of claims 14 to 18, characterized in that, The wireless communication device further includes: The sending module is used to send indication information to the terminal; The indication information is used to instruct the terminal to activate the first verification matrix determination method; The method for determining the first verification matrix corresponds to at least two hashing processes.

22. The apparatus according to any one of claims 14 to 18 or 21, characterized in that, The wireless communication device further includes: The receiving module is used to receive capability information from the terminal; The capability information is used to indicate that the terminal supports the first verification matrix determination method; The method for determining the first verification matrix corresponds to at least two hashing processes.

23. A communication device, characterized in that, It includes a processor and a memory, the memory storing a program or instructions that can run on the processor, the program or instructions being executed by the processor to implement the steps of the wireless communication method as described in any one of claims 1 to 13.

24. A terminal, characterized in that, It includes a processor and a memory, the memory storing a program or instructions that can run on the processor, the program or instructions being executed by the processor to implement the steps of the wireless communication method as described in any one of claims 1 to 11.

25. A network-side device, characterized in that, It includes a processor and a memory, the memory storing a program or instructions that can run on the processor, the program or instructions being executed by the processor to implement the steps of the wireless communication method as described in any one of claims 1 to 9 or 12 to 13.

26. A readable storage medium, characterized in that, The readable storage medium stores a program or instructions that, when executed by a processor, implement the wireless communication method as described in any one of claims 1 to 13.

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