A data processing method and device, electronic equipment and readable storage medium

Abstract

The application discloses a data processing method, which comprises the following steps: generating a plurality of initial matrices with the same size based on a key seed; performing a plurality of rounds of first operation on the plurality of initial matrices respectively through a vector instruction of an assembly language until a preset number of operations is reached, so as to obtain a target matrix corresponding to each initial matrix; generating a key stream corresponding to the key seed based on the plurality of target matrices; and respectively encrypting plaintext data to be encrypted through the key stream, so as to obtain ciphertext data corresponding to the plaintext data, thereby improving the efficiency of generating the key and the efficiency of encryption and decryption.

Description

Technical Field

[0001] This application belongs to the field of computer technology, and specifically relates to a data processing method, apparatus, electronic device, and readable storage medium. Background Technology

[0002] With the development of the digital age, secure data transmission and storage have become core needs for enterprises, organizations, and individuals. Due to the lightweight encryption characteristics of stream cipher algorithms, stream ciphers are widely used in scenarios such as high-concurrency data interaction, hybrid cloud data sharing, and IoT device communication. Among them, the Salsa20 algorithm is one of the mainstream high-performance stream cipher solutions in the industry today.

[0003] In existing technologies, Salsa20's 20 rounds of iterative computation can often only process a set of 64 bytes of data at a time to obtain a set of 64 bytes of key stream, which is time-consuming and has low performance, and cannot meet the security requirements of large data volume scenarios. Summary of the Invention

[0004] The purpose of this application is to provide a data processing method, apparatus, electronic device, and readable storage medium that can shorten the key generation time and improve the efficiency of encryption and decryption.

[0005] In a first aspect, embodiments of this application provide a data processing method, the method comprising: Based on the key seed, generate multiple initial matrices of the same size; Using vector instructions in assembly language, multiple rounds of first operations are performed on the initial matrices until a preset number of operations are reached, thereby obtaining the target matrix corresponding to each initial matrix. Based on the multiple target matrices, a key stream corresponding to the key seed is generated; The plaintext data to be encrypted is encrypted using the key stream to obtain the ciphertext data corresponding to the plaintext data.

[0006] Secondly, embodiments of this application provide a data processing apparatus, the apparatus comprising: A matrix generation module is used to generate multiple initial matrices of the same size based on a key seed; these initial matrices are used to generate a key stream. The operation module is used to perform multiple rounds of first operations on the multiple initial matrices using vector instructions in assembly language, until a preset number of operations are reached, to obtain the target matrix corresponding to each initial matrix. A key stream generation module is used to generate a key stream corresponding to the key seed based on multiple target matrices; The encryption module is used to encrypt the plaintext data to be encrypted using the key stream to obtain the ciphertext data corresponding to the plaintext data.

[0007] Thirdly, embodiments of this application provide an electronic device including a processor, a memory, and a program or instructions stored in the memory and executable on the processor, wherein the program or instructions, when executed by the processor, implement the steps of the method described in the first aspect.

[0008] Fourthly, embodiments of this application provide a readable storage medium on which a program or instructions are stored, and when the program or instructions are executed by a processor, the steps of the method described above are implemented.

[0009] Fifthly, embodiments of this application provide a chip, the chip including a processor and a communication interface, the communication interface being coupled to the processor, the processor being used to run programs or instructions to implement the method described above.

[0010] In this embodiment, the key seed is initialized into multiple matrices of the same size, elements at the same position are grouped into the same parallel storage unit, and then multiple rounds of parallel operations are synchronously performed on all matrices using assembly language vector instructions. This fully utilizes the vector operation capabilities of the electronic device to improve the key generation speed. Vector shuffling instructions transform the previously interleaved elements into a state where elements of the same matrix are stored consecutively in the storage unit, achieving address continuation of the key stream elements. This reduces cross-address access latency during encryption, improving the encryption speed of the key stream and plaintext. Furthermore, separate data processing is performed on the plaintext data, further improving the data encryption and decryption rate and meeting the security requirements of large data volume scenarios. Attached Figure Description

[0011] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the description of the embodiments of this application will be briefly introduced below.

[0012] Figure 1 This is a flowchart illustrating the steps of an embodiment of a data processing method according to this application; Figure 2 This is a flowchart illustrating the steps of another data processing method embodiment of this application; Figure 3 This is a structural block diagram of a key generation device according to this application; Figure 4 This is a structural block diagram of an electronic device provided in this application. Detailed Implementation

[0013] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings.

[0014] Method Implementation Examples Reference Figure 1The diagram illustrates a flowchart of an embodiment of a key generation method according to this application, the method comprising: Step 101: Generate multiple initial matrices of the same size based on the key seed.

[0015] In this embodiment, the key seed refers to the initial parameters used to generate the keystream. It should be noted that the keystream generation in this application is achieved by implementing the Salsa20 algorithm. The Salsa20 algorithm is a stream cipher algorithm that uses a generator structure based on a pseudo-random number function to generate a keystream from the input parameters through multiple rounds of computation, thereby achieving strong cryptographic security. The Salsa20 algorithm performs 20 rounds of computation on the input parameters. This algorithm can also be varied into the Salsa12 algorithm, which performs the same computation process but reduces the number of rounds to 12 rounds, or the Salsa8 algorithm, which performs 8 rounds of computation on the input parameters.

[0016] In this embodiment, the key seed is the input parameter of the Salsa algorithm. The input parameters of the Salsa algorithm include: a constant, an encryption key, a random number, and a counter. For example, the input parameters of the Salsa algorithm contain four types of elements, all of which are binary data: a 128-bit fixed constant, a 256-bit encryption key, a 64-bit random number, and a 64-bit counter. The 128-bit fixed constant, such as "expand 32-byte k" or "expand 16-byte k", corresponds to the ASCII-encoded binary value and is used to ensure the basic pseudo-randomness of the key stream. The 256-bit encryption key can be user-defined or system-assigned and is the core guarantee of key stream security. The 64-bit random number (nonce) is a one-time random value; a new nonce is generated for each encryption to avoid generating duplicate key streams with the same key and to resist replay attacks. The 64-bit counter is used to identify the sequence number of key stream segments, supporting the generation and concatenation of key stream segments, and adapting to long plaintext encryption scenarios. Therefore, the total initial parameter length of the Salsa algorithm is 512 bits, or 64 bytes.

[0017] The structure of the initial matrix is ​​usually 4 A 4-bit matrix, where each element is a 32-bit word. The size of the matrix is ​​determined by the design of the Salsa20 algorithm. All initial matrices have the same structure, being 4-bit. 4. Matrices. The elements of the key seed are arranged in a uniform manner in the matrix, meaning that the constants, encryption key, random number, and counter are in the same positions in all initial matrices. For example, the structure of the generated initial matrices is as follows: 0x61707865Key0Key1Key2 Key30x3320646eNonce0Nonce1 Counter0Counter10x79622d32Key4 Key5Key6Key70x6b206574 The matrix elements are stored in left-to-right and top-to-bottom order. Key0 to Key7 are 8 elements resulting from dividing the encryption key into 32-bit words. Nonce0 + Nonce1 are 2 elements resulting from dividing the 64-bit nonce into 32-bit words. Counter0 + Counter1 are 2 elements resulting from dividing the 64-bit counter into 32-bit words. The remaining constants are ASCII encoding of "expand 32-byte k" (little-endian). It should be noted that the counters are different in multiple initial matrices. The counter setting rule can be as follows: there are M initial matrices. The counter value of the first initial matrix is ​​C, and the counter value of each subsequent initial matrix increments by 1 sequentially. That is, the counter value of matrix 1 is C+1, the counter value of matrix 2 is C+2, ..., and the counter value of matrix M-1 is C+M-1. For example, there are 4 initial matrices: the counter value of matrix 0 is 0, the counter value of matrix 1 is 1, the counter value of matrix 2 is 2, and the counter value of matrix 3 is 3. When generating other initial matrices, the key seed is filled in according to the above positions to obtain an initial matrix.

[0018] It should be noted that, in this embodiment, since the same operation is performed on multiple initial matrices, the corresponding data in all initial matrices can be packaged and a vector instruction can be used to complete one operation step on the same data of all matrices at once. Operations using vector instructions enable simultaneous operations on multiple initial matrices. A vector instruction refers to a single instruction with multiple data points; one vector instruction can perform the same operation on a group of data simultaneously. Therefore, one vector instruction can operate on N data points simultaneously. In this application, N initial matrices can be operated on simultaneously, thus generating N initial matrices during the initial matrix generation process.

[0019] Step 102: Using vector instructions in assembly language, perform multiple rounds of first operations on the initial matrices until a preset number of operations are reached, to obtain the target matrix corresponding to each initial matrix.

[0020] Based on the above, vector instructions refer to single-instruction, multiple-data instructions, and the first operation refers to a double-round operation, performing multiple rounds of the first operation on an initial matrix. Typically, this means performing 10 rounds of double-round operations on an initial matrix of size 4. The system consists of 4 matrices. Each double-round operation includes 4 QR operations on the row and column sides of the initial matrix, meaning one double-round operation comprises 8 QR operations. The preset number of operations depends on the encryption requirements, but is usually 10. The target matrix is ​​the final matrix obtained after multiple rounds of operations on the initial matrix. Each initial matrix undergoes multiple rounds of the first operation to obtain a target matrix.

[0021] In existing technologies, the Salsa20 algorithm is usually implemented using high-level languages, such as Go in the crypto library of the Go compiler. However, implementing it in a high-level language is more time-consuming. In contrast, the application uses assembly instructions to perform low-level operations directly, which can further improve the efficiency of generating the key stream.

[0022] For example, there are two initial matrices as follows: Initial matrix 0 (counter = 0): 0x61707865Key0Key1Key2 Key30x3320646eNonce0Nonce1 000x79622d32Key4 Key5Key6Key70x6b206574 Initial matrix 1 (counter = 1): 0x61707865Key0Key1Key2 Key30x3320646eNonce0Nonce1 1 00x79622d32Key4 Key5Key6Key70x6b206574 Normally, when performing operations on the initial matrix, the operands are (0x61707865, Key3, 0, Key5), and the operands are a single 0x61707865, a single Key3, a single 0, and a single Key5. However, when using vector commands to perform operations on the first columns of two matrices simultaneously (0x61707865, Key3, 0, Key5) and (0x61707865, Key3, 1, Key5), the operands are ((0x61707865, Key3, 0, Key ...3, Key5, Key3, Key3, Key5, Key3, Key3, Key3, Key5, Key3, Key3, Key3, Key5, Key3, Key3, Key3, Key5, Key3, Key3, Key3, Key5, Key3, Key3, Key3, Key5, Key3, Key3, Key3, Key5, Key3, Key3, Key3, Key5, Key3, Key3, Key3, Key5, Key3, Key3, Key3, Key5, Key3, Key3, Key3, Key3, Key5, Key3, Key 7865, (Key3, Key3), (0, 1), (Key5, Key5) means that the operands of the vector instruction are not single elements, but corresponding elements in multiple initial matrices at the same time, namely (0x61707865, 0x61707865), (Key3, Key3), (0, 1), (Key5, Key5). If the operation is performed on the first and fourth elements in the first column, it means that the operation is performed on two 0x61707865 and two Key5 at the same time.

[0023] Step 103: Based on the multiple target matrices, generate the key stream corresponding to the key seed.

[0024] The target matrix, transformed from the initial matrix, is added to the initial matrix to obtain the keystream generated based on the key seed. A single initial matrix can yield a 64-byte keystream block, but this application can operate on multiple initial matrices simultaneously, thus generating multiple 64-byte keystreams concurrently. For example, given N initial matrices, after transformation using the Salsa algorithm, N target matrices are obtained. Each initial matrix is ​​added to its corresponding target matrix to obtain N keystream blocks, each with a total length of 64 bytes. The complete keystream consists of the data following the sequence of N key matrices; that is, the complete keystream is N consecutively arranged 64-byte keystream blocks.

[0025] For example, suppose there are 4 initial matrices, and the counters in each initial matrix increment sequentially. Initial matrix 0 (counter = 0): 0x61707865Key0Key1Key2 Key30x3320646eNonce0Nonce1 000x79622d32Key4 Key5Key6Key70x6b206574 Initial matrix 1 (counter = 1): 0x61707865Key0Key1Key2 Key30x3320646eNonce0Nonce1 1 00x79622d32Key4 Key5Key6Key70x6b206574 Similarly, the only difference between initial matrix 2 and initial matrix 3 is the element at the counter position.

[0026] The target matrix 0 after the transformation of the initial matrix 0 is: A00A01A02A03 A10A11A12A13 A20A21A22A23 A30A31A32A33 The target matrix 1 after the transformation of the initial matrix 1 is: B00B01B02B03 B10B11B12B13 B20B21B22B23 B30B31B32B33 Keystream block 0 = Initial matrix 0 + Target matrix 0: 0x61707865+A00Key0+A01Key1+A02Key2+A03 Key3+A100x3320646e+A11Nonce0+A12Nonce1+A13 0+A200+A210x79622d32+A22Key4+A23 Key5+A30Key6+A31Key7+A320x6b206574+A33 Keystream block 1 = Initial matrix 1 + Target matrix 1: 0x61707865+B00Key0+B01Key1+B02Key2+B03 Key3+B100x3320646e+B11Nonce0+B12Nonce1+B13 1+B200+B210x79622d32+B22Key4+B23 Key5+B30Key6+B31Key7+B320x6b206574+B33 The complete keystream is formed by arranging the four keystream blocks sequentially. First, each 32-bit word is converted into a byte sequence according to little-endian byte order. Then, the elements in the matrix are arranged from left to right and from top to bottom. The four keystream blocks are then combined to obtain a keystream of 256.

[0027] For example, the keystream block 0 matrix: 0x8a7d8a7d0x3f3f3f3f0x1b1b1b1b0x8e8e8e8e 0x4a4a4a4a0x5c5c5c5c 0x6d6d6d6d 0x7e7e7e7e 0x9f9f9f9f 0xaaaaaaaa0xbbbbbbbb0xcccccccc 0xdddddddd0xeeeeeeee0xffffffff0x01234567 The keystream after arranging the first keystream block should be 0x7d, 0x8a, 0x7d, 0x8a, 0x3f, 0x3f, 0x3f, 0x3f, 0x1b, 0x1b, 0x1b, 0x1b, 0x8e, 0x8e, 0x8e, 0x8e....0x67, 0x45, 0x23, 0x01. The other keystream blocks are arranged in the same way to obtain the final keystream.

[0028] Step 104: Encrypt the plaintext data to be encrypted using the key stream to obtain the ciphertext data corresponding to the plaintext data.

[0029] When the length of the plaintext data is less than or equal to the length of the keystream, a keystream segment of the same length as the plaintext data is extracted from the keystream and XORed with the plaintext data to encrypt the plaintext data.

[0030] For example, the ASCII encoding of plaintext data is: 54 68 65 20 71 75 69 63 6b 20 62 72 6f77 6e 20. The corresponding keystream segment is: 7d 8a 7d 8a 3f 3f 3f 3f 1b 1b 1b 1b 8e 8e 8e8e. Perform a bitwise XOR operation on the plaintext data and keystream fragments: Plaintext byte 0: 0x54 (01010100) ⊕ Keystream byte 0: 0x7d (01111101) = 0x29 (00101001), Plaintext byte 1: 0x68 (01101000) ⊕ Keystream byte 1: 0x8a (10001010) = 0xe2 (11100010)... Similarly, all subsequent plaintext data is encrypted.

[0031] When the length of the plaintext data is greater than the length of the keystream, multiple keystreams need to be generated to encrypt the plaintext data. This means that the process of generating keystreams needs to be repeated multiple times. This can be done serially or in parallel. The plaintext data is divided into multiple plaintext data segments according to the length of the keystream. Each keystream is responsible for encrypting one plaintext data segment. The specific encryption process is the same as above. The keystream and the plaintext data segment are XORed bitwise to encrypt the plaintext data segment, resulting in multiple ciphertext data segments. The ciphertext data segments are then concatenated to obtain the final ciphertext data.

[0032] In this embodiment, parallel computation is achieved on multiple matrices. It should be noted that the vector register used to respond to vector instruction calls a register capable of simultaneously storing multiple elements of the same type. For a vector register, a single instruction can operate on multiple elements within the register simultaneously; the vector register is the object of assembly language vector instructions. This transforms the original method of processing elements one by one into a method of parallel processing multiple elements separately, enabling simultaneous computation of multiple initial matrices, increasing the length of each generated keystream, and shortening the time required to generate the same keystream. Using assembly language-level vector instructions to directly manipulate the data in the vector register avoids the performance overhead of high-level language compilation, thus improving the efficiency of keystream generation.

[0033] Reference Figure 2 The diagram illustrates a flowchart of another data processing embodiment of this application, the method comprising: Step 201: Based on the key seed, generate multiple initial matrices of the same size.

[0034] Step 201 can be referred to step 101 above, and will not be repeated here.

[0035] Optionally, step 201 may specifically include the following steps: Step S11: Obtain the first bit of the storage unit; Step S12: Determine the first quantity based on the first number of digits and the second number of digits; the second number of digits is the number of digits preset for each element in the initial matrix; Step S13: Based on the key seed, generate a first number of initial matrices of the same size.

[0036] For steps S11 to S13, the first digit refers to the total bit width of the storage unit, such as the bit width of the vector register. This is a physical characteristic determined by the processor hardware architecture. The first quantity indicates the number of initial Salsa20 matrices that can be processed in parallel simultaneously. In this embodiment, since each matrix element is 32 bits, and each vector register is used to store elements at the same position in multiple matrices, the number of initial matrices that can be processed in parallel is limited by the hardware storage capacity. The maximum number of matrix elements that can be stored in each vector register determines the maximum number of matrices that the vector instruction can process in parallel.

[0037] The first quantity is less than or equal to the quotient of the first digit divided by the second digit. Typically, to maximize the length of the keystream generated by sequential computation and improve keystream generation efficiency, the first quantity is determined to be the quotient of the first digit divided by the second digit. The first quantity refers to the number of initial matrices processed in parallel. Transforming an initial matrix to obtain the target matrix, and then adding the target matrix and the initial matrix, yields a 64-byte keystream block. Therefore, the first quantity is also the number of 64-byte keystream blocks in the keystream.

[0038] For example, the first bit is 128, indicating that the vector register has a bit width of 128. The second bit is 32, indicating that the preset length of the elements in the initial matrix is ​​32. The quotient of the first and second bits is 4. When the quotient is 4, the vector register can store 1, 2, 3, or 4 elements, meaning it can store a maximum of 4 elements at the same position in the initial matrix simultaneously. Setting the first quantity to 4 means that the CPU performs operations on the matrix elements in the 4 initial matrices simultaneously. When a vector instruction processes an element in the vector register, it processes the elements at the same position in the 4 initial matrices simultaneously, meaning it can process a maximum of 4 matrices in parallel. With a 128-bit vector register, each element in a single matrix is ​​32 bits, and a single vector register can store a maximum of 4 matrix elements simultaneously, allowing operations on 4 matrix elements to be performed concurrently, meaning it can process a maximum of 4 initial matrices in parallel. When the vector register is 256 bits, each element in a single matrix is ​​32 bits. A vector register can store a maximum of 8 matrix elements at the same time, and operations can be performed on 8 matrix elements simultaneously. This means that a maximum of 8 initial matrices can be processed in parallel to obtain 8 target matrices. Each target matrix is ​​added to each initial matrix to obtain the key matrix. Similarly, elements at the same position in multiple key matrices are stored in the same vector register.

[0039] It should be noted that, in this embodiment, elements at the same position in multiple initial matrices are stored in the same vector register. Transforming the elements in the vector register only changes the numerical value of the elements in the vector register, without changing the position of the matrix elements in the vector register. Therefore, for example, the elements of the first column in multiple initial matrices are stored in vector registers V0, V4, V8, and V12 respectively, and other elements are distributed similarly. The first column elements of the target matrix obtained after transforming multiple initial matrices are also stored in vector registers V0, V4, V8, and V12. The first column elements of the multiple key matrices obtained by adding each initial matrix and each target matrix are also stored in V0, V4, V8, and V12.

[0040] In this embodiment, the physical capacity of the vector register is identified, the maximum number of parallel matrices is calculated based on the algorithm characteristics, and the fixed algorithm structure is dynamically adapted to the variable hardware capabilities. The number of matrices processed in parallel is dynamically determined according to the actual bit width of the vector register. This design ensures that the optimal performance under the current conditions can be achieved on any hardware platform, improves resource utilization, and also improves the cross-platform compatibility of the algorithm.

[0041] Step 202: Store the elements at the same position in each of the multiple initial matrices into the same storage unit in turn; the number of storage units is the same as the number of elements in the initial matrices. Step 203: Using the vector instructions of the assembly language, perform multiple rounds of first operations on the elements stored in each memory unit until the preset number of operations is reached.

[0042] Regarding steps 202 and 203, a storage unit refers to a container used to store elements at the same position in multiple matrices. For example, each storage unit of a vector register is dedicated to storing a specific element position in the matrix. For instance, given four initial matrices, the 16 elements from these four initial matrices are broadcast sequentially to vector registers V0 to V15. This means that the four elements at the same position in each initial matrix are stored in the same vector register, and each vector register stores four identical 32-bit elements. For example, V0 stores four "0x61707865" elements, and V1 stores four Key0 elements.

[0043] It should be noted that V8 and V9 store a 64-bit counter. The high 32 bits of the counter are stored in V9, and the low 32 bits are stored in V8. That is, V9 stores four counters [63:32], and V8 stores four counters [31:0]. These four counters [63:0] are in an incrementing relationship. For example, if the values ​​of the four 64-bit counters are 1, 2, 3, and 4, then the four counters [31:0] stored in V8 from the low bit to the high bit are 0x1, 0x2, 0x3, and 0x4, and the four counters [63:32] stored in V9 from the low bit to the high bit are 0x0, 0x0, 0x0, and 0x0. Each storage unit stores an element at one position in the matrix. Therefore, the total number of storage units is the same as the number of elements in a single matrix. In this embodiment, each initial matrix is ​​a 4*4 matrix, and a single matrix includes 16 matrix elements, which means there are 16 storage units.

[0044] All elements in each storage unit are treated as a single operand and participate in vector operations as a whole. Vector instructions treat the entire operand as an operand, with all elements participating in the same operation simultaneously, and the result maintaining the same element structure. By using a single vector instruction to synchronously perform operations on the same positional elements of multiple matrices in a single vector register, it is equivalent to simultaneously completing operations on the same position of multiple matrices. The operational efficiency is positively correlated with the number of matrices. For example, storing four elements in a vector register improves efficiency by four times compared to the traditional method of incrementing a counter after completing a single matrix operation and then recalculating.

[0045] The operands of vector instructions are sets of elements at the same position in multiple matrices stored in each memory unit. For example, vector register 0 stores the elements at position (0,0) in four matrices. This set is an independent operand. There are 16 operands corresponding to 16 memory units. All operands are processed synchronously through vector instructions.

[0046] For example, The vector register has a bit width of 128 bits (SSE instruction set), the matrix element size is 32 bits (fixed), and the number of rows is 4 (128 / 32=4); the task requirement is to generate 4 key stream blocks (corresponding to 4 initial matrices), and the operation type is Salsa20 QR operation.

[0047] The traditional serial computing method is as follows: Step 1: Process matrix 0: Load the 16 elements of matrix 0 into the register, perform 80 QR operations (20 rounds × 4 times / round) to obtain the target matrix 0, then calculate: key stream block 0 = target matrix 0 + initial matrix 0, and store 64 bytes of key stream block 0.

[0048] Step 2: Processing Matrix 1: Load the 16 elements of matrix 1 into the register, perform 80 QR operations to obtain target matrix 1, then calculate: key stream block 1 = target matrix 1 + initial matrix 1, and store 64 bytes of key stream block 1.

[0049] Step 3: Process matrix 2 (similar to step 1).

[0050] Step 4: Process matrix 3 (similar to step 1).

[0051] The computational complexity of serial processing is as follows: the total number of QR operations is 4 matrices × 80 times / matrix = 320 times. The data was loaded 4 times as a complete matrix load, and the results were stored 4 times as complete results storage.

[0052] The time consumption for serial processing is: T_QR is the time to perform one QR operation, T_load is the time to load one matrix, T_store is the time to store one result, and the total time is 4×T_load+320×T_QR+4×T_store.

[0053] In this embodiment, elements at the same position in multiple initial matrices are stored in the same vector register, as follows: Vector register V0 = [matrix 0 [0][0], matrix 1 [0][0], matrix 2 [0][0], matrix 3 [0][0]] Vector register V1 = [matrix 0[0][1], matrix 1[0][1], matrix 2[0][1], matrix 3[0][1]] ... Vector register V15 = [matrix 0[3][3], matrix 1[3][3], matrix 2[3][3], matrix 3[3][3]] Taking the QR operation on the first column of multiple initial matrices as an example, the vector instruction performs the operation on the elements stored in the vector registers V0, V4, V8, and V12 simultaneously. That is, the operation is performed on the first column elements of matrix 0, matrix 1, matrix 2, and matrix 3 at the same time. Similarly, the operation is performed on other columns and rows.

[0054] Clearly, by loading all data into 16 vector registers in batches, storing all operation results into vector registers in batches, and performing only 80 QR operations instead of 320, the efficiency of generating keystreams of the same length is significantly improved.

[0055] In this embodiment, by packaging elements at the same position of multiple matrices into the same storage unit and performing overall computation using vector instructions, a fusion of instruction-level parallelism and data-level parallelism is achieved. A single computation can generate a key stream equivalent to multiple matrices, increasing throughput several times. By fully utilizing the single-instruction multiple-data architecture of modern processors, hardware utilization is improved, and the efficiency of key stream generation is increased.

[0056] Optionally, multiple rounds of first operations are performed on the multiple initial matrices until a preset number of operations are reached to obtain the target matrix corresponding to each initial matrix, including: Step S21: In each round of the first operation, the second operation is performed on each column element of the multiple initial matrices simultaneously by using vector addition instructions, vector shift instructions and vector XOR instructions to obtain multiple first intermediate matrices; Step S22: Using the vector addition instruction, the vector shift instruction, and the vector XOR instruction, perform the second operation on each row element of the plurality of first intermediate matrices simultaneously to obtain the second intermediate matrix, until the preset number of operations is reached to obtain the plurality of target matrices.

[0057] For steps S21 and S22, the second operation refers to the QR operation in the Salsa20 algorithm, which achieves a powerful obfuscation and diffusion effect by performing a series of arithmetic and logical operations on four 32-bit words. The QR operation rules are as follows: def QR(a, b, c, d): b ^= rotl(a + d, 7) operation ① The operation c ^= rotl(b + a, 9) ② The operation d^= rotl(c + b, 13) ③ The operation a^= rotl(d + c, 18) ④ return a, b, c, d Where a, b, c, and d are elements of a row or column in the matrix, and rotl(x, n) is a function that circularly shifts a 32-bit element left by n bits. For example, "b ^= rotl(a + d, 7)" means first adding elements a and d, then circularly shifting them left by 7 bits, and then XORing the shifted result with b to obtain the updated b. The initial matrix is ​​added word-by-word to the matrix after 80 rounds of QR operations, the result is serialized into a 64-byte keystream block, and then a counter is incremented for the next round of permutation operations. Column rounds of operations in the matrix involve QR operations on 4 columns, and row rounds involve QR operations on 4 rows. For each column, according to the above formula, the QR operation involves updating each element in each column, and the update of each element depends on the other two elements in the current column. Specifically, updating each element involves: performing addition and circular left shift on the other two elements to obtain the result, then performing an XOR operation between the result and the element itself to obtain the updated element. The updates to other elements depend on the previously updated elements.

[0058] It should be noted that in the embodiments of this application, not only can multiple matrices be operated on simultaneously through vector instructions, but the same operation is also performed simultaneously on the four groups of elements in the column wheel. For example, operation ① is performed simultaneously on the four columns in multiple initial matrices, and operations ②, ③, and ④ and the four operations in the row wheel are also performed simultaneously.

[0059] In each iteration, the second operation is performed simultaneously on all columns of multiple initial matrices. The update method for the four elements of a single column in these initial matrices is as follows: Elements 'a' and 'd' from the multiple initial matrices are simultaneously added using vector addition; the results of the previous operation are simultaneously shifted left by 7 bits using vector shift; and the results of the previous operation are XORed with the element 'b' in the multiple initial matrices using vector XOR to obtain the updated element 'b' in the matrices. Similarly, this process is repeated to update other elements in the same column until all elements in the same column have been updated.

[0060] While performing operations on one column, operations are also performed simultaneously on the other columns of multiple initial matrices. Specifically, vector addition instructions are executed on elements 'a' in all columns and elements 'd' in all rows of the multiple initial matrices. Vector shift instructions are then executed on the results of the previous operation in all columns of the multiple initial matrices. Finally, a vector XOR instruction is executed on the results of the previous operation in all columns of the multiple initial matrices and element 'b' in the multiple initial matrices to obtain the updated element 'b' in all columns of the multiple matrices. Similarly, the same operation process is performed on the other three elements 'a', 'c', and 'd' in all columns of the multiple matrices to update them simultaneously.

[0061] After the second operation is performed on all columns, multiple first intermediate matrices with all elements updated are obtained. The second operation is performed on all rows in the multiple first intermediate matrices simultaneously to obtain second intermediate matrices. The above loop is repeated on the multiple second intermediate matrices until it reaches 10 times, and the target matrix corresponding to each initial matrix is ​​obtained.

[0062] Specifically, the matrix indices are arranged from left to right and from top to bottom, in the order of (0, 1, 2, ... 15). The matrix element indices (a, b, c, d) in the QR operation take the following values: column rounds (0, 4, 8, 12), (5, 9, 13, 1), (10, 14, 2, 6), (15, 3, 7, 11); row rounds (0, 1, 2, 3), (5, 6, 7, 4), (10, 11, 8, 9), (15, 12, 13, 14). An example of vector commands used on the Dragon architecture platform is as follows:

[0063] Among them, VADDW is the vector addition instruction, VROTRW is the vector right shift instruction, and VXORV is the vector XOR instruction. These vector instructions update element b in the four columns. It should be noted that performing the second operation on each column element of multiple initial matrices (i.e., performing the second operation on the elements in the storage units storing each column element of the multiple initial matrices) requires determining the target storage unit for the operation based on the index of each column in the initial matrices, reading the column element from the target storage unit, and performing the operation. Similarly, performing the second operation on each row element of the first intermediate matrix (i.e., performing the second operation on the elements in the storage units storing each row element of the multiple initial matrices) requires determining the target storage unit for the operation based on the index of each row in the initial matrix, reading the row element from the target storage unit, and performing the operation. For example, the instruction for calculating the updated element in vector register V4 after calculating the elements in the first column of multiple initial matrices (i.e., the elements stored in vector registers V0, V4, V8, and V12) is as follows: VADDWV0, V12, V26 VROTRW$25, V26, V26 VXORVV4, V26, V4 Specifically, "VADDWV0, V12, V26" performs a vector addition operation on all elements in vector registers V0 and V12, storing the result in vector register V26; "VROTRW$25, V26, V26" performs a circular right shift instruction on all elements in vector register V26, shifting right by 25 bits (equivalent to circular left shifting by 7 bits), and storing the shifted elements back in vector register V26; "VXORVV4, V26, V4" performs a vector XOR instruction on all elements in vector register V26 and all elements in vector register V4, storing the result back in vector register V4. Similarly, the same operation is performed on all elements in the other vector registers.

[0064] In this embodiment, vector addition, vector shift, and vector XOR instructions are specifically used to perform the same operation on all columns of all matrices simultaneously. After all column operations are completed, the same operation is performed on all rows of all intermediate matrices simultaneously. The operation is repeated a preset number of times to obtain the final target matrix, which significantly improves the efficiency of generating the key stream.

[0065] Step 204: Based on the multiple target matrices, generate the key stream corresponding to the key seed.

[0066] Step 204 can be referred to step 103 above, and will not be repeated here.

[0067] Optionally, step 205 may specifically include the following steps: Step S31: Perform addition operations on each of the initial matrices and the corresponding target matrices to obtain multiple key matrices; Step S32: By reordering the elements in all the storage units, the elements belonging to the same key matrix are stored in a predetermined target storage unit group; the target storage unit group stores only the elements of one key matrix. Step S33: Determine the elements stored in each group of target storage units as the key stream.

[0068] Regarding steps S31 to S33, it should be noted that in this application, sorting the elements in all storage units can be achieved by executing shuffle instructions. Shuffle instructions are a special type of vector instruction, such as the instructions VILVL.W, VILVH.W, VILVL.V, and VILVH.V on the Dragon architecture. Executing shuffle instructions on all vector registers—that is, on all 16 vector registers—rearranges the order of elements in the vector registers, reorganizing the data according to a preset pattern. After the computation is complete, to facilitate subsequent encryption of the keystream and plaintext, the elements in each vector register are reordered, allowing the keystream to be stored sequentially in the vector registers. This ensures that elements from the same target matrix are stored in the same vector register, and elements from the same target matrix are stored in vector registers with contiguous addresses.

[0069] Specifically, the original method of storing data involved storing elements at the same position in multiple matrices in the same storage unit. Therefore, the elements of a key matrix were distributed across different storage units. For example, if a key matrix had 16 elements distributed across 16 storage units, reading the key stream of one key matrix required reading all 16 storage units. When reading the key stream of the next key matrix, it was necessary to read from the first storage unit to the last storage unit of the 16 storage units again. Similarly, when reading the key stream of each subsequent key matrix, it was necessary to read from the first storage unit to the last storage unit again. In other words, the process of reading the entire key stream required repeatedly accessing 16 storage units, and the process involved reading to the end and then jumping back to the starting address to read again, rather than reading continuously. After reordering, elements belonging to the same key matrix are grouped together in the target storage unit group. In other words, all storage units are grouped according to the key matrix, with each target storage unit group storing only one key matrix. Therefore, when reading all key matrices, only one consecutive read of all storage units is needed. Each storage unit is accessed only once, and the reads are sequential, eliminating the need for address jumps or repeated accesses to all storage units. For example, if each storage unit can store 4 matrix elements, the 16 matrix elements belonging to the same key matrix are grouped into 4 storage units, forming the target storage unit group for that key matrix. Reading the keystream of one key matrix only requires reading 4 consecutive storage units. To read the key of the next key matrix, simply continue reading the next 4 storage units, and so on, until all key matrices have been read. This centralized storage facilitates unified operation by vector instructions, avoiding the need to traverse multiple storage unit addresses when reading elements of each key matrix.

[0070] For example, after performing addition operations on the initial matrix and the processed target matrix respectively, the storage method of each element in the vector register is as follows: V0: block0, block16, block32, block48 V1: block1, block17, block33, block49 V2: block2, block18, block34, block50 ... V15: block15, block31, block47, block63 After shuffling, the data in the vector register is stored as follows: V0: block0, block1, block2, block3 V1: block4, block5, block6, block7 V2: block8, block9, block10, block11 ... V15: block60, block61, block62, block63 In this structure, blocks 0 to 15 represent the keystream segments obtained by adding the first initial matrix to its corresponding target matrix; blocks 16 to 31 represent the keystream segments obtained by adding the second initial matrix to its corresponding target matrix; blocks 32 to 47 represent the keystream segments obtained by adding the third initial matrix to its corresponding target matrix; and blocks 48 to 63 represent the keystream segments obtained by adding the fourth initial matrix to its corresponding target matrix. Before shuffling, accessing the keystream segments generated based on each initial matrix required traversing vector registers V0 to V15. After shuffling, the reordered keystream segments are stored contiguously in memory, and this contiguous access significantly improves the efficiency of accessing the keystream.

[0071] In this embodiment, each initial matrix and its corresponding target matrix are explicitly added word by word, ensuring that the generated keystream is fully compatible with the standard Salsa20 algorithm and avoiding compatibility issues caused by different implementation methods. The shuffling instruction transforms the data layout from computationally efficient to output-efficient, allowing the final keystream to be stored contiguously in memory. This reduces memory access latency during subsequent encryption operations and improves overall system performance.

[0072] Step 205: Create a preset number of threads for each of the plaintext data; Step 206: Initialize the execution parameters corresponding to each thread respectively; the execution parameters include: the key seed, the starting address of the plaintext data segment, and the storage address of the ciphertext data segment; Step 207: Each thread obtains the plaintext data fragment from the starting address, encrypts the plaintext data fragment based on the key stream formed by the key seed, and writes the ciphertext data fragment to the storage address.

[0073] In this embodiment, a multi-threaded parallel mechanism is used when encrypting plaintext data. Each thread independently handles the complete encryption process of a plaintext data segment and encrypts plaintext data segments of the same length. The plaintext data is divided into units according to the preset length of the keystream, ensuring that the length of each plaintext data segment is compatible with the preset length of the subsequent keystream for encryption. The division of the plaintext data yields the number of plaintext data segments. A corresponding thread is created for each plaintext data segment, and the preset number of threads is determined. The processor creates the corresponding preset number of threads, and these threads encrypt the plaintext data segments respectively. It should be noted that, except for the last thread responsible for the end of the plaintext data, the lengths of the plaintext data segments and the keystream are equal during the execution of each thread. In the last thread, the length of the plaintext data segment is less than or equal to the length of the keystream.

[0074] Plaintext data refers to the raw data that needs to be encrypted. It can be any binary content and is usually a sequence of bytes stored contiguously in memory.

[0075] The plaintext data fragments and the keystream are encrypted by performing a bitwise XOR operation. If the plaintext data fragment handled by the last thread is shorter than the length of the keystream, then a keystream of the same length as the plaintext data fragment is used for XOR encryption. After multiple threads performing encryption operations simultaneously encrypt the plaintext data fragments, a corresponding ciphertext data fragment is obtained for each plaintext data fragment. The ciphertext data fragments are then concatenated by each thread and written to their corresponding positions, with each position being consecutive, to obtain the final ciphertext data.

[0076] For example, the plaintext data is 640 bytes; the vector register is 128 bits; one vector register can store 4 matrix elements and perform operations on 4 initial matrices to generate a 256-byte key stream; the plaintext data is divided into 3 plaintext data segments according to the length of the key stream, the first 2 plaintext data segments are 256 bytes each, and the last plaintext data segment is 128 bytes each, and a corresponding thread is created for each plaintext data segment, that is, 3 threads are created.

[0077] During the execution of the first two threads, a 256-byte keystream is generated, and a 256-byte plaintext data segment is encrypted to obtain a 256-byte ciphertext data segment. During the execution of the last thread, a 256-byte keystream is generated, and a 128-byte keystream segment is extracted from the keystream to encrypt a 128-byte plaintext data segment. Since each thread is allocated a storage address for the ciphertext data segment, and the storage addresses are contiguous, each thread encrypts the plaintext data segment to obtain the ciphertext data segment and writes the ciphertext data segment to the corresponding storage address, thus ensuring that the complete ciphertext data is stored contiguously.

[0078] Optionally, step 205 may specifically include the following steps: Step S41: Obtain the quotient of the total length of the plaintext data and the preset length of the key stream; Step S42: If the quotient is an integer, determine the quotient as the preset quantity; otherwise, round the quotient up and determine the result as the preset quantity, and create the preset quantity of threads.

[0079] For steps S41 and S42, the preset length of the keystream is directly determined by the maximum number of matrix elements that can be stored simultaneously in the vector register or by the number of matrices processed in parallel. A single matrix can generate a 64-byte keystream segment. The preset length of the keystream is the number of matrices multiplied by the length of the keystream segment generated by a single matrix. For example, when each matrix element is 4 bytes (32 bits), a 128-bit vector register can store a maximum of 4 matrix elements simultaneously, meaning 4 matrices can be processed in parallel. Therefore, the preset length of the keystream is 256 bytes. A 256-bit vector register can store a maximum of 8 matrix elements simultaneously, meaning 8 matrices can be processed in parallel. The preset length of the keystream is 512 bytes.

[0080] The keystream is a pseudo-random sequence generated by a cryptographic algorithm. Encryption is achieved by XORing the keystream with the plaintext data. The preset length is the length of a single keystream generation, which is also the data length processed by a single thread in one encryption operation. The total length refers to the total length of the plaintext data to be encrypted, such as the total number of bytes. Plaintext data segments are the logically divided sub-parts of the total plaintext data, with each thread responsible for one segment. It should be noted that, except for the last thread which may process data shorter than the preset length, the remaining threads process the complete preset length data. The preset number is the number of parallel worker threads, determined by the plaintext data length and the keystream length. It should be noted that in a single-core system, multiple threads execute in parallel through time-slice round-robin on the single-core CPU; in a multi-core CPU, multiple threads are allocated to different cores for implementation, achieving parallel execution. For example, the process of multiple threads executing simultaneously includes: the operating system automatically assigning threads to different CPU cores, each thread accessing different memory regions without conflict; and achieving synchronous execution of multiple threads through thread join.

[0081] The quotient is the mathematical result of dividing the total length by the preset length, representing the number of complete plaintext data segments. If the quotient is not an integer, it means that plaintext data segments shorter than the preset length will remain. When the total length is not an integer multiple of the preset length, it is essential to ensure that no bytes are lost and that all data is processed. Therefore, by rounding up, a final thread is created to process the remaining plaintext data segments. For example, when the total length of the plaintext data is 1024 bytes and the preset length is 256 bytes, the quotient is an integer 4. Therefore, creating four threads is sufficient to encrypt all the plaintext data. When the total length of the plaintext data is 800 bytes and the preset length is 256 bytes, the quotient 3.125 is not an integer. By rounding up, we get 4. Four threads are created. The first three threads process the complete plaintext data segment, that is, they call the cryptographic stream to perform an XOR operation on the plaintext data segment of size 256 bytes to achieve encryption. The last thread processes the remaining data, that is, it calls the cryptographic stream to perform an XOR operation on the plaintext data segment of 800-256*3=32 bytes to achieve encryption, thereby ensuring that all plaintext data is encrypted.

[0082] In this embodiment, a rounding-up mathematical strategy ensures that even data segments shorter than a preset length can be processed by a dedicated thread, preventing data loss or incomplete encryption. This calculation method is simple and efficient, accurately calculating the minimum number of threads required to complete the encryption task, avoiding both resource excess and resource shortage.

[0083] The execution parameters refer to the set of configuration information required for each thread to work independently. The key seed is the initial parameter required to generate the keystream, and the counter for the key seed is different in each initial matrix used by each thread. The starting address of the plaintext data segment is the starting position of the plaintext data that the thread is responsible for encrypting in memory, and the storage address of the ciphertext data segment is the writing position of the encryption result in memory. The keystream is a pseudo-random sequence generated by a cryptographic algorithm. Multiple matrix keystreams are generated simultaneously using vector instructions. Different counter values ​​ensure that the keystreams of each thread are different, and a keystream of 256 bytes or longer is generated at a time. The plaintext data segment is a subset of the plaintext data that a single thread is responsible for processing.

[0084] It should be noted that in this application, the initial key seed, the global starting address of the plaintext data, and the global starting address of the ciphertext data are obtained. Then, based on the data length handled by each thread, the starting address of the plaintext data segment handled by each thread and the storage address of the ciphertext data segment can be determined. The starting address of the plaintext data segment handled by each thread is determined based on the global starting address of the plaintext data and the offset position of the current plaintext data segment within the plaintext data. Similarly, the storage address of each ciphertext data segment is determined based on the offset position of the ciphertext data segment within the ciphertext data. The difference between the key seeds used by different threads and the initial key seed lies in the counter. By changing the value of the counter and repeating other parameters, the key seed required by each thread can be obtained.

[0085] In this embodiment, by initializing independent execution parameters for each thread, it is ensured that each thread reads and writes different memory regions during operation, eliminating the need for complex locking mechanisms and greatly reducing the complexity and performance loss of multithreaded programming.

[0086] Specifically, the method for initializing execution parameters is as follows: For each thread, assign a unique identifier to the thread and calculate the product of the preset length and the identifier; determine the key seed based on the initial key seed, the identifier, and the number of initial matrices corresponding to the key stream; determine the starting address of the plaintext data segment based on the global starting address of the plaintext data and the product; and determine the storage address of the ciphertext data segment based on the global storage address of the ciphertext data and the product.

[0087] A thread identifier is a unique numerical identifier for each worker thread, used to distinguish different thread instances. Its value ranges from 0 to (total number of threads - 1), increasing sequentially according to the matrix to ensure uniqueness. The thread identifier can be the thread order minus 1; for example, the thread identifier for the first thread is 0. Therefore, the product of the preset length and the thread identifier is equal to the product of the preset length and the thread order minus one. The preset length is the length of data that a single thread is responsible for processing. Therefore, the mathematical product of the preset length and the thread identifier represents the offset of the data processed by that thread within the global data. Specifically, it is the offset of plaintext data segments within plaintext data, and the offset of ciphertext data segments within ciphertext data.

[0088] For each thread's key seed, variables, encryption keys, and random values ​​are copied from the initial key seed. These parameters are kept consistent across all threads. The thread identifier is multiplied by the number of initial matrices to obtain the thread's counter offset. The initial base counter value in the initial key seed is added to the calculated counter offset to form a thread-specific base counter. The copied base parameters and the calculated thread-specific counters are combined to form the complete key seed. The reason for multiplying the thread identifier by the number of initial matrices to obtain the thread's counter offset is that a single thread is responsible for multiple initial matrices, and the counters in each initial matrix within a single thread are also different. Typically, this is distinguished by incrementing by 1. Therefore, the counter offset between threads is equal to the number of initial matrices. For example, if the initial base counter in the initial key seed is `ori_counter`, and four initial matrices are generated in a single thread, then the base counter for each thread is `counter = ori_counter + 4`. (n-1) represents the base counter of the first thread, which is also the initial base counter. For example, if the initial base counter value is 0, then the base counter of the first thread is also 0, and the base counter of the second thread is 4. If the initial matrix size is 8, then the base counter of the first thread is also 0, and the base counter of the second thread is 8.

[0089] For the starting address of the plaintext data segment in each thread, read the global starting address of the plaintext data, add the global starting address to the offset of the plaintext data segment, and that is the starting address of the plaintext data segment. For example, if `ori_in` is the global starting address of the plaintext data, and the preset length is 256 bytes, then the starting address of the plaintext data segment `in` = `ori_in` + 256. (n-1). Similarly, for the storage address of the ciphertext data segment in each thread, read the global storage start address of the ciphertext data, add the global storage address to the offset of the ciphertext data segment, and that is the storage address of the ciphertext data segment. For example, with a preset length of 256 bytes, ori_out is the global start address of the ciphertext data, and the storage address out of the ciphertext data segment is out = ori_out + 256. (n-1). Among them, except for the plaintext data segment whose length is less than or equal to 256 handled by the last thread, the plaintext data segments handled by the other threads are all 256. That is, except for the plaintext data segment whose length is less than or equal to the preset length handled by the last thread, the plaintext data segments handled by the other threads are all equal to the preset length.

[0090] For example, the first total length of the plaintext data is 1024, the preset length is 256 bytes, the number of matrices is 4, and therefore the number of threads is 4.

[0091] If the initial key seed is {encryption key, random number, variable, initial base counter = 0}, then the global starting address of the plaintext is 0x1000 and the global storage address of the ciphertext is 0x2000.

[0092] For the first thread: the thread identifier is 1-1=0; the key seed is {encryption key, random number, variable, basic counter=0}; the starting address of the plaintext data segment is 0x1000+256×(1-1)=0x1000; the storage address of the ciphertext data segment is 0x2000+256×(1-1)=0x2000.

[0093] For the second thread: the thread identifier is 2-1=1; the key seed is {encryption key, random number, variable, basic counter=4}; the starting address of the plaintext data segment is 0x1000+256×(2-1)=0x1100; the storage address of the ciphertext data segment is 0x2000+256×(2-1)=0x2100.

[0094] For the third thread: the thread identifier is 3-1=2; the key seed is {encryption key, random number, variable, basic counter=8}; the starting address of the plaintext data segment is 0x1000+256×(3-1)=0x1200; the storage address of the ciphertext data segment is 0x2000+256×(3-1)=0x2200.

[0095] For the 4th thread: the thread identifier is 4-1=3; the key seed is {encryption key, random number, variable, basic counter=12}; the starting address of the plaintext data segment is 0x1000+256×(4-1)=0x1300; the storage address of the ciphertext data segment is 0x2000+256×(4-1)=0x2300.

[0096] In this embodiment, a dedicated counter for each thread is calculated using the thread identifier and the initial matrix count, ensuring that the keystream sequences generated by all threads are completely unique—the cornerstone of stream cipher security. Furthermore, the thread parameter calculation method provided in this application efficiently and accurately determines the plaintext data segment responsible for each thread.

[0097] In this embodiment, a multi-threaded parallel mechanism is added to the vectorized parallel key stream generation, forming a hybrid parallel computing architecture, which further improves the efficiency of key generation and encryption. This allows encryption performance to increase almost linearly with the number of processor cores. By dynamically allocating threads according to data length, it can efficiently process large files while avoiding the system overhead of creating too many threads for small data, achieving adaptive load balancing.

[0098] Step 208: Create the preset number of threads for the ciphertext data to be decrypted; Step 209: Execute the preset number of threads respectively. During the execution of each thread, generate the key stream and decrypt the ciphertext data fragments using the key stream to obtain plaintext data fragments. Step 210: Based on all the plaintext data fragments, obtain the plaintext data corresponding to the ciphertext data.

[0099] It should be noted that the keystream generation method in the decryption process is the same as that in the encryption process, both employing multi-threaded parallelism and multi-matrix parallelism to improve the efficiency of keystream generation. The operations for encrypting plaintext data and decrypting ciphertext data are also the same, both using an XOR operation, only the operands differ: in encryption, the keystream and plaintext data are XORed; in decryption, the keystream and ciphertext data are XORed.

[0100] Generate a keystream identical to the encryption process, read ciphertext data fragments from a specified location, perform an XOR decryption operation, and write the decrypted plaintext to the specified location. Read the total number of bytes of data to be decrypted, use the same preset length configuration as encryption, calculate the ratio of the total ciphertext length to the preset length and round up, determine the number of threads, and ensure that all data is processed by a dedicated thread. It should be noted that the decryption process uses the exact same encryption key and random number as the corresponding encryption process, maintaining the same counter offset calculation rules to ensure that the generated keystream is consistent with that used in encryption.

[0101] For example, the plaintext length before encryption is 640 bytes; the key is configured as key K, random number N, and start counter 0; the number of threads is 3; each thread generates a 256-byte key stream; the ciphertext length after encryption is 640 bytes; the ciphertext is stored in the contiguous memory area cipher

[640] .

[0102] Therefore, the data to be decrypted is 640 bytes of ciphertext, and the decryption key is the same as the encryption key K; the decryption random number is the same as the encryption random number N, with a starting counter of 0, also the same as the encryption. The preset length configuration is the same as during encryption. Each thread generates a 256-byte keystream and processes 256-byte ciphertext data segments. The total ciphertext length is 640 bytes, with a preset length configuration of 256 bytes / thread. The number of threads is determined in the same way as during encryption, and the number of threads is the same as during encryption.

[0103] Thread 1 processes ciphertext data segment 1: Ciphertext [0-255] (256 bytes) Thread 2 processes ciphertext data segment 2: Ciphertext [256-511] (256 bytes) Thread 3 processes ciphertext data segment 3: Ciphertext [512-639] (128 bytes) Thread 1 is responsible for the ciphertext fragment: bytes 0-255. It generates initial matrices 0 to 3 based on counters 0, 1, 2, and 3. After a series of transformations based on the initial matrices, it generates a 256-byte key stream. It performs an XOR operation on the 256-byte key stream and the ciphertext data fragment to obtain the plaintext data fragment, and writes it to the plain_buffer[0-255].

[0104] Thread 2 is responsible for the ciphertext fragment: bytes 256-511. Based on counters 4, 5, 6, and 7, it generates initial matrices 4 to 7. After a series of transformations based on the initial matrices, it generates a 256-byte key stream. Based on the 256-byte key stream and the ciphertext data fragment, it performs an XOR operation to obtain the plaintext data fragment. After decryption, the plaintext data fragment is written to the plain_buffer[256-511].

[0105] Thread 3 is responsible for the ciphertext segment: bytes 512-639. Based on counters 8, 9, 10, and 11, it generates initial matrices 8 to 11. After a series of transformations based on the initial matrices, it generates a 256-byte key stream. However, it only uses the first 128 bytes of the key stream to perform an XOR operation on the ciphertext data segment to obtain the plaintext data segment, which is then written to the plain_buffer[512-639].

[0106] In summary, the data processing method provided in this application improves key generation efficiency by uniformly operating on all elements in the vector register using vector instructions during key generation, enabling parallel computation of multiple matrices. Furthermore, this application directly uses assembly language vector instructions to operate on the vector registers, rather than a high-level language, further reducing performance overhead from high-level language compilation and improving key stream generation efficiency. Finally, after obtaining the target matrix, the initial matrices and the target matrix are added together, and a shuffling instruction is used to adjust the order of elements stored in all vector registers, re-storing the continuous key stream into contiguous vector registers. This avoids the need to access the key stream across registers, reducing access latency and improving the efficiency of subsequent key stream access, thereby shortening the time required for data encryption and improving encryption efficiency. Based on parallel key stream generation, a multi-threaded parallel computing system is further constructed, fully utilizing each computing unit in the processor. This system can handle different scales, especially large-scale data encryption and decryption needs, significantly improving the efficiency of data encryption and decryption. Furthermore, the decryption process uses the same key generation, multithreading, and vectorization techniques as the encryption process, thus improving decryption speed and meeting the high latency requirements of scenarios such as real-time communication and video playback. Encryption and decryption can use the same core code and hardware optimization logic, significantly reducing system complexity, development costs, and maintenance burden.

[0107] Device Examples Reference Figure 3 The diagram illustrates a logical block diagram of a data processing apparatus according to an embodiment of this application. The apparatus may include: Matrix generation module 310 is used to generate multiple initial matrices of the same size based on the key seed. The operation module 320 is used to perform multiple rounds of first operations on the multiple initial matrices using vector instructions in assembly language, until a preset number of operations are reached, to obtain the target matrix corresponding to each initial matrix. The key stream generation module 330 is used to generate a key stream corresponding to the key seed based on multiple target matrices; The encryption module 340 is used to encrypt the plaintext data to be encrypted using the key stream to obtain the ciphertext data corresponding to the plaintext data.

[0108] Optionally, the computing module includes: The writing module is used to successively store elements at the same position in multiple initial matrices into the same storage unit; the number of storage units is the same as the number of elements in the initial matrices; The first operation submodule is used to perform multiple rounds of first operations on the elements stored in each memory unit using vector instructions in assembly language, until the preset number of operations is reached.

[0109] Optionally, the computing module includes: The second operation submodule is used to perform a second operation on each column element of the multiple initial matrices simultaneously in each round of the first operation by using vector addition instructions, vector shift instructions and vector XOR instructions to obtain multiple first intermediate matrices. The third operation submodule is used to perform a second operation on each row element of the plurality of first intermediate matrices simultaneously using the vector addition instruction, the vector shift instruction, and the vector XOR instruction to obtain a second intermediate matrix, until the preset number of operations is reached to obtain a plurality of target matrices.

[0110] Optionally, the keystream generation module includes: The addition module is used to perform addition operations on each of the initial matrices and the corresponding target matrices to obtain multiple key matrices; The shuffling module is used to reorder the elements in all the storage units and store the elements belonging to the same key matrix into a predetermined target storage unit group; the target storage unit group stores only the elements of one key matrix. The first keystream generation submodule is used to determine the elements stored in each of the target storage unit groups as the keystream.

[0111] Optionally, the matrix generation module includes: A bit acquisition module is used to acquire the first bit of the storage unit; The matrix quantity determination module is used to determine a first quantity based on the first number of digits and the second number of digits; the second number of digits is a preset number of digits for each element in the initial matrix; The matrix generation submodule is used to generate a first number of initial matrices of the same size based on the key seed.

[0112] Optionally, the encryption module includes: The thread creation module is used to create a preset number of threads for each plaintext data. An initialization module is used to initialize the execution parameters corresponding to each of the threads respectively; the execution parameters include: the key seed, the starting address of the plaintext data segment, and the storage address of the ciphertext data segment; The encryption submodule is used by each thread to obtain the plaintext data fragment from the starting address, encrypt the plaintext data fragment based on the key stream formed by the key seed, and write the ciphertext data fragment to the storage address.

[0113] Optionally, the thread creation module includes: The quotient determination module is used to obtain the quotient of the total length of the plaintext data and the preset length of the key stream; The quantity determination module is used to determine the quotient as the preset quantity if the quotient is an integer, and otherwise to round the quotient up and determine the result as the preset quantity.

[0114] Optionally, the device further includes: A creation module is used to create the preset number of threads for the ciphertext data to be decrypted; An execution module is used to execute the preset number of threads respectively. During the execution of each thread, the key stream is generated, and the ciphertext data fragments are decrypted using the key stream to obtain plaintext data fragments. The decryption module is used to obtain the plaintext data corresponding to the ciphertext data based on all the plaintext data fragments.

[0115] In summary, the data processing apparatus provided in this application performs unified operations on all elements in a vector register using vector instructions, enabling parallel computation of multiple matrices and further improving key generation efficiency. Furthermore, this application directly uses assembly language vector instructions to operate on the vector registers, rather than a high-level language, further reducing the performance overhead of high-level language compilation and improving keystream generation efficiency. By using shuffling instructions, the order of elements stored in all vector registers is adjusted, restoring consecutive keystreams in contiguous address vector registers. This avoids the need to cross registers when accessing the keystream, reducing access latency and improving the efficiency of subsequent keystream access, thus enhancing encryption efficiency. Based on parallel keystream generation, a multi-threaded parallel computing system is further constructed, allowing encryption and decryption to use the same core code and hardware optimization logic, significantly reducing system complexity, development costs, and maintenance burden.

[0116] As the device embodiment is basically similar to the method embodiment, the description is relatively simple, and relevant parts can be found in the description of the method embodiment.

[0117] Reference Figure 4 This is a structural block diagram of an electronic device provided in an embodiment of this application. Figure 4 As shown, the electronic device includes: a processor, a memory, a communication interface, and a communication bus. The processor, the memory, and the communication interface communicate with each other through the communication bus. The memory is used to store executable instructions, which cause the processor to execute the method of the aforementioned embodiment.

[0118] The processor can be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), or other programmable devices, transistor logic devices, hardware components, or any combination thereof. The processor can also be a combination that implements computational functions, such as a combination of one or more microprocessors, or a combination of a DSP and a microprocessor.

[0119] The communication bus may include a path for transmitting information between the memory and the communication interface. The communication bus may be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus, etc. The communication bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 4 The symbol is represented by only one line, but this does not mean that there is only one bus or one type of bus.

[0120] The memory may be ROM (Read Only Memory) or other types of static storage devices that can store static information and instructions, RAM (Random Access Memory) or other types of dynamic storage devices that can store information and instructions, or it may be EEPROM (Electrically Erasable Programmable Read Only Memory), CD-ROM (Compact Disc Read Only Memory), magnetic tape, floppy disk, and optical data storage devices, etc.

[0121] This application also provides a non-transitory computer-readable storage medium that, when the instructions in the storage medium are executed by a processor of an electronic device (server or terminal), enables the processor to perform the methods of the foregoing embodiments.

[0122] This application embodiment also provides a chip, which includes a processor and a communication interface. The communication interface is coupled to the processor. The processor is used to run programs or instructions to implement the various processes of the above embodiments and achieve the same technical effect. To avoid repetition, it will not be described again here.

[0123] It should be understood that the chip mentioned in the embodiments of this application may also be referred to as a system-on-a-chip, system chip, chip system, or system-on-a-chip, etc.

[0124] The above provides a detailed description of a data processing method, apparatus, electronic device, and readable storage medium provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A data processing method, characterized in that, The method includes: Based on the key seed, generate multiple initial matrices of the same size; Using vector instructions in assembly language, multiple rounds of first operations are performed on the initial matrices until a preset number of operations are reached, thereby obtaining the target matrix corresponding to each initial matrix. Based on the multiple target matrices, a key stream corresponding to the key seed is generated; The plaintext data to be encrypted is encrypted using the key stream to obtain the ciphertext data corresponding to the plaintext data.

2. The method according to claim 1, characterized in that, The process of performing multiple rounds of first operations on multiple initial matrices includes: Elements at the same position in multiple initial matrices are successively stored into the same storage unit; the number of storage units is the same as the number of elements in the initial matrices. Using vector instructions in assembly language, multiple rounds of first operations are performed on the elements stored in each memory unit until the preset number of operations is reached.

3. The method according to claim 1 or 2, characterized in that, The step of performing multiple rounds of first operations on multiple initial matrices until a preset number of operations is reached includes: In the first operation, the second operation is performed on each column element of the multiple initial matrices simultaneously by vector addition instructions, vector shift instructions and vector XOR instructions to obtain multiple first intermediate matrices. By using the vector addition instruction, the vector shift instruction, and the vector XOR instruction, the second operation is performed on each row element of the plurality of first intermediate matrices simultaneously to obtain a second intermediate matrix, until the preset number of operations is reached to obtain a plurality of target matrices.

4. The method according to claim 2, characterized in that, The step of generating the key stream corresponding to the key seed based on multiple target matrices includes: Each of the initial matrices and the corresponding target matrices is added to obtain multiple key matrices; By reordering the elements in all the storage units, elements belonging to the same key matrix are stored in a predetermined target storage unit group; the target storage unit group stores only the elements of one key matrix. The elements stored in each of the target storage unit groups are determined as the key stream.

5. The method according to claim 2, characterized in that, The generation of multiple initial matrices of the same size based on the key seed includes: Obtain the first bit of the storage unit; Based on the first digit and the second digit, a first quantity is determined; the second digit is the number of digits preset for each element in the initial matrix. Based on the key seed, a first number of initial matrices of the same size are generated.

6. The method according to claim 1, characterized in that, The encryption of the plaintext data to be encrypted using the key stream includes: For the plaintext data, create a preset number of threads; Initialize the execution parameters corresponding to each thread respectively; the execution parameters include: the key seed, the starting address of the plaintext data segment, and the storage address of the ciphertext data segment; Each thread retrieves the plaintext data fragment from the starting address, encrypts the plaintext data fragment using a key stream formed based on the key seed, and then writes the ciphertext data fragment to the storage address.

7. The method according to claim 6, characterized in that, The creation of a preset number of threads includes: Obtain the quotient of the total length of the plaintext data and the preset length of the key stream; If the quotient is an integer, the quotient is determined as the preset quantity; otherwise, the quotient is rounded up, the result is determined as the preset quantity, and the preset quantity of threads is created.

8. The method according to claim 1, characterized in that, The method further includes: For the ciphertext data to be decrypted, create the preset number of threads; The preset number of threads are executed respectively. During the execution of each thread, the key stream is generated, and the ciphertext data fragments are decrypted using the key stream to obtain plaintext data fragments. Based on all the plaintext data fragments, the plaintext data corresponding to the ciphertext data is obtained.

9. A data processing apparatus, characterized in that, The device includes: A matrix generation module is used to generate multiple initial matrices of the same size based on a key seed; these initial matrices are used to generate a key stream. The operation module is used to perform multiple rounds of first operations on the multiple initial matrices using vector instructions in assembly language, until a preset number of operations are reached, to obtain the target matrix corresponding to each initial matrix. A key stream generation module is used to generate a key stream corresponding to the key seed based on multiple target matrices; The encryption module is used to encrypt the plaintext data to be encrypted using the key stream to obtain the ciphertext data corresponding to the plaintext data.

10. An electronic device, characterized in that, The electronic device includes a memory and one or more programs, wherein one or more programs are stored in the memory and configured to be executed by one or more processors according to any one of claims 1 to 8.

11. A readable storage medium, characterized in that, When the instructions in the storage medium are executed by the processor of the electronic device, the processor is enabled to perform the method as described in any one of claims 1 to 8.

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