Receiver coefficient guided adaptation to pre-equalizer coefficients

Abstract

The disclosed equalizers, transceivers, communication systems, and associated methods provide adaptation to pre-equalizer coefficients based on at least one receive filter coefficient. An illustrative equalizer includes a discrete time finite impulse response ("FIR") filter configured to convert a received signal to a filtered signal; a decision element for determining a channel symbol represented by the filtered signal; and a controller. The controller: is configured to adjust coefficients for the FIR filter based on performance of the equalizer, the coefficients including a first post cursor coefficient; and an equalizer configured to change the first post-cursor coefficient of the pre-equalizer if the first post-cursor coefficient of the FIR filter has a magnitude exceeding a first threshold.

Description

Technical Field

[0001] This disclosure generally relates to training a communication transceiver, and more specifically to a communication transceiver and method for prioritizing pre-equalizer coefficients based on an adaptive order of coefficient values ​​of a trained receive filter. Background Technology

[0002] The Peripheral Component Interconnect High Speed ​​(“PCIe”) specification is one of several standards for general-purpose input / output interconnects. This type of interconnect is frequently used as an expansion bus to enhance the resources and functionality of computers and other electronic systems by accepting expansion cards or other interchangeable components. The PCI Special Interest Group (SPIC) is an industry alliance that updates the PCIe specification every few years to double the data rate while maintaining backward compatibility. The supported data rates make PCIe attractive for systems designed for machine learning, artificial intelligence, real-time image processing, gaming, high-bandwidth data storage, and even computer-centric networks.

[0003] Because it was originally a parallel bus, PCIe has strict latency constraints, which benefit load-to-memory interconnect protocols. This latency constraint inevitably limits the range of a given PCIe link, especially at high symbol rates where noise or other signal integrity issues may require relatively frequent retransmissions. Equalizers and retimers can address such signal integrity issues and improve consistency, significantly reducing average transaction latency (although this increases minimum latency).

[0004] The latest versions of this specification have partially improved the data rate by changing the signaling scheme to use 4-level pulse amplitude modulation (PAM4) channel symbols instead of non-return-to-zero (NRZ) channel symbols. This change reduces the signal margin, typically requiring the use of equalizers and / or retimers to ensure the bit error rate remains at a sufficiently low level.

[0005] Like most integrated circuit devices, receivers and retimers have become so complex that it is impractical for electronics designers to design them from scratch. Instead, electronics designers rely on predefined modular cells of integrated circuit layout design, arranging and assembling them as needed to achieve the various functions of the desired device. Each modular cell has a defined interface and behavior that has been verified by its creator. Although each modular cell may require significant effort and investment to create, the availability of modular cells for reuse and further development greatly reduces product cycle time and leads to better products. Predefined cells can be organized hierarchically, where a given cell contains one or more lower-level cells, and is in turn contained within higher-level cells. Many organizations have libraries of such predefined modular cells for sale or licensing, including, for example, embedded processors, memories, interfaces for different bus standards, power converters, frequency multipliers, sensor transducer interfaces, etc. Predefined modular cells are also referred to as cells, blocks, cores, and macros; these terms have different meanings and variations (“IP core”, “soft macro”), but are often used interchangeably.

[0006] Modular cells can be expressed in different ways, such as as Hardware Description Language (HDL) files or as fully routed designs that can be directly represented as a series of manufacturing process masks. Fully routed designs are typically process-specific, meaning additional design work is often required to migrate the modular cell to different processes or manufacturers. Modular cells in HDL form require subsequent synthesis, placement, and routing steps to implement, but they are process-independent, meaning different manufacturers can apply their preferred automated synthesis, placement, and routing processes to implement the cell using a wide range of manufacturing processes. Due to their higher-level representation, HDL cells are more accommodating to the use of modified and variable design parameters, while fully routed cells offer better predictability in terms of area requirements, reliability, and performance. While there are no fixed rules, digital modular designs are more commonly specified in HDL form, while analog and mixed-signal cells are more often specified in lower-level physical descriptions.

[0007] For device designs employing modern data communication standards that are continuously evolving towards higher symbol rates and greater bits per channel, a serializer-deserializer (SerDes) core is often required. At higher symbol rates, channel symbols become more attenuated and dispersed during their propagation, leading to increasingly severe inter-symbol interference (ISI) at the receiver. When attempting to detect channel symbols, the receiver must contend with this ISI in addition to the channel noise that contaminates the received signal. Recent versions of the PCIe standard specify the use of pre-equalization in the transmitter to reduce ISI. Between the receiver and transmitter, there may be more than 20 filter coefficients and other equalization parameters that need to be optimized upon power-on or reset, taking into account not only variations in channel response but also potential changes in the performance of equalizer components due to process variations, power supply voltage variations, and temperature variations (collectively referred to as "PVT variations"), as well as drift caused by component aging.

[0008] A popular technique for dealing with such variations is called adaptive equalization, which is a technique that iteratively adjusts the parameters of the equalizer until the equalizer's performance converges to its optimal value. A known challenge of adaptive equalization is the training time that can be required for such convergence, especially when many parameters are adaptively adjusted. Convergence can be accelerated by focusing on a few parameters at a time, where appropriate. Summary of the Invention

[0009] Therefore, this document discloses an equalizer, transceiver, communication system, and associated method that provides adaptive pre-equalizer coefficients based on at least one receive filter coefficient. An illustrative equalizer includes: a discrete-time finite impulse response (“FIR”) filter configured to convert a received signal into a filtered signal; a decision element for determining channel symbols represented by the filtered signal; and a controller. The controller is configured to: adjust coefficients for the FIR filter based on the performance of the equalizer, the coefficients including a first post-vernier coefficient; and is configured to: change the first post-vernier coefficient of the pre-equalizer if the first post-vernier coefficient of the FIR filter has a magnitude exceeding a first threshold.

[0010] An illustrative equalization method includes: converting a received signal into a filtered signal using a discrete-time finite impulse response (“FIR”) filter; using a decision element to determine the channel symbols represented by the filtered signal; adjusting coefficients for the FIR filter based on the performance of the equalizer, the coefficients including a first back vernier coefficient; and changing the first back vernier coefficient of the pre-equalizer if the first back vernier coefficient of the FIR filter has a magnitude exceeding a first threshold.

[0011] The aforementioned methods and equalizers can be embodied as semiconductor IP cores stored on non-transitory information storage media. When used by a suitably configured computer, the semiconductor IP cores provide circuit and / or process mask designs for manufacturing integrated circuit devices having the aforementioned components, thereby implementing the methods described above.

[0012] The illustrative communication system includes a remote port coupled to a local port. The remote port includes: a pre-equalizer configured to convert a digital transmitted signal into an equalized transmitted signal; and a digital-to-analog converter configured to convert the equalized transmitted signal into a channel signal. The local port includes: an analog-to-digital converter configured to provide a digital received signal representing the channel signal; a discrete-time finite impulse response (“FIR”) filter configured to convert the digital received signal into a filtered signal; a decision element for determining the channel symbols represented by the filtered signal; and a local controller configured to adjust at least one coefficient of the FIR filter based on equalization performance, further configured to change at least one corresponding coefficient of the pre-equalizer if at least one coefficient of the FIR filter has a magnitude exceeding a first threshold.

[0013] Each of the foregoing can be implemented individually or in combination, and can be combined with any one or more of the following optional features: 1. Performance is based on at least one of the filtered signal or the input signal to the decision element and the channel symbols. 2. The controller changes the first back vernier coefficient of the pre-equalizer in part by sending a change request to the remote transmitter via an embedded reverse channel. 3. The change request is a request to increment the value of a specified coefficient. 4. The coefficient includes a first front vernier coefficient. 5. The controller is configured to change the first front vernier coefficient of the pre-equalizer if the first front vernier coefficient has a value exceeding a second threshold. 6. The controller is further configured to iteratively adjust the coefficients and change the first back vernier coefficient or the first front vernier coefficient until the performance reaches the target. 7. The controller is further configured to store coefficients for the FIR filter and for the pre-equalizer for use as initial values ​​after power-on or reset. 8. The local controller changes at least one corresponding coefficient of the pre-equalizer in part by sending a change request to the controller at the remote port via an embedded reverse channel. 9. At least one coefficient is a first front vernier coefficient for the FIR filter, and at least one corresponding coefficient is a first front vernier coefficient for the pre-equalizer. 10. The local controller is further configured to change the first back vernier coefficient for the pre-equalizer if the first back vernier coefficient for the FIR filter has a value exceeding a second threshold. Attached Figure Description

[0014] Figure 1 It is a block diagram of an illustrative computer system that uses a PCIe bus interface to interconnect a processor module with multiple peripheral slots.

[0015] Figure 2 This is a schematic diagram illustrating a retimer with multiple channels.

[0016] Figure 3 This is a flowchart illustrating the equalizer training method. Detailed Implementation

[0017] Although specific embodiments are given in the accompanying drawings and the following description, please remember that they do not limit this disclosure. Rather, they provide a basis for those skilled in the art to identify alternative forms, equivalents, and modifications that are included within the scope of the appended claims.

[0018] The disclosed adaptive equalizer and training method are best understood within an explanatory context. Therefore, Figure 1 An illustrative computer system 102 is shown, having a processing module 104 (labeled CPU) connected to system memory 106 to retrieve instructions and data for implementing programmable functions. The processing module 104 is shown having multiple PCIe bus interfaces 108 for connection to various other components via connectors, for example, having a standard card electromagnetic (CEM) slot form factor. Other PCIe connector form factors are known and can be used.

[0019] Figure 1 CEM slots 110, 120, 140, and 150 are shown, which can support different numbers of channels and different PCIe data rates depending on the needs of different types of components. Components such as graphics processing units and video display cards can use connectors that use the highest data rates and the highest number of channels, while bridges to peripheral components, printers, keyboards, pointing devices, and general purpose input / output buses can use connectors that use slower data rates and fewer channels. Intermediate connectors can be used for hard drives, solid-state drives, network interfaces, cameras, and scanners. Some slots (such as CEM slot 110) are shown without retimers. Some retimers (such as retimer 121 and retimer 122) can support communication to multiple CEM slots 120 that require fewer channels than a given retimer can support. Retimer 123 provides retiming for communication between the processing module and CEM slot 130. CEM slot 140 has no retimer but accepts expansion card 142. The expansion card 142 has a retimer 151, which can provide retiming for communication with the expansion card's (multiple) CEM slots 150.

[0020] Figure 2 An illustrative retimer in the form of a monolithic integrated circuit chip 200 is shown, having contacts for receiving signals from outside the chip and contacts for providing signals from outside the chip. Although the figure shows contacts for single-ended signals, in practice, some of the input and output signals may be differential signals, requiring a pair of contacts for each such signal. The contacts can be pads, pins, balls, bond wires, or any suitable conductive path from the integrated circuit substrate to a trace on the outer surface.

[0021] Chip 200 includes multiple channels, from channel 0 to channel (N-1), each channel transmitting upstream PCIe signals from downstream to upstream and vice versa. Each channel includes a downstream retimer module with a deserializer (DES) that converts the downstream input PCIe signal into a downstream digital symbol stream and a serializer that converts the downstream digital symbol stream into a retimed downstream PCIe signal. Each channel further includes an upstream retimer module with a deserializer that converts the upstream input PCIe signal into an upstream digital symbol stream and a serializer that converts the upstream digital symbol stream into a retimed upstream PCIe signal. The core logic (CORE) buffers the digital symbol stream and can optionally implement additional functions such as descrambling, deskewing between channels, ordered set (OS) decoding, link training state machine implementation, and scrambling.

[0022] The training controller coordinates, for example, the adaptation of serializer and deserializer equalization parameters for pre-equalization filter coefficients; in some implementations, the training controller is an integrated part of the core logic. Furthermore, the training controller receives pre-equalizer adaptation information (“reverse channel information”) from remote ends of upstream and downstream links via a reverse channel, and accordingly generates pre-equalizer adaptation information locally to transmit to the remote ends of upstream and downstream links (“local information”). Suitable communication protocols for transmitting local information and receiving reverse channel information via frame headers are described in PCI Express Base Specification Revision 6.1 (July 12, 2023), and particularly in sections 4.2.4 and 4.2.5.

[0023] Each channel further includes output drivers 202 and 212 to provide downstream PCIe output signals and upstream PCIe output signals to downstream and upstream links, respectively. Output drivers 202 and 212 buffer the serializer output and, in some cases, can convert single-ended on-chip signals into differential signals for output contacts. In other implementations, the analog on-chip signals are always kept differential.

[0024] Figure 2 Additional implementation details of the illustrative serializer and deserializer are also shown. The deserializer implements the receive function of the retimer module, implements decision feedback equalization (“DFE”) or any other suitable equalization technique, including those employing discrete-time finite impulse response (“FIR”) filters with adjustable tap coefficients, such as linear equalization and partial response equalization.

[0025] Each deserializer includes a continuous-time linear equalizer (CTLE) to attenuate out-of-band noise and optionally provide some spectral shaping to amplify the high-frequency components of the received signal. An analog-to-digital converter (ADC) is provided to digitize the input signal, and a digital filter (also known as a feedforward equalizer or "FFE") performs further equalization to further shape the overall channel response of the system and minimize the impact of preamble inter-symbol interference on the current symbol. As part of the overall channel response shaping, the FFE can also be designed to shorten the channel response of the filtered signal while minimizing any accompanying noise enhancement. A decision feedback equalizer (DFE) subtracts the feedback signal before making symbol decisions to reduce the impact of trailing inter-symbol interference. A clock recovery (CR) module converts the equalization error (the difference between the symbol decision and the input of the symbol decision element) into a sampling clock for the ADC. A serial-to-parallel (S2P) module converts the sequence of symbol decisions into a parallel stream of digital symbols for buffering or processing at a lower clock rate.

[0026] Each illustrative serializer includes a parallel-to-serial (P2S) module that converts a parallelized stream of digital symbols into a sequence of channel symbols. An optional pre-equalizer (PRE) can be used to shape the signal spectrum to at least partially compensate for channel attenuation of the output signal. A digital-to-analog converter (DAC) uses a transmit clock to generate a retiming PCIe signal.

[0027] Although not explicitly shown here, it is anticipated that the filter can be parallelized, and the receiver enhanced with one or more level detectors to help determine the decision threshold and cumulative probability distribution of the signal at the upper and lower edges of the decision eye used for equalizing the signal. Implementation and configuration details for such features can be found in co-owned U.S. Patent 11,018,656, entitled “Multi-function level finder for SerDes,” published May 25, 2021, which is incorporated herein by reference.

[0028] Each channel further includes the aforementioned trained controller to coordinate the adaptation of the equalization parameters. The controller can apply any of the many suitable adaptive methods described in the open literature, including steepest descent, gradient descent, LMS, and exhaustive search, to optimize the coefficient values ​​of the FFE and optional DFE feedback filters. The PCIe specification provides two protocols for the controller: "preset" and "coefficients," to also optimize the pre-equalizer coefficient values ​​at the remote end of the communication link. Under the preset protocol, the controller selects from a set of registers, each containing preset coefficient values ​​for the entire set of pre-equalizer coefficients. While the preset method is relatively fast, the resulting equalizer performance is often suboptimal due to the limited range of pre-equalizer configurations suitable for the most common channel distributions. The coefficients approach provides independent tuning for each of the pre-equalizer coefficients, offering optimized performance at the cost of increased training time.

[0029] The pre-equalizer and FFE are each finite impulse response filters, producing an output sequence y that is a weighted sum of the most recent input values ​​x: The index *i* typically ranges from 0 to N-1, where N is the number of coefficients. However, in some implementations, the index can take negative values, for example, varying from -2 to N-3. In such cases, *i = 0* corresponds to the cursor position, *i > 0* corresponds to the position before or prior to the cursor, and *i < 0* corresponds to the position after the cursor, i.e., the subsequent cursor position. The coefficients *c1*, *c2*, *c3*, *c4*, *c5*, *c6*, *c7*, *c8*, *c9 ... -1 These correspond to the first front cursor position and the first back cursor position, respectively.

[0030] In one anticipated implementation, the FFE has three rear vernier coefficients, one vernier coefficient, and sixteen front vernier coefficients. Two of the front vernier coefficients can have adjustable positions relative to the vernier. The anticipated pre-equalizer has two rear vernier coefficients, one vernier coefficient, and one front vernier coefficient. For higher data rates, the number of coefficients can be expected to increase. It is observed here that most of the filter "energy" tends to concentrate near the vernier; that is, filter coefficients more than two taps away from the vernier position tend to be much smaller than the vernier coefficients. It can also be observed that the polarity of the first front and first rear vernier coefficients is opposite to the polarity of the vernier coefficients, which are generally considered positive. Due to this expectation, an "increment" in the first front or first rear vernier coefficient is an increase in the coefficient value, typically increasing the coefficient in the negative direction.

[0031] Pre-equalizer training can be significantly slower than deserializer equalization parameter training due to the communication overhead required for adapting the pre-equalizer coefficients. However, this paper anticipates employing an independent coefficient training method for pre-equalizer optimization, independent of pre-defined training methods. This coefficient training method benefits from a target optimization approach based on the faster-optimized values ​​of the receiver equalization parameters.

[0032] Here it was observed that, at a symbol rate of 32 GHz, the optimized FFE filter coefficients have typical first front vernier coefficient values ​​between 30% and 70% of the vernier coefficients and typical first back vernier coefficient values ​​between 10% and 50% of the vernier coefficients. These FFE coefficient thresholds can vary based on the symbol rate, channel specifications, and parameter settings of any continuous-time filter, but in any case, they can serve as a guide for the adaptive process used for the pre-equalizer coefficients.

[0033] Figure 3 This is a flowchart illustrating the equalizer training method that occurs during the training process as described in the PCIe specification. For each PCIe link, the upstream and downstream ports exchange ordered sets of training data to establish the operation. In box 302, the upstream port sends initial pre-equalizer coefficient values ​​to the downstream port. These initial values ​​can be default values, values ​​from a selected preset register, stored values ​​from previous operations, or any suitable set of starting values. In the absence of another starting point, both the front and rear cursor coefficients can be set to zero.

[0034] In box 304, the downstream port configures the pre-equalizer and begins transmitting the training data sequence at the desired symbol rate. Based on the received signal, the upstream port sets optimized receiver equalization parameters, including FFE and DFE coefficients, for a given pre-equalizer coefficient.

[0035] In box 306, the upstream port evaluates whether the optimized receiver equalization parameters provide acceptable performance, for example, below 10. -6 The error rate. If not, then in block 308, the upstream port compares the optimized FFE front and back cursor coefficients with a predetermined threshold. In a anticipated embodiment, the difference DIFFc is produced by subtracting the previous front cursor threshold from the magnitude of the first front cursor coefficient value of the FFE. +1 (or DIFF CP1). The difference DIFFc is generated by subtracting the upper cursor threshold from the value of the first cursor coefficient of FFE. -1(Or DIFF CM1). The differences can be compared to determine which coefficient exceeds the expected threshold to the greatest extent. If the first front cursor coefficient value exceeds the threshold to the greatest extent, then in box 310, the upstream port requests an increase in the magnitude of the first front cursor coefficient of the downstream port's pre-equalizer. Similarly, if the first back cursor coefficient value exceeds the threshold to the greatest extent, then in box 312, the upstream port requests an increase in the magnitude of the first back cursor coefficient of the downstream port's pre-equalizer.

[0036] It is expected that within a few iterations, the upstream port will find that sufficient performance has been achieved in box 306. In box 314, the upstream port can transmit its optimized FFE coefficient values ​​to the downstream port and obtain optimized pre-equalizer coefficients from the downstream port. Before the upstream port begins sending the training data sequence to the downstream port at the desired data rate, the upstream and downstream ports can apply these settings to their pre-equalizers and FFEs, respectively. In box 316, the downstream port optimizes its receiver equalization parameters.

[0037] In box 318, the downstream performance evaluation assesses whether the optimized receiver equalization parameters provide acceptable performance, for example, below 10. -6 The error rate. If not, then in block 320, the downstream port compares the optimized FFE front and back cursor coefficients with a predetermined threshold. In a anticipated embodiment, the difference DIFFc is produced by subtracting the previous front cursor threshold from the magnitude of the first front cursor coefficient value of the FFE. +1 (or DIFF CP1). The difference DIFFc is generated by subtracting the upper cursor threshold from the value of the first cursor coefficient of FFE. -1 (Or DIFF CM1). The differences can be compared to determine which coefficient exceeds the expected threshold to the greatest extent. If the first front cursor coefficient value exceeds the threshold to the greatest extent, then in box 322, the upstream port requests an increase in the magnitude of the first front cursor coefficient of the downstream port's pre-equalizer. Similarly, if the first back cursor coefficient value exceeds the threshold to the greatest extent, then in box 324, the upstream port requests an increase in the magnitude of the first back cursor coefficient of the upstream port's pre-equalizer.

[0038] It is expected that within a few iterations, the downstream port will find that sufficient performance has been achieved in box 318. In box 326, the upstream and / or downstream ports can store their optimized coefficient values ​​for reuse during subsequent startup processes for the link.

[0039] Once fully understanding the above disclosure, numerous alternatives, equivalents, and modifications will become apparent to those skilled in the art. For example, a PCIe link has been used in the foregoing description, but the principles disclosed herein also apply to other digital communication protocols provided for the use of pre-equalizers. The claims are intended to be interpreted as covering all such alternatives, equivalents, and modifications included within the scope of the appended claims.

Claims

1. An equalizer, comprising: A discrete-time finite impulse response ("FIR") filter, the discrete-time finite impulse response ("FIR") filter being configured to convert a received signal into a filtered signal; A decision element, the decision element being used to determine the channel symbols represented by the filtered signal; as well as Controller, the controller: Configured to adjust coefficients for the FIR filter based on the performance of the equalizer, the coefficients including a first back vernier coefficient; as well as It is configured to change the first post-verb coefficient of the pre-equalizer if the first post-verb coefficient of the FIR filter has a value exceeding a first threshold.

2. The equalizer according to claim 1, characterized in that, The performance is based on at least one of the filtered signal or the input signal to the decision element and the channel symbols.

3. The equalizer according to claim 1, characterized in that, The controller partially alters the first post-cursor coefficient of the pre-equalizer by sending a change request to the remote transmitter via an embedded reverse channel.

4. The equalizer according to claim 3, characterized in that, The change request is a request to increase the value of the first subsequent vernier coefficient.

5. The equalizer according to claim 1, characterized in that, The coefficients include a first front vernier coefficient, and the controller is configured to change the first front vernier coefficient of the pre-equalizer if the first front vernier coefficient has a value exceeding a second threshold.

6. The equalizer according to claim 5, characterized in that, The controller is further configured to iteratively adjust the coefficients and change the first rear vernier coefficient or the first front vernier coefficient until the performance reaches the target.

7. The equalizer according to claim 6, characterized in that, The controller is further configured to store coefficients for the FIR filter and the pre-equalizer for use as initial values ​​after power-on or reset.

8. An equilibrium method, comprising: The received signal is converted into a filtered signal using a discrete-time finite impulse response ("FIR") filter; Decision elements are used to determine the channel symbols represented by the filtered signal; The coefficients used for the FIR filter are adjusted based on the performance of the equalizer, the coefficients including a first back vernier coefficient; as well as If the first post-cursor coefficient of the FIR filter has a value exceeding the first threshold, then the first post-cursor coefficient of the pre-equalizer is changed.

9. The equalization method according to claim 8, characterized in that, The performance is based on at least one of the filtered signal or the input signal to the decision element and the channel symbols.

10. The equalization method according to claim 8, characterized in that, The controller partially alters the first post-cursor coefficient of the pre-equalizer by sending a change request to the remote transmitter via an embedded reverse channel.

11. The equalization method according to claim 10, characterized in that, The change request is a request to increase the value of the first subsequent vernier coefficient.

12. The equalization method according to claim 8, characterized in that, The coefficients include a first front vernier coefficient, and the controller is configured to change the first front vernier coefficient of the pre-equalizer if the first front vernier coefficient of the FIR filter has a value exceeding a second threshold.

13. The balancing method according to claim 12, characterized in that, The controller is further configured to iteratively adjust the coefficients of the FIR filter and change the first back vernier coefficient or the first front vernier coefficient of the pre-equalizer until the performance target is achieved.

14. The balancing method according to claim 13, characterized in that, The controller is further configured to store coefficients for the FIR filter and the pre-equalizer for use as initial values ​​after power-on or reset.

15. A system comprising: A remote port, the remote port having: A pre-equalizer, configured to convert a digital transmission signal into an equalized transmission signal; as well as A digital-to-analog converter, configured to convert the equalized transmitted signal into a channel signal; as well as Local port, the local port having: An analog-to-digital converter, configured to provide a digital received signal representing the channel signal; A discrete-time finite impulse response ("FIR") filter, the discrete-time finite impulse response ("FIR") filter being configured to convert the digital received signal into a filtered signal; A decision element, the decision element being used to determine the channel symbols represented by the filtered signal; as well as A local controller configured to adjust at least one coefficient of the FIR filter based on equalization performance, the local controller being further configured to change at least one corresponding coefficient of the pre-equalizer if the at least one coefficient of the FIR filter has an amount exceeding a first threshold.

16. The system according to claim 15, characterized in that, The local controller partially alters the at least one corresponding coefficient of the pre-equalizer by sending a change request to the controller of the remote port via an embedded reverse channel.

17. The system according to claim 16, characterized in that, The change request is a request to increase the value of the at least one corresponding coefficient.

18. The system according to claim 15, characterized in that, The at least one coefficient is a first front vernier coefficient for the FIR filter, and the at least one corresponding coefficient is a first front vernier coefficient for the pre-equalizer.

19. The system according to claim 18, characterized in that, The local controller is further configured to change the first back-cursor coefficients for the pre-equalizer if the first back-cursor coefficients for the FIR filter have a value exceeding a second threshold.

20. The system according to claim 15, characterized in that, The local controller is further configured to iteratively adjust the at least one coefficient for the FIR filter and change the at least one corresponding coefficient for the pre-equalizer until the performance target is achieved.

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