Ferroelectric semiconductor floating gate transistor and preparation method thereof

Abstract

The invention provides a ferroelectric semiconductor floating gate transistor. The ferroelectric semiconductor floating gate transistor sequentially comprises a floating gate layer, a tunneling layer and a channel layer from bottom to top, wherein the channel layer is made of a ferroelectric semiconductor material. The invention also provides a method for preparing the ferroelectric semiconductor floating gate transistor. The ferroelectric semiconductor floating gate transistor provided by the invention can realize multi-valued storage, and has reconfigurable three-terminal and two-terminal operation modes. In addition, the ferroelectric semiconductor floating gate transistor can also realize floating gate adjustable ferroelectric resistance change (FRS) and three-valued logic of optical and electric pulse mixed input, so that the function of the device is further expanded, and the ferroelectric semiconductor floating gate transistor is expected to be applied to memristors and memory logic.

Description

Technical Field

[0001] This invention belongs to the field of microelectronic device technology. Specifically, this invention relates to ferroelectric semiconductor floating-gate transistors and their fabrication methods. Background Technology

[0002] Storage technology plays a crucial role in the semiconductor industry and has made significant progress over the past few decades. Non-volatile memory (NVM), in particular, has become an indispensable part of numerous applications, from consumer electronics to data centers, due to its ability to retain data even when power is off. Since the invention of the floating-gate transistor (FGT) in 1967, silicon-based NVM (i.e., "flash memory") has been widely used and plays a key role in solid-state drives and enterprise-class storage due to its high speed, reliability, and low manufacturing cost. However, with the explosive growth of information, traditional silicon-based memory devices are facing bottlenecks in size reduction, such as the unavoidable dangling bond problem in ultra-thin silicon. Furthermore, the integration density of floating-gate transistors is limited by the required gate and its control circuitry, putting them at a disadvantage compared to current two-terminal random access memory (RAM). Additionally, achieving multi-value storage in floating-gate transistors is challenging because it is difficult to achieve moderate charge density within the floating gate using constant voltage pulses, and additional voltage pulses are needed to erase the charge.

[0003] As early as 1957, ferroelectric field-effect transistors (Fe-FETs) were studied as non-volatile memory. Their advantage lies in the ability to control the channel through a ferroelectric gate insulating layer, enabling non-destructive data reading. However, due to the strong depolarization field of traditional ferroelectric thin film materials and compatibility issues with silicon-based processes, coupled with the structural instability of ferroelectric field-effect transistors and charge diffusion between the semiconductor and the ferroelectric gate dielectric, ferroelectric field-effect transistors have not yet been commercialized.

[0004] Emerging two-dimensional materials exhibit a wealth of physical properties, such as metallicity, semiconductority, and insulation. Many of these materials are excellent ferroelectrics, exhibiting greater stability than traditional ferroelectric materials and even maintaining ferroelectric polarization at atomic-level thicknesses. The most important characteristic of two-dimensional materials is their atomic-level thickness and the absence of dangling bonds on their surface, allowing them to be stacked into various functional van der Waals (vdW) heterojunctions, potentially overcoming the shortcomings of traditional silicon-based non-volatile memories.

[0005] Currently, there are floating gate memories based on InSe (or MoS2) / h-BN / MLG van der Waals heterojunctions, which have achieved nanosecond-level ultra-high-speed erase and write and have a large on / off ratio (Nat Nanotechnol 2021, 16, 874., Nat Nanotechnol 2021, 16, 882.). Its disadvantages are: (1) high operating voltage of floating gate transistor; (2) single operating mode (three-terminal device, state erase and write depend on the gate); (3) difficult to achieve multi-value storage (it is difficult to achieve stable intermediate resistance state writing through constant voltage pulse, i.e., medium charge density in the floating gate, and an erase operation is required before writing the intermediate resistance state).

[0006] Therefore, there is an urgent need for a new type of non-volatile memory that can achieve multi-value storage and has reconfigurable three-terminal and two-terminal operation modes. Summary of the Invention

[0007] The purpose of this invention is to provide a ferroelectric semiconductor floating-gate transistor that can achieve multi-value storage and has reconfigurable three-terminal and two-terminal operating modes. In addition to functioning as a memory, the device configuration of this invention implements floating-gate adjustable ferroresistivity (FRS) and ternary logic with mixed photoelectric pulse inputs, enriching the device's functionality and enabling its use in in-memory computing architectures.

[0008] The above-mentioned objective of the present invention is achieved through the following technical solution.

[0009] In a first aspect, the present invention provides a ferroelectric semiconductor floating gate transistor, which comprises, from bottom to top: a floating gate layer, a tunneling layer, and a channel layer; wherein the channel layer is made of a ferroelectric semiconductor material.

[0010] The inventors of this application unexpectedly discovered that when ferroelectric semiconductor materials are used as the channel layer in floating gate transistors, the modulation effects of both ferroelectricity and floating gate on the channel resistance can be integrated into a single device without increasing the complexity of the floating gate transistor device, thereby achieving the characteristic of multi-value storage.

[0011] Preferably, in the ferroelectric semiconductor floating gate transistor of the present invention, the floating gate layer is composed of multiple layers of graphene and / or metal. The present invention does not particularly limit the metal used; it can be platinum.

[0012] Preferably, in the ferroelectric semiconductor floating gate transistor of the present invention, the tunneling layer is composed of at least one selected from hexagonal boron nitride, Al2O3, and HfO2. The present invention does not impose any particular limitation on the tunneling layer, which can be a common insulating dielectric material.

[0013] Preferably, in the ferroelectric semiconductor floating gate transistor of the present invention, the channel layer is composed of α-In2Se3.

[0014] Preferably, in the ferroelectric semiconductor floating gate transistor of the present invention, the thickness of the floating gate layer is 5 nm-10 nm. It should be noted that the number of layers in the multilayer graphene is determined by the thickness.

[0015] Preferably, in the ferroelectric semiconductor floating gate transistor of the present invention, the thickness of the tunneling layer is 10 nm-15 nm.

[0016] Preferably, in the ferroelectric semiconductor floating gate transistor of the present invention, the thickness of the channel layer is 15-50 nm.

[0017] Preferably, in the ferroelectric semiconductor floating gate transistor of the present invention, the ferroelectric semiconductor floating gate transistor further includes a gate dielectric layer located below the floating gate layer.

[0018] Preferably, in the ferroelectric semiconductor floating gate transistor of the present invention, the gate dielectric layer is composed of SiO2.

[0019] Preferably, in the ferroelectric semiconductor floating gate transistor of the present invention, the ferroelectric semiconductor floating gate transistor further includes a control gate located below the gate dielectric layer.

[0020] Preferably, in the ferroelectric semiconductor floating gate transistor of the present invention, the control gate is made of Si(P) ++ It is composed of a silicon (P) and / or a metal substrate; wherein, Si (P) ++ () refers to p-type heavily doped Si. This invention does not impose any particular limitation on the control gate; any metallic conductive material can be used as the gate.

[0021] Preferably, in the ferroelectric semiconductor floating gate transistor of the present invention, the ferroelectric semiconductor floating gate transistor further includes a source and a drain located at both ends of the channel layer.

[0022] In a second aspect, the present invention provides a method for preparing the ferroelectric semiconductor floating-gate transistor of the present invention, which includes the following steps:

[0023] (1) The materials constituting the channel layer, tunneling layer and floating grid layer are separated by mechanical stripping method to obtain the thin material of the channel layer, the thin material of the tunneling layer and the thin material of the floating grid layer;

[0024] (2) The floating gate layer thin film material, the tunneling layer thin film material and the channel layer thin film material are sequentially transferred and stacked on the gate dielectric layer to obtain a channel layer / tunneling layer / floating gate layer heterojunction;

[0025] (3) Optionally, source and drain electrodes are prepared for the channel layer in the heterojunction using standard microfabrication procedures.

[0026] In some embodiments of the present invention, the method of the present invention includes the following steps:

[0027] (1) α-In2Se3, hexagonal boron nitride and graphite crystals were separated by mechanical exfoliation to obtain α-In2Se3 thin-layer material, hexagonal boron nitride thin-layer material and multilayer graphene thin-layer material;

[0028] (2) The multilayer graphene thin film material, hexagonal boron nitride thin film material and α-In2Se3 thin film material are sequentially transferred and stacked on the gate dielectric layer to obtain α-In2Se3 / hexagonal boron nitride / multilayer graphene heterojunction;

[0029] (3) Optionally, source and drain electrodes are prepared for the α-In2Se3 channel in the heterojunction using standard microfabrication procedures.

[0030] The present invention has the following beneficial effects:

[0031] 1. Implement multi-valued non-volatile storage

[0032] Existing non-volatile memories, including floating-gate transistors and ferroelectric field-effect transistors, still face certain challenges in multi-value storage. For example, it is difficult to program a constant, moderate charge density within the floating gate or a moderate ferroelectric polarization in the ferroelectric gate dielectric using a fixed voltage pulse; and a large erase voltage is required to reset the device to its initial state each time state programming is performed. In the ferroelectric semiconductor floating-gate transistor of this invention, it is not necessary to reset the device to its initial state. A smaller operating voltage pulse can be used to control the ferroelectric polarization direction of the α-In2Se3 channel without affecting the charge density within the floating gate, achieving switching of moderate channel resistance states. Furthermore, by experimentally testing a voltage pulse of appropriate amplitude to make the ferroelectric polarization reverse operation in a polarization saturation state, a constant channel resistance value can be obtained.

[0033] 2. Implement reconfigurable three-terminal and two-terminal operations.

[0034] Existing non-volatile memories, including floating-gate transistors and ferroelectric field-effect transistors, mostly operate in a three-terminal mode. This means that the channel resistance is programmed by applying a voltage pulse to the gate, and the channel conduction state is read by applying a voltage between the source and drain electrodes. The gate (including the gate dielectric and gate electrode) of such devices often occupies a large space and requires additional gate control circuitry, resulting in lower integration density compared to two-terminal random access memory (RAM) that only utilizes the source-drain electrodes. The device of this invention features reconfigurable three-terminal and two-terminal operating modes, and can achieve 2-bit multi-value storage in both modes, increasing the device's operational flexibility and applicability to various circuit scenarios.

[0035] Specifically, this invention utilizes an α-In₂Se₃ / h-BN / MLG two-dimensional van der Waals heterojunction to construct a ferroelectric semiconductor floating-gate transistor. Testing has demonstrated that this device possesses reconfigurable three-terminal and two-terminal operating modes, significantly improving its operational flexibility. Furthermore, the two-terminal operating mode offers higher integration density compared to the traditional three-terminal operating mode. Regardless of whether the device operates in three-terminal or two-terminal mode, it can achieve 2-bit multi-value storage. This achievement is attributed to the integration of ferroelectricity and the floating gate in the device, and fully utilizes the simultaneous in-plane and out-of-plane ferroelectric polarization of α-In₂Se₃. The implementation of multi-value storage effectively enhances the device's storage density.

[0036] 3. Enriched device functionality

[0037] Existing non-volatile memories, including floating-gate transistors and ferroelectric field-effect transistors, are typically used only as non-volatile memories. Our proposed device configuration, in addition to functioning as a memory, implements tunable ferroresistivity change (FRS) with a floating gate and ternary logic with mixed optical and electrical pulse inputs, enriching the device's functionality and potentially enabling its use in in-memory computing architectures. By controlling the charge density within the floating gate, the device of this invention can achieve effective regulation of the channel ferroresistivity change (FRS), providing insights into the construction of novel memristors. Furthermore, the device of this invention implements ternary logic with mixed optical and electrical pulse inputs, performing logic computation within the memory device, and holds promise for applications in the field of in-memory computing.

[0038] 4. Providing insights into the construction of future non-volatile memories.

[0039] This invention is the first to use two-dimensional ferroelectric semiconductor materials as the channel of a floating-gate transistor, and the device is constructed based on an α-In2Se3 / h-BN / MLG van der Waals heterojunction. This invention integrates ferroelectric properties into the floating-gate transistor, bringing new degrees of control freedom to traditional floating-gate transistors and providing important insights for the construction of future non-volatile memories. This invention can be applied to the fields of two-dimensional semiconductor device physics, microelectronics, non-volatile memory technology, flash memory technology, and in-memory computing. Potential applications include the construction of multi-valued non-volatile memories, non-volatile memories with multiple operating modes, novel floating-gate transistors, memristors, and in-memory computing devices. Attached Figure Description

[0040] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings, wherein:

[0041] Figure 1 The device structure and optical micrograph of a ferroelectric semiconductor floating gate transistor according to a specific embodiment of the present invention are shown.

[0042] Figure 2 The test results of the transfer curve of the ferroelectric semiconductor floating gate transistor of Embodiment 1 of the present invention are shown;

[0043] Figure 3 The test results of the output curve of the ferroelectric semiconductor floating gate transistor of Embodiment 1 of the present invention are shown;

[0044] Figure 4 This invention illustrates the implementation of multi-value storage in three-terminal operation mode of the ferroelectric semiconductor floating gate transistor of Embodiment 1 of the present invention and its storage performance;

[0045] Figure 5 This invention illustrates the implementation of multi-value storage in two-terminal operation mode of the ferroelectric semiconductor floating gate transistor of Embodiment 1 of the present invention and its storage performance;

[0046] Figure 6 The ferroelectric semiconductor floating gate transistor of Embodiment 1 of the present invention exhibits a channel ferroresistance variation with adjustable charge within the floating gate;

[0047] Figure 7 This illustrates the ternary logic operation of the ferroelectric semiconductor floating gate transistor with mixed optical and electrical pulse inputs according to Embodiment 1 of the present invention. Detailed Implementation

[0048] The present invention will be further described in detail below with reference to specific embodiments. The embodiments given are only for illustrating the present invention and are not intended to limit the scope of the present invention.

[0049] Example 1

[0050] This embodiment uses 300nm SiO2 with a SiO2 / Si (P) ratio. ++ A novel device with an α-In2Se3 / h-BN / MLG structure was constructed on a substrate, in which the two-dimensional ferroelectric semiconductor α-In2Se3 serves as the channel, h-BN as the tunneling layer of the floating gate device, MLG as the floating gate layer, SiO2 as the gate dielectric for controlling the floating gate, and Si(P) ++ Then it serves as the control gate of the device.

[0051] The device fabrication and testing processes are as follows:

[0052] (1) α-In2Se3, h-BN, and graphite crystals were repeatedly dissociated using 3M tape and then mechanically exfoliated onto polydimethylsilane (PDMS) to obtain α-In2Se3, h-BN, and graphene thin-layer materials with thicknesses of 35 nm, 10 nm, and 5 nm, respectively. Using a transfer stage, multilayer graphene (MLG), h-BN, and α-In2Se3 thin layers were sequentially transferred and stacked on a SiO2 / Si(P++) substrate to obtain an α-In2Se3 / h-BN / MLG heterojunction.

[0053] (2) Source and drain electrodes were fabricated for the α-In2Se3 channel in the heterojunction using a standard microfabrication process. The main steps included spin-coating of electron resist (polymethyl methacrylate, PMMA), baking, electron beam lithography, metal deposition, and lift-off. The fabrication of the ferroelectric semiconductor floating-gate transistor was completed. Its structural schematic diagram and optical microscope images are shown below. Figure 1 As shown in a and b.

[0054] Electrode preparation process:

[0055] i. First, PMMA 950A5 is spin-coated onto the SiO2 / Si substrate with an α-In2Se3 / h-BN / MLG heterojunction, and then baked at 150℃ for 2 min at a speed of 4000 r / s to allow the solvent to evaporate;

[0056] ii. Expose the structure obtained in step (i) according to the pre-designed electrode pattern using an electron beam exposure system (RAITH 1500);

[0057] iii. Subsequently, the sample was immersed in the developer (methyl isobutyl ketone MIBK: isopropanol IPA = 1:3) and the fixer (IPA) for 40 s and 30 s respectively to complete the development and fixing process;

[0058] iv. Subsequently, a Ti / Au (3 nm / 75 nm) metal thin film is deposited on the structure obtained in step (iii) using electron beam evaporation;

[0059] v. After metal deposition is completed, the substrate is immersed in acetone at 55°C for dissolution, and finally the device fabrication is completed.

[0060] It should be noted that the term V in the following diagram... DS V represents the voltage applied between the source and drain terminals. CG Indicates the voltage applied to the control gate; l DS This represents the current flowing through the device channel.

[0061] Performance testing

[0062] (i) Testing of the basic transfer curve of the device

[0063] To test the transfer characteristic curves of ferroelectric semiconductor floating-gate transistors, we followed... Figure 2 The circuit diagram shown in Figure a was tested, wherein a constant read voltage V was applied between the source current electrodes. DS = 0.1 V; with Si(P ++ The substrate serves as the control gate, and a scan voltage V is applied that changes from negative to positive and back to negative. CG The maximum gate scan voltage V of the device was obtained. CG，max The double-scan transfer curves for values ​​less than 10 V and greater than 10 V are shown below. Figure 2 As shown in Figures b and c, the device exhibits a clockwise storage window in both ranges, which further enables non-volatile storage of the channel resistance state. Figure 2 The d-plot shows the transition curve from the double-scan curve ( Figure 2 The storage window size and the switching ratio of the channel current at gate voltage 0, extracted from figures b and c, are related to V. CG，max The relationship between the changes in V can be seen from the device's performance in V. CG，max = 10 V shows a clear change before and after, V CG，max When V < 10 V, as V CG，max As V increases, the current switching ratio and storage window gradually saturate; while when V CG，max When V > 10 V, as V CG，max As the voltage increases, the current switching ratio and the storage window continue to increase. This phenomenon indicates that the device... CG，max For values ​​less than and greater than 10 V, the storage window is derived from V respectively. CG Modulation of the out-of-plane ferroelectric polarization of α-In₂Se₃ and modulation of the charge within the floating gate. In summary, it can be seen that in three-terminal operation mode, by applying positive and negative VB values ​​of less than 10 V and greater than 10 V to the device control gate, respectively... CGThe pulse can respectively modulate the out-of-plane ferroelectric polarization of α-In2Se3 and the charge state inside the floating gate, thereby realizing 2-bit multi-value storage.

[0064] (ii) Testing of the device's basic output curve

[0065] To test the output characteristic curve of the ferroelectric semiconductor floating-gate transistor, we followed... Figure 3 The circuit diagram shown in Figure a is tested, wherein a scanning voltage V is applied between the source current electrodes from negative to positive and back to negative. DS The maximum gate scan voltage V of the device was obtained. DS，max The dual-scan output curves for values ​​less than 10 V and greater than 10 V are shown below. Figure 3 As shown in Figures b and c, the device exhibits a storage window in both ranges, enabling further non-volatile storage of the channel resistance state. Figure 3 The d-plot is the output curve from the double scan ( Figure 3 The channel current extracted from the data in figures b and c is used to read the voltage V. DS The switching ratio at =0.1 V changes with V DS，max The relationship between the changes in V can be seen from the device's performance. DS，max = 10 V shows a clear change before and after, V DS，max When V < 10 V, as V DS，max As V increases, the current switching ratio gradually saturates; while when V DS，max When V > 10 V, as V CG，max As the voltage increases, the current switching ratio continues to increase. This phenomenon indicates that the device... DS，max For values ​​less than and greater than 10 V, the storage window is derived from V respectively. DS Modulation of in-plane ferroelectric polarization of α-In₂Se₃ and modulation of charge within the floating gate. In summary, it can be concluded that, in two-terminal operation mode, by applying positive and negative VT values ​​up to 10 V and greater than 10 V... DS The pulse can respectively modulate the in-plane ferroelectric polarization of α-In2Se3 and the charge state in the floating gate, and can also realize 2-bit multi-value storage.

[0066] (iii) Implementation of multi-value storage under three-terminal operation mode

[0067] like Figure 4 As shown in Figure a, V is applied to the control gate of the device. CG After a voltage pulse of ±10 V and a half-maximum width (FWHM) of 1 s, a moderately high resistance state modulated by out-of-plane ferroelectric polarization is obtained. For example... Figure 4 As shown in Figure b, a V is applied to the control gate of the device. CGAfter a voltage pulse of ±20 V and FWHM = 160 ns, a high-resistivity state controlled by a floating gate is obtained. This enables four resistive states and 2-bit multi-value storage. Figure 4 The c and d plots show the durability and retention of the device's resistance state switching, respectively, with the vertical axis representing the channel current read in four different resistance states.

[0068] (iv) Implementation of multi-value storage in two-end operation mode

[0069] like Figure 5 As shown in Figure a, V is applied to the source-drain of the device. DS After a voltage pulse of ±6 V and FWHM = 1 s, a moderately high resistance state modulated by in-plane ferroelectric polarization is obtained. For example... Figure 5 As shown in Figure b, a V is applied to the control gate of the device. DS After a voltage pulse of ±13V and FWHM = 10 ms, a high-resistivity state controlled by a floating gate is obtained. This enables four resistive states and 2-bit multi-value storage. Figure 5 The c and d plots show the durability and retention of the device's resistance state switching, respectively, with the vertical axis representing the channel current read in four different resistance states.

[0070] (v) Floating grid adjustable ferroresistivity transformer (FRS)

[0071] By applying a series of voltage pulses to the gate, for example, applying a single V CG = -20 V, FWHM = 160ns pulse fills the floating gate with holes, followed by applying different numbers of V CG A pulse of +18 V and FWHM = 160 ns causes the charge stored in the floating gate to gradually transition from holes to electrons. This process leads to the gradual depletion of electron carriers in the α-In2Se3 channel, causing the carriers to transition from thermal field emission to thermionic emission via the Schottky barrier. Therefore, the carriers become sensitive to the height of the Schottky barrier modulated by in-plane ferroelectric polarization, such as... Figure 6 As shown, the ferroresistivity change (FRS), i.e., the hysteresis window, of its dual-scan output curve gradually increases.

[0072] (vi) Implementation of ternary logic for photoelectric pulse input

[0073] like Figure 7 As shown in Figure a, Q1: Applying V to the device CGAfter a +20 V pulse, the device is in a high-resistance state, denoted as logic "0"; Q2: Subsequently, after applying a 532 nm laser irradiation to the device, the device is in an intermediate-resistance state, denoted as logic "0.5"; Q3: After applying a V pulse to the device... CG After a -20 V pulse, the device is in a low-resistance state, denoted as logic "1"; Q4: Subsequently, after applying a 532 nm laser irradiation to the device, it still maintains a low-resistance state, denoted as logic "1". Therefore, the ternary logic of the photoelectric pulse input can be obtained, and its truth table is as follows: Figure 7 As shown in Figure b. Figure 7 Figure c shows the timing diagram of the device after 10 logic operation cycles, and the device can still work normally.

[0074] In summary, the core of this invention is the use of a semiconductor with ferroelectric properties as the channel of a floating-gate transistor. An example of this device was successfully constructed using an α-In₂Se₃ / h-BN / MLG two-dimensional material heterojunction. Electrical testing revealed that the device can achieve reconfigurable three-terminal and two-terminal operation modes, and can realize 2-bit multi-valued storage in each mode. Furthermore, the device can also implement tunable ferroresistivity change (FRS) of the floating gate and ternary logic with mixed inputs of optical and electrical pulses, further expanding its functionality and promising applications in memristors and in-memory logic.

Claims

1. A ferroelectric semiconductor floating-gate transistor, comprising, from bottom to top: The structure comprises a floating gate layer, a tunneling layer, and a channel layer; wherein the channel layer is composed of a ferroelectric semiconductor material.

2. The ferroelectric semiconductor floating gate transistor according to claim 1, wherein, The floating grid layer is composed of multiple layers of graphene and / or metal; Preferably, the tunneling layer is composed of at least one selected from hexagonal boron nitride, Al2O3, and HfO2; Preferably, the channel layer is composed of α-In2Se3.

3. The ferroelectric semiconductor floating gate transistor according to claim 1, wherein, The thickness of the floating gate layer is 5 nm-10 nm.

4. The ferroelectric semiconductor floating gate transistor according to claim 1, wherein, The thickness of the tunneling layer is 10 nm-15 nm.

5. The ferroelectric semiconductor floating gate transistor according to claim 1, wherein, The thickness of the channel layer is 15-50 nm.

6. The ferroelectric semiconductor floating gate transistor according to claim 1, wherein, The ferroelectric semiconductor floating gate transistor also includes a gate dielectric layer located below the floating gate layer; Preferably, the gate dielectric layer is composed of SiO2.

7. The ferroelectric semiconductor floating-gate transistor according to claim 6, wherein, The ferroelectric semiconductor floating gate transistor also includes a control gate located below the gate dielectric layer; Preferably, the control gate is made of Si(P) ++ It consists of a metal substrate and / or a metal base.

8. The ferroelectric semiconductor floating gate transistor according to claim 1, wherein, The ferroelectric semiconductor floating gate transistor also includes a source and a drain located at opposite ends of the channel layer.

9. A method for fabricating a ferroelectric semiconductor floating-gate transistor according to any one of claims 1-8, comprising the following steps: (1) The materials constituting the channel layer, tunneling layer and floating grid layer are separated by mechanical stripping method to obtain the thin material of the channel layer, the thin material of the tunneling layer and the thin material of the floating grid layer; (2) The floating gate layer thin film material, the tunneling layer thin film material and the channel layer thin film material are sequentially transferred and stacked on the gate dielectric layer to obtain a channel layer / tunneling layer / floating gate layer heterojunction; (3) Optionally, source and drain electrodes are prepared for the channel layer in the heterojunction using standard microfabrication procedures.

10. The method according to claim 9, wherein, The method includes the following steps: (1) α-In2Se3, hexagonal boron nitride and graphite crystals were separated by mechanical exfoliation to obtain α-In2Se3 thin-layer material, hexagonal boron nitride thin-layer material and multilayer graphene thin-layer material; (2) The multilayer graphene thin film material, hexagonal boron nitride thin film material and α-In2Se3 thin film material are sequentially transferred and stacked on the gate dielectric layer to obtain α-In2Se3 / hexagonal boron nitride / multilayer graphene heterojunction; (3) Optionally, source and drain electrodes are prepared for the α-In2Se3 channel in the heterojunction using standard microfabrication procedures.

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