Pixel unit and manufacturing method thereof

Abstract

The invention discloses a pixel unit and a manufacturing method of the pixel unit. The pixel unit comprises a semiconductor substrate; a photoelectric conversion region in the semiconductor substrate; vertical transfer gates each extending into the semiconductor substrate from the first surface of the semiconductor substrate toward the photoelectric conversion region; the projection contour of the vertical transmission gate on the first surface comprises any one of a rectangle, an ellipse and a dot matrix rectangle. According to the invention, the vertical transmission grids extend from the first surface of the semiconductor substrate to the photoelectric conversion region, so that the projection outlines of the vertical transmission grids on the first surface are annularly connected with the PD connection region, the connection region is enlarged, and points with maximum potential values can be connected with each other. A linear path for connecting charge transmission with the maximum potential value is constructed, electron extraction distributed in a PD area is increased, charges detained in the PD are reduced, and the image trailing phenomenon is avoided.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and in particular to a pixel unit and a method for manufacturing a pixel unit. Background Technology

[0002] In the prior art, an image sensor is a semiconductor device used to convert optical signals into electrical signals. For example, an image sensor can be a complementary metal-oxide-semiconductor (CMOS) image sensor.

[0003] Typically, a CMOS image sensor can include multiple pixel units, each of which can include a photodiode (PD). Incident light passes through the PD in each pixel unit, generating a charge. The charge generated in the PD can be transferred to the floating diffusion region (FD) via a transmission transistor (TX). Ideally, all the charge generated in the PD should be transferred to the FD. However, in reality, factors such as insufficient transmission gate (TG) voltage, excessive charge under strong light, or uneven potential distribution causing the suction force on electrons in the PD region far from the TX to gradually weaken, preventing more charge from being transferred to the FD, can lead to some charge remaining in the PD. Consequently, the charge of the current frame is transferred during the transmission of the next frame, resulting in the next frame retaining information from the current frame and causing image trailing.

[0004] Therefore, how to transfer more charge to FD is an important research topic to solve the image trailing problem in existing technologies. Summary of the Invention

[0005] This application provides a pixel unit and a method for manufacturing the pixel unit, so as to transfer more charge to the FD and solve the problem of image trailing in the prior art.

[0006] In a first aspect, embodiments of this application provide a pixel unit, including:

[0007] Semiconductor substrate;

[0008] The photoelectric conversion region is located in the semiconductor substrate;

[0009] The vertical transmission gates extend from the first surface of the semiconductor substrate into the photoelectric conversion region and into the semiconductor substrate; the projection outline of the vertical transmission gate on the first surface includes any one of the shapes of rectangle, ellipse, and lattice rectangle.

[0010] This application sets the vertical transmission gates to extend from the first surface of the semiconductor substrate to the photoelectric conversion region. When the projected outline of the vertical transmission gate on the first surface includes any shape among rectangle, ellipse, and dot matrix rectangle, the transmission gate constructed by the vertical transmission gate is connected to the PD connection region in a ring, making the connection region larger. As a result, each point with the maximum potential value can be connected to each other, constructing a straight path for charge transport connected to the maximum potential value. This can increase the electron extraction force distributed in the PD region, reduce the charge stuck in the PD, and avoid image trailing.

[0011] In one alternative implementation, the projection profile of the vertical transmission gate on the first surface at least partially overlaps with the projection profile of the photoelectric conversion region on the first surface.

[0012] This application sets the relationship between the vertical transmission gate and the projection contour of the PD on the first surface to be partially overlapping, so that the transmission gate constructed by the vertical transmission gate is connected to the PD connection area in a ring. In this way, each point with the maximum potential value can be connected to each other, constructing a straight path for charge transport connected to the maximum potential value, reducing the charge stuck in the PD and avoiding image trailing.

[0013] In one optional implementation, the pixel unit further includes:

[0014] The semiconductor substrate has a well region and a floating diffusion region, both of which are disposed adjacent to the first surface of the semiconductor substrate. The floating diffusion region is spatially separated from the vertical transmission gate. The doping type of the well region is different from that of the photoelectric conversion region, while the doping type of the floating diffusion region is the same as that of the photoelectric conversion region.

[0015] This application sets the positional relationship between the well region and the floating diffusion region and the vertical transmission gate in the semiconductor substrate, and sets the relationship between the doping types of the well region, the floating diffusion region and the photoelectric conversion region, respectively. This makes the transmission gate constructed by the vertical transmission gate larger and the PD connection area larger, increases the electron pumping force distributed in the PD region, reduces the charge stuck in the PD, and avoids image trailing.

[0016] In one optional implementation, the pixel unit further includes:

[0017] A horizontal transmission gate is located on a first surface of the semiconductor substrate, and the horizontal transmission gate is electrically connected to each of the vertical transmission gates.

[0018] This application can further enhance the electronic pumping force distributed in the PD region by simultaneously setting multiple vertical and horizontal transmission gates in a pixel unit, reduce the charge retained in the PD, and avoid image trailing.

[0019] In one alternative embodiment, the projection profile of the horizontal transmission gate on the first surface lies within the projection profile of the vertical transmission gate on the first surface.

[0020] This application sets the positional relationship between the horizontal and vertical transmission gates, making the transmission gate jointly constructed by the horizontal and vertical transmission gates larger and the PD connection area larger. The electron pumping force distributed in the PD area is stronger, reducing the charge retained in the PD and avoiding image trailing.

[0021] In one optional implementation, the pixel unit further includes:

[0022] An impurity region is located between the floating diffusion region and the vertical transmission gate closest to the floating diffusion region, and the doping type of the impurity region is the same as that of the floating diffusion region.

[0023] This application, by setting the positional relationship of the impurity regions in the semiconductor substrate and setting the doping type of the impurity regions, can reasonably design the positional relationship of multiple vertical transport gates and the charge transport path relationship between multiple vertical transport gates and FD.

[0024] In one alternative implementation, the doping concentration of the impurity region is less than or equal to the doping concentration of the floating diffusion region.

[0025] This application improves pixel unit performance by setting the doping concentration relationship between the impurity region and the floating diffusion region, thereby making the voltage more stable during charge transport.

[0026] In one alternative embodiment, the vertical transmission gate extends 2.5µm-3µm in the semiconductor substrate.

[0027] This application, by setting the numerical value of the extension length of the vertical transmission gate in the semiconductor substrate, can make the transmission gate constructed by the vertical transmission gate and the PD connection area reasonably distributed, reduce the charge remaining in the PD, and avoid image trailing.

[0028] Secondly, embodiments of this application provide a method for manufacturing a pixel unit, the method comprising:

[0029] A semiconductor substrate is provided, and trenches are etched on a first surface of the semiconductor substrate according to a first specified shape; the first specified shape includes any one of a rectangle, an ellipse, and a lattice rectangle.

[0030] A dielectric layer and a conductive layer are sequentially filled into the trench to form a vertical transmission gate, and the projection profile of the vertical transmission gate on the first surface is the first specified shape.

[0031] Thirdly, embodiments of this application provide a method for manufacturing a pixel unit, the method comprising:

[0032] A semiconductor substrate is provided, and trench etching is performed on a first surface of the semiconductor substrate according to a first specified shape, wherein the first specified shape includes any one of a rectangle, an ellipse, and a lattice rectangle.

[0033] After the trench is sequentially filled with a dielectric layer and a conductive layer, it is etched again according to the second specified shape to remove the portion of the conductive layer outside the trench, forming a horizontal transmission gate on the first surface. The conductive layer in the trench forms a vertical transmission gate, and the projection outline of the vertical transmission gate on the first surface is the first specified shape.

[0034] Fourthly, embodiments of this application provide an image sensor, the image sensor comprising:

[0035] The system comprises multiple pixel units, an analog-to-digital converter (ADC), and an accumulator; the ADC is connected to each pixel unit and the accumulator, respectively.

[0036] Each pixel unit is a pixel unit as described in any of the first aspects, and the plurality of pixel units are arranged in an array;

[0037] The plurality of pixel units are used to generate electrical signals and send the generated electrical signals to the analog-to-digital converter;

[0038] The analog-to-digital converter is used to convert the electrical signal into a digital signal and send the digital signal to the accumulator;

[0039] The accumulator is used to perform addition and accumulation on the digital signal to obtain the image signal.

[0040] In one optional implementation, the image sensor further includes:

[0041] A line decoder and a timing controller; the line decoder is connected to each pixel unit and the timing controller, and the timing controller is also connected to the mode converter and the accumulator.

[0042] The timing controller is used to send a first control signal to the line decoder;

[0043] The row decoder is configured to send a pixel driving signal to the pixel unit of a specified row among the plurality of pixel units according to the first control signal;

[0044] The plurality of pixel units are specifically used to generate the electrical signal according to the pixel driving signal;

[0045] The timing controller is also used to send a second control signal to the analog-to-digital converter and a third control signal to the accumulator;

[0046] The analog-to-digital converter is specifically used to convert the electrical signal corresponding to the pixel unit in a specified row of the plurality of pixel units into a digital signal according to the second control signal;

[0047] The accumulator is specifically used to perform addition and accumulation on the digital signal according to the third control signal to obtain the image signal.

[0048] Fifthly, embodiments of this application provide an apparatus for manufacturing a pixel unit, the apparatus comprising:

[0049] A first shape etching module is used to provide a semiconductor substrate and perform trench etching on a first surface of the semiconductor substrate according to a first specified shape, wherein the first specified shape includes any one of a rectangle, an ellipse, or a dot matrix rectangle.

[0050] The first pixel unit determination module is used to sequentially fill the trench with a dielectric layer and a conductive layer to form a vertical transmission gate, wherein the projection contour of the vertical transmission gate on the first surface is the first specified shape.

[0051] Sixthly, embodiments of this application provide an apparatus for manufacturing a pixel unit, the apparatus comprising:

[0052] A first shape etching module is used to provide a semiconductor substrate and perform trench etching on a first surface of the semiconductor substrate according to a first specified shape, wherein the first specified shape includes any one of a rectangle, an ellipse, or a dot matrix rectangle.

[0053] The second pixel unit determination module is used to sequentially fill the trench with a dielectric layer and a conductive layer, and then etch it again according to the second specified shape to remove the part of the conductive layer located outside the trench, form a horizontal transmission gate on the first surface, and form a vertical transmission gate in the conductive layer in the trench. The projection outline of the vertical transmission gate on the first surface is the first specified shape.

[0054] The technical effects that may be achieved by the pixel unit manufacturing methods disclosed in the second and third aspects above, the image sensor disclosed in the fourth aspect, and the pixel unit manufacturing apparatus disclosed in the fifth and sixth aspects, can be referred to the above description of the technical effects that can be achieved by the various possible solutions in the first aspect, and will not be repeated here.

[0055] Other features and advantages of this application will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the application. The objectives and other advantages of this application may be realized and obtained by means of the structures particularly pointed out in the written description, claims, and drawings. Attached Figure Description

[0056] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0057] Figure 1a A schematic diagram of the circuit structure of a pixel unit provided for related technologies;

[0058] Figure 1b A schematic diagram of the cross-sectional structure of a pixel unit provided for related technologies;

[0059] Figure 1c A top view structural diagram of a pixel unit provided for related technologies;

[0060] Figure 2a This is a schematic diagram of the cross-sectional structure of a pixel unit provided in an embodiment of this application;

[0061] Figure 2b This is a top view structural diagram of a pixel unit provided in an embodiment of this application;

[0062] Figure 3a The vertical transmission gate 202-1, vertical transmission gate 202-2, ..., vertical transmission gate 202-n provided in the embodiments of this application are constructed in an elliptical shape.

[0063] Figure 3b A schematic diagram showing the shape of the vertical transmission gate 202-1, vertical transmission gate 202-2, ..., vertical transmission gate 202-n as a dot matrix provided in the embodiments of this application;

[0064] Figure 3c This is a schematic diagram of the cross-sectional structure of a pixel unit provided in an embodiment of this application;

[0065] Figure 4 This is a schematic diagram of the cross-sectional structure of a pixel unit provided in an embodiment of this application;

[0066] Figure 5a This is a schematic diagram of the cross-sectional structure of a pixel unit provided in an embodiment of this application;

[0067] Figure 5b This is a schematic diagram of the cross-sectional structure of a pixel unit provided in an embodiment of this application;

[0068] Figure 6 This is a schematic diagram of the cross-sectional structure of a pixel unit provided in an embodiment of this application;

[0069] Figure 7 A schematic diagram illustrating the workflow of a pixel unit fabrication method provided in this application embodiment;

[0070] Figure 8 A schematic diagram illustrating the manufacturing process of a pixel unit provided in an embodiment of this application;

[0071] Figure 9 A schematic diagram illustrating the workflow of a pixel unit fabrication method provided in this application embodiment;

[0072] Figure 10a A schematic diagram illustrating the manufacturing process of a pixel unit provided in an embodiment of this application;

[0073] Figure 10b A schematic diagram of the integral forming of the conductive layer of the horizontal transmission gate 203 and the vertical transmission gate 202-1, vertical transmission gate 202-2, ..., vertical transmission gate 202-n after etching, provided in an embodiment of this application;

[0074] Figure 10c This is a schematic diagram showing that the vertical transmission gate 202-1, vertical transmission gate 202-2, ..., vertical transmission gate 202-n provided in the embodiments of this application are rectangular in shape, and the vertical transmission gate 202-1, vertical transmission gate 202-2, ..., vertical transmission gate 202-n and horizontal transmission gate 203 are integrally formed.

[0075] Figure 10d The vertical transmission gate 202-1, vertical transmission gate 202-2, ..., vertical transmission gate 202-n provided in the embodiments of this application are constructed in an elliptical shape, and the vertical transmission gate 202-1, vertical transmission gate 202-2, ..., vertical transmission gate 202-n and horizontal transmission gate 203 are integrally formed.

[0076] Figure 10eThis is a schematic diagram showing that the vertical transmission gate 202-1, vertical transmission gate 202-2, ..., vertical transmission gate 202-n provided in the embodiments of this application are constructed in the shape of a dot matrix rectangle, and the vertical transmission gate 202-1, vertical transmission gate 202-2, ..., vertical transmission gate 202-n and horizontal transmission gate 203 are integrally formed.

[0077] Figure 11 This is a schematic diagram of the structure of an image sensor provided in an embodiment of this application;

[0078] Figure 12 This is a schematic diagram of the structure of an image sensor provided in an embodiment of this application;

[0079] Figure 13 A schematic diagram of a pixel unit fabrication apparatus provided in an embodiment of this application;

[0080] Figure 14 This is a schematic diagram of a pixel unit fabrication apparatus provided in an embodiment of this application. Detailed Implementation

[0081] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0082] It should be noted that the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0083] An image sensor is a semiconductor device used to convert optical signals into electrical signals. For example, an image sensor can be a CMOS image sensor. A CMOS image sensor can include multiple pixel units, such as... Figure 1aAs shown, each pixel unit may include a semiconductor substrate 101, which includes a P-type photodiode (P-PD) 101-1 and an FD 101-2. A TG 102 is disposed on the first surface of the semiconductor substrate 101. The FD 101-2 is connected to a reset transistor (RST) 103, and a source follower transistor (SF) 104 is connected to the RST 103 and a selection transistor (SEL) 105. The SEL 105 is also connected to the column output bus L.

[0084] Incident light generates charge through P-PD101-1 in each pixel unit. The charge generated in P-PD101-1 can be transferred to FD101-2 via TG102. Ideally, all the charge generated in P-PD101-1 should be transferred to FD101-2; however, in reality... Figure 1b and Figure 1c As shown, in the cross-sectional view and top view of each pixel unit, due to the uneven distribution of electric potential, the suction force of the P-PD101-1 region, which is far away from TX102-1, on electrons gradually weakens. That is, the P-PD101-1 region, which is far away from TX102-1, will retain more charge, causing the charge of the current frame to be transferred in the transmission of the next frame, so that the information of the current frame image is retained in the next frame image, resulting in the image trailing phenomenon.

[0085] Based on this, embodiments of this application provide a pixel unit and a method for fabricating the pixel unit. By extending the vertical transmission gates from the first surface of the semiconductor substrate towards the photoelectric conversion region, the projected contours of the vertical transmission gates on the first surface are connected in a ring to the PD connection region. This increases the size of the connection region, allowing each point with the maximum potential value to be interconnected, thus constructing a straight path connecting charge transport to the maximum potential value. By adjusting the TX structure from horizontal to vertical, the charge capture capability is enhanced in a portion of the space, thereby increasing the electron extraction force distributed in the PD region, reducing the charge retained in the PD, and avoiding image trailing.

[0086] The objectives, functional features, and advantages of this application will be further explained in conjunction with embodiments and with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0087] The technical solution in this application will now be described with reference to the accompanying drawings:

[0088] Figure 2a The diagram shows a cross-sectional view of the pixel unit provided in an embodiment of this application. Figure 2b A top view structural diagram of a pixel unit provided in an embodiment of this application is shown.

[0089] In one embodiment of this application, a pixel unit is provided, comprising:

[0090] Semiconductor substrate 201;

[0091] The photoelectric conversion region 201-3 is located in the semiconductor substrate 201;

[0092] The vertical transmission gates (e.g., vertical transmission gate 202-1, vertical transmission gate 202-2, ..., vertical transmission gate 202-n, where n is a positive integer) all extend from the first surface 201-1 of the semiconductor substrate 201 to the photoelectric conversion region 201-3 into the semiconductor substrate 201; the projected outline of the vertical transmission gate on the first surface 201-1 includes any shape among rectangle, ellipse, and lattice rectangle.

[0093] For example, such as Figure 2a As shown, both the vertical transmission gate 202-1 and the vertical transmission gate 202-n can be disposed adjacent to the first surface 201-1 of the semiconductor substrate 201, and the extension length of the vertical transmission gate 202-1 and the vertical transmission gate 202-n in the semiconductor substrate 201 can be 2.5μm-3μm.

[0094] It should be understood that in this application, the vertical transmission gate 202-1, vertical transmission gate 202-2, ..., vertical transmission gate 202-n can all be disposed adjacent to the first surface 201-1 of the semiconductor substrate 201, or can extend vertically from above the first surface 201-1 of the semiconductor substrate 201 into the semiconductor substrate 201. This is only an example for illustration, and this application does not limit the positional relationship between each vertical transmission gate and the first surface 201-1.

[0095] Optionally, in order to construct a ring-shaped connection between the transmission gate and the PD connection region, thereby allowing each point with a maximum potential value to be interconnected and constructing a straight path connecting charge transport to the maximum potential value, this application can further configure the projected outline of the vertical transmission gate on the first surface 201-1 to at least partially overlap with the projected outline of the photoelectric conversion region 201-3 on the first surface 201-1. For example, as Figure 2b As shown, in a top view of the pixel unit from the first surface 201-1 to the second surface 201-2 of the semiconductor substrate 201, the vertical transmission gates 202-1, 202-2, ..., 202-n are configured with a rectangular shape. Figure 3a The diagram shows a schematic representation of vertical transmission gates 202-1, 202-2, ..., 202-n, constructed in an elliptical shape. Figure 3bThe diagram shows a schematic of a dot matrix structure consisting of vertical transmission gates 202-1, 202-2, ..., 202-n.

[0096] here, Figure 2a It can be along Figure 2b A cross-sectional diagram along the A-A' direction, or... Figure 3a A cross-sectional diagram along the A-A' direction, or... Figure 3b A schematic diagram of the cross section along the A-A' direction. Figure 3c It can be Figure 3b A schematic diagram of the cross section in the B-B' direction.

[0097] It should be understood that this is merely an example illustrating the shape of the transmission gate constructed with multiple vertical transmission gates. This application does not limit the specific number of vertical transmission gates, nor does it limit the specific shape of the multiple vertical transmission gates.

[0098] like Figure 4 As shown, a pixel unit may also include:

[0099] Well region 201-4 and floating diffusion region 201-5 are both disposed adjacent to the first surface 201-1 of semiconductor substrate 201; floating diffusion region 201-5 is spatially separated from vertical transmission gate, for example... Figure 4 The floating diffusion region 201-5 shown is not in contact with either the vertical transmission gate 202-1 or the vertical transmission gate 202-n. The doping type of the well region 201-4 is different from that of the photoelectric conversion region 201-3, while the doping type of the floating diffusion region 201-5 is the same as that of the photoelectric conversion region 201-3.

[0100] For example, if the photoelectric conversion region 201-3 is doped with N-type, the well region 201-4 is doped with P-type, and the floating diffusion region 201-5 is doped with N-type, then the P-type doped well region 201-4 can be used as a surface pinning layer to reduce the dark current caused by surface defects in the pixel unit.

[0101] Optional, such as Figure 4 As shown, each vertical transmission gate (e.g., vertical transmission gate 202-1, vertical transmission gate 202-n) extends from the first surface 201-1 of the semiconductor substrate 201 through the well region 201-4 to the photoelectric conversion region 201-3.

[0102] like Figure 5a and Figure 5b As shown, a pixel unit may also include:

[0103] A horizontal transmission gate 203 is located on the first surface 201-1 of the semiconductor substrate 201, and the horizontal transmission gate 203 is electrically connected to each vertical transmission gate.

[0104] For example, the projected outline of the horizontal transmission gate 203 on the first surface 201-1 may be located outside the projected outlines of the vertical transmission gates 202-1, 202-2, ..., 202-n on the first surface 201-1, such as... Figure 5a A schematic diagram illustrating the positional relationship between the horizontal transmission gate 203 and the vertical transmission gates 202-1 and 202-n is shown. The projected outline of the horizontal transmission gate 203 on the first surface 201-1 can also lie within the projected outlines of the vertical transmission gates 202-1, 202-2, ..., 202-n on the first surface 201-1, as shown below. Figure 5b A schematic diagram showing the positional relationship between the horizontal transmission gate 203 and the vertical transmission gates 202-1 and 202-n is shown.

[0105] like Figure 6 As shown, a pixel unit may also include:

[0106] Impurity region 204 is located between the floating diffusion region 201-5 and the vertical transmission gate (e.g., vertical transmission gate 202-1) closest to the floating diffusion region. The doping type of impurity region 204 can be the same as that of the floating diffusion region 201-5, for example, both can be doped with N-type ions.

[0107] In one possible implementation, the doping concentration of the impurity region 204 is less than or equal to the doping concentration of the floating diffusion region 201-5, so that the charge generated in the photoelectric conversion region 201-3 can be better transferred to the floating diffusion region 201-5 under the control of the vertical transfer gate.

[0108] Figure 7 The diagram illustrates the workflow of a pixel unit fabrication method according to an embodiment of this application. Figure 7 As shown, the specific process of this method is as follows:

[0109] Step S701: Provide a semiconductor substrate and perform trench etching on the first surface of the semiconductor substrate according to a first specified shape. The first specified shape includes any one of a rectangle, an ellipse, or a dot matrix rectangle.

[0110] In step S702, a dielectric layer and a conductive layer are sequentially filled into the trench to form a vertical transmission gate, wherein the projection profile of the vertical transmission gate on the first surface is a first specified shape.

[0111] Optionally, after applying a resist to the first surface of the semiconductor substrate, the coated first surface is exposed and developed, and trenches are etched according to a first specified shape. Then, silicon oxide and polysilicon are sequentially filled into the trenches to form a vertical transmission gate. Here, the dielectric layer may include silicon oxide, High-K materials, etc., and the conductive layer may include polysilicon, metal layers (such as TiN, W, Cu, etc.).

[0112] For example, such as Figure 8 As shown, photoresist (PR) treatment is first performed on the first surface 201-1 of the semiconductor substrate 201, followed by exposure and development treatment, and trench etching is performed according to the shape and number of vertical transmission gates. Figure 8 (Taking two vertical transmission gates TX1 and TX2 as an example for illustration). Then, a silicon oxide layer (not shown in the figure) is deposited on the inner wall of each trench and the first surface 201-1 of the semiconductor substrate 201 to obtain the gate dielectric layer. Then, a polysilicon layer is deposited to obtain the gate layer. Each trench is filled with polysilicon, and excess polysilicon is etched away. Finally, the polysilicon in the two trenches (i.e., the two vertical transmission gates TX1 and TX2) is electrically connected (denoted by metal W) to obtain the pixel unit.

[0113] Figure 9 The diagram illustrates the workflow of a pixel unit fabrication method according to an embodiment of this application. Figure 9 As shown, the specific process of this method is as follows:

[0114] Step S901: Provide a semiconductor substrate and perform trench etching on the first surface of the semiconductor substrate according to a first specified shape. The first specified shape includes any one of a rectangle, an ellipse, and a dot matrix rectangle.

[0115] In step S902, after the trench is filled with a dielectric layer and a conductive layer in sequence, it is etched again according to the second specified shape to remove the part of the conductive layer outside the trench, and a horizontal transmission gate is formed on the first surface. The conductive layer in the trench forms a vertical transmission gate, and the projection outline of the vertical transmission gate on the first surface is the first specified shape.

[0116] Optionally, after applying a resist coating to the first surface of the semiconductor substrate, the coated first surface is exposed and developed, and trenches are etched according to a first specified shape. Then, the trenches are sequentially filled with silicon oxide and polysilicon, and etched again according to a second specified shape to remove the polysilicon filler outside each trench; the second specified shape is determined based on the shape of the horizontal transmission gate. Finally, each trench filled with polysilicon after re-etching is electrically connected to the raised polysilicon on the first surface of the semiconductor substrate to obtain a pixel unit.

[0117] For example, such as Figure 10a As shown, firstly, photoresist (PR) processing is performed on the first surface 201-1 of the semiconductor substrate 201, followed by exposure and development processing, and then trench etching is performed according to the shape and number of vertical transfer gates and the shape and number of horizontal transfer gates. Figure 10a (Taking two vertical transmission gates TX1 and TX2, and one horizontal transmission gate TX3 as an example). A silicon oxide layer (not shown in the figure) is then deposited on the inner wall of each trench and on the first surface 201-1 of the semiconductor substrate 201 to obtain the gate dielectric layer. Then, a polysilicon layer is deposited to obtain the gate layer. Each trench is filled with polysilicon, and excess polysilicon is etched away. Finally, the polysilicon in the two trenches (i.e., the two vertical transmission gates TX1 and TX2) and the raised polysilicon on the first surface 201-1 of the semiconductor substrate 201 (i.e., the horizontal transmission gate TX3) are electrically connected (denoted by metal W) to obtain the pixel unit.

[0118] In one embodiment of this application, the conductive layers of the etched horizontal transport gate and the vertical transport gate can be integrally formed. For example... Figure 10b As shown, both the vertical transmission gate 202-1 and the vertical transmission gate 202-n can be disposed adjacent to the first surface 201-1 of the semiconductor substrate 201, and the vertical transmission gate 202-1 and the horizontal transmission gate 203 are also disposed adjacent to each other on the first surface 201-1 of the semiconductor substrate 201, so that the conductive layers of the horizontal transmission gate 203 and the vertical transmission gates 202-1, 202-2, ..., 202-n can be integrally formed after etching. Figure 10c A schematic diagram is shown showing that the vertical transmission gate 202-1, vertical transmission gate 202-2, ..., vertical transmission gate 202-n are constructed in a rectangular shape, and the vertical transmission gate 202-1, vertical transmission gate 202-2, ..., vertical transmission gate 202-n and horizontal transmission gate 203 are integrally formed. Figure 10d A schematic diagram is shown showing that the vertical transmission gate 202-1, vertical transmission gate 202-2, ..., vertical transmission gate 202-n are constructed in an elliptical shape, and the vertical transmission gate 202-1, vertical transmission gate 202-2, ..., vertical transmission gate 202-n and horizontal transmission gate 203 are integrally formed. Figure 10e A schematic diagram is shown showing that the vertical transmission gate 202-1, vertical transmission gate 202-2, ..., vertical transmission gate 202-n are constructed in the shape of a dot matrix rectangle, and the vertical transmission gate 202-1, vertical transmission gate 202-2, ..., vertical transmission gate 202-n and horizontal transmission gate 203 are integrally formed.

[0119] It should be understood that this is merely an example illustrating the shape of the transmission gate constructed from multiple vertical and horizontal transmission gates. This application does not limit the specific number of vertical and horizontal transmission gates, nor does it limit the specific shape of the multiple vertical and horizontal transmission gates.

[0120] like Figure 11 As shown, this application embodiment provides an image sensor, which includes:

[0121] Multiple pixel units (e.g., pixel unit 1101-1, pixel unit 1101-2, ..., pixel unit 1101-m, where m is a positive integer), analog-to-digital converter 1102, and accumulator 1103; the analog-to-digital converter 1102 is connected to each pixel unit and the accumulator 1103 respectively.

[0122] Each pixel unit is a pixel unit as described in any of the above embodiments, and multiple pixel units are arranged in an array; multiple pixel units can generate electrical signals and send the generated electrical signals to analog-to-digital converter 1102; analog-to-digital converter 1102 converts the electrical signals into digital signals and sends the digital signals to accumulator 1103; accumulator 1103 adds and accumulates the digital signals to obtain an image signal.

[0123] Optional, such as Figure 12 As shown, the image sensor also includes:

[0124] The line decoder 1104 and the timing controller 1105 are respectively connected to each pixel unit and the timing controller 1105. The timing controller 1105 is also connected to the mode converter and the accumulator 1103 respectively.

[0125] The timing controller 1105 can send a first control signal to the line decoder 1104, and then the line decoder 1104 sends pixel drive signals to the pixel units of a specified row among the multiple pixel units according to the first control signal. The multiple pixel units generate electrical signals according to the pixel drive signals. The timing controller 1105 can also send a second control signal to the analog-to-digital converter 1102 and a third control signal to the accumulator 1103, so that the analog-to-digital converter 1102 converts the electrical signals corresponding to the pixel units of the specified row among the multiple pixel units into digital signals according to the second control signal, and the accumulator 1103 performs addition and accumulation on the digital signals according to the third control signal to obtain the image signal.

[0126] like Figure 13 As shown, this application embodiment provides a pixel unit fabrication apparatus, the apparatus comprising:

[0127] A first shape etching module 1301 is used to provide a semiconductor substrate and perform trench etching on a first surface of the semiconductor substrate according to a first specified shape, wherein the first specified shape includes any one of a rectangle, an ellipse, or a dot matrix rectangle.

[0128] The first pixel unit determination module 1302 is used to sequentially fill the trench with a dielectric layer and a conductive layer to form a vertical transmission gate, wherein the projection contour of the vertical transmission gate on the first surface is the first specified shape.

[0129] like Figure 14 As shown, this application embodiment provides a pixel unit fabrication apparatus, the apparatus comprising:

[0130] A first shape etching module 1401 is used to provide a semiconductor substrate and perform trench etching on a first surface of the semiconductor substrate according to a first specified shape, wherein the first specified shape includes any one of a rectangle, an ellipse, or a dot matrix rectangle.

[0131] The second pixel unit determination module 1402 is used to sequentially fill the trench with a dielectric layer and a conductive layer, and then etch it again according to the second specified shape to remove the part of the conductive layer located outside the trench, form a horizontal transmission gate on the first surface, and form a vertical transmission gate in the conductive layer in the trench. The projection outline of the vertical transmission gate on the first surface is the first specified shape.

[0132] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A pixel unit, characterized in that, include: Semiconductor substrate; The photoelectric conversion region is located in the semiconductor substrate; The vertical transmission gates extend from the first surface of the semiconductor substrate into the photoelectric conversion region and into the semiconductor substrate; the projection outline of the vertical transmission gate on the first surface includes any one of the shapes of rectangle, ellipse, and lattice rectangle.

2. The pixel unit as described in claim 1, characterized in that, The projection profile of the vertical transmission gate on the first surface at least partially overlaps with the projection profile of the photoelectric conversion region on the first surface.

3. The pixel unit as described in claim 1, characterized in that, The pixel unit further includes: The semiconductor substrate has a well region and a floating diffusion region, both of which are disposed adjacent to the first surface of the semiconductor substrate. The floating diffusion region is spatially separated from the vertical transmission gate. The doping type of the well region is different from that of the photoelectric conversion region, while the doping type of the floating diffusion region is the same as that of the photoelectric conversion region.

4. The pixel unit as described in claim 1, characterized in that, The pixel unit further includes: A horizontal transmission gate is located on a first surface of the semiconductor substrate, and the horizontal transmission gate is electrically connected to each of the vertical transmission gates.

5. The pixel unit as described in claim 1, characterized in that, The projection profile of the horizontal transmission gate on the first surface lies within the projection profile of the vertical transmission gate on the first surface.

6. The pixel unit as described in claim 3, characterized in that, The pixel unit further includes: An impurity region is located between the floating diffusion region and the vertical transmission gate closest to the floating diffusion region, and the doping type of the impurity region is the same as that of the floating diffusion region.

7. The pixel unit as described in claim 6, characterized in that, The doping concentration in the impurity region is less than or equal to the doping concentration in the floating diffusion region.

8. The pixel unit as described in any one of claims 1-7, characterized in that, The vertical transmission gate extends 2.5 μm to 3 μm in the semiconductor substrate.

9. A method for manufacturing a pixel unit, characterized in that, The method includes: A semiconductor substrate is provided, and trench etching is performed on a first surface of the semiconductor substrate according to a first specified shape, wherein the first specified shape includes any one of a rectangle, an ellipse, and a lattice rectangle. A dielectric layer and a conductive layer are sequentially filled in the trench to form a vertical transmission gate, and the projection profile of the vertical transmission gate on the first surface is the first specified shape.

10. A method for manufacturing a pixel unit, characterized in that, The method includes: A semiconductor substrate is provided, and trench etching is performed on a first surface of the semiconductor substrate according to a first specified shape, wherein the first specified shape includes any one of a rectangle, an ellipse, and a lattice rectangle. After the trench is sequentially filled with a dielectric layer and a conductive layer, it is etched again according to the second specified shape to remove the portion of the conductive layer outside the trench, forming a horizontal transmission gate on the first surface. The conductive layer in the trench forms a vertical transmission gate, and the projection outline of the vertical transmission gate on the first surface is the first specified shape.

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