Silicon-on-insulator substrate and preparation method thereof

Abstract

The invention provides a silicon-on-insulator substrate and a preparation method thereof, and the preparation method comprises the steps: carrying out the ion beam planarization processing of the top silicon of a silicon-on-insulator intermediate, so as to obtain the silicon-on-insulator substrate, the ion beam planarization treatment comprises the following steps: determining reference thermal deformation of the silicon-on-insulator intermediate caused in the process of performing ion beam planarization treatment on top silicon of the silicon-on-insulator intermediate by an ion beam with reference treatment parameters; according to the reference thermal deformation of the silicon-on-insulator intermediate and the difference between the initial morphology and the target morphology of the top silicon before ion beam planarization processing, determining a design film thickness removal amount matrix for scanning and etching the top silicon of the silicon-on-insulator intermediate; and according to the designed film thickness removal amount matrix, carrying out scanning etching on the top silicon of the silicon-on-insulator by adopting an ion beam so as to obtain a silicon-on-insulator substrate of which the thickness deviation of the top silicon is smaller than a preset threshold value.

Description

Technical Field

[0001] This application relates to the field of semiconductor processing technology, and more particularly to silicon-on-insulator substrates and their preparation methods. Background Technology

[0002] With the rapid development of semiconductor technology, the feature size of integrated circuits is constantly shrinking, and the performance requirements for the semiconductor substrate materials that form the basis of them are becoming increasingly stringent. Silicon-on-insulator (SOI) structures have become a key material for manufacturing high-performance, low-power integrated circuits due to their significant advantages in improving device switching speed, reducing power consumption, and enhancing radiation resistance, playing an indispensable role in various cutting-edge fields.

[0003] In silicon-on-insulator (SiI) structures, the physical properties of the top silicon layer directly determine the performance consistency and reliability of the semiconductor devices built upon it. Therefore, how to precisely control the thickness of the top silicon layer to ensure uniformity and thus stably improve device performance has always been a pressing technical challenge in this field. Summary of the Invention

[0004] To address the aforementioned issues, embodiments of this application provide a silicon-on-insulator substrate and a method for its fabrication. This method combines the initial static morphology error of the silicon-on-insulator intermediate with the predictable dynamic thermal deformation error during processing to achieve feedforward precise control of the thickness of the top silicon layer.

[0005] The technical solution of this application is implemented as follows: In a first aspect, embodiments of this application provide a method for fabricating a silicon-on-insulator substrate, the method comprising: Ion beam planarization is performed on the top silicon layer of the silicon-on-insulator intermediate to obtain a silicon-on-insulator substrate, wherein the ion beam planarization process includes: Determine the reference thermal deformation of the silicon-on-insulator intermediate caused by the ion beam planarization process performed on the top silicon of the silicon-on-insulator intermediate by an ion beam with reference processing parameters. Based on the reference thermal deformation of the silicon-on-insulator intermediate and the difference between the initial morphology and the target morphology of the top silicon before ion beam planarization, a design thickness removal matrix for scanning etching of the top silicon of the silicon-on-insulator intermediate is determined. Based on the designed film thickness removal matrix, an ion beam is used to scan and etch the top silicon layer of silicon-on-insulator (SiO2) to obtain a SiO2 substrate with a thickness deviation of less than a predetermined threshold.

[0006] In some examples, the predetermined threshold is 10nm.

[0007] In some examples, the thickness of the top silicon layer on the silicon-on-insulator substrate is 1 nm to 3 μm.

[0008] In some examples, the step of scanning etching the top silicon of the silicon-on-insulator intermediate using an ion beam according to the designed film thickness removal matrix includes: The film thickness removal amount defined by the design film thickness removal amount matrix can be achieved by controlling at least one of the accelerating voltage of the ion beam, the current of the ion beam, the incident angle of the ion beam, and the residence time of the ion beam in different regions of the top silicon layer of the silicon-on-insulator intermediate.

[0009] In some examples, the steps to determine the design film thickness removal matrix include: Based on the difference between the initial morphology and the target morphology, the basic film thickness removal matrix is ​​calculated; Based on the reference thermal deformation, the basic film thickness removal matrix is ​​modified to compensate for the etching amount change caused by the range change of the ion beam to the top silicon of the silicon-on-insulator intermediate caused by the reference thermal deformation, thereby obtaining the designed film thickness removal matrix.

[0010] In some examples, the steps for determining the baseline thermal deformation include: The top silicon layer of the silicon-on-insulator intermediate is scanned and etched using an ion beam with reference processing parameters; and The thermal deformation of the silicon intermediate on the insulator during the scanning etching process is calculated to obtain the baseline thermal deformation.

[0011] In some examples, the steps for determining the reference thermal deformation include: calculating the reference thermal deformation based on the voltage and current in the reference processing parameters of the ion beam, as well as the thermal conductivity, coefficient of thermal expansion, and elastic modulus of the silicon intermediate on the insulator.

[0012] In some examples, the voltage of the ion beam is in the range of 500 eV to 5 keV, and the current of the ion beam is in the range of 5 mA to 300 mA.

[0013] In some examples, after performing scanning etching according to the designed film thickness removal matrix, ion beam planarization also includes: Measuring the film thickness parameters of the top silicon layer in the silicon intermediate on the insulator; and Based on the measured film thickness parameters, the film thickness removal matrix is ​​modified.

[0014] In some examples, ion beam planarization is performed at less than 1 × 10⁻⁶. -6 The procedure is performed in a vacuum environment of millibars.

[0015] In some examples, silicon-on-insulator intermediates are obtained by at least one of grinding, chemical mechanical planarization, and thermal treatment of the bonded wafer.

[0016] In some examples, the surface roughness of the top silicon layer on the silicon-on-insulator substrate is less than 0.5 nm.

[0017] Secondly, embodiments of this application provide a silicon-on-insulator substrate, which is fabricated using the method for fabricating a silicon-on-insulator substrate according to the first aspect, and the silicon-on-insulator substrate includes: Support wafer; A silicon oxide layer disposed on a support wafer; and The top silicon layer is set on the silicon oxide layer. The thickness deviation of the top silicon layer is less than 10 nm, and the thickness of the top silicon layer is in the range of 1 nm to 3 μm.

[0018] In some examples, the surface roughness of the top silicon layer is less than 0.5 nm.

[0019] The embodiments of this application provide a silicon-on-insulator (SiS) substrate and its fabrication method. This fabrication method first transforms a dynamically generated, unpredictable physical error source during processing—represented by a reference thermal deformation—into a known, quantifiable correction basis by determining a reference thermal deformation. Furthermore, this fabrication method combines this reference thermal deformation, representing dynamic physical error, with the difference between the initial and target morphologies, representing static geometric error, to jointly determine a final, doubly corrected processing blueprint, namely, a design thickness removal matrix. By strictly adhering to this design thickness removal matrix during scanning etching, both the initial thickness non-uniformity (static error) and the thermal deformation non-uniformity generated during processing (dynamic error) can be systematically eliminated in the same processing step. It is through this comprehensive identification and synergistic compensation of errors that this fabrication method can ultimately stably and repeatedly manufacture SiS substrates with unprecedented thickness uniformity, thereby breaking through the precision bottleneck of correlated technologies and providing key technical support for the manufacturing of high-performance semiconductor devices. Attached Figure Description

[0020] Figure 1 A schematic cross-sectional view of the silicon-on-insulator intermediate provided in an embodiment of this application.

[0021] Figure 2 This is a schematic diagram of the surface morphology of the top silicon layer of the silicon-on-insulator intermediate.

[0022] Figure 3 A process flow diagram for preparing the silicon-on-insulator intermediate provided in the embodiments of this application.

[0023] Figure 4 This is a schematic diagram of an ion beam planarization apparatus provided in an embodiment of this application.

[0024] Figure 5 A flowchart illustrating a method for fabricating a silicon-on-insulator substrate provided in an embodiment of this application.

[0025] Figure 6 This is a schematic diagram of the reference thermal deformation provided in the embodiments of this application.

[0026] Figure 7 This is a schematic diagram of the design film thickness removal matrix provided in the embodiments of this application.

[0027] Figure 8 This is a schematic diagram of the top silicon thickness distribution of a silicon-on-insulator substrate provided as a comparative example of this application.

[0028] Figure 9 This is a schematic diagram of the top silicon thickness distribution of a silicon-on-insulator substrate provided in an embodiment of this application. Detailed Implementation

[0029] The technical solutions in this application will now be clearly and completely described with reference to the accompanying drawings.

[0030] Silicon-on-insulator (SOI) substrates are composite semiconductor substrate structures typically composed of three stacked layers: a top layer of single-crystal silicon thin film, known as the device layer; a middle layer of silicon dioxide insulating layer, known as the buried oxide (BOX) layer; and a bottom support wafer. In SOI substrates, the device layer is the active region used to fabricate semiconductor devices such as transistors. The buried oxide layer provides excellent electrical isolation, effectively reducing parasitic capacitance and suppressing latch-up effects. The support wafer primarily provides mechanical support, ensuring the structural integrity of the entire substrate during the complex and precise manufacturing process.

[0031] In advanced semiconductor manufacturing processes, such as when fabricating substrates for fully depleted SOI (FD-SOI) devices, the industry aims to achieve ultrathin top-layer silicon with a thickness ranging from 1 nanometer (nm) to 3 micrometer (μm) and a global thickness range better than 10 nm on large-size wafers with a diameter of 300 mm. One technological approach to achieving this goal is the use of a bond-etch backside (BESOI) process, which involves wafer bonding followed by a series of thinning processes such as mechanical polishing and chemical mechanical planarization (CMP) to fabricate SOI wafers.

[0032] However, the study found that even when the top silicon layer is thinned to near the target thickness using only mechanical polishing and CMP processes, the thickness non-uniformity of the wafer surface is still significant, with the thickness deviation typically still exceeding 100 nm, which is far from meeting the requirements of high-end devices.

[0033] To further improve the thickness uniformity of the top silicon layer, the study attempted to introduce a higher-precision non-contact processing technology, namely ion beam planarization (IBP), as the final finishing step. In principle, IBP technology is like a digital engraving tool, which can use an ion beam to peel away material from excessively thick areas in order to achieve better flatness.

[0034] However, further problems were discovered during actual process development and experiments: despite using this high-precision IBP equipment, while the wafer thickness uniformity was improved, it was consistently unable to break through a technical bottleneck, such as 50nm, making it difficult to reach the final target of less than 10nm. Furthermore, the processed wafer surface often exhibited a regular, non-random ring-shaped or saddle-shaped thickness distribution error. Analysis suggested that an unidentified and uncontrolled systematic error source might exist during the execution of the IBP process, and this error source was precisely what undermined the technology's intended maximum precision.

[0035] To explore the underlying causes of this phenomenon, extensive theoretical analysis and simulation calculations were conducted. The study found that the root cause lies in the physical effects inherent in the ion beam planarization process itself.

[0036] Specifically, the research recognizes that the operation of ion beam planarization equipment is based on a precisely calibrated and theoretically constant spatial relationship between the ion source and the wafer surface to be processed. The wafer is fixed on a movable wafer stage, and a preset, perpendicular working distance is maintained between the ion source's exit port and the wafer surface. The entire process control system's algorithm, including the calculation of the ion beam's residence time at various points on the wafer, is strictly based on the assumption that this working distance is constant.

[0037] However, in reality, when a high-energy ion beam bombards the surface of a silicon wafer, most of its energy is converted into heat and deposited in a shallow region near the bombardment point. Because the ion beam performs localized scanning etching, this energy injection is highly non-uniform in both time and space, resulting in a dramatic, dynamically changing temperature gradient within the wafer.

[0038] According to the principles of thermoelasticity, this non-uniform temperature field inevitably causes non-uniform thermal expansion, leading to microscopic and dynamic physical deformation of the entire wafer, i.e., thermally induced warping. This warping causes the wafer surface to bulge or dent in real time during processing, thus dynamically changing the actual working distance between the ion source and various points on the wafer surface. Since the ion beam has a certain divergence angle during propagation, even small changes in the working distance significantly affect the ion flux density reaching the wafer surface, directly causing local etching rates to deviate from the preset value. Specifically, when a region of the wafer warps upwards due to heat and approaches the ion source, its actual etching rate will be faster than expected, leading to over-etching and resulting in an excessively thin final thickness. Conversely, when a region sinks relatively downwards and moves away from the ion source, its actual etching rate will be slower than expected, leading to under-etching and resulting in an excessively thick final thickness.

[0039] Based on the above understanding and analysis, the essence of the problem is revealed: it is this uncompensated thermal physical deformation that is dynamically generated during the processing that constitutes the fundamental physical bottleneck that limits the IBP technology from reaching its theoretical limit of precision. This causes a precision process originally intended to eliminate initial errors to introduce new and unpredictable secondary errors.

[0040] The research also recognized that simply pursuing higher precision processing tools cannot solve the problem. A new technical approach must be proposed, starting from the control level, to proactively address and eliminate this inherent thermal deformation error. Based on this understanding, a further improvement scheme is proposed, namely the method for fabricating silicon-on-insulator substrates based on predictive physical modeling and feedforward compensation control provided in the embodiments of this application, and the silicon-on-insulator substrates fabricated by this method.

[0041] In summary, this preparation method improves the ion beam planarization process. Specifically, it performs a specially controlled ion beam planarization process on the top silicon layer of a silicon-on-insulator (SOS) intermediate as the processing target, ultimately obtaining a SOS substrate with desired thickness uniformity. To better understand the technical solutions of this application's embodiments, the processing target, namely the SOS intermediate, and the processing equipment, namely the ion beam planarization device, will first be introduced below. Then, based on this, the preparation method of the SOS substrate provided by this application's embodiments will be described in detail.

[0042] The starting workpiece of the preparation method provided in this application is a silicon-on-insulator (SOI) intermediate. Structurally, this SOI intermediate already possesses the basic three-layer structure of SOI. For example... Figure 1As shown, the silicon-on-insulator (SiO2) intermediate 20 may include a support wafer 202 as a mechanical support, a buried oxide layer 204 disposed on the support wafer 202, and a top silicon layer 206 disposed on the buried oxide layer 204 for final finishing. The thickness uniformity of the top silicon layer 206 of this SiO2 intermediate 20 has not yet met the specifications of the final product. Figure 2 As shown, this is a three-dimensional surface map, i.e. a contour map, obtained by a high-precision topography measurement device, such as an ellipsomerometer, schematically showing the top silicon surface morphology of the silicon-on-insulator intermediate after preliminary thinning. Figure 2 This is a topographic image showing the thickness (in nm) on the XY plane (in mm). The scale indicates that the thickness varies from approximately 1000 nm to over 1300 nm, exhibiting significant inhomogeneity. The image reveals macroscopic, long-wavelength thickness undulations on the surface of the top silicon layer, exhibiting a bowl-shaped distribution with a thinner central region and thicker edge regions. The global thickness deviation, i.e., the difference between the maximum and minimum thickness, is typically still above 100 nm.

[0043] Furthermore, the silicon-on-insulator intermediate 20 is obtained through a series of preceding process steps. For example, a bond-etch backside (BESOI) technique can be used. Figure 3 As shown, the process may include: First, preparing two wafers, such as the first wafer 302 and the second wafer 304, and performing step S1 on the surface of at least one of them, i.e., performing a thermal oxidation operation to grow an oxide layer L with a thickness greater than 5 nm. Then, the edge of one of the wafers, such as the edge of the second wafer 304, can be trimmed for the first time using a diamond grinding tool, i.e., performing step S2. For example, the trimming depth can be less than 50 μm, with a penetration depth of less than 3 mm, to optimize the subsequent bonding quality. The execution order of steps S1 and S2 can be changed according to actual process requirements. Next, performing step S3, i.e., after plasma activation treatment of the surfaces to be bonded on the two wafers, bonding is performed in a vacuum environment to form a bonded wafer. The gas used for plasma activation treatment can be any one of Ar, N2, O2, or a mixture thereof; bonding is performed in a vacuum bonding chamber, and the vacuum pressure can be in the range of 0.001 mbar to 1000 mbar.

[0044] To enhance bond strength, the bonded wafers typically require heat treatment annealing. Annealing temperatures can range from 200°C to 800°C for 2 to 6 hours to achieve a bond strength greater than 1.8 joules per square meter (J / m²). 2In some applications with high edge quality requirements, step S4 can be performed to perform a second edge trimming on the bonding wafer. For example, the trimming depth is less than 800 μm and the penetration depth is less than 3 mm. When product quality requirements are not high, this second edge trimming step can be omitted. Finally, step S5 is performed, which involves a series of thinning processes, such as mechanical polishing, chemical mechanical planarization (CMP), or a combination of both, to remove most of the material from one of the wafers, thereby forming a silicon-on-insulator intermediate 20 with a top silicon layer 206.

[0045] Some embodiments of this application also provide an ion beam planarization apparatus for the final finishing of the aforementioned silicon-on-insulator intermediate. For example... Figure 4 An ion beam planarization apparatus 100 for performing this process is schematically shown. This apparatus 100 is typically configured to maintain an ultra-high vacuum environment (e.g., less than 1 × 10⁻⁶). -6 The ion beam planarization apparatus 100 may include an ion source 102 for generating and emitting an ion beam according to instructions; a wafer stage 106 for supporting and fixing the silicon-on-insulator intermediate 20 to be processed; and a controller 108. The controller 108 is operatively connected to other components of the ion beam planarization apparatus 100 and is used to execute the core control algorithm provided in the embodiments of this application.

[0046] It should be noted that, due to the ion beam planarization process being less than 1×10 -6 The process is carried out in a millibar vacuum environment. To complement the baseline thermal deformation model established based on parameters such as thermal conductivity, the wafer stage 106 can be equipped with a heat dissipation or temperature control mechanism during the actual processing. This mechanism is used to maintain heat exchange between the silicon-on-insulator (SiO2) intermediate and the wafer stage under vacuum conditions, ensuring that the temperature distribution of the SiO2 intermediate is under control, thereby supporting the accurate execution of feedforward thermal deformation compensation.

[0047] Using the aforementioned processing object and processing equipment, the core preparation method provided in the embodiments of this application can be performed. See also Figure 5 The ion beam planarization process may include the following steps S02 to S06.

[0048] In step S02, the reference thermal deformation of the silicon-on-insulator intermediate caused by the ion beam planarization process performed on the top silicon of the silicon-on-insulator intermediate by an ion beam with reference processing parameters is determined.

[0049] The baseline processing parameters can be understood as a pre-defined set of process parameters used to perform standard ion beam planarization, such as the voltage and current of the ion beam. In some specific implementations, the ion beam voltage can range from 500 electron volts (eV) to 5 kiloelectron volts (keV), while the ion beam current can range from 5 mA to 300 mA. Furthermore, the full width at half maximum (FWHM) of the ion beam can be selected from 8 mm to 20 mm, and the selected ion source can be one or more combinations of inert gases (such as Ar, N2, O2) or reactive gases (such as NF3, CF4, CHF3, CO2, Cl2, Br2, HBr, SiCl4). By controlling these parameters, the etching rate of the ion beam can be made to 1 × 10⁻⁶. - 3 mm 3 / s to 20×10 -3 mm 3 The value varies between / s.

[0050] Accordingly, the baseline thermal deformation can be interpreted as: under the standard processing conditions defined by the aforementioned baseline processing parameters, the predictable, microscopic physical deformation distribution of the silicon intermediate on the insulator due to the absorption of ion beam energy. This distribution is essentially an error prediction map that reveals the systematic errors that the planarization process itself will introduce without any compensation. Figure 6 This is a 3D schematic diagram illustrating baseline thermal deformation, where the X and Y axes represent the planar coordinates of the wafer (unit: mm), and the Z axis (unit: μm) represents the vertical displacement or warpage caused by thermal effects. The diagram shows a non-uniform deformation from the center (approximately 0 μm) to the edge (approximately -5 μm). It can be seen from the diagram that under the heating effect of ion beam scanning etching, the Z-axis displacement, i.e., the warpage, is greatest in the central region of the wafer, gradually decreasing towards the edge, exhibiting a centrally convex morphology.

[0051] The reference thermal deformation can be primarily used to provide a feedforward, quantifiable correction basis for subsequent compensation control. This transforms a dynamically generated, uncontrollable error source during processing into a known quantity that is precisely understood before processing begins.

[0052] There are several ways to determine the baseline thermal deformation. For example, this step can be done through calculation. Specifically, the baseline thermal deformation can be calculated based on baseline processing parameters, such as the voltage and current of the ion beam, and the physical properties of the silicon intermediate on the insulator. Physical properties refer to macroscopic physical constants inherent to the material that do not change with the specific morphology, such as the thermal conductivity, coefficient of thermal expansion, and elastic modulus of the top silicon layer. The calculation process can involve solving one or more physical equations.

[0053] Below is a specific, unrestricted calculation example: Assuming the process conditions are for removing 500 Å of top-layer silicon, the selected baseline processing parameters are: ion beam current I = 35 mA, voltage 1 keV, and FWHM 15 mm. It is also assumed that 50% (i.e., coefficient f = 0.5) of the ion beam energy is converted into heat. The physical properties of silicon are known: thermal conductivity k = 150 W / (m·K), and coefficient of thermal expansion α = 2.6 × 10⁻⁶. -6 K -1 The elastic modulus E = 169.5 × 10 9 Pa, and assuming that 50% (i.e., f=0.5) of the ion beam energy is converted into heat. The calculation process may include the following steps: The beam density J is calculated using the following formula (1). b (1); The power density P is calculated based on the beam current density using the following formula (2). d (2); The energy density U is calculated using the following formula (3). (3); The local temperature rise ΔT is calculated using the following formula (4). max (4); The resulting thermal stress σ is calculated using the following formula (5). thermal (5); The thermal deformation δ caused by thermal stress is calculated using the following formula (6). thermal (6).

[0054] By performing the above calculations, it can be found that under this specific process condition, the range of thermal deformation is approximately between 0.24 nm and 2.41 nm.

[0055] In other embodiments of this application, the step of determining the reference thermal deformation can also be accomplished through experimental measurement. For example, the silicon-on-insulator to be processed can be used as a test wafer, and an ion beam with reference processing parameters can be used to scan and etch it. During the scanning etching process, high-precision in-situ measurement equipment, such as a laser interferometer or a pyrometer, can be used to measure the thermal deformation generated by the test wafer during the scanning etching process, thereby obtaining an empirical reference thermal deformation data that can be directly used for subsequent production. For example, thickness measurement can be performed simultaneously with scanning etching, and the ion beam residence time can be dynamically changed through film thickness data feedback to achieve instantaneous compensation, accurately complete the process, and reduce the total process time.

[0056] In step S04, based on the reference thermal deformation of the silicon-on-insulator intermediate and the difference between the initial morphology and the target morphology of the top silicon before ion beam planarization, a design film thickness removal matrix for scanning etching of the top silicon of the silicon-on-insulator intermediate is determined.

[0057] The initial morphology refers to the surface thickness distribution of the top silicon layer in the silicon-on-insulator intermediate. The target morphology is typically an ideal, perfectly flat plane whose height corresponds to the target average thickness of the final product. Therefore, the difference between the initial and target morphologies constitutes the error distribution, which precisely describes the base thickness of the material to be removed at every location in the top silicon layer.

[0058] The film thickness removal matrix can be designed as a two-dimensional spatial distribution map, which specifies the amount of film thickness to be removed during the entire planarization process for each location or pixel on the top silicon surface. Figure 7 A schematic diagram of the designed film thickness removal matrix is ​​shown, where the XY plane represents wafer coordinates (in mm), and the color scale represents the thickness to be removed (in angstroms (Å)). This figure shows a calculated, non-uniform removal distribution to accurately compensate for initial topography and thermal deformation errors.

[0059] Designing the film thickness removal matrix can reflect the interaction between various technical features. Specifically, determining the film thickness removal matrix is ​​done simultaneously based on two independent information sources: error distribution and dynamic error distribution. The error distribution, which is the difference between the initial morphology and the target morphology, determines the amount of basic material to be removed at each point. The dynamic error distribution, which is the reference thermal deformation, is used to compensate for and correct the amount of basic material.

[0060] These two information sources can support and cooperate with each other. The relationship between them is explained below with reference to specific implementation methods. In some implementations, the controller 108 can first calculate a basic film thickness removal matrix based on the error distribution, used only to eliminate initial unevenness. Then, the controller 108 further corrects this basic film thickness removal matrix point by point according to the reference thermal deformation distribution. For example, for a region that appears to bulge upwards by 1 nm in the reference thermal deformation distribution, the controller 108 determines that the actual etching rate of this region will be faster than the nominal value. Therefore, the controller 108 will correspondingly reduce the target film thickness corresponding to this region in the final designed film thickness removal matrix to compensate for this increased rate effect. Conversely, for relatively concave regions, the target removal amount will be correspondingly increased.

[0061] In this way, the elimination of static errors and the compensation of dynamic errors can be perfectly integrated into a unified control algorithm, ultimately generating a final processing blueprint that can both eliminate initial unevenness and pre-counteract the effects of thermal deformation, namely, the design film thickness removal matrix.

[0062] In step S06, according to the designed film thickness removal matrix, an ion beam is used to scan and etch the top silicon layer of silicon-on-insulator to obtain a silicon-on-insulator substrate with a thickness deviation of less than a predetermined threshold.

[0063] The design thickness removal matrix determined here can also be referred to as the final design thickness removal matrix. Step S06 transforms the digital blueprint of the design thickness removal matrix obtained in step S04 into the actual physical processing action. The scanning etching process of the top silicon layer of the silicon-on-insulator substrate is precisely controlled by the design thickness removal matrix. Specifically, this can be achieved by controlling the residence time of the ion beam in different regions of the top silicon layer. For example, for regions in the design thickness removal matrix that require a higher dose, the control system can slow down the scanning etching rate or allow the ion beam to remain in that region for a longer time; conversely, it can speed up the scanning etching rate or shorten the residence time. In some other implementations, the thickness removal amount defined by the design thickness removal matrix is ​​achieved by controlling at least one of the ion beam acceleration voltage, ion beam current, ion beam incident angle, and residence time of the ion beam in different regions of the top silicon layer of the silicon-on-insulator intermediate.

[0064] The reason why the embodiment of this application can achieve the desired thickness uniformity by performing the above series of interrelated steps is that the preparation method systematically solves the two core error sources that affect the final accuracy through a feedforward compensation control logic.

[0065] First, this preparation method introduces the key technical feature of reference thermal deformation, transforming an error source that was originally dynamically generated and unpredictable during processing into a quantifiable correction basis that is precisely controlled before processing begins. This is equivalent to establishing a precise dynamic error model for the entire planarization process.

[0066] Moreover, the advantage of this preparation method lies in the fact that it does not treat errors in isolation, but rather synergistically processes two different error sources: the static geometric error represented by the difference between the initial and target morphologies, and the dynamic physical error represented by the reference thermal deformation. Specifically, the final generated design film thickness removal matrix is ​​not a simple superposition of these two error sources, but a unified processing blueprint that has been precisely calculated and can compensate for both simultaneously.

[0067] During scanning etching, strictly adhering to this designed film thickness removal matrix ensures that the actual etching effect applied to each point on the wafer surface precisely corresponds to the required, double-corrected material removal amount for that point. Thus, the two main sources of error—initial thickness non-uniformity (static error) and thermally induced deformation non-uniformity (dynamic error)—are simultaneously and systematically eliminated in the same processing step. It is through this comprehensive identification and synergistic compensation of errors that this fabrication method can ultimately stably and repeatedly produce silicon-on-insulator substrates with unprecedented thickness uniformity, thereby overcoming the precision bottleneck of correlated technologies.

[0068] Furthermore, the aforementioned predetermined threshold can be 10nm. This means that on a wafer with a diameter of 300mm, the difference between the maximum and minimum thickness of the top silicon layer is less than 10nm. This is an order of magnitude improvement compared to the thickness deviation of more than 100nm in related technologies.

[0069] In addition, the thickness of the top silicon layer of the finally obtained silicon-on-insulator substrate can be in the range of 1 nm to 3 μm.

[0070] Furthermore, since the fabrication method provided in this application is an improvement on the non-contact finishing step of ion beam planarization, it can maintain excellent surface quality of the top silicon layer while significantly improving thickness uniformity. In some implementations, the surface roughness of the top silicon layer of the final silicon-on-insulator substrate can be less than 0.5 nm.

[0071] To further improve processing accuracy, after performing scanning etching according to the designed film thickness removal matrix, ion beam planarization may further include: measuring the film thickness parameters of the top silicon layer of the silicon-on-insulator intermediate; and correcting the designed film thickness removal matrix based on the measured film thickness parameters. This correction can be used for subsequent batches of wafer processing or for a second compensation etching of the current wafer, thus forming an iterative optimization closed loop.

[0072] In some implementations, ion beam planarization is performed at a speed of less than 1 × 10⁻⁶. -6 The process is carried out under a vacuum of millibars. In some implementations, the silicon-on-insulator intermediate is obtained by at least one of grinding, chemical mechanical planarization, and thermal treatment of the bonded wafer.

[0073] Examples and Comparative Examples To more clearly illustrate the beneficial effects of the embodiments of this application, specific embodiments and comparative examples are provided below.

[0074] Comparative Example A silicon-on-insulator intermediate with a diameter of 300 mm prepared by BESOI process is provided. The average thickness of the top silicon layer is 800 nm, and the thickness deviation (range) of its initial morphology is measured to be 120 nm.

[0075] The intermediate was placed in an ion beam planarization apparatus, at a density of less than 1×10⁻⁶. -6 The process is carried out in a vacuum environment of millibars.

[0076] A conventional ion beam planarization method is employed, which determines a film thickness removal matrix based solely on the difference between the initial morphology of the top silicon layer and a target thickness of 750 nm, without considering thermally induced deformation during processing.

[0077] Based on the film thickness removal matrix, the top silicon layer is scanned and etched using an ion beam.

[0078] After processing, the obtained silicon-on-insulator substrate was measured, and the thickness deviation of the top silicon layer was 58 nm. Although this is an improvement over the initial state, it is still much greater than 10 nm, and the surface exhibits a clear annular error distribution caused by thermal effects, such as... Figure 8 As shown. Figure 8 The thickness distribution data shown illustrates this error, where the XY coordinates represent the wafer plane (in mm) and the scale represents the thickness (in Å). The "+" marks in the figure indicate uneven thickness distribution, with significant differences between the center and edge regions, and the thickness varies from approximately 2880 Å to over 2980 Å, showing very poor uniformity.

[0079] Example A silicon-on-insulator intermediate with the same specifications as in the comparative example is provided, with an average thickness of 800 nm for the top silicon layer and a thickness deviation of 120 nm for the initial morphology.

[0080] The intermediate was placed in the same ion beam planarization equipment and processed under the same vacuum environment.

[0081] The method provided in this application embodiment is adopted. First, based on preset reference processing parameters, namely voltage 1keV and current 35mA, the reference thermal deformation distribution to be generated under the process conditions is determined by calculation. Then, based on the difference between the initial morphology of the intermediate and a target thickness of 750nm, and the determined reference thermal deformation distribution, a final film thickness removal matrix is ​​jointly determined.

[0082] Based on the final film thickness removal matrix, the top silicon layer is scanned and etched using an ion beam. The scanning etching process is achieved by precisely controlling the residence time of the ion beam at each point.

[0083] After processing, the obtained silicon-on-insulator substrate was measured, and the thickness deviation of the top silicon layer was 8 nm, which is less than the predetermined threshold of 10 nm. Figure 7 As shown. Its surface thickness distribution is uniform, with no obvious systematic errors observed, such as... Figure 9 As shown. Figure 9 The thickness distribution data shown (units) Figure 6 The same) shows the effect of the embodiments of this application, where all “+” markers fall within a very narrow thickness range (approximately 2720 Å to 2820 Å) and are distributed very uniformly across the entire wafer surface.

[0084] Results Comparison

[0085] As can be seen from the comparison of the above embodiments and comparative examples, the preparation method provided by the above embodiments of this application can fundamentally solve the endogenous error sources in the ion beam planarization process by creatively introducing the determination and compensation of the reference thermal deformation, thereby improving the thickness uniformity of the top silicon to a high level.

[0086] It should be noted that the technical solutions described in this application can be combined arbitrarily without conflict.

[0087] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for preparing a silicon-on-insulator substrate, characterized in that, The preparation method includes: An ion beam planarization process is performed on the top silicon layer of the silicon-on-insulator intermediate to obtain a silicon-on-insulator substrate, wherein the ion beam planarization process includes: During the ion beam planarization process performed on the top silicon of the silicon-on-insulator intermediate by an ion beam with reference processing parameters, a reference thermal deformation of the silicon-on-insulator intermediate is determined. Based on the reference thermal deformation of the silicon-on-insulator intermediate and the difference between the initial morphology and the target morphology of the top silicon before the ion beam planarization process, a design thickness removal matrix for scanning etching of the top silicon of the silicon-on-insulator intermediate is determined. According to the designed film thickness removal matrix, the top silicon of the silicon-on-insulator intermediate is scanned and etched using an ion beam to obtain a silicon-on-insulator substrate with a thickness deviation of less than a predetermined threshold.

2. The method for preparing a silicon-on-insulator substrate according to claim 1, characterized in that, The predetermined threshold is 10nm.

3. The method for preparing a silicon-on-insulator substrate according to claim 2, characterized in that, The thickness of the top silicon layer on the silicon-on-insulator substrate is 1 nm to 3 μm.

4. The method for preparing a silicon-on-insulator substrate according to any one of claims 1 to 3, characterized in that, The steps of scanning etching the top silicon layer of the silicon-on-insulator intermediate using an ion beam according to the designed film thickness removal matrix include: The film thickness removal amount defined by the designed film thickness removal amount matrix is ​​achieved by controlling at least one of the accelerating voltage of the ion beam, the current of the ion beam, the incident angle of the ion beam, and the residence time of the ion beam in different regions of the top silicon layer of the silicon-on-insulator intermediate.

5. The method for preparing a silicon-on-insulator substrate according to any one of claims 1 to 3, characterized in that, The steps for determining the design film thickness removal matrix include: Based on the difference between the initial morphology and the target morphology, the basic film thickness removal matrix is ​​calculated; Based on the reference thermal deformation, the basic film thickness removal matrix is ​​modified to compensate for the etching amount change caused by the range change of the ion beam to the top silicon of the silicon-on-insulator intermediate caused by the reference thermal deformation, thereby obtaining the designed film thickness removal matrix.

6. The method for fabricating a silicon-on-insulator substrate according to any one of claims 1 to 3, characterized in that, The steps for determining the reference thermal deformation include: The top silicon layer of the silicon-on-insulator intermediate is scanned and etched using the ion beam having the aforementioned reference processing parameters; and The reference thermal deformation is obtained by calculating the thermal deformation of the silicon intermediate on the insulator during the scanning etching process.

7. The method for preparing a silicon-on-insulator substrate according to any one of claims 1 to 3, characterized in that, The step of determining the reference thermal deformation includes: calculating the reference thermal deformation based on the voltage and current in the reference processing parameters of the ion beam, as well as the thermal conductivity, coefficient of thermal expansion and elastic modulus of the silicon intermediate on the insulator.

8. The method for preparing a silicon-on-insulator substrate according to claim 7, characterized in that, The voltage of the ion beam is in the range of 500eV to 5keV, and the current of the ion beam is in the range of 5mA to 300mA.

9. The method for preparing a silicon-on-insulator substrate according to any one of claims 1 to 3, characterized in that, After performing the scanning etching according to the designed film thickness removal matrix, the ion beam planarization process further includes: Measuring the film thickness parameters of the top silicon layer of the silicon-on-insulator intermediate; and The designed film thickness removal matrix is ​​corrected based on the measured film thickness parameters.

10. The method for preparing a silicon-on-insulator substrate according to any one of claims 1 to 3, characterized in that, The ion beam planarization process is less than 1×10 -6 The procedure is performed in a vacuum environment of millibars.

11. The method for preparing a silicon-on-insulator substrate according to any one of claims 1 to 3, characterized in that, The silicon-on-insulator intermediate is obtained by at least one of grinding, chemical mechanical planarization, and heat treatment of the bonded wafer.

12. The method for preparing a silicon-on-insulator substrate according to any one of claims 1 to 3, characterized in that, The surface roughness of the top silicon layer of the silicon-on-insulator substrate is less than 0.5 nm.

13. A silicon-on-insulator substrate, said silicon-on-insulator substrate being fabricated using the method for fabricating a silicon-on-insulator substrate according to any one of claims 1 to 12, characterized in that, The silicon-on-insulator substrate includes: Support wafer; A silicon oxide layer disposed on the support wafer; and The top silicon layer disposed on the silicon oxide layer The thickness deviation of the top silicon layer is less than 10 nm, and the thickness of the top silicon layer is in the range of 1 nm to 3 μm.

14. The silicon-on-insulator substrate according to claim 13, characterized in that, The surface roughness of the top silicon layer is less than 0.5 nm.

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