An atomic manipulation method, a chip, and a readable storage medium

Abstract

This application provides an atomic operation method, a chip, and a readable storage medium. The method is applied to a chip, which includes a first core, a second core, and an accelerator. The method includes: the accelerator receiving a first atomic operation sent by the first core and a second atomic operation sent by the second core, and sequentially adding the first and second atomic operations to the accelerator's task queue according to the receiving order; and processing the first and second atomic operations sequentially according to a first-in-first-out (FIFO) principle. Through this process, the accelerator processes only one atomic operation at a time according to the task queue, avoiding multiple atomic operations simultaneously operating on data at the same address, thereby avoiding data contention and data inconsistency problems.

Description

Technical Field

[0001] This application relates to the field of chips, and more particularly to an atomic manipulation method, a chip, and a readable storage medium. Background Technology

[0002] In a chip with multiple cores, while one core is executing a first instruction, other cores executing instructions simultaneously may operate on the same memory region, leading to data races and causing program errors and crashes. To solve this problem, the first core performs atomic operations, exclusively occupying a specific memory address space corresponding to the atomic operation. After completing the data modification operation, it releases its exclusive right to that memory address space. During this process, each core in the chip can be aware of the first core's exclusive control over that memory address space, or the modified data, and can avoid processing that memory address space simultaneously with the first core, thus resolving data races and data inconsistency issues.

[0003] However, if the cores in the chip cannot perceive the exclusive state of the first core over the memory address space, as well as the modified data, the atomic operation performed by any core other than the first core may process the same memory region as the atomic operation performed by the first core, causing the atomic operation to fail to complete normally, resulting in problems such as data races and data inconsistencies. Summary of the Invention

[0004] This application discloses an atomic operation method, a chip, and a readable storage medium. The method involves receiving multiple atomic operations sent by multiple cores in the chip through an accelerator, adding the multiple atomic operations to a task queue in sequence according to the reception time, and processing the multiple atomic operations sequentially according to the first-in-first-out (FIFO) principle. This can avoid the problem of multiple atomic operations operating on the same address at the same time in all chip scenarios, thereby avoiding data race and data inconsistency issues.

[0005] In a first aspect, embodiments of this application provide an atomic operation method applied to a chip, wherein the chip includes a first core, a second core, and an accelerator. The method includes: the accelerator receiving a first atomic operation sent by the first core and a second atomic operation sent by the second core, and adding the first atomic operation and the second atomic operation to the accelerator's task queue in sequence according to the receiving time; the accelerator processing the first atomic operation and the second atomic operation in sequence according to the first-in-first-out principle.

[0006] In summary, the accelerator receives atomic operations from any core in the chip and processes them sequentially according to the FIFO principle. This ensures that only one atomic operation is processed at a time, preventing multiple atomic operations from simultaneously accessing data at the same address and avoiding data contention and inconsistency issues. Furthermore, compared to current methods where each core relies on global chip consistency to execute atomic operations, the atomic operation method provided in this application is applicable to more scenarios. For example, it can be applied to chips with global consistency, chips with global inconsistency, and chips with both local and global consistency, without requiring more complex software or hardware devices.

[0007] For example, in a chip that includes a first subdomain, the first subdomain includes a first core, a second core, and a first temporary memory, and the first core and the second core share data in the first temporary memory, when the first core determines that the first temporary memory includes first data, the first core sends a first atomic operation to the accelerator, the accelerator receives the first atomic operation and puts the first atomic operation into the accelerator's first task queue, wherein the first data is the data corresponding to the first address included in the first atomic operation.

[0008] Similarly, the second core sends the second atomic operation to the accelerator, the accelerator receives the second atomic operation and puts it into the accelerator's first task queue, where the second data is the data corresponding to the first address included in the second atomic operation.

[0009] In the above process, when the first data and the second data are in the first temporary memory, the first core determines that the first atomic operation is an atomic operation within a subdomain, and the second core determines that the second atomic operation is an atomic operation within a subdomain. Each core then sends the first and second atomic operations to the accelerator for execution. Compared to the current method of cores processing atomic operations within subdomains, the accelerator can ensure the normal implementation of atomic operations based on existing atomic operation code, even when there is no cache coherence within the first subdomain and the core cannot guarantee the normal completion of the atomic operation. This eliminates the need to add complex software or hardware devices to the chip for the normal implementation of atomic operations.

[0010] For example, the accelerator processes the first atomic operation and the second atomic operation according to the first-in-first-out principle as follows: The accelerator reads the first data and the second data from the first temporary memory in sequence according to the first-in-first-out principle, generates the third data based on the first data, and generates the fourth data based on the second data. The second data is the data corresponding to the second address included in the second atomic operation. Then, the third data is written back to the first address and the fourth data is written back to the second address in sequence.

[0011] In the above process, after the accelerator reads the first data and the second data, it locks the cache line corresponding to the first data and the second data in the first temporary memory until the third data and the fourth data are written back, and then unlocks the cache line. This can prevent other operations from processing based on the first data and the second data, which could cause data inconsistency and other problems.

[0012] For example, the chip includes a first subdomain, a second subdomain, and a second temporary memory. The first subdomain includes at least one core, the second subdomain includes at least one core, the first subdomain includes a first core, and the second subdomain includes a second core. The at least one core in the first subdomain and the at least one core in the second subdomain share data in the second temporary memory. The specific process of the accelerator receiving a first atomic operation sent by the first core and adding the first atomic operation to the accelerator's task queue is as follows: If the first core determines that the second temporary memory includes fifth data, it sends the first atomic operation to the accelerator. The accelerator receives the first atomic operation and adds it to the accelerator's second task queue, wherein the fifth data is the data corresponding to the third address included in the first atomic operation.

[0013] Similarly, when the second core determines that the second temporary memory includes the sixth data, it sends the second atomic operation to the accelerator. The accelerator receives the second atomic operation and adds it to the accelerator's second task queue. The sixth data is the data corresponding to the fourth address included in the second atomic operation.

[0014] In the above process, when the fifth and sixth data are in the second temporary memory, the first core determines the first atomic operation as an atomic operation between subdomains, and the second core determines the second atomic operation as an atomic operation between subdomains. Each core then sends the first and second atomic operations to the accelerator for execution. Compared to the current kernel's reliance on global consistency to implement atomic operations between subdomains, the accelerator can guarantee the normal implementation of atomic operations between subdomains even when there is no cache consistency between subdomains in the chip and the core cannot guarantee the normal completion of atomic operations between subdomains. This eliminates the need to add complex software or hardware devices to the chip for the proper implementation of atomic operations.

[0015] For example, the accelerator processes the first and second atomic operations according to the first-in-first-out principle as follows: The accelerator reads the fifth and sixth data from the second temporary memory in sequence according to the first-in-first-out principle, generates the seventh data based on the fifth data, and generates the eighth data based on the sixth data. The sixth data is the data corresponding to the fourth address included in the second atomic operation. Then, the seventh data is written back to the third address and the eighth data is written back to the fourth address in sequence.

[0016] In the above process, after reading the fifth and sixth data, the accelerator locks the corresponding cache lines in the first temporary memory until the seventh and eighth data are written back, at which point the cache lines are unlocked. This prevents other operations from processing based on the fifth and sixth data, which could lead to data inconsistencies. Furthermore, compared to the current method of reading data from the second temporary memory to the first temporary memory, then from the first temporary memory to the kernel's private cache, and then modifying and writing back during atomic operations between subdomains, the method provided in this application for the accelerator to perform atomic operations between subdomains can improve data transmission efficiency.

[0017] Secondly, embodiments of this application provide a chip including a first core, a second core, and an accelerator. The accelerator is configured to receive a first atomic operation sent by the first core and a second atomic operation sent by the second core, and to add the first and second atomic operations to the accelerator's task queue; it is also configured to process the first and second atomic operations according to a first-in-first-out (FIFO) principle.

[0018] For example, the chip includes a first subdomain, which includes a first core and a second core, as well as a first temporary memory. The first core and the second core share data in the first temporary memory. The first core is configured to send a first atomic operation to the accelerator when it is determined that the first temporary memory contains first data, wherein the first data is data corresponding to a first address included in the first atomic operation.

[0019] For example, the accelerator is specifically used to read first data and second data sequentially from the first temporary memory according to the first-in-first-out (FIFO) principle, generate third data based on the first data, and generate fourth data based on the second data, wherein the second data is the data corresponding to the second address included in the second atomic operation; and sequentially write the third data back to the first address and the fourth data back to the second address.

[0020] For example, the chip includes a first subdomain, a second subdomain, and a second temporary memory. The first subdomain includes at least one core, the second subdomain includes at least one core, the first subdomain includes a first core, and the second subdomain includes a second core. The at least one core in the first subdomain and the at least one core in the second subdomain share data in the second temporary memory. The first core is configured to send a first atomic operation to the accelerator if it is determined that the second temporary memory contains fifth data, wherein the fifth data is data corresponding to a third address included in the first atomic operation.

[0021] For example, the accelerator is specifically used to read the fifth data and the sixth data sequentially from the second temporary memory according to the first-in-first-out (FIFO) principle, generate the seventh data based on the fifth data, and generate the eighth data based on the sixth data, wherein the sixth data is the data corresponding to the fourth address included in the second atomic operation; and sequentially write the seventh data back to the third address and the eighth data back to the fourth address.

[0022] Thirdly, embodiments of this application also provide an accelerator applied in the chip described in the second aspect for executing the atomic operation method provided in the first aspect.

[0023] Fourthly, embodiments of this application also provide a computer program product containing instructions that, when executed by an accelerator, cause the accelerator to implement the atomic operation method provided in the first aspect.

[0024] Fifthly, embodiments of this application also provide a computer-readable storage medium including computer program instructions, which, when executed by an accelerator, enable the accelerator to implement the atomic operation method provided in the first aspect.

[0025] Based on the implementation methods provided in the above aspects, this application can be further combined to provide more implementation methods. Attached Figure Description

[0026] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below.

[0027] Figure 1 This is a schematic diagram of the structure of a chip provided in an embodiment of this application;

[0028] Figure 2 This is a schematic diagram of another chip structure provided in an embodiment of this application;

[0029] Figure 3 This is a flowchart of an atomic operation method provided in an embodiment of this application;

[0030] Figure 4 This is a flowchart of another atomic operation method provided in the embodiments of this application;

[0031] Figure 5 This is a schematic diagram of the structure of an atomic manipulation device provided in an embodiment of this application;

[0032] Figure 6 This is a schematic diagram of the structure of a computing device provided in an embodiment of this application. Detailed Implementation

[0033] The technical solutions of the embodiments of this application will be described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0034] like Figure 1 As shown, Figure 1 This is a schematic diagram of a chip structure provided in an embodiment of this application. The chip includes multiple sub-domains (tiles) 110, wherein each sub-domain 110 includes at least one core 111, multiple core private caches 112 and a first temporary memory 113. The chip also includes a second temporary memory 120 and a bus 130. The multiple sub-domains 110 and the second temporary memory 120 are connected through the bus 130.

[0035] In specific implementation, the chip is a Central Processing Unit (CPU) chip, and core 111 is a processor core used to independently execute instructions and process data. Multiple cores in the chip can work simultaneously to achieve parallel processing, thereby enabling the system to handle multiple tasks or threads at the same time, accelerating the system's response speed and processing capacity. In one possible implementation, each subdomain may include one core, two cores, or three or more cores. This application does not specifically limit the number of cores in each subdomain.

[0036] In one possible implementation, each subdomain 110 includes multiple cores 111, multiple core-private caches 112, and a first temporary memory 113. Each subdomain 110 may include one core, two cores, or three or more cores; this application does not specifically limit the number of cores in a subdomain. The number of cores included in different subdomains may be exactly the same, completely different, or partially the same. For example, the first subdomain includes 2 cores, the second subdomain includes 2 cores, ..., the nth subdomain includes 2 cores. Alternatively, the first subdomain includes 2 cores, the second subdomain includes 3 cores, ..., the nth subdomain includes n+1 cores. Or, the first subdomain includes 8 cores, the second subdomain includes 2 cores, ..., the nth subdomain includes 2 cores.

[0037] In a specific implementation, the kernel-private cache 112 is used to store frequently used data and instructions from the kernel, reducing the number of accesses to the second temporary memory and thus reducing latency. The kernel-private cache 112 can be a level 1 cache, which is the cache closest to the kernel and the fastest, with a small capacity, including an instruction cache (for storing instructions to be executed) and a data cache (for storing data to be processed). In one possible implementation, the kernel-private cache can also be a level 2 cache, etc. This application does not specifically limit the type of kernel-private cache. The kernel can quickly access and modify the data in the corresponding kernel-private cache, but this will not directly affect the kernel-private caches included in other kernels.

[0038] Each core can only access its own corresponding private cache and cannot access the private caches of other cores, ensuring the independence of each core and the security of its data. In one specific implementation, the chip includes a first subdomain, which includes a first core, a second core, and a third core. The first core includes a first core private cache, the second core includes a second core private cache, and the third core includes a third core private cache. The first core can only access its own private cache and cannot access the second or third core private caches; the second core can only access its own private cache and cannot access the first or third core private caches; and the third core can only access its own private cache and cannot access the first or second core private caches.

[0039] If the core cannot find the target data in the corresponding kernel private cache, it retrieves the target data by searching the first temporary memory included in the subdomain.

[0040] In a specific implementation, the first temporary memory 113 can serve as a subdomain shared cache, and may be a level 2 cache. A level 2 cache is farther from the core than a level 1 cache, is slower, but has a larger capacity. Data in the first temporary memory is shared among multiple cores within the subdomain to which the first temporary memory belongs; that is, any core within the subdomain to which the first temporary memory belongs can process the data in the first temporary memory. In one possible implementation, the second temporary memory may also be a level 3 cache, etc. This application does not specifically limit the type of the first temporary memory. In one possible implementation, each subdomain includes one or more first temporary memories; this application does not specifically limit the number of first temporary memories.

[0041] Each subdomain may include one or more first temporary memories. This application does not specifically limit the number of first temporary memories in a subdomain. The number of first temporary memories included in different subdomains may be exactly the same, completely different, or partially the same. For example, the first subdomain includes 2 first temporary memories, the second subdomain includes 2 first temporary memories, ..., the nth subdomain includes 2 first temporary memories. Alternatively, the first subdomain includes 2 first temporary memories, the second subdomain includes 3 first temporary memories, ..., the nth subdomain includes n+1 first temporary memories. Or, the first subdomain includes 8 first temporary memories, the second subdomain includes 2 first temporary memories, ..., the nth subdomain includes 2 first temporary memories. In a specific embodiment, the number of each first temporary memory can be set according to the number of cores in the subdomain. For example, when the first subdomain includes 2 cores, the first subdomain includes 2 first temporary memories; when the second subdomain includes 3 cores, the second subdomain includes 3 first temporary memories; ...; when the nth subdomain includes n+1 cores, the nth subdomain includes n+1 first temporary memories.

[0042] In a specific implementation, the second temporary memory 120 is a memory chip in the chip, used to store a large amount of data and program code for multiple cores in multiple subdomains to read and write data. The second temporary memory can be double data rate synchronous dynamic random access memory (DDR), or a memory including input output (IO) cache. The second temporary memory can also be more types of memory, which is not specifically limited in this application. Furthermore, this application does not specifically limit the number of second temporary memories in the chip.

[0043] In one possible implementation, the DDR includes operating system and application code and data, while the I / O cache includes data not yet written to persistent memory, data recently read from external devices but not yet processed by the core, and frequently read / written data. The data in the DDR and I / O cache may also include many other types and quantities of data, which are not specifically limited in this application. The data stored in the aforementioned second temporary memory is shared among all cores in multiple subdomains, meaning that any core in the chip can process the data in the second temporary memory.

[0044] In a specific implementation, bus 130 can be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. The bus can be divided into address bus, data bus, control bus, etc. Bus 130 is used to implement data transfer between multiple cores and secondary temporary memory within the subdomain.

[0045] It should be understood that Figure 1 This is merely one possible implementation provided by the embodiments of this application. The chip may also include more types and numbers of components, and this application does not specifically limit this.

[0046] In one possible implementation, in the above Figure 1 In the chip shown, if the first core receives a higher-priority second operation while executing the first operation, it pauses the first operation to process the second, causing the first operation to be interrupted. At this point, only a portion of the first operation has been executed; the remaining portion continues after the second operation finishes processing, resulting in a fragmentation of the first operation. When multiple operations similar to the first core are executed concurrently in the chip, data errors and inconsistencies are likely to occur. Specifically, after one core executes the first operation and reads the first data, another core executes the second operation, also reading and modifying the first data, and writes the modified second data back. Then, the first core modifies the data based on the first data and writes it back.

[0047] The first core can solve the above problem by performing atomic operations through load-reserved (LR) / store-conditional (SC) pairings. The specific process is as follows.

[0048] In one specific implementation, the processor includes four processor cores and two subdomains. The first subdomain includes a first processor core, a second processor core, and a first temporary memory 1. The second subdomain includes a third processor core, a fourth processor core, and a first temporary memory 2. The first and second processor cores share data in the first temporary memory 1, and the third and fourth processor cores share data in the first temporary memory 2. Each core also includes a monitor, which includes a state machine and an address cache. The state machine includes two states: idle and exclusive.

[0049] The first processor core, according to the first atomic operation, reads first data from the first temporary memory 1 into its own core-private cache. It caches the first address, the first data size, and the first processor core identifier in the address cache, sets the state machine to an exclusive state, generates new second data based on the first data and the operation code included in the first atomic operation, and writes the second data back to the first address with the same address and data size as the first data, while the state machine remains in an exclusive state. Then, it modifies the state machine to an idle state, allowing the processor core to execute other atomic operations targeting the first address. At this point, the first atomic operation completes normally. If the state machine is not in an exclusive state, or if the write address corresponding to the new data does not match the address in the address cache, the new data cannot be written. Similarly, the state machine is modified to an idle state, and the first data loading operation is re-executed. This process ensures that atomic operations are not affected by other operations, are not interrupted or fragmented, thus guaranteeing data consistency and correctness.

[0050] During the process where the first processor core modifies the first data into the second data by executing the first atomic operation, if the second processor core can perceive that the first address is in an exclusive state of the first processor core, or can perceive the updated second data, then it can be determined that the first subdomain has cache coherence. Cache coherence refers to a mechanism in a system with multiple processor cores that ensures the consistency of cached data across all processor cores when multiple processor cores share the same data cache. When data in the cache is modified, this modification is visible to all processor cores. If the second processor core cannot perceive that the first address is in an exclusive state of the first processor core, and cannot perceive the updated second data, then it can be determined that the first subdomain does not have cache coherence.

[0051] The above process is a specific execution procedure for atomic operations within a subdomain. The processor core can also implement atomic operations by executing atomic memory operations (AMOs). For example, when the first processor core receives a first atomic operation, it reads first data from the first temporary memory 1 into its own core-private cache based on the first address included in the first atomic operation, and locks the cache line corresponding to the first address to invalidate it, thus ensuring that the cache line cannot be affected by other atomic operations. The first processor core processes the first data and the opcode corresponding to the first atomic operation to obtain second data. After writing the second data back to the first address, it unlocks the cache line corresponding to the first address so that the data corresponding to that cache line can be modified by other atomic operations after the first atomic operation is completed.

[0052] The above description uses atomic operations within a subdomain as an example. The processor chip also includes atomic operations between subdomains. The atomic operations within a subdomain and the atomic operations between subdomains are determined based on the location of the data corresponding to the operation. If the data processed by the atomic operation is in the first temporary memory, the atomic operation is determined to be an atomic operation within a subdomain. If the data processed by the atomic operation is in the second temporary memory, the atomic operation is determined to be an atomic operation between subdomains.

[0053] In one specific implementation, the processor chip further includes a second temporary memory. This second temporary memory is connected to the first and second subdomains via a bus. When the first processor core determines that the third data corresponding to the second address included in the second atomic operation is stored in the second temporary memory, it needs to read the third data from the second temporary memory into the first temporary memory, and then read the third data from the first temporary memory into the core-private cache included in the first processor core. Afterward, the process of executing the second atomic operation is similar to the process of executing the first atomic operation, until the newly generated fourth data is written back to the second address.

[0054] When cache consistency exists between subdomains, the second, third, and fourth processor cores can detect that the second address is exclusively used by the first processor core, thus ceasing simultaneous operations on the third data; alternatively, they can detect the updated fourth data. When cache consistency does not exist between subdomains, the second, third, and fourth processor cores cannot detect that the second address is exclusively used by the first processor core. During the execution of the second atomic operation, the third data may still be affected by other atomic operations, leading to data contention and inconsistency issues.

[0055] In the above process, in order to ensure that the processor core executes atomic operations within the subdomain and atomic operations between subdomains, cache consistency is required both within and between subdomains. This can be called global consistency. However, when cache consistency exists both within and between subdomains, the overhead of maintaining consistency increases as the number of processor cores increases. When the consistency control flow exceeds the processing capacity of the cache and bus, it will lead to a decrease in the performance of multi-core concurrent programs running on the chip.

[0056] Chips with global inconsistency, or chips with both local consistency and global inconsistency, can solve the problems associated with chips with global consistency. In chips with global inconsistency, the processor core cannot detect updates to the first temporary memory and the second temporary memory by any other processor core, nor can it detect the exclusive access of memory addresses by other processor cores. Therefore, the normal implementation of atomic operations and data consistency cannot be guaranteed through the aforementioned atomic operation execution process.

[0057] In chips exhibiting both local consistency and global inconsistency, a processor core can detect updates to data in the first temporary memory within its subdomain, or it can detect the exclusive access of other processor cores to memory addresses in the first temporary memory. Through the execution of the aforementioned atomic operations, the normal implementation of atomic operations and the consistency of data in the first temporary memory can be guaranteed. However, a processor core cannot detect updates to data in the second temporary memory by other processor cores, nor can it detect the exclusive access of other processor cores to memory addresses in the second temporary memory. Therefore, the normal implementation of atomic operations and the consistency of data in the second temporary memory cannot be guaranteed through the aforementioned atomic operation execution process. Both of these processes can reduce the number of communications required to maintain global data consistency, thereby reducing the overhead of maintaining consistency and improving the performance of multi-core concurrent programs. In both scenarios, achieving the normal implementation of atomic operations may require more complex mechanisms or protocols, leading to a decrease in the efficiency of the atomic operation implementation method.

[0058] To address the aforementioned issues, this application provides a novel method for implementing atomic operations: the accelerator receives a first atomic operation sent by a first core and a second atomic operation sent by a second core, adds the first and second atomic operations to the accelerator's task queue, and processes the first and second atomic operations in the task queue sequentially according to the first-in-first-out (FIFO) principle. In this method, the accelerator, through the FIFO principle and the task queue, ensures that only one atomic operation is executed at a time, thereby avoiding multiple atomic operations processing data at the same address simultaneously. This method guarantees the normal implementation of atomic operations in scenarios with globally consistent chips, globally inconsistent chips, or chips with both local and global consistency, eliminating the dependence of atomic operation completion on global consistency and requiring no more complex software or hardware intervention.

[0059] The novel atomic operation implementation method provided in this application is applied to... Figure 2 In the chip shown, Figure 2 This is a schematic diagram of another chip structure provided in an embodiment of this application, such as... Figure 2 As shown, the chip includes multiple subdomains 110, a second temporary memory 120, a bus 130, and an accelerator 140. Each subdomain 110 includes at least one core 111, multiple core private caches 112, and a first temporary memory 113. The multiple subdomains 110 and the second temporary memory 120 are connected through the bus 130.

[0060] In its specific implementation, core 111 includes a memory management unit (MMU) 11 and an atomic operation memory (ATOM dispatcher) 12.

[0061] The memory management unit 11 is used to support the translation of virtual addresses to physical addresses and to manage virtual memory; it is used to provide memory access permission control for different processes or tasks and to support different memory access modes, such as read-only, read-write, etc. The MMU can utilize memory resources more efficiently, thereby ensuring the security and stability of the chip.

[0062] The memory management unit 11 includes a translation lookaside buffer (TLB). The TLB contains a correspondence between memory addresses and their respective temporary storage locations, or between memory addresses and shared attributes. When a memory address is in a first temporary storage location, the data at that memory address is shared among multiple cores within the subdomain to which that first temporary storage location belongs. When a memory address is within a second temporary storage location, the data at that memory address is shared among all cores in the chip. Specifically, the shared attribute corresponding to a memory address in the TLB can be identified by 0 or 1. For example, if the memory address is identified as 1, it is determined that the memory address belongs to the second temporary storage location, and the data at that memory address is shared among multiple cores in multiple subdomains. Alternatively, if the memory address is identified as 0, it is determined that the memory address belongs to the first temporary storage location, and the data at that memory address is shared among multiple cores within a certain subdomain. It should be understood that the temporary storage location to which a memory address belongs, or the shared attribute of a memory address, can also be represented in other ways, and this application does not specifically limit this representation.

[0063] exist Figure 2 In the case of a chip with local consistency and global inconsistency, the core can determine whether the data corresponding to the memory address has a consistency attribute by using the shared attributes of the memory address. For example, if the memory management unit determines that the memory address is in the second temporary memory and the data in the memory address is shared among multiple cores in multiple subdomains, the data is determined to have no consistency attribute. If the memory management unit determines that the memory address is in the first temporary memory and the data in the memory address is shared among multiple cores in the subdomains to which the first temporary memory belongs, the data is determined to have a consistency attribute.

[0064] The atomic operation dispatch unit 12 can be implemented in software or hardware. It is used to determine the location of the address included in the atomic operation and send the atomic operation to the accelerator. The address may belong to the first temporary memory or the second temporary memory.

[0065] In one possible implementation, regardless of Figure 2 Whether the chip shown has global consistency is determined by the atomic operation distribution unit sending all atomic operations to the accelerator.

[0066] In another possible implementation, since, in Figure 2The chip shown exhibits both local consistency and global inconsistency. When the atomic operation is a subdomain-level atomic operation, the core may not need to send it to the accelerator. It can implement the atomic operation normally through load-reserved (LR) / store-conditional (SC) pairing or by executing atomic memory operations (AMO). In this case, the atomic operation dispatch unit determines the location of the address included in the atomic operation. It sends the atomic operation to the accelerator only if the address belongs to the second temporary memory; if the address belongs to the first temporary memory, it stops sending the atomic operation, determining that the atomic operation is implemented by the core.

[0067] Core 111 also includes an instruction fetch unit (IFU) 13, a load / store unit (LSU) 14, and an arithmetic and logic unit (ALU) 15. The instruction fetch unit receives atomic operation instructions; the load / store unit, when the core performs an atomic operation, loads the data at the address corresponding to the atomic operation from the first temporary memory into the core's private cache, locks the cache line at the address corresponding to the atomic operation, stores modified data at the address corresponding to the atomic operation, and unlocks the cache line at the address corresponding to the atomic operation; the arithmetic and logic unit calculates new data based on the opcode of the atomic operation and the data at the address corresponding to the atomic operation, and sends the data to the load / store unit.

[0068] In a specific implementation, the accelerator 140 can be deployed on the bus 130 as a hardware accelerator controller (HAC) or integrated on the second temporary memory 120; this application does not specifically limit this. The number of accelerators 140 can be one or more. For example, when there are multiple accelerators 140, one can be a primary accelerator and another a backup accelerator. When the primary accelerator is working normally, the backup accelerator does not operate; when the primary accelerator fails, the backup accelerator takes over and operates normally.

[0069] A hardware acceleration controller is a specially designed hardware component or integrated circuit used to accelerate specific types of computations or operations through specialized hardware logic and circuitry. For example, an encryption hardware acceleration controller is specifically designed for the rapid execution of encryption and decryption algorithms; a network hardware acceleration controller can quickly handle operations such as routing, forwarding, and security checks of network packets. By offloading the CPU's workload, the hardware acceleration controller enables the system to complete more tasks in a shorter time, thereby improving performance. Figure 2 The chip's performance and efficiency are shown. When integrated into the second temporary memory, the accelerator is a specially designed hardware module, including arithmetic logic units, ensuring that atomic operations are completed within the second temporary memory without needing to transfer data to the core for processing. This reduces data transfer latency and overhead, improving the execution efficiency of atomic operations.

[0070] Accelerator 140 communicates with multiple cores 111 included in subdomain 110 via bus 130.

[0071] Accelerator 140 is used to receive and execute atomic operation instructions sent by the atomic operation distribution unit in the core. The atomic operation instructions sent by the atomic operation distribution unit include a subdomain identifier, a core identifier, an opcode, the address corresponding to the atomic operation, and operands. The core identifier indicates the core that sent the atomic operation, and the subdomain identifier indicates the subdomain to which the core that sent the atomic operation belongs. Specifically, when receiving atomic operations sent by multiple cores within multiple subdomains, the accelerator places the atomic operations into a task queue sequentially according to their arrival time, so that the accelerator processes multiple atomic operations sequentially according to a first-in-first-out principle. For example, if the accelerator first receives the first atomic operation within a subdomain sent by the first core, and then receives the second atomic operation within a subdomain sent by the second core, the accelerator first adds the first atomic operation to the first task queue, and then adds the second atomic operation to the first task queue, so that the accelerator processes the first atomic operation first, and then processes the second atomic operation. The accelerator receives a third atomic operation outside the subdomain sent by the third core, and then receives a fourth atomic operation outside the subdomain sent by the fourth core. The accelerator first adds the third atomic operation to the second task queue, and then adds the fourth atomic operation to the second task queue, so that the accelerator processes the third atomic operation first and then processes the fourth atomic operation.

[0072] Accelerator 140 is used to read data from the address corresponding to the atomic operation from either the first temporary memory or the second temporary memory, and lock the cache line corresponding to the address included in the atomic operation. Then, the arithmetic logic unit 15 in the accelerator calculates new data based on the read data and the opcode of the atomic operation. After writing the new data back to the address corresponding to the atomic operation, the accelerator unlocks the address. After completing the atomic operation, the accelerator sends an atomic operation completion message to a core in the corresponding subdomain based on the subdomain identifier and core identifier in the atomic operation. The software code for handling atomic operations in the accelerator is the same as the software code for handling atomic operations in a globally consistent chip. It does not require more complex software and hardware mechanisms to ensure the consistency of caches shared between multiple cores in different subdomains, thus simplifying the implementation of atomic operations.

[0073] It should be understood that Figure 2 This is merely one possible implementation provided by the embodiments of this application. The chip may also include more types and numbers of components, and this application does not specifically limit this.

[0074] like Figure 3 As shown, Figure 3 This is a flowchart of an atomic operation method provided in an embodiment of this application, which is applied to... Figure 2 In the chip shown, the method includes the following steps.

[0075] S310: The first core receives the first atomic operation, determines the temporary memory to which the first address corresponding to the first atomic operation belongs, and sends the first atomic operation to the accelerator.

[0076] The first core is any core in any subdomain of the chip.

[0077] An atomic operation includes bits, an opcode, the address corresponding to the atomic operation, and operands. The bit value indicates that the operation is atomic; it can be 1, or 0, indicating a non-atomic read / write operation. Alternatively, a bit value of 1 also indicates a non-atomic read / write operation. Other possible values ​​for the bit indicating an atomic operation are not specifically limited in this application. The opcode is a set of binary codes determined by the processor architecture in the chip. It determines the type of atomic operation, such as an atomic read-modify-write operation or an atomic comparison / swap operation. This application does not specifically limit the type of atomic operation. The address is determined based on the processor architecture in the chip, and the data corresponding to that address is the data processed by the atomic operation. Operands are used to determine the conditions and data for the atomic operation. These can be data values ​​to be stored at a specified address. In the case of an atomic comparison and swap operation, the operands can include the value to be compared with the data value in memory, and the value to be written if the comparison is successful, to ensure the correct execution of the atomic operation. Specifically, the atomic operation includes a first operand 6 and a second operand 2. If the data read from the address corresponding to the atomic operation is 6, it is determined that it is the same as the first operand, and the second operand 2 is then written to the address corresponding to the atomic operation. In one possible implementation, the atomic operation may also include more types and quantities of data, which is not specifically limited in this application. The address corresponding to an atomic operation can be a physical address, a virtual address, or a logical address. A physical address is the actual memory location address, which can be a 32-bit or 64-bit consecutive sequence of numbers, represented in hexadecimal form, for example, from 0x00000000 to 0xFFFFFFFF. Hardware accesses data based on the physical address. When the address corresponding to the atomic operation is a virtual address, the virtual address can be converted to a physical address by the MMU, and its representation is similar to that of the physical address. A logical address can consist of a memory segment number and an offset. For example, when the memory segment size is 4KB (i.e., 0x1000), 2:0x500 represents the address at offset 0x500 within the second memory segment. The address type can be determined based on memory management mechanisms, etc. This application does not specifically limit the address type for atomic operations.

[0078] Temporary storage can be either the first temporary storage within a subdomain or the second temporary storage outside the subdomain.

[0079] The first core receives the instruction for the first atomic operation through a specific instruction set interface. Then, it decodes the instruction for the first atomic operation to determine the atomic operation type and the first address corresponding to the atomic operation. The atomic operation type includes atomic read-modify-write operations, atomic compare-swap operations, etc. After determining the first address, the first core queries the TLB in the memory management unit to determine the physical memory address corresponding to the first address and the temporary storage to which the data corresponding to the first address belongs. Then, it sends the first atomic operation to the accelerator.

[0080] In one specific implementation, in the TLB such as Figure 2 In the case shown, when the identifier corresponding to the physical memory address corresponding to the first address is 0 according to the TLB, the first core determines that the first data corresponding to the first address belongs to the first temporary memory. The data corresponding to the first address is shared among multiple cores in the subdomain to which the first temporary memory belongs, and the first atomic operation is determined to be an atomic operation within the subdomain.

[0081] In another specific implementation, in the TLB such as Figure 2 In the case shown, when the first core determines that the identifier corresponding to the physical memory address corresponding to the first address is 1 according to the TLB, it determines that the first data corresponding to the first address belongs to the second temporary memory. The first data corresponding to the first address is shared among multiple cores in multiple subdomains in the chip, and the first atomic operation is determined to be an atomic operation between subdomains.

[0082] The first core sends a first atomic operation to the accelerator. This first atomic operation includes an opcode, a first address, and operands, as well as a first subdomain identifier and a first core identifier. The first core identifier indicates the first core sending the first atomic operation, and the first subdomain identifier indicates the subdomain to which the first core belongs. Both the first core identifier and the first subdomain identifier can be represented by decimal numbers. For example, if the first core identifier is 3 and the first subdomain identifier is 2, then the first atomic operation is determined to be... Figure 2 The second subdomain in the system shown is sent by the third core. In one possible implementation, the first core identifier and the first subdomain identifier can also be represented in binary or other forms, which is not specifically limited in this application.

[0083] In one possible implementation, the first core encodes and encapsulates the first atomic operation to be sent to the accelerator, so that the first atomic operation includes data such as a first subdomain identifier, a first core identifier, an opcode, a first address, and operands. In addition, if there are multiple atomic operations to be sent, the first core performs priority judgment and sorts the multiple atomic operations. Then, through communication methods such as bus protocols, the atomic operations are sent to the accelerator in order of priority. This application does not specifically limit the communication method between the core and the accelerator.

[0084] In the above process, the first core does not directly execute the atomic operation. Instead, it first checks the temporary memory corresponding to the first address of the first atomic operation to determine whether the atomic operation is an intra-subdomain or inter-subdomain atomic operation. Then, it sends the atomic operation to the accelerator for execution. This process avoids situations where the core cannot complete the atomic operation correctly in globally inconsistent chips, or in chips with both local and global consistency, thus preventing data inconsistency issues.

[0085] Similarly, other cores in the chip, following the process described above, determine the temporary memory corresponding to the address of each atomic operation after receiving the atomic operation, and then send the atomic operation to the accelerator.

[0086] S320: The second core receives the second atomic operation, determines the temporary memory to which the second address corresponding to the second atomic operation belongs, and sends the second atomic operation to the accelerator.

[0087] S330: The accelerator receives the first atomic operation and the second atomic operation, and adds the first atomic operation and the second atomic operation to the accelerator's task queue.

[0088] In one possible implementation, the accelerator receives a first atomic operation and a second atomic operation, determines that both the first atomic operation and the second atomic operation are atomic operations within a subdomain, and adds the first atomic operation and the second atomic operation to the accelerator's first task queue according to the reception time.

[0089] For example, the accelerator first receives the first atomic operation sent by the first core, then receives the second atomic operation sent by the second core. After that, the first atomic operation is added to the first task queue, and then the second atomic operation is added to the first task queue. Both the first and second atomic operations are atomic operations within a subdomain.

[0090] In another possible implementation, the accelerator receives a first atomic operation and a second atomic operation, determines that both the first atomic operation and the second atomic operation are atomic operations between subdomains, and adds the first atomic operation and the second atomic operation to the accelerator's second task queue.

[0091] It should be understood that the accelerator can also add all received atomic operations to a single task queue without needing to determine the type of the atomic operation.

[0092] S340: The accelerator processes the first and second atomic operations according to the first-in-first-out principle.

[0093] The accelerator processes the first atomic operation and the second atomic operation sequentially according to the first-in-first-out (FIFO) principle and the task queue. If both the first and second atomic operations are intra-subdomain atomic operations or inter-subdomain atomic operations, they are processed sequentially according to the FIFO principle. If the first and second atomic operations have different operation types, the accelerator can process them based on principles such as task priority and resource availability.

[0094] In one specific implementation, the accelerator sequentially receives a first atomic operation, a second atomic operation, a third atomic operation, and a fourth atomic operation. The first and third atomic operations are atomic operations within a subdomain, and are sequentially added to a first task queue. The second and fourth atomic operations are atomic operations between subdomains, and are sequentially added to a second task queue. The accelerator may first process the first atomic operation in the first task queue, then process the second atomic operation in the second task queue, then process the third atomic operation in the first task queue, and finally process the fourth atomic operation in the second task queue.

[0095] When the accelerator is deployed on the bus as a hardware acceleration controller, the process of the accelerator performing the first atomic operation between subdomains is as follows: First data corresponding to the first address is read from the second temporary memory and loaded into the data buffer in the accelerator. The cache line corresponding to the first address in the second temporary memory is locked. Then, through the arithmetic logic unit in the accelerator, new data is calculated based on the opcode, operands, and data corresponding to the first address of the first atomic operation (e.g., data addition or data exchange). The new second data is then rewritten to the first address of the second temporary memory. Finally, the cache line corresponding to the first address in the temporary memory is unlocked, completing the first atomic operation. Based on the first subdomain identifier and the first core identifier included in the first atomic operation, the accelerator determines that the first core within the first subdomain sent the first atomic operation and sends the first atomic operation completion information to the first core within the first subdomain, so that the first core can confirm the completion of the first atomic operation.

[0096] When the accelerator is integrated on the second temporary memory, the process of the accelerator receiving and executing the first atomic operation is similar to the process described above, and will not be repeated here.

[0097] In the above process, because the accelerator follows a first-in, first-out (FIFO) principle, it processes only one atomic operation from the task queue at a time, avoiding the simultaneous processing of multiple atomic operations. This prevents data at the same address in temporary storage from being affected by different atomic operations at the same time, thus avoiding problems such as data races and data inconsistencies. Compared to the current method of kernel processing atomic operations, the process of the accelerator executing the first atomic operation is the same as that of the kernel. Therefore, the operation code for the accelerator to execute atomic operations is the same as that for the kernel, requiring no modification to the atomic operation code and no additional software or hardware mechanisms needed for the implementation of atomic operations.

[0098] Furthermore, during the execution of atomic operations by the accelerator, data only needs to be read from the temporary memory into the accelerator cache for processing. This is simpler and more efficient than the current process of the core reading data from the second temporary memory into the first temporary memory and then reading the data from the first temporary memory into the core's private cache.

[0099] The atomic operation method provided in the above embodiments of this application is applied to Figure 2 The chip shown may have global consistency, global inconsistency, or both local consistency and global inconsistency; this application does not specifically limit this.

[0100] In summary, the atomic operation method provided in this application embodiment receives multiple atomic operations sent by all cores in the chip via an accelerator, adds the atomic operations to a task queue according to the reception time, and processes multiple atomic operations sequentially according to a first-in-first-out principle. This method avoids the situation where multiple atomic operations simultaneously operate on data at the same address, thus preventing data contention and inconsistency issues. Furthermore, compared to current methods where each core relies on global consistency to execute atomic operations, the atomic operation method provided in this application embodiment is applicable to more scenarios and solves the problem of the normal implementation of atomic operations depending on global consistency.

[0101] In chips with global consistency, as the number of processor cores increases, the overhead of maintaining cache consistency in temporary memory across multiple cores also increases. When consistency control traffic exceeds the processing capacity of the cache and bus, it leads to a performance degradation of multi-core concurrent programs running on the chip. In chips with global inconsistency, explicit management of data distribution and synchronization across cores is required. This makes program coding more difficult and error-prone, and data communication between cores requires explicit code, resulting in poor compatibility and making many applications unportable or difficult to port, thus reducing the versatility of such chips. Chips with both local consistency and global inconsistency offer better overall performance and can be widely used.

[0102] like Figure 4 As shown, Figure 4 This is a flowchart of another atomic operation method provided in an embodiment of this application, which is also applicable to... Figure 2 The chip shown in this embodiment is, in the case of... Figure 2 The chip shown is an example of a chip with local consistency and global inconsistency. The method includes the following steps.

[0103] S410: The first core receives the first atomic operation and determines the temporary memory to which the first address corresponding to the first atomic operation belongs.

[0104] The first core is any core in any subdomain of the chip.

[0105] The specific content of atomic operations is the same as that described in step S310, and will not be repeated here.

[0106] Temporary storage can be either the first temporary storage within a subdomain or the second temporary storage outside the subdomain.

[0107] The first core receives the instruction of the first atomic operation through a specific instruction set interface. Then, it decodes the instruction of the first atomic operation, determines the atomic operation type and the first address corresponding to the atomic operation, and after determining the first address, the first core queries the TLB in the memory management unit to determine the temporary memory to which the first address belongs.

[0108] In the embodiments of this application, when the chip is a chip with local consistency and global inconsistency, modifications to the data in the first temporary memory or exclusive access to the cache line can be perceived by other cores in the subdomain to which the first temporary memory belongs. However, modifications to the data in the second temporary memory or exclusive access to the cache line cannot be perceived by other cores in the chip.

[0109] When the first core determines the first temporary memory to which the first address belongs based on the TLB, it determines that the first atomic operation is an atomic operation within a subdomain. Since the chip's local consistency allows the first atomic operation to be executed directly, the first core executes step S420.

[0110] When the first core determines the second temporary memory to which the first address belongs based on the TLB, it determines that the first atomic operation is an atomic operation between subdomains. Since the chip has no global consistency, the first core cannot guarantee the normal implementation of the first atomic operation, and the first core executes step S430.

[0111] In the above process, the first kernel does not directly execute atomic operations. Instead, it first judges the temporary memory to which the first address corresponding to the first atomic operation belongs, determines the type of different atomic operations, and determines the different execution methods of atomic operations. This ensures that atomic operations are completed normally in a chip with local consistency and global inconsistency, and avoids data inconsistency caused by atomic operations between subdomains executed by the kernel.

[0112] S420: The first core performs the first atomic operation.

[0113] The first core executes the first atomic operation according to the opcode included in the first atomic operation, following predetermined hardware logic and protocols.

[0114] In one possible implementation, the first core sends a first atomic operation to a load / store queue. The first core retrieves the first atomic operation from the load queue, loads the data at the first address corresponding to the first atomic operation from the first temporary memory into the core's private cache, and locks the cache line corresponding to the first address in the first temporary memory. The arithmetic logic unit in the first core calculates new data based on the data at the loaded first address and the opcode of the first atomic operation, and sends the new data to the storage queue. The core retrieves an atomic write request from the storage queue, writes the new data to the first address in the first temporary memory, and unlocks the cache line corresponding to the first address after writing the new data.

[0115] In another possible implementation, if the first core includes a monitor, the first core sends a first atomic operation to the load / store queue. If the data corresponding to the first address is not included in the core's private cache, the first core loads the data corresponding to the first address from the first temporary memory into the core's private cache and stores the first address in the address cache included in the monitor, modifying the state machine included in the monitor to an exclusive state. Then, the first core calculates new data based on the data read from the first address, the opcode and operand of the first atomic operation, and writes the new data into the first temporary memory. Before writing the new data, the first core needs to check the state machine and the address cache again. In one possible implementation, if it is determined that the state machine is still in an exclusive state and the address in the address cache is the same as the write address, the first core performs a data write operation and sets the state machine to an idle state; if it is determined that the state machine is not in an exclusive state but is in an idle state, or if the address in the address cache is different from the write address, the data write operation is not performed, the state machine is reset to an idle state, and the first core re-executes the corresponding data load operation based on the first atomic operation.

[0116] In the above process, the first core executes the first atomic operation through the existing atomic operation code, and after modifying the data at the first address, multiple cores in the subdomain to which the first core belongs can be aware of the modification of the data at the first address, thereby maintaining cache consistency among multiple cores in the subdomain.

[0117] S430: The first core sends the first atomic operation to the accelerator.

[0118] When the first core determines that the first atomic operation pertains to the second temporary memory containing the first address, it determines that the first atomic operation is an inter-subdomain atomic operation. Due to the global inconsistency of the chip, the first core cannot guarantee the normal implementation of the first atomic operation and sends it to the accelerator. At this time, the first atomic operation includes not only the opcode, the first address, and the operands, but also a first subdomain identifier and a first core identifier. The first core identifier indicates the first core that sent the first atomic operation, and the first subdomain identifier indicates the subdomain to which the first core that sent the first atomic operation belongs.

[0119] In the above process, the first core cannot guarantee the normal implementation of the first atomic operation in a chip with global inconsistency, nor can it guarantee data consistency. Sending the first atomic operation to the accelerator can guarantee the normal implementation of the atomic operation and avoid situations such as multiple cores processing the same data in the second temporary memory at the same time.

[0120] S440: The accelerator receives the first atomic operation, adds it to the task queue, and processes it according to the first-in-first-out principle.

[0121] In addition to receiving the first atomic operation sent by the first core, the accelerator can also receive... Figure 2 In the system shown, multiple kernels within multiple subdomains each send multiple atomic operations. At this time, the received atomic operations are all inter-subdomain atomic operations. The accelerator adds the atomic operations, including the first atomic operation, to the task queue according to the receiving order and processes them according to a first-in, first-out (FIFO) principle.

[0122] The process of the accelerator performing atomic operations is similar to step S340 above, and will not be repeated here.

[0123] In the above process, before executing an atomic operation, the core in the chip first determines whether the atomic operation is an atomic operation within a subdomain or an atomic operation outside the subdomain. If the atomic operation is an atomic operation within a subdomain and the chip has local consistency, the core can execute the atomic operation using the existing atomic operation code. If the atomic operation is an atomic operation between subdomains and the chip has global inconsistency, the core sends the atomic operation to the accelerator so that the accelerator can process the atomic operation according to the task queue and the first-in-first-out principle. This can ensure the normal completion of various atomic operations in the chip with both local consistency and global inconsistency, avoid data race problems, and thus maintain data consistency. Furthermore, the core and the accelerator complete the atomic operation using the same atomic operation code, without the need for more complex software and hardware mechanisms.

[0124] like Figure 5 As shown, Figure 5 This is a schematic diagram of an atomic manipulation device provided in an embodiment of this application. The atomic manipulation device 500 includes a receiving unit 510 and a processing unit 520, and can be deployed in an accelerator. The receiving unit 510 is used to receive a first atomic operation sent by a first core and add the first atomic operation to the accelerator's task queue; and to receive a second atomic operation sent by a second core and add the second atomic operation to the accelerator's task queue. The processing unit 520 is used to process the first and second atomic operations according to a first-in, first-out (FIFO) principle.

[0125] For example, in a chip comprising a first subdomain, the first subdomain comprising a first core and a second core, and a first temporary memory, wherein the first core and the second core share data in the first temporary memory, the receiving unit 510 is configured to, when the first core determines that the first temporary memory contains first data, receive a first atomic operation sent by the first core and add the first atomic operation to the first task queue of the accelerator, wherein the first data is the data corresponding to the first address included in the first atomic operation. Similarly, when the second core determines that the first temporary memory contains second data, receive a second atomic operation sent by the second core and add the second atomic operation to the first task queue of the accelerator, wherein the second data is the data corresponding to the second address included in the second atomic operation.

[0126] For example, the processing unit 520 is configured to read first data and second data sequentially from the first temporary memory according to the first-in-first-out (FIFO) principle, generate third data based on the first data, generate fourth data based on the second data, and then sequentially write the third data back to the first address and the fourth data back to the second address.

[0127] For example, in a chip comprising a first subdomain, a second subdomain, and a second temporary memory, wherein the first subdomain includes at least one core, the second subdomain includes at least one core, the first subdomain includes a first core, the second subdomain includes a second core, and the at least one core in the first subdomain and the at least one core in the second subdomain share data in the second temporary memory, the receiving unit 510 is configured to receive a first atomic operation sent by the first core when the first core determines that the second temporary memory includes fifth data, and to add the first atomic operation to the second task queue of the accelerator, wherein the fifth data is the data corresponding to the third address included in the first atomic operation. Similarly, the receiving unit 510 is configured to receive a second atomic operation sent by the second core when the first core determines that the second temporary memory includes sixth data, and to add the second atomic operation to the second task queue of the accelerator, wherein the sixth data is the data corresponding to the fourth address included in the second atomic operation.

[0128] For example, the processing unit 520 is configured to read the fifth data and the sixth data sequentially from the second temporary memory according to the first-in-first-out (FIFO) principle, generate the seventh data based on the fifth data, generate the eighth data based on the sixth data, and then write the seventh data back to the third address and the eighth data back to the fourth address sequentially.

[0129] In one possible implementation, the atomic operation apparatus further includes a sending unit 530, which is configured to send an atomic operation completion message to a core of the corresponding subdomain based on the subdomain identifier and the core identifier included in the atomic operation after the processing unit has finished processing the atomic operation.

[0130] Specifically, the receiving unit 510 can perform... Figure 3 The steps S330 and S330 shown are as follows: Figure 4 The processing unit 520 can execute some of the operations in step S440 shown. Figure 3 The steps S340 and S340 shown are as follows: Figure 4 The steps in step S440 shown are partial operations. In other embodiments, the specific steps performed by the receiving unit 510, processing unit 520, and sending unit 530 can be specified as needed, and this application does not impose specific limitations.

[0131] It should be understood that Figure 5 This is merely one possible implementation provided by the embodiments of this application. The atomic manipulation device may also include more types and numbers of units, and this application does not specifically limit this.

[0132] like Figure 6 As shown, Figure 6 This is a schematic diagram of a computing device 600 provided in an embodiment of this application. The computing device 600 includes: a bus 610, a processor 620, a memory 630, a communication interface 640, and an accelerator 650. The processor 620, memory 630, communication interface 640, and accelerator 650 communicate with each other via the bus 610. The computing device 600 can be a server. It should be understood that this application does not limit the number of processors, memory, and accelerators in the computing device 600. The computing device 600 can be used for deployment. Figure 2 The chip shown.

[0133] The bus 610 can be a Peripheral Component Interconnect Express (PCIe) bus, an Extended Industry Standard Architecture (EISA) bus, a Unified Bus (Ubus or UB), a Compute Express Link (CXL), a Cache Coherent Interconnect for Accelerators (CCIX), etc. The Unified Bus is also known as the Lingqu Bus. Buses can be divided into address buses, data buses, control buses, etc. For ease of representation, Figure 6 The bus is represented by only one line, but this does not mean that there is only one bus or one type of bus. Bus 610 may include a path for transmitting information between various components of computing device 600 (e.g., processor 620, memory 630, communication interface 640, and accelerator 650). The unified bus may also be referred to as the Lingqu bus.

[0134] The processor 620 may include any one or more of the following: a central processing unit (CPU), a graphics processing unit (GPU), a microprocessor (MP), a digital signal processor (DSP), an offload card, etc. In this embodiment, the processor 620 includes multiple processor cores 621, and this application does not specify a particular number of processor cores.

[0135] Memory 630 may include volatile memory, such as random access memory (RAM). Memory 630 may also include non-volatile memory, such as read-only memory (ROM), flash memory, hard disk drive (HDD), or solid-state drive (SSD). Furthermore, memory 630 may also be implemented using storage class memory (SCM), phase change memory (PCM), or other types of storage media. It is worth noting that the same type of storage media can be configured in the same computing device to implement the function of memory 630, or two or more types of storage media can be configured to implement the function of memory 630; this application does not limit this.

[0136] The memory stores executable program code corresponding to one or more of the receiving unit 510, processing unit 520, and transmitting unit 530. The accelerator, by executing the executable program code, can respectively implement the functions of the aforementioned receiving unit 510, processing unit 520, and transmitting unit 530. The memory also stores executable program code corresponding to one or more of the memory management unit 11, atomic operation dispatch unit 12, instruction fetching unit 13, load / store unit 14, and arithmetic logic unit 15. The processor, by executing the executable program code, can respectively implement the functions of the aforementioned multiple units, thereby achieving… Figure 3 and Figure 4 The atomic operation method shown refers to the memory 630 storing instructions for performing the atomic operation method. Furthermore, the memory 630 may also store more types and quantities of data, such as data read or written by atomic operations; this application does not specifically limit this.

[0137] The communication interface 640 uses transceiver modules, such as, but not limited to, network interface cards and transceivers, to enable communication between the computing device 600 and other devices or communication networks.

[0138] It should be understood that Figure 6 This is one possible implementation provided by the embodiments of this application. The computing device may also include more or fewer devices, and this application does not make specific limitations in this regard.

[0139] This application also provides a computer-readable storage medium storing instructions that, when executed on a processor, Figure 3 and Figure 4 The atomic operation method flow shown is thus implemented.

[0140] This application also provides a computer program product that, when run on an accelerator, Figure 3 The atomic operation method flow shown is thus implemented.

[0141] When computer program instructions are loaded or executed on a computer, all or part of the processes or functions according to the embodiments of this application are generated. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device.

[0142] Computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, computer instructions can be transmitted from one website, computer, server, or data center to another via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. A computer-readable storage medium can be any available medium that a computer can access, or a data storage node such as a server or data center that contains at least one set of available media. Available media can be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., high-density digital video discs (DVDs), or semiconductor media).

[0143] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for implementing atomic operations, characterized in that, This method is applied to a chip, wherein the chip includes a first core, a second core, and an accelerator, and the method includes: The accelerator receives the first atomic operation sent by the first core and adds the first atomic operation to the accelerator's task queue. The accelerator receives the second atomic operation sent by the second core and adds the second atomic operation to the task queue of the accelerator. The accelerator processes the first atomic operation and the second atomic operation according to the first-in-first-out (FIFO) principle.

2. The method according to claim 1, characterized in that, The chip includes a first subdomain, which includes a first core and a second core, as well as a first temporary memory, wherein the first core and the second core share data in the first temporary memory; The accelerator receiving a first atomic operation sent by the first core and adding the first atomic operation to the accelerator's task queue includes: When the first core determines that the first temporary memory contains the first data, the accelerator receives the first atomic operation sent by the first core and adds the first atomic operation to the first task queue of the accelerator, wherein the first data is the data corresponding to the first address included in the first atomic operation.

3. The method according to claim 2, characterized in that, The accelerator processes the first atomic operation and the second atomic operation according to the first-in-first-out (FIFO) principle, including: The accelerator reads the first data and the second data from the first temporary memory in sequence according to the first-in-first-out (FIFO) principle, generates the third data based on the first data, and generates the fourth data based on the second data, wherein the second data is the data corresponding to the second address included in the second atomic operation; The accelerator sequentially writes the third data back to the first address and the fourth data back to the second address.

4. The method according to claim 1, characterized in that, The chip includes a first subdomain, a second subdomain, and a second temporary memory. The first subdomain includes at least one core, the second subdomain includes at least one core, the first subdomain includes the first core, the second subdomain includes the second core, and the at least one core in the first subdomain and the at least one core in the second subdomain share data in the second temporary memory. The accelerator receiving a first atomic operation sent by the first core and adding the first atomic operation to the accelerator's task queue includes: When the first core determines that the second temporary memory contains fifth data, the accelerator receives the first atomic operation sent by the first core and puts the first atomic operation into the second task queue of the accelerator. The fifth data is the data corresponding to the third address included in the first atomic operation.

5. The method according to claim 4, characterized in that, The accelerator processes the first atomic operation and the second atomic operation according to the first-in-first-out (FIFO) principle, including: The accelerator reads the fifth and sixth data sequentially from the second temporary memory according to the first-in-first-out (FIFO) principle, generates the seventh data based on the fifth data, and generates the eighth data based on the sixth data, wherein the sixth data is the data corresponding to the fourth address included in the second atomic operation; The accelerator sequentially writes the seventh data back to the third address and the eighth data back to the fourth address.

6. A chip, characterized in that, The chip includes a first core, a second core, and an accelerator: The accelerator is used to receive the first atomic operation sent by the first core and put the first atomic operation into the task queue of the accelerator. The accelerator is configured to receive the second atomic operation sent by the second core and add the second atomic operation into the task queue of the accelerator. The accelerator is used to process the first atomic operation and the second atomic operation according to the first-in-first-out (FIFO) principle.

7. The chip according to claim 6, characterized in that, The chip includes a first subdomain, which includes a first core and a second core, as well as a first temporary memory, wherein the first core and the second core share data in the first temporary memory; The first core is configured to send the first atomic operation to the accelerator when it is determined that the first temporary memory contains first data, wherein the first data is the data corresponding to the first address included in the first atomic operation.

8. The chip according to claim 7, characterized in that, The accelerator is specifically used for, According to the first-in-first-out (FIFO) principle, the first data and the second data are read sequentially from the first temporary memory, and the third data is generated based on the first data, and the fourth data is generated based on the second data, wherein the second data is the data corresponding to the second address included in the second atomic operation; The third data is written back to the first address in sequence, and the fourth data is written back to the second address.

9. The chip according to claim 6, characterized in that, The chip includes a first subdomain, a second subdomain, and a second temporary memory. The first subdomain includes at least one core, the second subdomain includes at least one core, the first subdomain includes the first core, the second subdomain includes the second core, and the at least one core in the first subdomain and the at least one core in the second subdomain share data in the second temporary memory. The first core is configured to send the first atomic operation to the accelerator if it is determined that the second temporary memory contains fifth data, wherein the fifth data is data corresponding to the third address included in the first atomic operation.

10. The chip according to claim 9, characterized in that, The accelerator is specifically used for, According to the first-in-first-out (FIFO) principle, the fifth data and the sixth data are read sequentially from the second temporary memory, and the seventh data is generated based on the fifth data, and the eighth data is generated based on the sixth data, wherein the sixth data is the data corresponding to the fourth address included in the second atomic operation; The seventh data is written back to the third address in sequence, and the eighth data is written back to the fourth address.

11. An accelerator, characterized in that, It is applied in a chip to perform the method described in any one of claims 1-5.

12. A computer program product containing instructions, characterized in that, When the instruction is executed by the accelerator, the accelerator performs the method as described in any one of claims 1-5.

13. A computer-readable storage medium, characterized in that, Includes computer program instructions that, when executed by the accelerator, cause the accelerator to perform the method as described in any one of claims 1-5.

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