Display panel, electronic equipment and fault positioning method

Abstract

The invention discloses a display panel, electronic equipment and a fault positioning method, and relates to the technical field of electronics. The display panel provided by the invention comprises a display driving integrated circuit, a pixel array, a first test circuit and a second test circuit, a data output end of the display driving integrated circuit is connected with a data receiving end of a pixel circuit in the pixel array; the first test circuit and the second test circuit are respectively connected with the data receiving end of the pixel circuit; the first test circuit is used for determining that the first target module has a fault or the first target module does not have a fault under the condition that the display panel has a fault; the second test circuit is used for determining that the second target module has a fault or the second target module does not have a fault under the condition that the first target module does not have a fault; wherein the first target module comprises one of a display driving integrated circuit and a pixel circuit, and the second target module comprises the other one of the display driving integrated circuit and the pixel circuit.

Description

Technical Field

[0001] This application belongs to the field of electronic technology, specifically relating to a display panel, electronic device, and fault location method. Background Technology

[0002] As users increasingly demand higher device lifespan and screen-to-body ratio, Liquid Injection Package Optimization (Lipo) technology has become a key process in pursuit of ultra-narrow bezels. It effectively narrows the bottom bezel by encapsulating and fixing the driver chip bonding area with a special colloid.

[0003] The current production process for display panels using Lipo technology involves injecting and curing encapsulating adhesive into the entire pad bending area after the driver chip is bonded, forming a robust encapsulation layer to achieve physical protection and a narrow bezel design.

[0004] However, when abnormal display features such as vertical lines appear on the screen, the potentially failed bonding area has been completely sealed by the adhesive, becoming a black box. Existing non-destructive electrical testing methods cannot penetrate the adhesive to accurately locate the internal fault location, forcing fault analysis to rely on destructive debonding, resulting in low analysis efficiency and high cost, which seriously restricts the improvement of production yield and process optimization. Summary of the Invention

[0005] This application provides a display panel, an electronic device, and a fault location method, solving the problem in related technologies that it is impossible to accurately locate internal faults by penetrating colloids.

[0006] In a first aspect, embodiments of this application provide a display panel, including: a display driver integrated circuit, a pixel array, a first test circuit, and a second test circuit; the data output terminal of the display driver integrated circuit is connected to the data receiving terminal of the pixel circuit in the pixel array; The first test circuit and the second test circuit are respectively connected to the data receiving end of the pixel circuit; The first test circuit is used to determine whether the first target module is faulty or not, in the event of a fault in the display panel. The second test circuit is used to determine whether the second target module is faulty or not, provided that the first target module is not faulty. The first target module includes one of a display driver integrated circuit and a pixel circuit, and the second target module includes the other of a display driver integrated circuit and a pixel circuit.

[0007] Secondly, embodiments of this application provide an electronic device, including: a display panel as described in the first aspect.

[0008] Thirdly, embodiments of this application propose a fault location method for a display panel, applied to the display panel as described in the first aspect, comprising: In the event of a fault in the display panel, the first test circuit is controlled to provide a first test signal to the pixel circuit in the pixel array, and the data output terminal of the display driver integrated circuit is simultaneously controlled to stop providing display signals to the data receiving terminal of the pixel circuit. The response of the pixel array is detected to obtain first test information; wherein, the first test information includes whether the first target module has failed or not; the first target module includes one of a display driver integrated circuit and a pixel circuit; If the first test information indicates that the first target module is not faulty, the second test circuit is controlled to provide a second test signal to the pixel circuit, and the data output terminal of the display driver integrated circuit is simultaneously controlled to stop providing a display signal to the data receiving terminal of the pixel circuit. The response of the pixel array is detected to obtain second test information; wherein, the second test information includes whether the second target module has failed or not; the second target module includes the other of the display driver integrated circuit and the pixel circuit.

[0009] In this embodiment, the display panel includes a display driver integrated circuit, a pixel array, a first test circuit, and a second test circuit. The data output terminal of the display driver integrated circuit is connected to the data receiving terminal of the pixel circuit in the pixel array. The first test circuit and the second test circuit are respectively connected to the data receiving terminal of the pixel circuit. The first test circuit is used to determine whether a first target module is faulty or not when the display panel is faulty. The second test circuit is used to determine whether a second target module is faulty or not when the first target module is not faulty. The first target module includes one of the display driver integrated circuit and the pixel circuit, and the second target module includes the other of the display driver integrated circuit and the pixel circuit. Thus, by integrating the first and second test circuits into the display panel, in the event of a display panel fault, the first and second test circuits are used to determine whether the display driver integrated circuit and the pixel circuit are faulty. If neither is faulty, it can be determined that the fault lies in the data line between the display driver integrated circuit and the pixel circuit, achieving non-destructive and precise fault location. Attached Figure Description

[0010] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which: Figure 1 These are schematic diagrams of display panels provided in some embodiments of this application; Figure 2 These are schematic diagrams of display panels provided in some embodiments of this application; Figure 3 These are schematic diagrams of display panels provided in some embodiments of this application; Figure 4 These are schematic diagrams of display panels provided in some embodiments of this application; Figure 5 These are schematic diagrams of display panels provided in some embodiments of this application; Figure 6 These are schematic diagrams of display panels provided in some embodiments of this application; Figure 7 These are schematic diagrams of display panels provided in some embodiments of this application; Figure 8 These are schematic diagrams of display panels provided in some embodiments of this application; Figure 9 This is a schematic flowchart of a fault location method for a display panel provided in some embodiments of this application; Figure 10 These are schematic diagrams of electronic devices provided in some embodiments of this application.

[0011] Explanation of reference numerals in the attached figures: 10 - Display panel; 100 - Display driver integrated circuit; 200 - Pixel array; 210 - Pixel circuit; 300 - First test circuit; 400 - Second test circuit; 500 - Third test circuit; 600 - Fourth test circuit; P1 - First enable signal output terminal; P2 - Second enable signal output terminal; V1 - First target voltage terminal; V2 - Second target voltage terminal; A - First bending point; B - Second bending point; 1000 - Electronic device. Detailed Implementation

[0012] The embodiments of this application will now be described in detail. Examples of these embodiments are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0013] The terms "first" and "second" in the specification and claims of this application may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise stated, "multiple" means two or more. Furthermore, "and / or" in the specification and claims indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0014] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "connected" and "linked" should be interpreted broadly. For example, they can refer to a direct connection, an indirect connection through an intermediate medium, or a connection within two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0015] The terminology used in the implementation section of this application is only for explaining specific embodiments of this application and is not intended to limit this application. The terminology involved in the embodiments of this application is explained below.

[0016] A display panel is a functional device module used to display images by controlling optical states through electrical signals. A display panel includes at least a substrate providing mechanical support and a circuit base, a pixel array formed on the substrate, and a driving circuit system that provides driving signals to the pixel array. The driving circuit system may include, but is not limited to, display driver integrated circuits, light-emitting driver integrated circuits, and scanning driver integrated circuits. The display panel constitutes the core display component of a display device, and its specific technical types may include, but are not limited to, liquid crystal display panels, organic light-emitting diode display panels, quantum dot light-emitting diode display panels, or micro light-emitting diode display panels, etc.

[0017] Display driver integrated circuits (ICCs) are application-specific integrated circuit chips (ASICs) used to receive image data and timing control signals from an external processing system and convert them into specific voltage or current signals required to drive each pixel circuit in the pixel array. They are typically electrically and physically connected to the pixel array on the display panel through bonding processes. This IC can be integrated as a single chip or its functionality can be achieved by multiple driver chips working together.

[0018] A pixel array is a collection of multiple pixel circuits arranged in a row-column matrix within the display area of ​​a display panel. Each pixel circuit includes at least a storage capacitor for storing data voltage, a driving transistor for controlling the current flowing to the light-emitting element based on the stored voltage, and a light-emitting element electrically connected to the driving transistor. The pixel array is a functional area that performs electro-optical conversion and ultimately forms a visual image.

[0019] Test circuit: This is an auxiliary circuit structure located in the non-display area of ​​the display panel. Its main function is not to participate in normal image display, but to be activated in test mode or diagnostic mode to inject predetermined test signals into the normal display signal path of the display panel to evaluate or locate the functional status of a specific part of the display panel. Specifically, the test circuit in this application includes a first test circuit, a second test circuit, a third test circuit, and a fourth test circuit, which have different signal injection nodes to achieve segmented fault isolation and non-destructive, precise fault location.

[0020] For example, when the data output terminal of the display driver integrated circuit is connected to the data receiving terminal of the pixel circuit in the pixel array via a data line, the data line can be divided into a first part, a second part, and a third part. The first part of the data line is the segment from the point where the data line connects to the data output terminal of the display driver integrated circuit to the first bend point of the data line. The second part of the data line is the bent segment from the first bend point to the second bend point of the data line, and this second part is located in the pad bend area within the non-display area of ​​the display panel. The third part of the data line is the segment from the second bend point of the data line to the point where the data line connects to the data receiving terminal of the pixel circuit. In this application scenario, the output terminal of the first test circuit (i.e., the signal injection node) is the point where the data line connects to the data output terminal of the display driver integrated circuit, used to isolate and test whether the display driver integrated circuit is faulty. The output terminal of the second test circuit (i.e., the signal injection node) is the point where the data line connects to the data receiving terminal of the pixel circuit, used to isolate and test whether the pixel circuit is faulty. The output terminal of the third test circuit (i.e., the signal injection node) is the first bend point of the data line, used to isolate and test whether the first part of the data line is faulty. The output of the fourth test circuit (i.e., the signal injection node) is the second bend of the data line, used to isolate and check whether the third part of the data line is faulty.

[0021] Currently, with the rapid development of Active Matrix Organic Light Emitting Diode (AMOLED) display technology, the display quality, contrast, and response speed of electronic devices such as smartphones have been revolutionaryly improved, greatly optimizing the human-computer interaction experience. At the same time, users' expectations for device durability and lifespan have also increased, expecting end products to maintain high-performance displays for longer periods. To meet consumers' pursuit of extreme screen-to-body ratios and immersive visual experiences, narrow bezels or even bezel-less designs for display panels have become a clear technological evolution direction for the industry. Against this backdrop, Liquid Injection Molding (Lipo) technology has emerged. As an advanced encapsulation and bonding area protection technology, it effectively achieves physical narrowing of the bottom bezel of the panel by encapsulating and fixing the driver chip bonding area with a special colloid, making it one of the key processes for achieving ultra-narrow bezels.

[0022] In existing mass production solutions for AMOLED displays using Lipo technology, the core process typically involves: after completing the electrical connection between the display driver integrated circuit and the pads on the panel glass substrate, a specific liquid encapsulant is precisely injected and filled into the entire pad bending and bonding area. Subsequently, this encapsulant cures to form a robust encapsulation layer, completely sealing and securing the fragile metal traces, pads, and interfaces. While this physical encapsulation structure significantly improves the module's mechanical reliability and bending resistance, and successfully reduces the space required for the bezel, it also fundamentally alters the physical accessibility of this area. Currently, the industry's functional testing and failure analysis of display modules still primarily rely on traditional methods of testing overall electrical performance by inputting signals from external interfaces.

[0023] The applicant notes a significant inherent flaw in the aforementioned existing technical solutions: when the display exhibits faults such as vertical lines, partial display failure, or display anomalies, the potential failure location—for example, the pad bending area within the non-display area of ​​the display panel—is completely encapsulated and covered by the cured Lipo encapsulating adhesive, forming a black box structure. Without physically damaging this encapsulating adhesive, existing external electrical testing methods cannot directly apply test signals to specific traces or nodes within this area, nor can they effectively monitor its internal electrical state. This makes it difficult to accurately and non-destructively pinpoint the root cause of the failure—whether it stems from poor bonding contact within the encapsulating adhesive, micro-cracks in the traces, or from the driver chip itself or the peripheral pixel circuitry. Therefore, failure analysis must rely on destructive decapsulation inspection, a process that is not only inefficient and costly but also irreversible, making it unsuitable for yield sampling or online diagnostics. This severely hinders rapid improvements in production yield, timely improvement of process issues, and accurate after-sales repair, becoming a key bottleneck restricting the further reliable application and development of Lipo technology. In particular, removing adhesive from the pad bending area of ​​Lipo technology is difficult, and it is hard to distinguish whether the cracks were caused by the adhesive removal process or were already there before.

[0024] Therefore, in order to quickly locate the fault location without damaging the Lipo encapsulation adhesive of the display panel, this application embodiment integrates at least one test circuit on the existing architecture of the display panel. When the display driver integrated circuit stops providing display signals to the data receiving end of the pixel circuit, the test circuit provides test signals to the pixel circuit, thereby determining whether the display driver integrated circuit and the pixel circuit have failed. This achieves non-destructive and precise fault location. Furthermore, it is applicable to automated production line operations, significantly reducing fault analysis time and improving fault analysis efficiency. This application embodiment can also be combined with some patterns of traditional normal testing for even better results.

[0025] The display panel, electronic device, and fault location method provided in the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0026] In some embodiments of this application, such as Figure 1 or Figure 2 As shown, the display panel 10 provided in this application embodiment may include: a display driver integrated circuit 100, a pixel array 200, and a first test circuit 300; the data output terminal of the display driver integrated circuit 100 is connected to the data receiving terminal of the pixel circuit 210 in the pixel array 200; The first test circuit 300 is connected to the data receiving end of the pixel circuit 210; The first test circuit 300 is used to provide a first test signal to the pixel circuit 210 when the display driver integrated circuit stops providing display signals to the data receiving end of the pixel circuit 210; The first test signal is used to determine the first test information, which includes whether the first target module has failed or not; wherein the first target module includes one of the display driver integrated circuit 100 and the pixel circuit 210.

[0027] In this embodiment, the data output terminal of the display driver integrated circuit 100 can be connected to the data receiving terminal of the pixel circuit 210 in the pixel array 200 via a data line. In normal operating mode, the data line between the display driver integrated circuit 100 and the pixel circuit 210 is used to transmit normal display signals. If the display panel 10 exhibits abnormal display characteristics while in normal operating mode, it indicates a fault in the display panel 10, and the fault point may be located in the display driver integrated circuit 100, the pixel circuit 210, or the data line between them.

[0028] To quickly locate the fault point, this embodiment of the application provides a first test circuit 300, which is connected to the data receiving end of the pixel circuit 210 via a first test line. In test mode or diagnostic mode, the first test line is used to transmit test signals. When the display driver integrated circuit 100 stops providing display signals to the data receiving end of the pixel circuit 210, the first test circuit 300 provides a first test signal to the pixel circuit 210. At this time, the response of the pixel array is detected to obtain first test information. The first test information includes whether the first target module has failed or not, wherein the first target module includes either the display driver integrated circuit 100 or the pixel circuit 210.

[0029] In this way, by integrating the first test circuit 300 into the display panel 10, when the display driver integrated circuit 100 stops providing display signals to the data receiving end of the pixel circuit 210, the first test circuit 300 provides a first test signal to the pixel circuit 210 to determine whether one of the display driver integrated circuit 100 and the pixel circuit 210 has failed, thus achieving non-destructive and accurate location of the fault.

[0030] In some embodiments of this application, such as Figure 1 or Figure 2As shown, in order to determine whether either the display driver integrated circuit 100 or the pixel circuit 210 is faulty, in the display panel 10 provided in this application embodiment, the data output terminal of the display driver integrated circuit 100 is connected to the data receiving terminal of the pixel circuit 210 in the pixel array 200 via a data line; the output terminal of the first test circuit 300 is connected to the data receiving terminal of the pixel circuit 210 via a first test line.

[0031] Among them, such as Figure 1 As shown, when the first test line includes at least a portion of the data line, the first target module includes a display driver integrated circuit 100; or, as... Figure 2 As shown, when the first test line is a different trace than the data line, the first target module includes a pixel circuit.

[0032] In some embodiments of this application, such as Figure 1 As shown, when the first test line includes at least some data lines, the first target module includes a display driver integrated circuit 100. If the response of the pixel array is detected and it is determined that the display panel 10 is displaying normally, it indicates that the downstream data path from at least some data lines to the pixel circuit 210 is normal, thereby determining that the display driver integrated circuit 100 is faulty. If the response of the pixel array is detected and it is determined that the display panel 10 exhibits abnormal display features such as vertical lines, bright spots, and dark spots, it indicates that the downstream data path from at least some data lines to the pixel circuit 210 is faulty, while the display driver integrated circuit 100 is not faulty.

[0033] Thus, in this embodiment of the application, the first test circuit 300 provides a first test signal to the pixel circuit 210 via the data line to determine whether the display driver integrated circuit 100 is faulty. When the first test circuit 300 is working and the screen displays normally, it indicates that the entire downstream path from the data line to the pixel circuit is intact, and the fault is located in the display driver integrated circuit 100, thus confirming that the display driver integrated circuit 100 is faulty. When the first test circuit 300 is working and the screen displays abnormally, it indicates that the entire downstream path from the data line to the pixel circuit is abnormal, and the fault is located between the pixel circuit and the data line, thus ruling out the fault being in the display driver integrated circuit 100, thus confirming that the display driver integrated circuit 100 is not faulty, achieving non-destructive and accurate fault location.

[0034] In some embodiments of this application, such as Figure 2As shown, when the first test line and the data line are two different traces, the first target module includes a pixel circuit 210. If the response of the pixel array is detected and it is determined that the display panel 10 is displaying normally, it indicates that the pixel circuit 210 is not faulty; if the response of the pixel array is detected and it is determined that the display panel 10 has abnormal display features such as vertical lines, bright spots, and dark spots, it indicates that the pixel circuit 210 is faulty.

[0035] In this embodiment, the first test circuit 300 provides a first test signal to the pixel circuit 210 through a first test line different from the data line to determine whether the pixel circuit 210 is faulty. When the first test circuit 300 is working and the screen displays normally, it indicates that the pixel circuit 210 is intact and that the pixel circuit 210 is not faulty. When the first test circuit 300 is working and the screen displays abnormally, it indicates that the pixel circuit 210 is abnormal and that the pixel circuit 210 is faulty, thus achieving non-destructive and accurate location of the fault.

[0036] In some embodiments of this application, such as Figure 3 or Figure 4 As shown, in order to achieve precise coordinated control timing between the display driver integrated circuit 100 and the first test circuit 300, the control terminal of the first test circuit 300 is connected to the first enable signal output terminal P1 of the display driver integrated circuit 100. The display driver integrated circuit 100 is used to synchronously control the data output terminal of the display driver integrated circuit to stop providing display signals to the data receiving terminal of the pixel circuit 210 when the first enable signal is output to the control terminal of the first test circuit 300 through the first enable signal output terminal P1; the first enable signal is used to control the first test circuit 300 to enter the working state.

[0037] In this embodiment, the control terminal of the first test circuit 300 is connected to the first enable signal output terminal P1 of the display driver integrated circuit 100. That is, the control of the first test circuit 300 belongs to the display driver integrated circuit 100, indicating that the switching or activation command of the first test circuit 300 comes directly from a dedicated pin inside the display driver integrated circuit 100 (i.e., the first enable signal output terminal P1P1). The first enable signal is not a simple level signal, but a command signal with a defined timing controlled by the internal logic of the display driver integrated circuit 100.

[0038] In this embodiment, the display driver integrated circuit 100 is used to synchronously control the data output terminal of the display driver integrated circuit to stop providing display signals to the data receiving terminal of the pixel circuit 210 when the first enable signal is output to the control terminal of the first test circuit 300 through the first enable signal output terminal P1.

[0039] In this embodiment, the first enable signal is the main switch of the first test circuit 300. When the first enable signal is valid, the first test circuit connects the path between its test signal source and the first test line; when the first enable signal is invalid, the path is completely shut off, and the data line is completely controlled by the display driver integrated circuit 100.

[0040] In the first phase of testing, the display driver integrated circuit 100 itself is the initiator and the controller of the timing. Only one trigger instruction (such as via I2C command) is needed from the outside, and the subsequent complex synchronization operations are automatically completed by the internal logic of the display driver integrated circuit 100 chip.

[0041] Synchronous control means that when the display driver integrated circuit 100 decides to start the first stage test, it can perform an indivisible dual-thread operation. That is, it synchronously executes the activation of the first stage test operation and the self-isolation operation. At the same time as the first enable signal with a valid level is issued from the first enable signal output terminal P1, all data output terminals of the display driver integrated circuit 100 are placed in a high impedance state, a closed state, or output a fixed level, thereby physically / electrically "disconnecting" all data output terminals from the data lines, thereby controlling the data output terminals of the display driver integrated circuit to stop providing display signals to the data receiving terminal of the pixel circuit 210.

[0042] In this way, the display driver integrated circuit 100 performs activation testing and self-isolation in a dual-threaded operation, which can prevent bus conflicts and ensure that the display signal of the display driver integrated circuit 100 itself will not be short-circuited or compete with the test signal at the moment the test signal is injected into the first test line, thereby protecting the chip and ensuring the purity of the test signal.

[0043] In some embodiments of this application, if the first test information obtained in the first phase of testing includes that the first target module has not failed, a second phase of testing can also be performed to test whether the second target module has failed. For example... Figure 3 or Figure 4 As shown, the display panel 10 provided in this application embodiment may include: a display driver integrated circuit 100, a pixel array 200, a first test circuit 300 and a second test circuit 400; the data output terminal of the display driver integrated circuit 100 is connected to the data receiving terminal of the pixel circuit 210 in the pixel array 200; The first test circuit 300 and the second test circuit 400 are respectively connected to the data receiving end of the pixel circuit 210; The first test circuit 300 is used to determine whether the first target module is faulty or not, in the event of a fault in the display panel. The second test circuit 400 is used to determine whether the second target module is faulty or not, if the first target module is not faulty. The first target module includes one of the display driver integrated circuit 100 and the pixel circuit 210, and the second target module includes the other of the display driver integrated circuit 100 and the pixel circuit 210.

[0044] In the event of a display panel malfunction, the first test circuit 300 is used to provide a first test signal to the pixel circuit 210 when the display driver integrated circuit stops providing display signals to the data receiving end of the pixel circuit 210; the first test signal is used to determine first test information, which includes whether the first target module has malfunctioned or whether the first target module has not malfunctioned.

[0045] Specifically, if the first test information includes that the first target module is not faulty, it is determined that the first target module is not faulty. The second test circuit 400 is used to provide a second test signal to the pixel circuit 210 when the first target module is not faulty; the second test signal is used to determine the second test information, which includes whether the second target module is faulty or not.

[0046] It should be noted that, in order to quickly locate the fault point, this application embodiment sets up a first test circuit 300 and a second test circuit 400, which are respectively connected to the data receiving end of the pixel circuit 210. When the display driver integrated circuit 100 stops providing display signals to the data receiving end of the pixel circuit 210, the first test circuit 300 provides a first test signal to the pixel circuit 210. At this time, the response of the pixel array is detected to obtain first test information. The first test information includes whether the first target module has failed or not. The first target module includes either the display driver integrated circuit 100 or the pixel circuit 210.

[0047] Furthermore, if the first test information obtained in the first stage test includes that the first target module is not faulty, the second test circuit 400 can be used to perform the second stage test to determine whether the second target module is faulty. If neither the first target module nor the second target module is faulty, it can be determined that the data line between the display driver integrated circuit 100 and the pixel circuit 210 is faulty, thus achieving non-destructive and accurate location of the fault.

[0048] In this way, by integrating the first test circuit 300 and the second test circuit 400 into the display panel, in the event of a fault in the display panel, the first test circuit 300 and the second test circuit 400 are used to determine whether the display driver integrated circuit 100 and the pixel circuit 210 are faulty. If neither of them is faulty, it can be determined that the data line between the display driver integrated circuit 100 and the pixel circuit 210 is faulty, thus achieving non-destructive and accurate location of the fault.

[0049] For example, such as Figure 3 or Figure 4 As shown, the data output terminal of the display driver integrated circuit 100 is connected to the data receiving terminal of the pixel circuit 210 in the pixel array 200 via a data line; The output of the first test circuit 300 is connected to the data receiving end of the pixel circuit 210 via the first test line; the output of the second test circuit 400 is connected to the data receiving end of the pixel circuit 210 via the second test line.

[0050] Among them, such as Figure 3 As shown, when the first test line is a different trace from the data line and the second test line includes at least part of the data line, the first target module includes a pixel circuit 210 and the second target module includes a display driver integrated circuit 100.

[0051] Or, such as Figure 4 As shown, when the first test line includes at least a portion of the data line and the second test line is a different trace from the data line, the first target module includes a display driver integrated circuit 100 and the second target module includes a pixel circuit 210.

[0052] In a specific example, such as Figure 3 As shown, the first target module includes a display driver integrated circuit 100, and the second target module includes a pixel circuit 210. In the first stage of testing, the first test circuit 300 is used to test whether the display driver integrated circuit 100 is faulty. If the display driver integrated circuit 100 is determined to be faulty in the first stage of testing, the second stage of testing is unnecessary. If the display driver integrated circuit 100 is determined not to be faulty in the first stage of testing, the second stage of testing can be performed. In the second stage of testing, the second test circuit 400 is used to test whether the pixel circuit 210 is faulty. Furthermore, if the pixel circuit 210 is also determined not to be faulty in the second stage of testing, the data line between the display driver integrated circuit 100 and the pixel circuit 210 can be determined to be faulty using a process of elimination.

[0053] Thus, in this embodiment of the application, the first test information obtained in the first stage of testing includes the following: if the display driver integrated circuit 100 is not faulty, the second test circuit 400 provides a second test signal to the pixel circuit 210 through a second test line different from the data line to determine whether the pixel circuit 210 is faulty. When the second test circuit 400 is working and the screen displays normally, it indicates that the pixel circuit 210 is intact and that the pixel circuit 210 is not faulty. Then, the data line between the display driver integrated circuit 100 and the pixel circuit 210 is faulty according to the elimination method. When the second test circuit 400 is working and the screen displays abnormally, it indicates that the pixel circuit 210 is abnormal and that the pixel circuit 210 is faulty, thus achieving non-destructive and accurate positioning of the fault location.

[0054] In another specific example, such as Figure 4 As shown, the first target module includes a pixel circuit 210, and the second target module includes a display driver integrated circuit 100. In the first stage of testing, the first test circuit 300 is used to test whether the pixel circuit 210 is faulty. If the pixel circuit 210 is determined to be faulty in the first stage of testing, the second stage of testing is unnecessary. If the pixel circuit 210 is determined not to be faulty in the first stage of testing, the second stage of testing can be performed. In the second stage of testing, the second test circuit 400 is used to test whether the display driver integrated circuit 100 is faulty. Furthermore, if the display driver integrated circuit 100 is also determined not to be faulty in the second stage of testing, the data line between the display driver integrated circuit 100 and the pixel circuit 210 can be determined to be faulty using a process of elimination.

[0055] Thus, in this embodiment of the application, when the first test information obtained in the first stage of testing includes the fact that the pixel circuit 210 is not faulty, the second test circuit 400 provides a second test signal to the pixel circuit 210 through at least a portion of the data lines to determine whether the display driver integrated circuit 100 is faulty. When the second test circuit 400 is working and the screen displays normally, it indicates that the entire downstream path from the data line to the pixel circuit is intact, and the fault is located in the display driver integrated circuit 100, thus confirming that the display driver integrated circuit 100 is faulty. When the second test circuit 400 is working and the screen displays abnormally, it indicates that the entire downstream path from the data line to the pixel circuit is abnormal. Since the pixel circuit 210 is not faulty, the fault is located in the data line, thus achieving non-destructive and accurate fault location.

[0056] In some embodiments of this application, such as Figure 3 or Figure 4As shown, in order to achieve precise coordinated control timing between the display driver integrated circuit 100 and the second test circuit 400, the control terminal of the first test circuit 300 is connected to the first enable signal output terminal P1 of the display driver integrated circuit 100, and the control terminal of the second test circuit 400 is connected to the second enable signal output terminal P2 of the display driver integrated circuit 100. When the display driver integrated circuit 100 outputs a first enable signal to the control terminal of the first test circuit 300 via the first enable signal output terminal P1, it synchronously controls the data output terminal of the display driver integrated circuit to stop providing display signals to the data receiving terminal of the pixel circuit 210; the first enable signal is used to control the first test circuit 300 to enter the working state. The display driver integrated circuit 100 is also used to synchronously control the data output terminal of the display driver integrated circuit to stop providing display signals to the data receiving terminal of the pixel circuit 210 when the second enable signal is output to the control terminal of the second test circuit 400 through the second enable signal output terminal P2; the second enable signal is used to control the second test circuit 400 to enter the working state.

[0057] In this embodiment, the control terminal of the second test circuit 400 is connected to the second enable signal output terminal P2 of the display driver integrated circuit 100. That is, the control of the second test circuit 400 belongs to the display driver integrated circuit 100, indicating that the switching or activation command of the second test circuit 400 comes directly from a dedicated pin inside the display driver integrated circuit 100 (i.e., the second enable signal output terminal P2). The second enable signal is not a simple level signal, but a command signal with a defined timing controlled by the internal logic of the display driver integrated circuit 100.

[0058] In this embodiment, the display driver integrated circuit 100 is used to synchronously control the data output terminal of the display driver integrated circuit to stop providing display signals to the data receiving terminal of the pixel circuit 210 when outputting a second enable signal to the control terminal of the second test circuit 400 through the second enable signal output terminal P2.

[0059] In this embodiment, the second enable signal is the main switch of the second test circuit 400. When the second enable signal is valid, the second test circuit 400 connects the path between its test signal source and the second test line; when the second enable signal is invalid, the path is completely shut off, and the data line is completely controlled by the display driver integrated circuit 100.

[0060] In the second phase of testing, the display driver integrated circuit 100 itself is the initiator and the controller of the timing. Only one trigger instruction (such as via I2C command) is needed from the outside, and the subsequent complex synchronization operations are automatically completed by the internal logic of the display driver integrated circuit 100 chip.

[0061] Synchronous control means that when the display driver integrated circuit 100 decides to start the second-stage test, it can perform an indivisible dual-thread operation. That is, it synchronously executes the activation of the second-stage test operation and the self-isolation operation. At the same time that the second enable signal with a valid level is issued from the second enable signal output terminal P2, all data output terminals of the display driver integrated circuit 100 are placed in a high-impedance state, a closed state, or output a fixed level, thereby physically / electrically "disconnecting" all data output terminals from the data lines, thereby controlling the data output terminals of the display driver integrated circuit to stop providing display signals to the data receiving terminal of the pixel circuit 210.

[0062] In this way, the display driver integrated circuit 100 performs activation testing and self-isolation in a dual-threaded operation, which can prevent bus conflicts and ensure that the display signal of the display driver integrated circuit 100 itself will not be short-circuited or compete with the second test signal at the moment the second test signal is injected into the second test line, thereby protecting the chip and ensuring the purity of the test signal.

[0063] In practical applications, in the mass production of AMOLED display panels using Lipo technology, the data line between the display driver integrated circuit 100 and the pixel circuit 210 is divided into three parts by a bend. In this case, the embodiments of this application can divide the data line between the data output terminal of the display driver integrated circuit 100 and the data receiving terminal of the pixel circuit 210 into three parts according to the bend area of ​​the display panel. For example, the data line includes a first part, a second part, and a third part; the first part of the data line is the line segment from the location where the data line connects to the data output terminal of the display driver integrated circuit 100 to the first bend point A of the data line; the second part of the data line is the bent line segment from the first bend point A to the second bend point B of the data line, and the second part of the data line is located in the bend area of ​​the display panel; the third part of the data line is the line segment from the second bend point B of the data line to the location where the data line connects to the data receiving terminal of the pixel circuit 210.

[0064] If the first test information obtained in the first stage of testing includes that the display driver integrated circuit 100 and the pixel circuit 210 are not faulty, it can be determined that the data line between the display driver integrated circuit 100 and the pixel circuit 210 is faulty. In order to further pinpoint the fault location in the first, second, or third part of the data line, embodiments of this application may also set a third test circuit and a fourth test circuit with different test signal injection points.

[0065] In some embodiments of this application, if the data cable fails as determined by the first and second stage tests, a third stage test can be performed to test whether the first part of the data cable is faulty. Figure 5 or Figure 6 As shown, the display panel 10 also includes a third test circuit 500; the output of the third test circuit 500 is connected to the data receiving end of the pixel circuit 210 via a third test line; the third test line includes a second part and a third part of a data line; The third test circuit 500 can be used to determine whether the first part of the data line is faulty or not, provided that neither the first target module nor the second target module is faulty.

[0066] For example, if the second test information includes that the second target module is not faulty, the third test circuit 500 is used to provide a third test signal to the pixel circuit 210; The third test signal is used to determine the third test information, which includes whether the first part of the data line is faulty or not.

[0067] In the event of a display panel malfunction, if the first test circuit 300 and the second test circuit 400 determine that neither the first target module nor the second target module is faulty, the fault is determined to be located on the data line between the data output terminal of the display driver integrated circuit 100 and the data receiving terminal of the pixel circuit 210 through a process of elimination. At this point, a second stage of testing is performed, using the third test circuit 500 to determine whether the first part of the data line is faulty.

[0068] Thus, if the display driver integrated circuit 100 and pixel circuit 210 are found to be fault-free in the first and second stage tests, but the data line is faulty, this embodiment of the application utilizes a third test circuit 500 to provide a third test signal to the pixel circuit 210 through the second and third parts of the data line to determine whether the first part of the data line is faulty. When the third test circuit 500 is working and the screen displays normally, it indicates that the entire downstream path from the second and third parts of the data line to the pixel circuit is intact, and the fault is located in the first part of the data line, confirming that the first part of the data line is faulty. When the third test circuit 500 is working and the screen displays abnormally, it indicates that the entire downstream path from the second and third parts of the data line to the pixel circuit is abnormal, while the first part of the data line is not faulty, and the fault is located between the second and third parts of the data line, achieving non-destructive and accurate fault location.

[0069] In some embodiments of this application, if the first part of the data cable does not show a fault in the third-stage test, it indicates that the fault is located in the second or third part of the data cable. At this point, a fourth-stage test can be performed to further test whether the second or third part of the data cable is faulty. Figure 6As shown, the display panel also includes a fourth test circuit 600; the output of the fourth test circuit 600 is connected to the data receiving end of the pixel circuit 210 via a fourth test line; the fourth test line includes the third part of the data line. The fourth test circuit 600 can be used to determine whether the third part of the data line is faulty or not, provided that the first target module, the second target module, and the first part of the data line are all functioning correctly.

[0070] For example, if the third test information includes the first part of the data line without fault, the fourth test circuit 600 is used to provide a fourth test signal to the pixel circuit 210; The fourth test signal is used to determine the fourth test information, which includes whether the third part of the data cable is faulty or not.

[0071] In the third stage of testing, the third test circuit 500 is used to test whether the first part of the data cable is faulty. If the first part of the data cable is determined to be faulty in the third stage test, the fourth stage test is unnecessary. If the first part of the data cable is determined not to be faulty in the third stage test, the fourth stage test can be performed. In the fourth stage test, the fourth test circuit 600 is used to test whether the third part of the data cable is faulty. Furthermore, if the third part of the data cable is also determined not to be faulty in the fourth stage test, the fault can be determined to be in the second part of the data cable (i.e., the part of the data cable located in the bend area) by a process of elimination.

[0072] Thus, if the first, second, and third stage tests show that the display driver integrated circuit 100, pixel circuit 210, and the first part of the data line are not faulty, but the second and third parts of the data line are faulty, this embodiment of the application utilizes a fourth test circuit 600 to provide a fourth test signal to the pixel circuit 210 through the third part of the data line to determine whether the third part of the data line is faulty. When the fourth test circuit 600 is working and the screen display is normal, it indicates that the entire downstream path from the third part of the data line to the pixel circuit is intact, and the fault is located in the second part of the data line, confirming that the second part of the data line is faulty. When the third test circuit 500 is working and the screen display is abnormal, it indicates that the entire downstream path from the third part of the data line to the pixel circuit is abnormal, and the fault is located in the third part of the data line, achieving non-destructive and accurate fault location.

[0073] It should be noted that in practical applications, the first test circuit 300, the second test circuit 400, the third test circuit 500, and the fourth test circuit 600 are all of the same type of test circuit, and their internal circuit structures may be the same or different. For example, the test circuit may include multiple switching units, with one switching unit corresponding to one data line.

[0074] The test signal injection nodes (i.e., the locations where the output terminals are connected) of the first test circuit 300, the second test circuit 400, the third test circuit 500, and the fourth test circuit 600 are all different. For example, Figure 6 As shown, the output of the first test circuit 300 is connected to the location where the data line is connected to the data output of the display driver integrated circuit 100, the output of the second test circuit 400 is connected to the location where the data line is connected to the data receiving end of the pixel circuit 210, the output of the third test circuit 500 is connected to the first bend point A of the data line, and the output of the fourth test circuit 600 is connected to the second bend point B of the data line.

[0075] The internal circuit structure of the test circuit is illustrated below using the first test circuit 300 and the second test circuit 400 as examples.

[0076] In some embodiments of this application, the test circuit may include multiple switching units, with each switching unit connected to a corresponding data line.

[0077] like Figure 7 or Figure 8 As shown, the first test circuit 300 includes a plurality of first switch units T1, the number of which is the same as the number of data lines; A first terminal of a first switching unit T1 is connected to the target voltage terminal, a second terminal of a first switching unit T1 is connected to the first position of a data line, and a third terminal of a first switching unit T1 is connected to the first enable signal output terminal P1 of the display driver integrated circuit 100. When the first enable signal output terminal P1 outputs a first enable signal to the third terminal of the first switch unit T1, the first switch unit T1 is in the on state, and the target voltage terminal is used to provide the first test signal; the first position includes one of the position where the data line is connected to the data output terminal of the display driver integrated circuit 100, and the position where the data line is connected to the data receiving terminal of the pixel circuit 210.

[0078] Similarly, such as Figure 7 or Figure 8 As shown, the second test circuit 400 includes a plurality of second switch units T2, the number of which is the same as the number of data lines; The first end of a second switching unit T2 is connected to the target voltage terminal, the second end of a second switching unit T2 is connected to the second position of a data line, and the third end of a second switching unit T2 is connected to the second enable signal output terminal P2 of the display driver integrated circuit 100. The target voltage terminal is also used to provide a second test signal. The second position includes either the position where the data line is connected to the data output terminal of the display driver integrated circuit 100, or the position where the data line is connected to the data receiving terminal of the pixel circuit 210.

[0079] The first test circuit 300 can be a highly parallelized, precisely controllable switch array that corresponds one-to-one with each data line. Similarly, the second test circuit 400 can be another highly parallelized, precisely controllable switch array that corresponds one-to-one with each data line. Each data line (source line) is equipped with an independent, dedicated first switch unit T1 and an independent, dedicated second switch unit T2 for control. This allows for independent control of the test signal injection for each data line, and the characteristics of the switch units (such as drive capability) can be optimized for the load of a single data line, avoiding signal attenuation or crosstalk.

[0080] Since the number of switching units in the test circuit is the same as the number of data lines, the test circuit can drive all data lines at once and simultaneously, thereby generating a uniform test screen, such as pure white, pure black, pure red, pure green, etc., to detect pixel uniformity, dead pixels, and line defects.

[0081] In this test circuit, all switching units share a single enable signal, ensuring that the megapixels begin receiving the test signal at the same clock edge. This eliminates visual flicker or test errors that may be caused by scanning the signal row by row or column by column, resulting in stable and reliable test results.

[0082] In this test circuit, each switching unit independently drives a data line. The size of its transistor can be designed to be large enough to overcome the inherent large capacitive load of the data line, ensuring that the test signal voltage can be established quickly and accurately, and avoiding inaccurate grayscale or test failure caused by slow signal rise / fall time.

[0083] Thus, by configuring test circuits such as the first test circuit 300 and the second test circuit 400 into highly parallelized, one-to-one corresponding and precisely controllable switch arrays, this embodiment of the application ensures that test circuits such as the first test circuit 300 and the second test circuit 400 can apply full-screen, synchronous, and stable test signals.

[0084] In practical applications, the first switching unit T1 can be a first transistor. The first terminal of the first switching unit T1 is one of the source and drain terminals of the first transistor, the second terminal is the other of the source and drain terminals, and the third terminal is the gate terminal. Similarly, the second switching unit T2 is a second transistor. The first terminal of the second switching unit T2 is one of the source and drain terminals of the second transistor, the second terminal is the other of the source and drain terminals, and the third terminal is the gate terminal. Since each data line corresponds to one transistor, the width of the entire test circuit can be designed to be less than 30µm, thus having a relatively small impact on the bezel width.

[0085] Furthermore, each switching unit in the same test circuit is typically fabricated using a thin-film transistor (TFT) process, which can be directly utilized from the existing TFT process in the display panel without introducing additional special processes. Its layout can be consistent with the layout rules of the surrounding gate drive circuit or pixel array, resulting in a neat circuit structure that is easy to design and manufacture. In non-test states, all switching units are off, and the test circuit consumes almost no static power.

[0086] In practical applications, the test signal provided by the target voltage terminal can come from external test equipment or from the display driver integrated circuit 100. The test signal provided by the target voltage terminal can be a voltage signal with a fixed amplitude or can include multiple voltage signals with different amplitudes. This application does not limit this.

[0087] For example, the voltage amplitude at the target voltage terminal is adjustable, meaning the first test signal provided by the target voltage terminal can be a voltage signal with multiple voltage amplitudes. Because the voltage amplitude at the target voltage terminal is adjustable, different voltage amplitudes can be applied to different data lines, thereby achieving more complex test patterns such as grayscale gradients, checkerboard patterns, and vertical stripes, which can be used to detect advanced defects such as crosstalk and nonlinear response.

[0088] In a specific example, the target voltage terminal is at least one test signal interface located in the non-display area of ​​the display panel. This test signal interface is used to receive test signals from external testing equipment, including a first test signal and a second test signal. For example... Figure 7 As shown, the target voltage terminal includes a first target voltage terminal V1 and a second target voltage terminal V2. The first target voltage terminal V1 and the second target voltage terminal V2 are two test signal interfaces, such as two test signal pads, located in the non-display area of ​​the display panel, for receiving test signals from external devices.

[0089] In this way, the highly complex and costly programmable test signal source function is decoupled from external devices, which greatly simplifies the panel design and reduces costs. It provides a defined and standardized physical access point, overcomes the test access barriers brought about by advanced packaging, and is perfectly adapted to automated production line testing, ensuring the high reliability and mass production capability of the solution. It also establishes a flexible external signal interface, making the test content infinitely programmable and compatible with the existing industrial testing ecosystem, providing test flexibility and a very low threshold for promotion.

[0090] For example, in another specific example, such as Figure 8 As shown, the target voltage terminal is at least one voltage output terminal of the display driver integrated circuit 100, and the voltage amplitude of the target voltage terminal is adjustable. The display driver integrated circuit 100 is used to simultaneously provide a first test signal containing multiple voltage amplitudes to multiple first switching units through a target voltage terminal when outputting a first enable signal to multiple first switching units through a first enable signal output terminal P1; The display driver integrated circuit 100 is also used to simultaneously provide a second test signal containing multiple voltage amplitudes to multiple second switching units through a target voltage terminal when outputting a second enable signal to multiple second switching units through the second enable signal output terminal P2.

[0091] In this way, by reusing the voltage output terminal of the display driver integrated circuit 100 as the test signal source, external test pads and connections are completely eliminated, achieving an extremely simple appearance and higher physical reliability for the display panel. This sacrifices some signal flexibility in exchange for ultra-high system-level integration and ease of testing, making it suitable for product designs with the highest priority on screen-to-body ratio and reliability. Furthermore, by utilizing the existing power supply within the display panel as the test signal source, the display driver integrated circuit 100 is endowed with complete autonomous testing capabilities, supporting one-click self-testing, greatly simplifying the production line testing process and opening up new terminal self-testing functions.

[0092] In some embodiments of this application, to effectively analyze fault points with obvious abnormal display characteristics in monochrome display scenes, the target voltage terminal includes a first target voltage terminal and a second target voltage terminal. The test circuit may include multiple switching units, with an odd number of switching units connected to the first target voltage terminal and an even number of switching units connected to the second target voltage terminal. This allows for separate control of the odd and even number of switching units, enabling fault point analysis in monochrome display scenes. For example, test signals can be provided to the odd number of switching units individually via the first target voltage terminal to analyze fault points with abnormal display characteristics in red monochrome display scenes; or, test signals can be provided to the even number of switching units individually via the second target voltage terminal to analyze fault points with abnormal display characteristics in green monochrome display scenes.

[0093] like Figure 7 or Figure 8 As shown, in order to quickly distinguish and locate faults in a specific color channel, the target voltage terminal includes a first target voltage terminal V1 and a second target voltage terminal V2; both the first target voltage terminal V1 and the second target voltage terminal V2 are used to provide a first test signal and a second test signal. The first end of the odd number of the multiple first switching units is connected to the first target voltage terminal V1, and the first end of the even number of the multiple first switching units T1 is connected to the second target voltage terminal V2. The first end of the odd number of the multiple second switching units T2 is connected to the first target voltage terminal V1, and the first end of the even number of the multiple second switching units T2 is connected to the second target voltage terminal V2.

[0094] in, Figure 7 The first target voltage terminal V1 and the second target voltage terminal V2 shown are two test signal interfaces, such as two test signal pads, located in the non-display area of ​​the display panel, for receiving test signals from external devices.

[0095] in, Figure 8 The first target voltage terminal V1 and the second target voltage terminal V2 shown are two voltage output terminals of the display driver integrated circuit 100, used to output test signals containing multiple voltage amplitudes.

[0096] In this embodiment, test signals are provided to an odd number of switching units among multiple switching units through a first target voltage terminal V1, thereby effectively analyzing the fault points where abnormal display characteristics appear on the display panel in a red monochrome display scene. Alternatively, test signals are provided to an even number of switching units among multiple switching units through a second target voltage terminal V2, thereby effectively analyzing the fault points where abnormal display characteristics appear on the display panel in a green monochrome display scene.

[0097] In this way, by using an odd-even switch to select the corresponding red or green sub-pixel data line, independent driving and observation of red and green monochrome images are achieved, separating and locking composite color display faults to specific color channels. The fault information from each color channel provides targeted feedback for production line process improvement and precise instructions for maintenance, significantly improving manufacturing yield and after-sales maintenance efficiency while reducing costs.

[0098] In addition, the internal circuit structure and control method of the third test circuit 500 and the fourth test circuit 600 can be referenced from the first test circuit 300 and the second test circuit 400.

[0099] For example, the control terminal of the third test circuit 500 is connected to the third enable signal output terminal of the display driver integrated circuit 100 (not shown in the figure); the display driver integrated circuit 100 is used to synchronously control the data output terminal of the display driver integrated circuit to stop providing display signals to the data receiving terminal of the pixel circuit 210 when outputting a third enable signal to the control terminal of the third test circuit 500 through the third enable signal output terminal; the third enable signal is used to control the third test circuit 500 to enter the working state. The third test circuit 500 includes multiple third switch units, the number of which is the same as the number of data lines; the first end of a third switch unit is connected to the target voltage terminal, the second end of a third switch unit is connected to the third position of a data line, and the third end of a third switch unit is connected to the third enable signal output terminal of the display driver integrated circuit (not shown in the figure); wherein, when the third enable signal output terminal outputs a valid third enable signal to the third end of the third switch unit, the third switch unit is in the conducting state, and the target voltage terminal is also used to provide a third test signal; the third position includes the first bend point of the data line.

[0100] For example, the control terminal of the fourth test circuit 600 is connected to the fourth enable signal output terminal of the display driver integrated circuit 100 (not shown in the figure); the display driver integrated circuit 100 is used to synchronously control the data output terminal of the display driver integrated circuit to stop providing display signals to the data receiving terminal of the pixel circuit 210 when outputting a fourth enable signal to the control terminal of the fourth test circuit 600 through the fourth enable signal output terminal; the fourth enable signal is used to control the fourth test circuit 600 to enter the working state. The fourth test circuit 600 includes a plurality of fourth switch units, the number of which is the same as the number of data lines; the first end of a fourth switch unit is connected to the target voltage terminal, the second end of a fourth switch unit is connected to the fourth position of a data line, and the third end of a fourth switch unit is connected to the fourth enable signal output terminal of the display driver integrated circuit (not shown in the figure); wherein, when the fourth enable signal output terminal outputs a valid fourth enable signal to the third end of the fourth switch unit, the fourth switch unit is in the conducting state, and the target voltage terminal is also used to provide the fourth test signal; the fourth position includes the second bend point of the data line.

[0101] Thus, in the third stage test, the third test circuit 500 provides a third test signal to the pixel circuit 210 through the second and third parts of the data line, and in the fourth stage test, the fourth test circuit 600 provides a fourth test signal to the pixel circuit 210 through the third part of the data line, so as to accurately locate the fault point from the first, second or third part of the data line.

[0102] In addition, based on the same concept as the display panel provided in any of the above embodiments, this application also provides a fault location method for a display panel, which is applied to the display panel provided in any of the above embodiments.

[0103] For example, such as Figure 9 As shown, the fault location method for a display panel provided in this application embodiment may include: Step 910: In the event of a fault in the display panel, control the first test circuit to provide a first test signal to the pixel circuit in the pixel array, and simultaneously control the data output terminal of the display driver integrated circuit to stop providing display signals to the data receiving terminal of the pixel circuit; Step 920: Detect the response of the pixel array to obtain first test information; wherein, the first test information includes whether the first target module has failed or not; the first target module includes one of the display driver integrated circuit and the pixel circuit.

[0104] Thus, by integrating a first test circuit into the display panel, when the display driver integrated circuit stops providing display signals to the data receiving end of the pixel circuit, the first test circuit provides a first test signal to the pixel circuit to determine whether one of the display driver integrated circuit and the pixel circuit has failed, thereby achieving non-destructive and accurate location of the fault.

[0105] In some embodiments of this application, when the first test information includes that the first target module has not failed, in order to further locate the fault point, such as... Figure 9 As shown in the embodiments of this application, the fault location method for a display panel may further include: Step 930: If the first test information includes that the first target module is not faulty, control the second test circuit to provide a second test signal to the pixel circuit, and simultaneously control the data output terminal of the display driver integrated circuit to stop providing display signals to the data receiving terminal of the pixel circuit; Step 940: Detect the response of the pixel array to obtain second test information; wherein, the second test information includes whether the second target module has failed or not; the second target module includes the other of the display driver integrated circuit and the pixel circuit.

[0106] Thus, in this embodiment of the application, if the first test information obtained in the first stage test includes that the first target module is not faulty, the second test circuit can be used to perform the second stage test to determine whether the second target module is faulty. If neither the first target module nor the second target module is faulty, it can be determined that the data line between the display driver integrated circuit and the pixel circuit is faulty, thereby achieving non-destructive and accurate positioning of the fault location.

[0107] Furthermore, in some embodiments of this application, when the first target module includes a display driver integrated circuit and the first test information includes a fault in the first target module, the fault location method for the display panel provided in the embodiments of this application may further include: The display driver IC will be untied from the current first display panel and retied to a known functional second display panel; On the second display panel, the first test circuit is controlled to provide a first test signal to the pixel circuit in the pixel array, and the data output terminal of the display driver integrated circuit is simultaneously controlled to stop providing display signals to the data receiving terminal of the pixel circuit; the response of the pixel array is detected to obtain the target test information; If the location of the abnormal display feature on the second display panel changes in the target test information, it is determined that there is a fault in the bonding connection between the data output terminal of the display driver integrated circuit and the first display panel. If the location of the abnormal display features on the second display panel remains unchanged in the target test information, it is determined that there is a fault in the data output circuit inside the display driver integrated circuit.

[0108] Thus, in the case where the first test information obtained through the first stage test includes a fault in the display driver integrated circuit, the embodiments of this application can also conduct cross-testing, which involves unbinding the display driver integrated circuit from the current first display panel and rebinding it to a known functional second display panel to re-perform the first stage test, thereby further distinguishing whether the fault in the display driver integrated circuit is due to a fault in the binding connection between the data output terminal of the display driver integrated circuit and the first display panel, or a fault in the data output circuit inside the display driver integrated circuit.

[0109] In addition, based on the same concept as the display panel provided in any of the above embodiments, this application also provides an electronic device.

[0110] For example, such as Figure 10 As shown, the electronic device 1000 may include the display panel 10 provided in any of the above embodiments and can achieve the same function. To avoid repetition, it will not be described again here.

[0111] In the embodiments of this application, the electronic device can be a terminal or other devices besides a terminal. For example, the electronic device can be a mobile phone, tablet computer, laptop computer, handheld computer, in-vehicle electronic device, mobile internet device (MID), augmented reality (AR) / virtual reality (VR) device, robot, wearable device, ultra-mobile personal computer (UMPC), netbook, or personal digital assistant (PDA), etc. It can also be a server, network attached storage (NAS), personal computer (PC), etc. The embodiments of this application do not specifically limit the scope.

[0112] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0113] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.

Claims

1. A display panel, characterized in that, include: The system comprises a display driver integrated circuit, a pixel array, a first test circuit, and a second test circuit; the data output terminal of the display driver integrated circuit is connected to the data receiving terminal of the pixel circuit in the pixel array. The first test circuit and the second test circuit are respectively connected to the data receiving end of the pixel circuit; The first test circuit is used to determine whether the first target module is faulty or not, in the event that the display panel is faulty. The second test circuit is used to determine whether the second target module is faulty or not, if the first target module is not faulty. The first target module includes one of the display driver integrated circuit and the pixel circuit, and the second target module includes the other of the display driver integrated circuit and the pixel circuit.

2. The display panel according to claim 1, characterized in that, The control terminal of the first test circuit is connected to the first enable signal output terminal of the display driver integrated circuit; the control terminal of the second test circuit is connected to the second enable signal output terminal of the display driver integrated circuit. The display driver integrated circuit is used to simultaneously control the data output terminal of the display driver integrated circuit to stop providing display signals to the data receiving terminal of the pixel circuit when it outputs a first enable signal to the control terminal of the first test circuit through the first enable signal output terminal; the first enable signal is used to control the first test circuit to enter the working state. The display driver integrated circuit is also used to simultaneously control the data output terminal of the display driver integrated circuit to stop providing display signals to the data receiving terminal of the pixel circuit when outputting the second enable signal to the control terminal of the second test circuit through the second enable signal output terminal; the second enable signal is used to control the second test circuit to enter the working state.

3. The display panel according to claim 1, characterized in that, The data output terminal of the display driver integrated circuit is connected to the data receiving terminal of the pixel circuit in the pixel array via a data line; The output terminal of the first test circuit is connected to the data receiving terminal of the pixel circuit via a first test line; the output terminal of the second test circuit is connected to the data receiving terminal of the pixel circuit via a second test line. Wherein, if the first test line includes at least a portion of the data line and the second test line is a trace different from the data line, the first target module includes the display driver integrated circuit and the second target module includes the pixel circuit; or, if the first test line is a trace different from the data line and the second test line includes at least a portion of the data line, the first target module includes the pixel circuit and the second target module includes the display driver integrated circuit.

4. The display panel according to any one of claims 1-3, characterized in that, The first test circuit includes a plurality of first switching units, the number of which is the same as the number of data lines; A first terminal of the first switching unit is connected to the target voltage terminal, a second terminal of the first switching unit is connected to a first position of the data line, and a third terminal of the first switching unit is connected to the first enable signal output terminal of the display driver integrated circuit. Wherein, when the first enable signal output terminal outputs a first enable signal to the third terminal of the first switch unit, the first switch unit is in the on state, and the target voltage terminal is used to provide a first test signal; the first position includes one of the position where the data line is connected to the data output terminal of the display driver integrated circuit, and the position where the data line is connected to the data receiving terminal of the pixel circuit. The second test circuit includes a plurality of second switch units, the number of which is the same as the number of data lines; A first terminal of a second switching unit is connected to the target voltage terminal, a second terminal of a second switching unit is connected to a second position of a data line, and a third terminal of a second switching unit is connected to the second enable signal output terminal of the display driver integrated circuit. The target voltage terminal is also used to provide a second test signal, and the second position includes either the position where the data line is connected to the data output terminal of the display driver integrated circuit, or the position where the data line is connected to the data receiving terminal of the pixel circuit.

5. The display panel according to any one of claims 1-3, characterized in that, The display panel further includes a third test circuit; the output of the third test circuit is connected to the data receiving end of the pixel circuit via a third test line; the third test line includes a second part and a third part of the data line; The third test circuit is used to determine whether the first part of the data line is faulty or not, in the case that neither the first target module nor the second target module is faulty. The data line includes a first part, a second part, and a third part; the first part of the data line is a line segment from the location where the data line is connected to the data output terminal of the display driver integrated circuit to the first bend point of the data line; the second part of the data line is a bent line segment from the first bend point of the data line to the second bend point of the data line, and the second part of the data line is disposed in the bend area of ​​the display panel; the third part of the data line is a line segment from the second bend point of the data line to the location where the data line is connected to the data receiving terminal of the pixel circuit.

6. The display panel according to claim 5, characterized in that, The display panel further includes a fourth test circuit; the output of the fourth test circuit is connected to the data receiving end of the pixel circuit via a fourth test line; the fourth test line includes the third part of the data line. The fourth test circuit is used to determine whether the third part of the data line is faulty or not, provided that the first target module, the second target module, and the first part of the data line are all functioning correctly.

7. The display panel according to claim 4, characterized in that, The target voltage terminal is at least one voltage output terminal of the display driver integrated circuit, and the voltage amplitude of the target voltage terminal is adjustable; The display driver integrated circuit is used to simultaneously provide a first test signal containing multiple voltage amplitudes to the multiple first switching units through the target voltage terminal when outputting a first enable signal to the multiple first switching units through the first enable signal output terminal. The display driver integrated circuit is also used to simultaneously provide a second test signal containing multiple voltage amplitudes to the plurality of second switching units through the target voltage terminal when outputting a second enable signal to the plurality of second switching units through the second enable signal output terminal.

8. The display panel according to claim 7, characterized in that, The target voltage terminal includes a first target voltage terminal and a second target voltage terminal; both the first target voltage terminal and the second target voltage terminal are used to provide a first test signal and a second test signal. The first ends of the odd-numbered first switching units in the plurality of first switching units are connected to the first target voltage terminal, and the first ends of the even-numbered first switching units in the plurality of first switching units are connected to the second target voltage terminal; The first end of the odd-numbered second switching units in the plurality of second switching units is connected to the first target voltage terminal, and the first end of the even-numbered second switching units in the plurality of second switching units is connected to the second target voltage terminal.

9. An electronic device, characterized in that, Includes the display panel as described in any one of claims 1-8.

10. A fault location method for a display panel, applied to the display panel as described in any one of claims 1-8, characterized in that, include: In the event of a display panel malfunction, the first test circuit is controlled to provide a first test signal to the pixel circuit in the pixel array, and the data output terminal of the display driver integrated circuit is simultaneously controlled to stop providing display signals to the data receiving terminal of the pixel circuit. The response of the pixel array is detected to obtain first test information; wherein, the first test information includes whether the first target module has failed or not; the first target module includes one of the display driver integrated circuit and the pixel circuit. If the first test information includes that the first target module is not faulty, the second test circuit is controlled to provide a second test signal to the pixel circuit, and the data output terminal of the display driver integrated circuit is simultaneously controlled to stop providing a display signal to the data receiving terminal of the pixel circuit. The response of the pixel array is detected to obtain second test information; wherein, the second test information includes whether the second target module has failed or not; the second target module includes the display driver integrated circuit and the other of the pixel circuit.

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