Display device and method for driving display device

Abstract

This disclosure provides a display device and a method for driving the display device. The display device includes: a switching transistor that is turned on according to a scan signal applied through a scan line to transmit a data voltage applied through a data line to a capacitor; a signal delay compensation circuit that is turned on according to the scan signal to compensate for a signal delay of the scan signal in response to a change in the data voltage; a driving transistor configured to generate a driving current based on the data voltage stored in the capacitor; and a light-emitting diode configured to operate to emit light based on the driving current.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2024-0171165, filed on November 26, 2024, which is incorporated herein by reference as if fully set forth herein. Technical Field

[0002] This disclosure relates to display devices and methods for driving display devices. Background Technology

[0003] With the development of information technology, the market for display devices used to convey information to users is growing. As a result, the use of display devices such as light-emitting diode (LED) devices, quantum dot (QDD) devices, and liquid crystal display (LCD) devices is increasing.

[0004] The aforementioned display device includes: a display panel comprising sub-pixels, a driver that outputs drive signals for driving the display panel, and a power supply that generates power to be supplied to the display panel or the driver.

[0005] The aforementioned display device can display an image by causing selected sub-pixels to transmit light or emit light directly when driving signals such as scan signals and data signals are supplied to the sub-pixels formed on the display panel. Summary of the Invention

[0006] Therefore, this disclosure relates to a display device and a method for driving a display device that substantially avoids one or more problems caused by limitations and defects in related technologies.

[0007] The purpose of this disclosure is to mitigate horizontal crosstalk that may be caused per horizontal line (or per scan line) when writing data voltage by compensating for the delay of the scan signal (including signal delay variations) and thereby uniformly improve display quality.

[0008] Another objective of this disclosure is to eliminate the delay of the scan signal without increasing the load on the gate node of the driving transistor by differentially compensating for the amount of capacitance change caused by data voltage variations (or grayscale variations of the pattern).

[0009] Further advantages, objects, and features of this disclosure will be set forth in part in the description which follows, and will in part become apparent to those skilled in the art upon studying the following, or may be learned from practice of this disclosure. The objects and other advantages of this disclosure may be realized and obtained by means of the structures particularly pointed out in the written description, its claims, and the accompanying drawings.

[0010] To achieve these and other advantages, and for the purposes of this disclosure, as embodied and broadly described herein, a display device includes: a switching transistor that is turned on according to a scan signal applied via a scan line to transmit a data voltage applied via a data line to a capacitor; a signal delay compensation circuit that is turned on according to the scan signal to compensate for a signal delay of the scan signal in response to a change in the data voltage; a driving transistor configured to generate a driving current based on the data voltage stored in the capacitor; and a light-emitting diode configured to operate to emit light based on the driving current.

[0011] The signal delay compensation circuit can change the capacitance of the switching transistor in response to changes in data voltage.

[0012] The signal delay compensation circuit may include a compensation transistor having: a gate electrode connected to a scan line; and a first electrode connected to a DC voltage line.

[0013] The compensation transistor can change the capacitance of the switching transistor based on the change of DC voltage applied through the DC voltage line and the change of data voltage.

[0014] The signal delay compensation circuit may include: a compensation transistor having: a gate electrode connected to a scan line; and a first electrode connected to a high-level voltage line; and a compensation capacitor having: a first electrode connected to a second electrode of the compensation transistor; and a second electrode connected to a data line.

[0015] The capacitance of the compensation capacitor can be smaller than that of the capacitor.

[0016] In another aspect of this disclosure, a display device includes: a display panel including sub-pixels for displaying an image; and a driver configured to drive the display panel, wherein each of the sub-pixels includes a signal delay compensation circuit that is turned on according to a scan signal to compensate for the signal delay of the scan signal in response to a change in data voltage.

[0017] The signal delay compensation circuit may include: a compensation transistor having: a gate electrode connected to a scan line; and a first electrode connected to a DC voltage line; and a compensation capacitor having: a first electrode connected to a second electrode of the compensation transistor; and a second electrode connected to a data line.

[0018] The capacitance of the compensation capacitor can be smaller than the capacitance of the capacitor storing the data voltage.

[0019] In another aspect of this disclosure, a method of driving a display device includes: applying a scan signal to a scan line connected to the gate electrode of a switching transistor, and storing a data voltage applied through a data line in a capacitor; driving a signal delay compensation circuit based on the scan signal to compensate for signal delay of the scan signal in response to changes in the data voltage; and driving a driving transistor based on the data voltage to generate a driving current, and causing a light-emitting diode to emit light based on the driving current.

[0020] It should be understood that both the foregoing general description of this disclosure and the following detailed description are exemplary and illustrative, and are intended to provide further explanation of the claimed disclosure. Attached Figure Description

[0021] The accompanying drawings are included to provide a further understanding of this disclosure and are incorporated in and constitute a part of this application. These drawings illustrate embodiments of the disclosure and, together with the specification, serve to explain the principles of the disclosure. In the drawings:

[0022] Figure 1 This is a schematic block diagram illustrating a light-emitting display device;

[0023] Figure 2 and Figure 3 This is a diagram showing the configuration of the gate-type gate driver within the panel;

[0024] Figure 4 This is a diagram illustrating the circuit configuration of the sub-pixels according to the first embodiment;

[0025] Figure 5 This is a diagram illustrating the circuit configuration of the sub-pixels according to the second embodiment;

[0026] Figure 6 This is a diagram illustrating the circuit configuration of a sub-pixel according to the third embodiment;

[0027] Figure 7 This is a diagram showing the circuit configuration of the sub-pixels according to the fourth embodiment;

[0028] Figure 8 This is a diagram showing the driving waveform of a sub-pixel according to the fourth embodiment;

[0029] Figures 9 to 13 It shows the basis Figure 8 A diagram of the operational states of sub-pixels in the driving waveform;

[0030] Figure 14 The diagram shows a first scan signal, a data voltage, and the voltage value of a first switching transistor provided for describing signal delay compensation, in the case of a compensation transistor.

[0031] Figure 15 This is a simulation result showing the delay deviation of the first scan signal when the compensation transistor is not included;

[0032] Figure 16 This is a simulation result showing the delay deviation of the first scan signal when a compensation transistor is included. Detailed Implementation

[0033] The display device according to this disclosure can be implemented as a television, video player, personal computer (PC), home theater, automotive electrical system, smartphone, etc., but is not limited thereto. The display device according to this disclosure can be implemented as a light-emitting display (LED) device, a quantum dot display (QDD) device, a liquid crystal display (LCD) device, etc. However, for ease of description, a light-emitting display device based on direct emission from inorganic or organic light-emitting diodes is used as an example of the display device described below.

[0034] Furthermore, the transistors described below can be implemented as n-type transistors, p-type transistors, or a combination of n-type and p-type transistors. A transistor is a three-electrode device comprising a gate, a source, and a drain. The source is the electrode that supplies charge carriers to the transistor. In a transistor, charge carriers begin to flow from the source. The drain is the electrode through which charge carriers are released from the transistor. In other words, charge carriers flow from the source to the drain in a transistor.

[0035] In the case of a p-type transistor, the charge carriers are holes, and therefore the source voltage is higher than the drain voltage, allowing holes to flow from the source to the drain. Since holes flow from the source to the drain in a p-type transistor, current flows from the source to the drain. On the other hand, in the case of an n-type transistor, the charge carriers are electrons, and therefore the source voltage is lower than the drain voltage, allowing electrons to flow from the source to the drain. Since electrons flow from the source to the drain in an n-type transistor, current flows from the drain to the source. However, the source and drain of a transistor can change depending on the applied voltage. With this in mind, in the following description, one of the source and drain is described as the first electrode, and the other is described as the second electrode.

[0036] Figure 1 It is a schematic block diagram illustrating a light-emitting display device, and Figure 2 and Figure 3 This is a diagram showing the configuration of the gate-type gate driver within the panel.

[0037] like Figures 1 to 3 As shown, the light-emitting display device may include a timing controller 120, a gate driver (gate driving circuit) 130, a data driver (data driving circuit) 140, a display panel 150, and a power supply 180.

[0038] In addition to external image data signals or image data signals stored in internal memory, the image provider (device or host system) 110 can also output various drive signals. The image provider 110 can supply data signals and various drive signals to the timing controller 120.

[0039] The timing controller 120 can output a gate timing control signal GDC for controlling the operating timing of the gate driver 130, a data timing control signal DDC for controlling the operating timing of the data driver 140, and various synchronization signals (vertical synchronization signal Vsync and horizontal synchronization signal Hsync). The timing controller 120 can supply the data signal DATA supplied from the image provider 110 together with the data timing control signal DDC to the data driver 140. The timing controller 120 can be formed as an integrated circuit (IC) and mounted on a printed circuit board, but is not limited thereto.

[0040] Gate driver 130 can output a gate signal (or gate voltage) in response to a gate timing control signal GDC supplied from timing controller 120. Gate driver 130 can supply gate signals to sub-pixels included in display panel 150 via gate lines GL1 to GLm. Gate driver 130 can be formed as an IC, or it can be formed directly on display panel 150 as an in-panel gate structure, but is not limited thereto. However, as an example, for convenience, it will be described below as follows. Figure 2 and Figure 3 The in-panel gate type gate driver shown is illustrated.

[0041] The in-panel gate type gate driver 130 may include shift registers 130a and 130b formed on one side and the other side of the non-active region NA of the display panel 150 with an in-panel gate structure. The shift registers 130a and 130b may be formed in thin film on the non-active region NA of the display panel 150 with the in-panel gate structure. The in-panel gate type gate driver 130 may output gate signals Gate[1] to Gate[m] for turning on or off transistors formed in the active region AA of the display panel 150.

[0042] The in-panel gate type gate driver 130 can operate based on signals and voltages output from timing controller 120, power supply 180, and level shifter 160. The level shifter 160 can generate the gate control signals required to drive the in-panel gate type gate drivers 130, 130a, and 130b based on the signals and voltages output from timing controller 120 and power supply 180.

[0043] The data driver 140 can sample and latch the data signal DATA in response to the data timing control signal DDC supplied from the timing controller 120, convert the digital data signal into an analog data voltage based on the gamma reference voltage, and output the analog data voltage. The data driver 140 can supply data voltage to the sub-pixels included in the display panel 150 through data lines DL1 to DLn. The data driver 140 can be formed as an IC and mounted on the display panel 150 or a printed circuit board, but is not limited thereto.

[0044] Power supply 180 can generate high-level and low-level voltages based on an externally supplied input voltage, and output high-level and low-level voltages through the high-level voltage line EVDD and the low-level voltage line EVSS. Power supply 180 can not only generate and output high-level and low-level voltages, but also generate and output the voltages required to drive gate driver 130 or data driver 140.

[0045] Display panel 150 can be manufactured based on a rigid or flexible substrate such as glass, silicon, or polyimide. Display panel 150 may include a plurality of subpixels SP for displaying images. Subpixels SP can emit light directly toward an upper substrate, a lower substrate, or both of the upper and lower substrates of display panel 150. Each subpixel SP can emit a color, such as red, green, blue, or white. Display panel 150 can display images based on pixels composed of red, green, and blue subpixels, or pixels composed of red, green, blue, and white subpixels.

[0046] Meanwhile, the timing controller 120, gate driver 130, and data driver 140 are described as separate components. However, depending on the implementation method of the light-emitting display device, one or more of the timing controller 120, gate driver 130, and data driver 140 can be integrated into a single IC.

[0047] Figure 4 This is a diagram illustrating the circuit configuration of the sub-pixels according to the first embodiment. Figure 5 This is a diagram illustrating the circuit configuration of the sub-pixels according to the second embodiment. Figure 6 This is a diagram illustrating the circuit configuration of the sub-pixels according to the third embodiment, and Figure 7 This is a diagram showing the circuit configuration of a sub-pixel according to the fourth embodiment.

[0048] like Figure 4As shown, the sub-pixel SP according to the first embodiment may include a switching transistor T1, a compensation transistor CT, a driving transistor DT, a capacitor (or storage capacitor) CST, a compensation capacitor CB, and a light-emitting diode OLED. The compensation transistor CT and the compensation capacitor CB may be included in the signal delay compensation circuit CC.

[0049] The switching transistor T1 may have: a gate electrode connected to a first scan line SCAN1; a first electrode connected to a first data line DL1; and a second electrode connected to a gate node DTG. The switching transistor T1 may be turned on based on a first scan signal applied through the first scan line SCAN1, and may transmit a data voltage applied through the first data line DL1 to the first electrode of a capacitor CST connected to the gate node DTG. The switching transistor T1 may have capacitance due to a parasitic capacitance between the gate electrode and the first electrode. Therefore, the capacitance of the switching transistor T1 described below can be interpreted as parasitic capacitance.

[0050] The capacitor CST may have: a first electrode connected to the gate node DTG, the second electrode of the switching transistor T1 and the gate electrode of the driving transistor DT connected to the gate node DTG; and a second electrode connected to the source node DTS, the second electrode of the driving transistor DT and the anode of the light-emitting diode OLED connected to the source node DTS. The capacitor CST can apply a stored data voltage to the gate electrode of the driving transistor DT.

[0051] The compensation transistor CT may have: a gate electrode connected to a first scan line SCAN1; a first electrode connected to a high-level voltage line EVDD; and a second electrode connected to the first electrode of a compensation capacitor CB. The compensation transistor CT may be turned on based on a first scan signal applied through the first scan line SCAN1 to transmit a high-level voltage applied through the high-level voltage line EVDD to the first electrode of the compensation capacitor CB. The compensation transistor CT may be disposed adjacent to a switching transistor T1. The compensation transistor CT may compensate for the signal delay of the first scan signal applied to the gate electrode of the switching transistor T1 based on changes in the high-level voltage and changes in the data voltage, and a related description is given below.

[0052] The compensation capacitor CB may have: a first electrode connected to the second electrode of the compensation transistor CT; and a second electrode connected to the first data line DL1 and the first electrode of the switching transistor T1. The compensation capacitor CB can be used to prevent the formation of a current path between the second electrode of the compensation transistor CT and the first data line DL1 (or to prevent direct coupling between the data voltage and the high-level voltage applied through the compensation transistor). Therefore, the compensation capacitor CB corresponds to a circuit added to prevent the formation of a current path rather than for storing voltage, and can be implemented with a capacitance smaller than that of the capacitor CST.

[0053] The driving transistor DT may have: a gate electrode connected to the gate node DTG, the second electrode of the switching transistor T1 and the first electrode of the capacitor CST connected to the gate node DTG; a first electrode connected to the drain node DTD, which is connected to the high-level voltage line EVDD; and a second electrode connected to the source node DTS, the second electrode of the capacitor CST and the anode of the light-emitting diode OLED connected to the source node DTS. The driving transistor DT can operate based on the data voltage stored in the capacitor CST to generate a driving current.

[0054] An OLED can have: an anode connected to a source node DTS, a second electrode of a capacitor CST, and a second electrode of a driving transistor DT connected to the source node DTS; and a cathode connected to a low-level voltage line EVSS. The OLED can emit light based on a driving current generated from the driving transistor DT.

[0055] like Figure 5 As shown, the sub-pixel SP according to the second embodiment may include a switching transistor T1, a compensation transistor CT, a driving transistor DT, a capacitor CST, a compensation capacitor CB, a light-emitting diode OLED, and a pixel driving circuit PDC.

[0056] The sub-pixel SP according to the second embodiment is similar to the sub-pixel SP according to the first embodiment, but differs in that the sub-pixel SP according to the second embodiment further includes a pixel driving circuit PDC. The pixel driving circuit PDC may be related to the operation of at least one of a driving transistor DT, a capacitor CST, or a light-emitting diode OLED. The pixel driving circuit PDC may include circuitry that can apply a voltage applied from outside the sub-pixel SP to the interior of the sub-pixel SP or control the current or voltage generated inside the sub-pixel SP.

[0057] The pixel driving circuit (PDC) can be configured in various forms according to the circuitry included in the sub-pixel (SP) and its driving method, and is therefore shown as a box. In the following text, it will be based on... Figure 6 The third implementation method and Figure 7 The fourth implementation describes an example related to the pixel drive circuit PDC.

[0058] like Figure 6 As shown, the sub-pixel SP according to the third embodiment may include a first switching transistor T1, a second switching transistor T2, a third switching transistor T3, a fourth switching transistor T4, a compensation transistor CT, a driving transistor DT, a capacitor CST, a compensation capacitor CB, and a light-emitting diode OLED.

[0059] The second switching transistor T2, the third switching transistor T3, and the fourth switching transistor T4 may be included in Figure 5 The pixel driving circuit PDC shown is illustrated below. The second switching transistor T2, the third switching transistor T3, and the fourth switching transistor T4 will be described in the following text.

[0060] The second switching transistor T2 may have: a gate electrode connected to a second scan line SCAN2; a first electrode connected to a reference voltage line VREF; and a second electrode connected to a gate node DTG. The second switching transistor T2 may be turned on based on a second scan signal applied through the second scan line SCAN2 to transmit a reference voltage applied through the reference voltage line VREF to the gate node DTG.

[0061] The third switching transistor T3 may have: a gate electrode connected to a first emitter control line EM1; a first electrode connected to a high-level voltage line EVDD; and a second electrode connected to a drain node DTD. The third switching transistor T3 may be turned on based on a first emitter control signal applied through the first emitter control line EM1 to transmit a high-level voltage applied through the high-level voltage line EVDD to the first electrode of the driving transistor DT.

[0062] The fourth switching transistor T4 may have: a gate electrode connected to the second emission control line EM2; a first electrode connected to the source node (DTS); and a second electrode connected to the anode of the light-emitting diode OLED. The fourth switching transistor T4 may be turned on based on a second emission control signal applied through the second emission control line EM2 to transfer the drive current generated from the driving transistor DT to the anode of the light-emitting diode OLED.

[0063] like Figure 7As shown, the sub-pixel SP according to the fourth embodiment may include a first switching transistor T1, a second switching transistor T2, a third switching transistor T3, a fourth switching transistor T4, a fifth switching transistor T5, a sixth switching transistor T6, a compensation transistor CT, a driving transistor DT, a capacitor CST, a first compensation capacitor CB, a second compensation capacitor CA, and a light-emitting diode OLED.

[0064] The second switching transistor T2, the third switching transistor T3, the fourth switching transistor T4, the fifth switching transistor T5, the sixth switching transistor T6, and the second compensation capacitor CA can be included in... Figure 5 The pixel driving circuit PDC shown is described below. Since the second switching transistor T2, the third switching transistor T3, and the fourth switching transistor T4 have already been described in the third embodiment, the fifth switching transistor T5, the sixth switching transistor T6, and the second compensation capacitor CA will be described below.

[0065] The fifth switching transistor T5 may have: a gate electrode connected to a third scan line SCAN3; a first electrode connected to an initialization voltage line VAR; and a second electrode connected to the anode of the light-emitting diode OLED. The fifth switching transistor T5 may be turned on based on a third scan signal applied via the third scan line SCAN3 to transmit an initialization voltage applied via the initialization voltage line VAR to the anode of the light-emitting diode OLED.

[0066] The sixth switching transistor T6 may have: a gate electrode connected to the fourth scan line SCAN4; a first electrode connected to the reference voltage line VREF; and a second electrode connected to the first electrode of the second compensation capacitor CA. The sixth switching transistor T6 may be turned on based on a fourth scan signal applied through the fourth scan line SCAN4 to transmit a reference voltage applied through the reference voltage line VREF to the first electrode of the second compensation capacitor CA.

[0067] The second compensation capacitor CA may have: a first electrode connected to a second electrode of the sixth switching transistor T6, and a second electrode connected to the source node DTS. The second compensation capacitor CA enables a reference voltage applied through the sixth switching transistor T6 to be stably applied to / held at the source node DTS for a specific time period. In this way, when the second compensation capacitor CA is included in the sub-pixel SP, the compensation capacitor CB corresponds to circuitry added to prevent the formation of current paths rather than for storing voltage, and therefore can be implemented with a capacitance smaller than that of the capacitor CST and the second compensation capacitor CA.

[0068] In the first to fourth embodiments, examples have been shown and described where all transistors included in the sub-pixel SP are n-type transistors, but at least one of them may be a p-type transistor. That is, the transistors included in the sub-pixel SP may be configured as n-type transistors, p-type transistors, or a mixture of n-type and p-type transistors.

[0069] Furthermore, in the first to fourth embodiments, an example has been shown and described where the first electrode of the compensation transistor CT is connected to a high-level voltage line EVDD, but it can be connected to a DC voltage line that applies a voltage higher than the low-level voltage. That is, the compensation transistor CT can be connected to a separately provided DC voltage line.

[0070] The subpixel operations according to the first to third embodiments can be considered similar to the subpixel operations according to the fourth embodiment described below, and the subpixel operations will be described in the fourth embodiment.

[0071] Figure 8 This is a diagram showing the driving waveform of the sub-pixel according to the fourth embodiment, and Figures 9 to 13 It shows the basis Figure 8 A diagram showing the operational states of sub-pixels in the driving waveform.

[0072] like Figures 8 to 13 As shown, the sub-pixel SP according to the fourth embodiment can operate in the following order: first initialization phase INI, threshold voltage sensing phase SEN, data writing phase WRT, second initialization phase ART, and transmission phase EMT. The above operations will be described in sequence below.

[0073] like Figure 8 and Figure 9 As shown, during the first initialization phase INI, the second switching transistor T2, the fourth switching transistor T4, the fifth switching transistor T5, and the sixth switching transistor T6 can be turned on. For this purpose, a second transmit control signal Em2 at a high voltage can be applied to the second transmit control line EM2, a second scan signal Scan2 at a high voltage can be applied to the second scan line SCAN2, a third scan signal Scan3 at a high voltage can be applied to the third scan line SCAN3, and a fourth scan signal Scan4 at a high voltage can be applied to the fourth scan line SCAN4. Note that low voltage signals are applied to the remaining lines (not described).

[0074] During the first initialization phase INI, the second switching transistor T2, the fourth switching transistor T4, the fifth switching transistor T5, and the sixth switching transistor T6 can perform the following operations.

[0075] The second switching transistor T2 transmits the reference voltage Vref applied through the reference voltage line VREF to the gate node DTG. The sixth switching transistor T6 transmits the reference voltage Vref applied through the reference voltage line VREF to the first electrode of the second compensation capacitor CA. The fifth switching transistor T5 transmits the initialization voltage Var applied through the initialization voltage line VAR to the anode of the light-emitting diode OLED. The fourth switching transistor T4 transmits the initialization voltage Var applied through the fifth switching transistor T5 to the source node DTS.

[0076] Therefore, the voltage of the gate node DTG of the driving transistor DT can be increased based on the reference voltage Vref, and the voltage of the source node DTS of the driving transistor DT can be decreased based on the initialization voltage Var.

[0077] like Figure 8 and Figure 10 As shown, during the threshold voltage sensing phase (SEN), the second switching transistor T2, the third switching transistor T3, the drive transistor DT, the fifth switching transistor T5, and the sixth switching transistor T6 can be turned on. For this purpose, a first transmit control signal Em1 at a high voltage can be applied to the first transmit control line EM1, a second scan signal Scan2 at a high voltage can be applied to the second scan line SCAN2, a third scan signal Scan3 at a high voltage can be applied to the third scan line SCAN3, and a fourth scan signal Scan4 at a high voltage can be applied to the fourth scan line SCAN4. Note that low voltage signals are applied to the remaining lines (not described).

[0078] During the threshold voltage sensing phase (SEN), the second switching transistor T2, the third switching transistor T3, the drive transistor DT, the fifth switching transistor T5, and the sixth switching transistor T6 can perform the following operations.

[0079] The second switching transistor T2 transmits the reference voltage Vref applied through the reference voltage line VREF to the gate node DTG. The sixth switching transistor T6 transmits the reference voltage Vref applied through the reference voltage line VREF to the first electrode of the second compensation capacitor CA. The fifth switching transistor T5 transmits the initialization voltage Var applied through the initialization voltage line VAR to the anode of the light-emitting diode OLED. The third switching transistor T3 transmits the high-level voltage applied through the high-level voltage line EVDD to the first electrode of the driving transistor DT.

[0080] Therefore, the voltage at the gate node DTG of the driving transistor DT can be maintained at a level that increases based on the reference voltage Vref, and the voltage at the source node DTS of the driving transistor DT can increase based on the reference voltage Vref, and can sense (sample) a voltage similar to the threshold voltage.

[0081] like Figure 8 and Figure 11 As shown, during the data writing phase (WRT), the first switching transistor T1, the compensation transistor CT, the fifth switching transistor T5, and the sixth switching transistor T6 can be turned on. For this purpose, a first scan signal Scan1 at a high voltage can be applied to the first scan line SCAN1, a third scan signal Scan3 at a high voltage can be applied to the third scan line SCAN3, and a fourth scan signal Scan4 at a high voltage can be applied to the fourth scan line SCAN4. Note that low voltage signals are applied to the remaining lines (not described).

[0082] During the data writing phase (WRT), the first switching transistor T1, the compensation transistor CT, the fifth switching transistor T5, and the sixth switching transistor T6 can perform the following operations.

[0083] The first switching transistor T1 transmits the data voltage Vdata applied via the first data line DL1 to the gate node DTG. The compensation transistor CT transmits the high-level voltage applied via the high-level voltage line EVDD to the first electrode of the compensation capacitor CB. The sixth switching transistor T6 transmits the reference voltage Vref applied via the reference voltage line VREF to the first electrode of the second compensation capacitor CA. The fifth switching transistor T5 transmits the initialization voltage Var applied via the initialization voltage line VAR to the anode of the light-emitting diode OLED.

[0084] Therefore, the data voltage Vdata can be applied to the first electrode of capacitor CST, and the voltages of the gate node DTG and source node DTS of the driving transistor DT can be increased based on the data voltage Vdata.

[0085] like Figure 8 and Figure 12 As shown, during the second initialization phase (ART), the fourth switching transistor T4 and the fifth switching transistor T5 can be turned on. For this purpose, a second emission control signal Em2 at a high voltage can be applied to the second emission control line Em2, and a third scan signal Scan3 at a high voltage can be applied to the third scan line SCAN3. Note that low voltage signals are applied to the remaining lines (not described).

[0086] During the second initialization phase ART, the fourth switching transistor T4 and the fifth switching transistor T5 can perform the following operations.

[0087] The fifth switching transistor T5 can transmit the initialization voltage Var applied through the initialization voltage line VAR to the anode of the light-emitting diode OLED. The fourth switching transistor T4 can transmit the initialization voltage Var transmitted through the fifth switching transistor T5 to the source node DTS of the driving transistor DT.

[0088] Therefore, the anode of an OLED can be initialized based on the initialization voltage Var, and the voltages of the gate node DTG and source node DTS of the driving transistor DT can be reduced based on the initialization voltage Var.

[0089] like Figure 8 and Figure 13 As shown, during the transmit phase (EMT), the third switching transistor T3, the drive transistor DT, and the fourth switching transistor T4 can be turned on. For this purpose, a first transmit control signal Em1 at a high voltage can be applied to the first transmit control line EM1, and a second transmit control signal Em2 at a high voltage can be applied to the second transmit control line EM2. Note that low-voltage signals are supplied to the remaining lines (not described).

[0090] During the EMT phase, the third switching transistor T3, the drive transistor DT, and the fourth switching transistor T4 can perform the following operations.

[0091] The third switching transistor T3 can transmit a high-level voltage applied through the high-level voltage line EVDD to the first electrode of the driving transistor DT. The driving transistor DT can operate based on the data voltage stored in the capacitor CST to generate a driving current. The fourth switching transistor T4 can transmit the driving current generated from the driving transistor DT to the anode of the light-emitting diode OLED.

[0092] Therefore, the voltages DT Vgs of the gate node DTG and source node DTS of the driving transistor DT can be increased based on the operation caused by the generation of the driving current, and the light-emitting diode OLED can operate to emit light based on the driving current generated from the driving transistor DT.

[0093] Meanwhile, the compensation transistor CT and compensation capacitor CB included in the sub-pixel SP can be used as a signal delay compensation circuit CC to compensate for the signal delay (including signal delay variation) of the first scan signal, which will be described below.

[0094] Figure 14 The diagram shows a first scan signal, a data voltage, and the voltage values ​​of a first switching transistor provided for describing signal delay compensation, with the inclusion of a compensation transistor. Figure 15 It is a simulation result used to describe the delay deviation of the first scan signal according to the change in data voltage, and Figure 16 It is used to describe the simulation results of compensating for the delay deviation of the first scan signal based on the compensation capacitor.

[0095] Figure 14 The diagram illustrates the application of a first scan signal Scan1 as a high voltage (or on voltage) (on) and a low voltage (or off voltage) (off), and the application of a first data voltage W and a second data voltage B as examples of data voltage Vdata. Furthermore, Figure 14 The changes in the gate voltage G, source voltage S, and drain voltage D of the first switching transistor, the gate-source voltage Vgs, and the drain-source voltage Vds are shown due to the first scan signal Scan1 and the data voltage Vdata.

[0096] refer to Figure 14 The results show that when the first scan signal Scan1 is applied as a high voltage (or on-state voltage), the capacitance of the first switching transistor can change due to the accompanying operation of the compensation transistor CT in response to changes in the gate-source voltage Vgs. For example, when the data voltage is applied as a low grayscale voltage (e.g., the second data voltage B), the capacitance of the first switching transistor may decrease due to the accompanying operation of the compensation transistor CT, and when the data voltage is applied as a high grayscale voltage (e.g., the first data voltage W), the capacitance of the first switching transistor may increase due to the accompanying operation of the compensation transistor CT.

[0097] In this way, the signal delay compensation circuit, including the compensation transistor CT, can change the capacitance of the first switching transistor in response to changes in the data voltage Vdata, and thus can compensate for the signal delay (including signal delay variations) of the first scan signal. Furthermore, since the amount of capacitance change caused by variations in the data voltage (or grayscale changes in the pattern) can be differentially compensated, the signal delay of the scan signal can be eliminated without increasing the load on the gate node of the driving transistor. Moreover, horizontal crosstalk HXT that may be caused per horizontal line (or per scan line) during data voltage writing can be mitigated based on the compensation for the signal delay (including signal delay variations) of the first scan signal.

[0098] At the same time, it should be noted that Figure 14 The voltage values ​​shown in the results table are example values ​​used to describe signal delay compensation when a compensation transistor is included.

[0099] like Figure 15As shown, the delay deviation of the first scan signal may be caused by the capacitance difference of the first switching transistor due to changes in the data voltage. The delay deviation of the first scan signal can be inferred / predicted based on the difference between a first voltage V1 and a second voltage V2, which shows the capacitance difference of the first switching transistor due to changes in the data voltage.

[0100] like Figure 16 As shown, compensation for the delay deviation of the first scan signal can be improved based on the capacitance change of the first switching transistor, according to the operating conditions of the compensation transistor. The compensation for the delay deviation of the first scan signal can be inferred / predicted based on the difference between a first condition (TFT Cap@high Vds) and a second condition (TFT Cap@low Vds) representing the operating conditions of the compensation transistor according to the data voltage change and the capacitance change of the first switching transistor according to the data voltage change (or the difference between a third voltage V3 and a fourth voltage V4 based on the capacitance difference of the first switching transistor).

[0101] As described above, this disclosure has the effect of mitigating horizontal crosstalk (HXT) that may be caused per horizontal line (or per scan line) during data writing by compensating for the delay of the scan signal (including signal delay variations). Furthermore, this disclosure has the effect of eliminating scan signal delay without increasing the load on the gate node of the driving transistor by differentially compensating for the amount of capacitance change caused by variations in data voltage (or grayscale variations in the pattern). In addition, this disclosure has the effect of uniformly improving display quality based on reduced horizontal crosstalk.

[0102] It will be apparent to those skilled in the art that various modifications and variations can be made to this disclosure without departing from its spirit or scope. Therefore, this disclosure is intended to cover modifications and variations thereof, provided they fall within the scope of the appended claims and their equivalents.

Claims

1. A display device, comprising: A switching transistor that turns on according to a scan signal applied through a scan line to transfer a data voltage applied through a data line to a capacitor; A signal delay compensation circuit is activated according to the scan signal to compensate for the signal delay of the scan signal in response to changes in the data voltage; A driving transistor, configured to generate a driving current based on a data voltage stored in the capacitor; as well as A light-emitting diode, configured to operate to emit light based on the drive current.

2. The display device according to claim 1, wherein, The signal delay compensation circuit changes the capacitance of the switching transistor in response to changes in the data voltage.

3. The display device according to claim 1, wherein, The signal delay compensation circuit includes a compensation transistor having: a gate electrode connected to the scan line; and a first electrode connected to a DC voltage line.

4. The display device according to claim 3, wherein, The compensation transistor changes the capacitance of the switching transistor based on the change in the DC voltage applied through the DC voltage line and the change in the data voltage.

5. The display device according to claim 1, wherein, The signal delay compensation circuit includes: A compensation transistor has: a gate electrode connected to the scan line; and a first electrode connected to a high-level voltage line; and A compensation capacitor having: a first electrode connected to a second electrode of the compensation transistor; and a second electrode connected to the data line.

6. The display device according to claim 5, wherein, The capacitance of the compensation capacitor is smaller than the capacitance of the capacitor.

7. The display device according to claim 6, further comprising: A pixel driving circuit that relates to the operation of at least one of the driving transistor, the capacitor, or the light-emitting diode.

8. The display device according to claim 7, wherein, The pixel driving circuit includes: a second switching transistor, a third switching transistor, a fourth switching transistor, a fifth switching transistor, a sixth switching transistor, and a second compensation capacitor, wherein the second compensation capacitor is connected between the sixth switching transistor and the capacitor.

9. The display device according to claim 8, wherein, The capacitance of the compensation capacitor is less than the capacitance of the second compensation container.

10. A display device, comprising: The display panel includes sub-pixels for displaying images; as well as A driver configured to drive the display panel. Each of the sub-pixels includes a signal delay compensation circuit that is turned on according to the scan signal to compensate for the signal delay of the scan signal in response to changes in the data voltage.

11. The display device according to claim 10, wherein, The signal delay compensation circuit includes: A compensation transistor has: a gate electrode connected to a scan line; and a first electrode connected to a DC voltage line; and A compensation capacitor has: a first electrode connected to a second electrode of the compensation transistor, and a second electrode connected to a data line.

12. The display device according to claim 11, wherein, The capacitance of the compensation capacitor is less than the capacitance of the capacitor storing the data voltage.

13. A method for driving a display device, comprising: A scan signal is applied to the scan line connected to the gate electrode of the switching transistor, and the data voltage applied through the data line is stored in the capacitor; The scanning signal drives a signal delay compensation circuit to compensate for the signal delay of the scanning signal in response to changes in the data voltage. as well as The driving transistor is driven based on the data voltage to generate a driving current, and the light-emitting diode is made to emit light based on the driving current.

14. The method according to claim 13, wherein, The signal delay compensation circuit includes: changing the capacitance of the switching transistor in response to changes in the data voltage.

15. The method according to claim 13, wherein, The signal delay compensation circuit includes: A compensation transistor has: a gate electrode connected to a scan line; and a first electrode connected to a DC voltage line; and A compensation capacitor has: a first electrode connected to a second electrode of the compensation transistor, and a second electrode connected to a data line. The compensation transistor changes the capacitance of the switching transistor based on the change in the DC voltage applied through the DC voltage line and the change in the data voltage.

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