A circuit structure for LCD anti-inductive ESD

Abstract

This invention discloses a circuit structure for ESD protection of an LCD, including an LCD module and a circuit board electrically connected to the LCD module. The circuit board includes a reset potential stabilization unit electrically connected to the RES reset pin of the LCD module and a power surge protection unit electrically connected to the power supply terminal. The reset potential stabilization unit and the power surge protection unit cooperate to achieve ESD protection for the LCD. The reset potential stabilization unit includes a pull-up resistor, with its first end electrically connected to the power supply terminal and its second end electrically connected to the RES reset pin. The power surge protection unit includes at least one TVS diode connected in parallel between the power supply terminal and ground. This invention can stabilize the RES reset pin level and reduce ESD sensitivity, discharge ESD surges at the power supply terminal, and achieve ESD protection through the cooperation of two units. The circuit is extremely simple and has low modification costs.

Description

Technical Field

[0001] This invention relates to the field of electrostatic discharge (ESD) protection technology for electronic circuits, and more particularly to a circuit structure for LCD anti-induced ESD. Background Technology

[0002] With the widespread application of liquid crystal display (LCD) modules in consumer electronics, industrial control, and imaging equipment, the requirements for electrostatic discharge (ESD) performance of LCD modules are continuously increasing. ESD resistance has become one of the core indicators for measuring the reliability of LCD modules. Currently, most ESD protection solutions in the industry are designed for contact ESD scenarios where electrostatic discharge directly hits the LCD module body. For non-contact induced ESD scenarios—that is, scenarios where electrostatic discharge does not directly contact the LCD body but generates induced electrostatic voltage in the internal circuitry of the LCD through electric field coupling—existing technologies lack targeted failure mechanism research and efficient protection solutions.

[0003] CN218299350U discloses a novel LCD circuit protection structure. This structure constructs an RC discharge circuit and voltage clamping protection system by setting an RC protection unit consisting of a protective resistor and capacitor, a grounded TVS diode, and ferrite beads at the front end of the LCD cable. This aims to solve the problem of LCD internal display chip breakdown failure caused by ESD and EOS. However, this solution is a generalized full-pin protection design. It does not accurately locate the LCD failure mechanism and core failure point in induced ESD scenarios. By stacking multiple components to achieve protection, it not only increases circuit design complexity and material costs but also fails to address the LCD black screen problem caused by abnormal potentials on key pins due to electrostatic coupling in non-contact induced ESD scenarios. Therefore, it cannot meet the protection requirements of high-level induced ESD testing.

[0004] CN110346973A discloses a liquid crystal display backlight module, which achieves ESD protection by wrapping the driver IC with grounded conductive copper foil, setting a TVS diode on the module FPC, and optimizing the GND electrostatic discharge path of the backlight FPC. This solution relies on structural shielding and a global electrostatic discharge path design, and can only cope with application scenarios where electrostatic discharge directly hits the LCD module body. For special test scenarios where electrostatic discharge does not directly contact the LCD body but only generates induced electrostatic discharge through coupling via the grounded copper foil, it cannot effectively suppress the potential disturbances generated by induced electrostatic discharge on critical signal lines. Furthermore, this solution requires a complete modification of the LCD module's backlight structure and grounding system, resulting in high design and modification costs, and cannot meet the needs of rapid modification and mass application of existing standard LCD modules.

[0005] In summary, existing technologies all focus on direct contact ESD protection for LCDs, failing to reveal the failure mechanism of LCDs in non-contact ESD scenarios, and failing to propose targeted, precise, and efficient protection solutions. They cannot meet the high-level ESD testing requirements of end customers. Therefore, there is an urgent need to develop an anti-ESD technology solution that can accurately solve the problem of LCD display failure caused by ESD, with a simple solution, strong compatibility, and low modification cost. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to provide a circuit structure for LCD anti-induced ESD, which can stabilize the level of the RES reset pin and reduce ESD sensitivity, discharge ESD surge at the power supply terminal, and achieve anti-induced ESD through the cooperation of two units. The circuit is extremely simple and has low modification cost.

[0007] To solve the above-mentioned technical problems, the first aspect of the present invention discloses a circuit structure for LCD anti-induced ESD, including an LCD module and a circuit board electrically connected to the LCD module; The circuit board is provided with a reset potential stabilization unit electrically connected to the RES reset pin of the LCD module and a power surge protection unit electrically connected to the power supply terminal. The reset potential stabilization unit and the power surge protection unit work together to achieve anti-induced ESD protection of the LCD. The reset potential stabilization unit includes a pull-up resistor, the first end of which is electrically connected to the power supply terminal, and the second end of which is electrically connected to the RES reset pin. The power surge protection unit includes at least one TVS diode, which is connected in parallel between the power supply terminal and ground.

[0008] As an optional implementation, the reset potential stabilization unit further includes a filter capacitor, the first end of which is electrically connected to the RES reset pin, and the second end of which is grounded.

[0009] As another optional implementation, the pull-up resistor has a resistance value of 1kΩ to 10kΩ.

[0010] As another alternative implementation, the TVS tube is a bidirectional TVS tube.

[0011] As another optional implementation, the capacitance of the filter capacitor is 10nF or 0.1μF.

[0012] As another optional implementation, the circuit board is also provided with a multi-channel power filtering unit, which is electrically connected to the VDD pin and IOVDD pin of the LCD module respectively; each power filtering unit includes at least one power filtering capacitor, one end of which is electrically connected to the corresponding power pin, and the other end of which is grounded.

[0013] As another optional implementation, a zero-ohm isolation resistor is connected in series on the power supply lines of the VDD pin and the IOVDD pin, and the zero-ohm isolation resistor is located between the power input terminal and the corresponding power filter unit.

[0014] As another optional implementation, the circuit board is also provided with a signal protection unit that is electrically connected to the MIPI signal pins of the LCD module one by one. The signal protection unit includes a signal protection TVS tube that matches the number of MIPI signal pins. One end of the single signal protection TVS tube is electrically connected to the corresponding MIPI signal pin, and the other end of the signal protection TVS tube is grounded.

[0015] As another optional implementation, a MIPIBUFFER buffer is connected in series on the MIPI signal line of the circuit board, and the MIPIBUFFER buffer is located between the MIPI signal output terminal of the host and the MIPI signal pin of the LCD module.

[0016] As another optional implementation, an isolation unit is provided between the analog ground network and the digital ground network of the circuit board. The isolation unit includes a ferrite bead, an isolation resistor and an isolation capacitor arranged in parallel. The two ends of the isolation unit are electrically connected to the analog ground network and the digital ground network, respectively.

[0017] Compared with the prior art, the embodiments of the present invention have the following beneficial effects: The reset potential stabilization unit in this embodiment provides a stable pull-up level to the RES reset pin through a pull-up resistor, clamping the high-impedance reset pin to a fixed high level, significantly reducing its sensitivity to induced ESD interference, suppressing abnormal potential jumps of the reset pin caused by ESD at the source, and reducing LCD false reset and black screen failures; the power surge protection unit quickly discharges the induced ESD surge current coupled to the power supply VDD through a TVS diode, while clamping the overvoltage of the power supply VDD to avoid abnormal LCD operation caused by power fluctuations; the two units work together to achieve anti-induced ESD protection from two core dimensions: reset pin level stabilization and power rail protection. The circuit topology is extremely simple, requiring no additional complex chips, and can be directly adapted to the hardware design of existing LCD modules, with low modification costs. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of a circuit structure for LCD anti-inductive ESD disclosed in an embodiment of the present invention; Figure 2 This is a schematic diagram of the main circuit structure of another LCD anti-sensory ESD circuit structure disclosed in an embodiment of the present invention; Figure 3 This is a partial circuit structure diagram of an LCD anti-sensory ESD circuit structure disclosed in an embodiment of the present invention; Figure 4 This is a schematic diagram of the protection circuit for an LCD anti-induced ESD circuit structure disclosed in an embodiment of the present invention; Figure 5 This is a schematic diagram of the circuit structure of a BUFFER buffer, which is a circuit structure for LCD anti-inductive ESD disclosed in an embodiment of the present invention. Detailed Implementation

[0020] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] Example 1 See Figure 1 This invention discloses a circuit structure for resisting inductive ESD in an LCD, including an LCD module U2 and a circuit board electrically connected to the LCD module U2; The circuit board is provided with a reset potential stabilization unit electrically connected to the RES reset pin RESX of the LCD module U2, and a power surge protection unit electrically connected to the power supply terminal VDD. The reset potential stabilization unit and the power surge protection unit work together to achieve anti-induced ESD protection of the LCD. The reset potential stabilization unit includes a pull-up resistor R1, the first end of which is electrically connected to the power supply terminal VDD, and the second end of which is electrically connected to the RES reset pin RESX. The power surge protection unit includes at least one TVS diode D1, which is connected in parallel between the power supply terminal VDD and ground.

[0022] The RES reset pin RESX of LCD module U2 is in a high-impedance input state, making it extremely sensitive to spatially induced ESD interference. It is prone to abnormal potential jumps, triggering LCD malfunctions and black screens. This invention specifically optimizes the high-impedance state of the RES reset pin RESX. The reset potential stabilization unit provides a stable pull-up level to the RES reset pin RESX through a pull-up resistor R1, clamping the high-impedance reset pin to a fixed high level, significantly reducing its sensitivity to induced ESD interference. This fundamentally suppresses abnormal potential jumps in the reset pin caused by ESD, reducing LCD malfunctions and black screens. The power surge protection unit quickly discharges the induced ESD surge current coupled to the power supply VDD through a TVS diode D1, while simultaneously clamping overvoltage at the power supply VDD to prevent LCD malfunctions caused by power fluctuations. These two units work together to achieve anti-induced ESD protection from two core dimensions: reset pin level stabilization and power rail protection. The circuit topology is extremely simple, requiring no additional complex chips, and can be directly adapted to the existing hardware design of LCD module U2, resulting in low modification costs.

[0023] In this embodiment, the selection of the TVS tube D1 (including power protection and signal protection TVS tube D1) must meet the following requirements: the minimum breakdown voltage is higher than the rated operating voltage of the corresponding protection line, so as to avoid the TVS tube D1 from being mis-conducted when the circuit is working normally, which would affect the normal operation of the circuit.

[0024] In an optional embodiment, the reset potential stabilization unit further includes a filter capacitor C5, the first end of which is electrically connected to the RES reset pin RESX, and the second end of which is grounded.

[0025] The filter capacitor C5 and the pull-up resistor R1 in the core solution together form an RC filter branch, which is adapted to the normal reset timing requirements of the LCD reset pin. It can filter out the high-frequency induced ESD spike interference coupled on the RES reset pin RESX, further improve the potential stability of the reset pin, and form a two-level anti-interference protection with the pull-up resistor R1, without affecting the response timing of the normal reset signal of the LCD.

[0026] In another optional embodiment, the pull-up resistor R1 has a resistance value of 1kΩ to 10kΩ. This embodiment represents the preferred range of key parameters for the core solution. Those skilled in the art can select a specific resistance value within this range based on the drive specifications of the reset pin of the LCD module U2. This resistance range can simultaneously meet two core requirements: first, it ensures the pull-up drive capability of the RES reset pin RSX, avoiding static level deviation and ensuring level stability during normal LCD reset and standby states; second, it acts as a current limiter when ESD interference occurs, balancing the reset signal response speed and anti-interference capability, and is compatible with the electrical specifications of the reset pin of most LCD modules U2.

[0027] Optionally, the preferred value of the pull-up resistor R1 is 4.7kΩ. This value is the optimal value verified by actual circuits and can simultaneously meet the reset drive requirements of most LCD modules U2 and the ESD interference resistance.

[0028] In yet another optional embodiment, the TVS tube D1 is a bidirectional TVS tube D1.

[0029] This embodiment optimizes the selection of components for a power surge protection unit. It can simultaneously suppress both forward and reverse induced ESD surges on the power rail, adapting to bidirectional overvoltage interference scenarios that may occur in power lines. Compared to a unidirectional TVS diode D1, it offers more comprehensive protection coverage and is suitable for the complex electromagnetic interference environment of LCD power supply lines.

[0030] In yet another optional embodiment, the capacitance of the filter capacitor C5 is 10nF or 0.1μF.

[0031] This embodiment provides optimized parameters for the reset pin filter capacitor C5. Both capacitance values ​​are common and mature parameters for reset circuit filtering in the electronics industry, and can be directly adapted to general surface mount packages. The 10nF capacitance value is specifically adapted to the filtering requirements of high-frequency ESD spike interference, while the 0.1μF capacitance value takes into account the suppression capability of mid-to-low frequency ripple. Both capacitance values ​​can be matched with pull-up resistors R1 from 1kΩ to 10kΩ to form an RC filter time constant adapted to the LCD reset circuit. The preferred general capacitance value can be directly adapted to the miniaturized surface mount design of LCD circuit boards without the need for customized components, and has strong versatility.

[0032] Example 2 See Figures 2-5 This invention discloses another circuit structure for LCD anti-inductive ESD, which differs from Embodiment 1 in that: The circuit board is also provided with a multi-channel power filtering unit, which is electrically connected to the VDD pin and IOVDD pin of the LCD module respectively. Each power filtering unit includes at least one power filtering capacitor, one end of which is electrically connected to the corresponding power pin, and the other end of which is grounded.

[0033] This embodiment optimizes the entire power supply system by setting up separate filtering units for the two independent power supply links (VDD and IO interface power supply, IOVDD) of the LCD module, without any cross-linking. It can selectively filter out the ripple and coupled ESD interference of each power supply line, block the interference crosstalk between the VDD and IOVDD power supply links, and avoid the ESD interference of a single power supply affecting the power supply stability of the entire LCD module, thus achieving anti-interference optimization of the entire power supply link.

[0034] In an optional embodiment, a zero-ohm isolation resistor is connected in series on the power supply lines of both the VDD pin and the IOVDD pin (see [link to relevant documentation]). Figure 3 (R3 and R2 in the text), the zero-ohm isolation resistor is located between the power input terminal and the corresponding power filter unit.

[0035] This embodiment is an advanced protection design for power supply lines. The zero-ohm isolation resistor is connected in series between the power input terminal and the power filter unit. It can realize electrical isolation between the front and rear stages of the power supply line, block the conduction path of induced ESD interference on the power supply line, and at the same time, it does not affect the normal DC power supply of the power supply line. It can also serve as a test node for the power supply line, which is convenient for later hardware debugging and fault diagnosis.

[0036] In another optional embodiment, the circuit board is further provided with a signal protection unit that is electrically connected to the MIPI signal pins of the LCD module in a one-to-one correspondence. The signal protection unit includes a signal protection TVS diode that matches the number of MIPI signal pins (see [link]). Figure 4 D6~D11 in the middle correspond to Figure 5 (Six MIPI signal pins in the middle), one end of the signal protection TVS tube of a single channel is electrically connected to the corresponding MIPI signal pin, and the other end of the signal protection TVS tube is grounded.

[0037] This embodiment provides dedicated ESD protection for MIPI signal lines. Each MIPI signal pin corresponds to an independent signal protection TVS diode, eliminating the need for multiple channels to share protection devices. It can directly discharge induced ESD surge current coupled on the MIPI signal line, clamp overvoltage on the signal line, protect the MIPI signal pins of the LCD module and the back-end drive circuit, and avoid MIPI signal errors, LCD screen distortion, and screen flickering caused by ESD interference.

[0038] In another optional embodiment, a MIPIBUFFER buffer is connected in series on the MIPI signal line of the circuit board, and the MIPIBUFFER buffer is located between the MIPI signal output terminal of the host and the MIPI signal pin of the LCD module.

[0039] Optionally, the MIPIBUFFER can be a multi-channel differential signal buffer chip adapted to the MIPID-PHY communication protocol, with its number of channels matching the number of MIPI data channels and clock channels of the LCD module. The host unit is the main control device of the display system relative to the LCD module. Common specific devices / chips include: core control chips for consumer electronics / industrial equipment: such as SOC (System-on-a-Chip), MCU (Microcontroller), and dedicated LCD driver chips; and the device's LCD driver board: an interface on the driver board specifically for outputting MIPI display signals (controlled by the onboard main control chip).

[0040] This embodiment is a design for optimizing MIPI signal integrity. The MIPIBUFFER is connected in series between the host and the LCD module. It can buffer and amplify the MIPI differential signal, compensate for the attenuation and distortion of the MIPI signal after long-distance transmission through the circuit board, improve the MIPI signal integrity, and block the ESD interference conduction path between the host and the LCD module, further improving the anti-induced ESD capability of the MIPI line.

[0041] In another optional embodiment, an isolation unit is provided between the analog ground network and the digital ground network of the circuit board. The isolation unit includes a ferrite bead, an isolation resistor, and an isolation capacitor arranged in parallel. The two ends of the isolation unit are electrically connected to the analog ground network and the digital ground network, respectively.

[0042] This embodiment is a system-level anti-interference optimization. It achieves the isolation design between analog ground and digital ground by using a topology of parallel connection of ferrite beads, isolation resistors and isolation capacitors. The ferrite beads can suppress crosstalk of high-frequency switching noise from digital ground to analog ground. The isolation resistor ensures that analog ground and digital ground are DC equipotential, avoiding LCD false reset caused by ground potential difference. The isolation capacitor provides a low-impedance discharge path for high-frequency ESD interference. It blocks the propagation of induced ESD interference throughout the system from the ground plane level, improving the anti-interference consistency and stability of the entire circuit.

[0043] Those skilled in the art can combine the technical solutions of multiple optional embodiments in any way according to the actual application scenario and hardware specifications of the LCD module to form a full-link anti-ESD protection solution.

[0044] Figure 3The circuit shown in the upper right area is a VDD main power rail ESD protection + π-type filter circuit: ESD protection TVS diode D1 (model LESD9D3.3CT5G) is connected in parallel between the VDD power input terminal and ground, and together with the front-stage filter capacitor C8, 0Ω isolation resistor R2, and the rear-stage parallel filter capacitors C6+C7, it forms a complete topology of ESD protection + π-type power filtering.

[0045] Figure 3 The circuit shown in the upper left area is an independent ESD protection + π-type filter circuit for IOVDD (IO power rail): it forms a symmetrical design with the VDD main power supply. The ESD protection TVS diode D2 (model SE1V8FBN102) is connected in parallel between the IOVDD power input terminal and ground. It is paired with the front-stage filter capacitor C16, the 0Ω isolation resistor R3, and the rear-stage parallel filter capacitors C15+C14 to form an independent protection filter topology for the IO power rail.

[0046] Figure 3 The circuit shown in the lower area is an analog ground-digital ground isolation circuit (the core design for anti-interference of the ground network): a 1MΩ resistor R4, a ferrite bead R5 (model BLM15AG102SN1D), and an isolation capacitor C9 are connected in parallel, with their two ends connected across the digital ground network and the analog ground network, respectively.

[0047] Figure 4 The circuit shown is a dedicated ESD protection circuit for MIPI differential signals: D6~D11 in the figure are all low-capacitance ESD protection TVS diodes of model SE1V8FBN102, which are protection devices specifically adapted to MIPI high-speed differential signals; the topology is single-channel signal parallel protection to ground: one end of each TVS diode is connected to the corresponding MIPI differential signal line (DP1+ / DN1-, CLKP+ / CLKN-, DP0+ / DN0-), and the other end is directly grounded.

[0048] Figure 5 This is the hardware circuit schematic of the MIPID-PHY dedicated signal buffer (also called MIPI redrive / relay chip): The core function of this circuit is to buffer and amplify the MIPI differential signal of the LCD display, redrive the signal, and compensate for losses, so as to solve the problems of attenuation, distortion and bit error of MIPI signal after transmission through long FPC cables. At the same time, it works with ESD protection devices to improve the anti-interference and anti-induced ESD capabilities of the MIPI line.

[0049] The content disclosed in the embodiments of this invention is only a preferred embodiment of the invention and is used only to illustrate the technical solutions of the invention, not to limit it. Although the invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this invention.

Claims

1. A circuit structure for LCD anti-inductive ESD, characterized in that, Includes an LCD module and a circuit board electrically connected to the LCD module; The circuit board is provided with a reset potential stabilization unit electrically connected to the RES reset pin of the LCD module and a power surge protection unit electrically connected to the power supply terminal. The reset potential stabilization unit and the power surge protection unit work together to achieve anti-induced ESD protection of the LCD. The reset potential stabilization unit includes a pull-up resistor, the first end of which is electrically connected to the power supply terminal, and the second end of which is electrically connected to the RES reset pin. The power surge protection unit includes at least one TVS diode, which is connected in parallel between the power supply terminal and ground.

2. The LCD anti-inductive ESD circuit structure according to claim 1, characterized in that, The reset potential stabilization unit also includes a filter capacitor, the first end of which is electrically connected to the RES reset pin, and the second end of which is grounded.

3. The LCD anti-inductive ESD circuit structure according to claim 1, characterized in that, The pull-up resistor has a resistance of 1kΩ to 10kΩ.

4. The LCD anti-inductive ESD circuit structure according to claim 1, characterized in that, The TVS tube is a bidirectional TVS tube.

5. The LCD anti-induced ESD circuit structure according to claim 2, characterized in that, The capacitance of the filter capacitor is 10nF or 0.1μF.

6. The LCD anti-inductive ESD circuit structure according to claim 1, characterized in that, The circuit board is also provided with a multi-channel power filtering unit, which is electrically connected to the VDD pin and IOVDD pin of the LCD module respectively. Each power filtering unit includes at least one power filtering capacitor, one end of which is electrically connected to the corresponding power pin, and the other end of which is grounded.

7. The LCD anti-inductive ESD circuit structure according to claim 6, characterized in that, A zero-ohm isolation resistor is connected in series on the power supply lines of the VDD pin and the IOVDD pin. The zero-ohm isolation resistor is located between the power input terminal and the corresponding power filter unit.

8. The LCD anti-inductive ESD circuit structure according to claim 1, characterized in that, The circuit board is also provided with a signal protection unit that is electrically connected to the MIPI signal pins of the LCD module one by one. The signal protection unit includes a signal protection TVS tube that matches the number of MIPI signal pins. One end of the signal protection TVS tube is electrically connected to the corresponding MIPI signal pin, and the other end of the signal protection TVS tube is grounded.

9. The LCD anti-inductive ESD circuit structure according to claim 8, characterized in that, A MIPIBUFFER buffer is connected in series on the MIPI signal line of the circuit board. The MIPIBUFFER buffer is located between the MIPI signal output terminal of the host and the MIPI signal pin of the LCD module.

10. The LCD anti-inductive ESD circuit structure according to claim 1, characterized in that, An isolation unit is provided between the analog ground network and the digital ground network of the circuit board. The isolation unit includes a ferrite bead, an isolation resistor and an isolation capacitor arranged in parallel. The two ends of the isolation unit are electrically connected to the analog ground network and the digital ground network, respectively.

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