Sram memory computing structure

Abstract

This invention discloses an SRAM storage computing structure, relating to the field of storage computing technology, to solve the problems of large latency and high area overhead of subsequent circuit modules in existing SRAM storage computing circuits. The SRAM storage computing structure includes: multiple storage computing modules; each storage computing module includes a high-order extension unit, a base unit, and a low-order zero-padding unit; transistors are added to the base unit in the high-order extension unit; transistors are added to the base unit in the low-order zero-padding unit; each base unit includes 6T storage cells and computing transistors. This invention aims to reduce circuit latency and the area of ​​subsequent circuit modules.

Description

Technical Field

[0001] This invention relates to the field of storage computing technology, and more particularly to SRAM storage computing architecture. Background Technology

[0002] Artificial intelligence, especially deep learning, has become a core area of ​​global technological competition, with applications spanning multiple important scenarios such as autonomous driving, natural language processing, and medical image analysis. However, behind this technological boom lies a huge challenge in computing power. The traditional von Neumann architecture suffers from significant "memory walls" and "power walls," with frequent data transfer between storage and computing units severely restricting the improvement of chip computing power and energy efficiency. To overcome this bottleneck, the industry has gradually formed a technical approach that integrates storage and computing units, significantly optimizing chip performance by reducing data transfer. Since the core computation in convolutional neural networks is multiplication-accumulation, one of the core functions of storage-computing chips is to focus on efficiently implementing multiplication-accumulation operations.

[0003] For example, in 8-bit signed number multiplication, traditional architectures use a serial single-bit input method, where each bit of the multiplier is independently ANDed with the multiplicand to generate eight partial products. These partial products are then sign-extended and shift-accumulated to obtain the final result. To reduce the number of partial products and the number of subsequent shift-accumulation cycles, researchers introduced booth encoding to generate partial products into in-memory computing chips. After the 8-bit data is input to the Booth radix-4 encoder, a set of control signals is generated each clock cycle. Encoding the 8-bit data generates four sets of control signals, corresponding to four partial products. Compared to the traditional method, the number of partial products is reduced by 50%, and the number of shift-accumulation cycles is reduced from eight cycles to four cycles, effectively improving computational efficiency.

[0004] In existing technologies, there are storage and computation unit schemes that generate partial products based on signal groups generated by Booth radix-4 encoders. These schemes consist of SRAM (Static Random Access Memory) storage units and computation units, forming the smallest storage and computation unit. A 6T storage unit stores weight data, and the computation unit uses an XOR gate composed of multiple transistors to perform an inversion operation in response to the NEG signal, and then controls the left shift operation through the TWO signal. The entire basic storage and computation unit requires at least 12 transistors. Eight such basic storage and computation units are connected to form an 8-bit storage and computation array, storing 8 bits of signed data. By receiving NEG, TWO, and other signals generated by the Booth radix-4 encoder, it outputs a complete 9-bit partial product.

[0005] However, the existing technical solution has obvious defects: the partial product generated by this solution has the problem of incomplete bit width. The generation of the partial product and the high-bit sign bit padding cannot be completed synchronously, or the generation of the partial product and the low-bit 0 padding cannot be completed synchronously. The high-bit sign bit padding and the low-bit 0 padding both require subsequent additional sign extension units to complete the padding work, which not only increases the hardware complexity, but also introduces additional computational delay.

[0006] Therefore, how to provide an SRAM storage computing structure that can reduce computational latency and subsequent circuit module area overhead has become a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0007] The purpose of this invention is to provide an SRAM storage computing structure for reducing circuit latency and the area of ​​subsequent circuit modules.

[0008] To achieve the above objectives, the present invention provides the following technical solution: In a first aspect, the present invention provides an SRAM storage computing structure, comprising: multiple storage computing modules; Each storage computing module includes a high-order extension unit, a basic unit, and a low-order zero-padding unit; each basic unit includes a 6T storage unit and a computing transistor. A transistor is added to the basic unit in the high-order extension unit; A transistor is added to the basic unit in the low-bit zero-padding unit.

[0009] Optionally, the 6T storage cell has a first storage node and a second storage node; the first storage node and the second storage node are connected to computing transistors; The computing transistors include a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a first PMOS transistor.

[0010] Optionally, the gate of the first NMOS transistor is connected to the first memory node; the gate of the second NMOS transistor is connected to the second memory node. The drain of the first NMOS transistor and the drain of the second NMOS transistor are connected to the first node; The source of the second NMOS transistor is connected to the inverted signal; The source of the first NMOS transistor is connected to an inverted complementary signal; The gate of the third NMOS transistor is connected to the left shift signal, the source of the third NMOS transistor is connected to the first node, and the drain of the third NMOS transistor serves as the first output node of the basic unit. The gate of the first PMOS transistor is connected to a left-shift signal, the source of the first PMOS transistor is connected to the first node, and the drain of the first PMOS transistor serves as the second output node of the basic unit.

[0011] Optionally, the high-order extension unit includes a base unit and a second PMOS transistor; The gate of the second PMOS transistor is connected to the gate of the third NMOS transistor, the source of the second PMOS transistor is connected to the first node, and the drain of the second PMOS transistor is connected to the drain of the third NMOS transistor.

[0012] Optionally, the low-order zero-padding unit includes a basic unit and a fourth NMOS transistor; The gate of the fourth NMOS transistor is connected to the gate of the first PMOS transistor, the source of the fourth NMOS transistor is grounded, and the drain of the fourth NMOS transistor is connected to the drain of the first PMOS transistor.

[0013] Optionally, the SRAM storage computing structure further includes a mode controller and a Booth encoder; the mode controller is connected to the Booth encoder to form a signal selection control link, the mode controller outputs a 2-bit mode control signal, and the mode controller determines the generation source of the inverted signal and the left shift signal through the signal selection control link; When the mode control signal is 00, the mode controller selects the Bus encoder as the source of the inverted signal and the left shift signal. The inverted signal and the left shift signal are dynamically generated by the Bus encoder to realize the partial product generation function. When the mode control signal is 01, 10 or 11, the mode controller disables the Bus encoder and directly outputs the fixed invert signal and the left shift signal. When the mode control signal is 01, the invert signal output by the mode controller is high and the left shift signal is low, thereby realizing the invert calculation function; When the mode control signal is 10, the inverted signal output by the mode controller is low and the left shift signal is high, thereby realizing the arithmetic left shift function; When the mode control signal is 11, the inverted signal output by the mode controller is low and the left shift signal is low, thereby realizing the arithmetic right shift function.

[0014] Optionally, when the mode control signal is 00, the left shift signal generated by the Bus encoder is low, and the invert signal is low, the first PMOS transistor is turned on, the second PMOS transistor is turned on, the third NMOS transistor is turned off, the first NMOS transistor is turned on, and the second NMOS transistor is turned off. The first node outputs the potential of the first storage node, and the high-order extension unit completes the high-order sign bit and outputs the first complete partial product.

[0015] Optionally, when the mode control signal is 00, the left shift signal generated by the Bus encoder is low, and the invert signal NEG is high, the first PMOS transistor is turned on, the second PMOS transistor is turned on, the third NMOS transistor is turned off, the first NMOS transistor is turned off, and the second NMOS transistor is turned on. The first node outputs the potential of the second storage node, and the high-order extension unit completes the high-order sign bit and outputs the second complete partial product.

[0016] Optionally, when the mode control signal is 00, the left shift signal generated by the Bus encoder is high and the invert signal is low, the first PMOS transistor is off, the third NMOS transistor is on, the fourth NMOS transistor is on, the first NMOS transistor is on and the second NMOS transistor is off, the first node outputs the potential of the first storage node, and the low-bit zero-padding unit fills in the low bits with 0 and outputs the third complete partial product.

[0017] Optionally, when the mode control signal is 00, the left shift signal generated by the Bus encoder is high, and the invert signal is high, the first PMOS transistor is off, the third NMOS transistor is on, the fourth NMOS transistor is on, the first NMOS transistor is off, and the second NMOS transistor is on. The first node outputs the potential of the second storage node, and the low-bit zero-padding unit fills in the low bits with 0 and outputs the fourth complete partial product.

[0018] Compared with existing technologies, the SRAM storage and computing structure provided by this invention precisely solves the core problems of high latency and high area overhead caused by incomplete partial product widths and the need for additional modules to complete them in existing technologies by optimizing the unit composition and collaborative logic of the storage and computing modules. Specifically, each of the multiple storage and computing modules includes a high-order extension unit, a basic unit, and a low-order zero-padding unit. The high-order extension unit and the low-order zero-padding unit both add dedicated transistors to the basic unit. Each basic unit consists of 6T storage units and computing transistors. Storage and computing can be integrated without adding too many additional transistors. Compared with the existing technology that requires additional sign extension modules and zero-padding modules, the hardware structure is significantly simplified.

[0019] In the partial product generation mode, the high-order extension unit, multiple basic units, and low-order zero-padding unit receive control signals generated by the encoder and cooperate with each other to complete the partial product generation and high-order extension within the same clock cycle, or complete the partial product generation and low-order zero-padding within the same clock cycle. The high-order extension unit fills the high-order sign bit with an added transistor, and the low-order zero-padding unit fills the low-order 0 with an added transistor. It can directly output a 9-bit complete partial product without relying on subsequent additional sign extension modules or zero-padding modules.

[0020] This design avoids the secondary latency caused by "generating the basic partial product first and then supplementing the bit width with an additional module" in existing technologies. It also eliminates the need for an additional supplementation module by integrating the supplementation function. At the same time, it simplifies the hardware configuration of the computing unit, significantly reduces the chip's area overhead and static power consumption, and enables parallel computing and data reading and writing. It effectively breaks through the memory wall and power consumption wall bottlenecks of traditional architectures and is suitable for scenarios with extremely high requirements for multiplication and accumulation efficiency, such as artificial intelligence and edge computing. Attached Figure Description

[0021] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings: Figure 1 A schematic diagram of the circuit structure of the storage computing module in an SRAM storage computing structure provided for an embodiment of the present invention; Figure 2 A schematic diagram of the circuit structure of a basic unit in a storage computing module provided according to an embodiment of the present invention; Figure 3 A schematic diagram of the circuit structure of the high-order extension unit in a storage computing module provided in an embodiment of the present invention; Figure 4 A schematic diagram of the circuit structure of the low-order zero-padding unit in a storage computing module provided in an embodiment of the present invention; Figure 5 A schematic diagram of the circuit state of each unit in a storage computing module during a holding operation, provided as an embodiment of the present invention; Figure 6 A schematic diagram of the circuit state of each unit in a storage computing module during a read operation, provided as an embodiment of the present invention; Figure 7 A schematic diagram of the circuit state of each unit in a storage computing module during a write operation, provided as an embodiment of the present invention; Figure 8 This is a partial circuit structure diagram of the storage and computing module in specific embodiment 1 of the present invention; Figure 9 for Figure 8 A schematic diagram of the subsequent circuit structure; Figure 10 for Figure 9 The subsequent circuit structure diagram.

[0022] Figure reference numerals: 1-High-order extension unit; 2-Basic unit; 3-Low-order zero-padding unit; 20-6T memory unit; 21-Computation transistor. Detailed Implementation

[0023] To facilitate a clear description of the technical solutions in the embodiments of the present invention, the terms "first" and "second" are used to distinguish identical or similar items with essentially the same function and effect. For example, the first threshold and the second threshold are merely used to distinguish different thresholds and do not limit their order. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order, and that the terms "first" and "second" are not necessarily different.

[0024] It should be noted that in this invention, the terms "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in this invention should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0025] In this invention, "at least one" means one or more, and "more than one" means two or more. "And / or" describes the relationship between the associated objects, indicating that three relationships can exist.

[0026] This invention provides an SRAM storage computing structure, which may include: multiple storage computing modules; wherein the multiple storage computing modules are arranged in an array to form an SRAM storage computing structure; a transistor is added to the basic unit in the high-order extension unit 1; a transistor is added to the basic unit in the low-order zero-padding unit 3; as shown Figure 1 As shown, each storage computing module includes a high-order extension unit 1, at least one basic unit 2, and a low-order zero-padding unit 3.

[0027] It should be noted that each storage and computing module of the present invention can adapt to data processing requirements with different bit widths, and its unit composition can be flexibly configured according to the actual data bit width: for multi-bit data scenarios, each storage and computing module adopts a cascaded structure of "one high-bit extension unit, multiple basic units and one low-bit zero-padding unit", and the target data bit width is matched by adjusting the number of units; taking 8-bit data processing as an example, each storage and computing module may specifically include one high-bit extension unit, six basic units and one low-bit zero-padding unit cascaded in sequence, and the three together cover the storage and computing requirements of 8-bit weighted data.

[0028] Furthermore, the arrangement order of the high-order extension unit, the basic unit, and the low-order zero-padding unit follows the logic of data bits "from high to low": the high-order extension unit → first basic unit → second basic unit → ... → Nth basic unit (N is the total number of basic units, and N is a positive integer) → low-order zero-padding unit are concatenated in sequence to ensure that the output nodes of each unit can be spliced ​​in the order of bit width, and finally form a continuous complete partial product. For example, 8 bits of data correspond to a 9-bit complete partial product.

[0029] The core function of each storage and computation module is to combine the stored weights W with the encoder's control signals to generate the actual partial product. Finally, the sum of all partial products yields the final result of the multiplication, i.e., the complete partial product. A partial product is an intermediate result of the step-by-step calculation in a multiplication operation. For example, calculating 12 × 5 can be broken down into (10 × 5) + (2 × 5) = 50 + 10 = 60, where 50 and 10 are the partial products. In 8-bit signed number multiplication, the partial product is the intermediate value obtained by operating on each group of codes of the multiplier with the multiplicand (i.e., the stored weights W). Specifically, it includes... 2 , -2 Four types of partial products.

[0030] In this invention, the generation of the partial product depends on the control signals generated by the Boothradix-4 encoder (e.g., a Boothradix-4 encoder). The control signals include the invert signal NEG (controlling the invert operation) and the left shift signal TWO (controlling the left shift operation). The encoding and signal operation logic is as follows: In the in-memory computing chip multiply-accumulate operation scenario of the present invention, the multiplicand is the weight data W[7:0] stored in the SRAM array (W[7:0] represents an 8-bit signed number), and the multiplier is the input 8-bit signed number A[7:0]. Here, A[7:0] is the standard representation of an 8-bit binary number, representing all bits from the highest bit A[7] to the lowest bit A[0].

[0031] Encoding rules: The Booth radix-4 encoder uses a “3-bit group, 1-bit overlap” encoding method, and needs to add a virtual low bit A[-1] (value 0) to cover all bits of the 8-bit data and avoid encoding omissions.

[0032] The specific encoding steps are as follows: ①Padded with virtual low bits: A virtual bit A[-1]=0 is added to the right of the least significant bit A[0] of the 8-bit data. The data sequence after padding with 0 is A[7], A[6], A[5], A[4], A[3], A[2], A[1], A[0], A[-1] (a total of 9 bits).

[0033] ② Grouping: According to the rule of "take 3 positions from each group and the next group starts from the 2nd position of the current group", a total of 4 groups are obtained, namely: Group 1 A[1], A[0], A[-1], Group 2 A[3], A[2], A[1], Group 3 A[5], A[4], A[3], Group 4 A[7], A[6], A[5].

[0034] Signal Function: After encoding the four sets of data, the Booth radix-4 encoder outputs four sets of control signals. Each set of control signals includes NEG and TWO, and its core function is to inform the subsequent storage and calculation modules what needs to be generated. 2 , and Which part of the product is it?

[0035] In partial product generation mode, when each storage computing module is working, the high-order extension unit, multiple basic units, and low-order zero-padding unit receive the inverted signal NEG and the left-shift signal TWO, and cooperate to synchronously complete the following three key operations within the same clock cycle: The basic units are implemented through computing transistors. 2 , and -2 Once the basic partial product is generated, the high-order extension unit fills in the high-order sign bit with the added transistor, and the low-order zero-padding unit fills in the low-order 0 with the added transistor. It can directly output the 9-bit complete partial product without relying on subsequent additional sign extension modules or zero-padding modules.

[0036] The beneficial effects of this embodiment: 1) Addressing the core defects of existing technologies and reducing computational latency. Addressing the issue of increased latency caused by the need for additional modules to complete incomplete partial product widths in existing technologies, this invention employs a collaborative design of high-order extension units, basic units, and low-order zero-padding units within the storage and computation module. This allows for the simultaneous completion of three operations—generating the basic partial product, completing the high-order sign bit, and padding the low-order zeros—within the same clock cycle, eliminating the need for subsequent additional completion modules. This completely avoids the secondary latency caused by generating the basic partial product first and then padding the width, significantly improving the efficiency of multiply-accumulate operations.

[0037] 2) Simplified hardware structure, reducing area and power consumption. Existing technologies require additional sign extension units and zero-padding units to achieve partial integration, and the minimum storage computing unit has a large number of transistors, resulting in high chip area and power consumption. This invention integrates the completion function simply by adding dedicated transistors to the basic unit, without the need for additional independent modules. It also simplifies the hardware configuration of the computing unit, reduces unnecessary transistor redundancy, and thus reduces the overall chip area and static power consumption, meeting the requirements for large-scale array integration of storage computing chips.

[0038] 3) Ensuring the accuracy of partial product generation and adapting to signed number operations. Based on the standard encoding logic of the Booth radix-4 encoder, combined with the grouping rule of "3 bits per group, 1 bit overlap" and virtual low-bit padding with zeros, the integrity and accuracy of the multiplier encoding are ensured. Simultaneously, the high-order sign bit padding follows the signed number sign extension rule, and the low-order zero padding conforms to the left shift operation bit width adaptation logic, enabling the generated 9-bit complete partial product to accurately correspond to the target number. , , , Four types ensure the accuracy of signed number multiplication operations and avoid numerical deviations caused by improper bit width padding.

[0039] 4) Enhanced functional integration and compatibility to adapt to high-performance computing scenarios. Each storage computing module integrates basic partial product generation and bit width padding functions, outputting complete partial products without additional hardware assistance, demonstrating high functional integration. At the same time, the design of separating control signals from bit lines for transmission supports parallel computation and data reading and writing, further improving computational continuity and overall computing power. It is perfectly adapted to scenarios with extremely high requirements for multiplication and accumulation efficiency and integration, such as artificial intelligence and edge computing, effectively breaking through the memory wall and power consumption wall bottlenecks of traditional architectures.

[0040] 5) Flexible and adaptable structure, suitable for multi-bit data processing. The storage and computing module adopts a cascaded structure of "high-bit extension unit, multiple basic units combined with low-bit zero-padding unit". It can adapt to the data processing requirements of different bit widths by adjusting the number of basic units, without reconstructing the core hardware logic, which enhances the flexibility and versatility of the solution and makes it more widely applicable.

[0041] The internal structure of the basic unit will be described next. See [link / reference] Figure 2 Each basic unit includes 6T storage cells 20 and computing transistors 21.

[0042] The 6T memory cell 20 includes a cross-coupled inverter and an access transistor; the cross-coupled inverter includes a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifth NMOS transistor MN5, and a sixth NMOS transistor MN6; the access transistor includes a seventh NMOS transistor MN7 and an eighth NMOS transistor MN8.

[0043] The drains of the third PMOS transistor MP3, the fifth NMOS transistor MN5, and the seventh NMOS transistor MN7 are connected to the first memory node Q; therefore, the 6T memory cell has the first memory node Q. The drains of the fourth PMOS transistor MP4, the sixth NMOS transistor MN6, and the eighth NMOS transistor MN8 are connected to the second memory node QB. Therefore, the 6T memory cell has the second memory node QB; both the first memory node Q and the second memory node QB are connected to computing transistors.

[0044] The sources of the third PMOS transistor MP3 and the fourth PMOS transistor MP4 are both connected to the power supply VDD; the sources of the fifth NMOS transistor MN5 and the sixth NMOS transistor MN6 are both grounded; the gates of the seventh NMOS transistor MN7 and the eighth NMOS transistor MN8 are both connected to the word line WL; the source of the seventh NMOS transistor MN7 is connected to the bit line BL; and the source of the eighth NMOS transistor MN8 is connected to the bit line NB.

[0045] The computing transistor 21 includes a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, and a first PMOS transistor MP1.

[0046] The gate of the first NMOS transistor MN1 is connected to the first memory node Q; the gate of the second NMOS transistor MN2 is connected to the second memory node QB; the drain of the first NMOS transistor MN1 and the drain of the second NMOS transistor MN2 are connected to the first node A.

[0047] The source of the second NMOS transistor MN2 is connected to the inverted signal NEG; the source of the first NMOS transistor MN1 is connected to the inverted complementary signal NNEG; the gate of the third NMOS transistor MN3 is connected to the left shift signal TWO, the source of the third NMOS transistor MN3 is connected to the first node A, and the drain of the third NMOS transistor MN3 serves as the first output node of the basic unit; the gate of the first PMOS transistor MP1 is connected to the left shift signal TWO, the source of the first PMOS transistor MP1 is connected to the first node A, and the drain of the first PMOS transistor MP1 serves as the second output node of the basic unit.

[0048] Here, the inverted complementary signal NNEG is the complementary signal obtained by inverting the inverted signal NEG. The basic unit, together with the inverted signal NEG, the left-shifted signal TWO, and the inverted complementary signal NNEG, can generate a partial product.

[0049] The turn-on / turn-off logic of each transistor is based on the operating characteristics of the MOSFET and the signal level definition, as explained below: The conduction condition of a PMOS transistor is that the gate potential is low (forming a positive bias with the source potential). In this invention, the gates of the first PMOS transistor MP1 and the second PMOS transistor MP2 are both connected to the left shift signal TWO. Therefore, when TWO=0 (low level), the PMOS transistor meets the conduction condition, and when TWO=1 (high level), it is cut off.

[0050] The turn-on condition for an NMOS transistor is that the gate potential is high (forming a forward bias with the source potential): The gate of the third NMOS transistor MN3 is connected to the TWO signal, so it is turned on when TWO=1 and turned off when TWO=0; the gate of the fourth NMOS transistor MN4 is connected to the TWO signal, so it is turned on when TWO=1 and turned off when TWO=0; the gate of the first NMOS transistor MN1 is connected to the first storage node Q, and the source is connected to the inverse complementary signal NNEG. When NEG=0, NNEG=1 (high level). If Q is high, then MN1 satisfies the turn-on condition; the gate of the second NMOS transistor MN2 is connected to the second storage node QB (the inverted signal of Q), and the source is connected to the NEG signal. When NEG=1 (high level), if QB is high, then MN2 satisfies the turn-on condition.

[0051] The NEG and TWO signals are output by the Booth radix-4 encoder. The correspondence between their level combinations (4 cases) and the on / off states of each transistor is designed based on the functional requirement of generating the target partial product. For example, when TWO=0, a high-order sign bit needs to be added (PMOS is on), and when TWO=1, a low-order 0 needs to be added (NMOS is on), which conforms to the inherent operating characteristics of MOS transistors.

[0052] Next, the internal structure of the higher-order extension unit will be introduced. For example... Figure 3 As shown, the high-order extension unit includes a basic unit and a second PMOS transistor MP2; the gate of the second PMOS transistor MP2 is connected to the gate of the third NMOS transistor, therefore, the gate of the second PMOS transistor MP2 is also connected to the left shift signal TWO.

[0053] The source of the second PMOS transistor MP2 is connected to the first node A, and the drain of the second PMOS transistor MP2 is connected to the drain of the third NMOS transistor MN3 (the drain of the third NMOS transistor MN3 in the high-level extension unit 1 serves as the first output node P8 of the high-level extension unit).

[0054] The drain of the first PMOS transistor MP1 in the high-order extension unit 1 serves as the second output node P7 of the high-order extension unit, and P7 is connected to the first output node of the adjacent basic unit. P8 = P7 is achieved by turning on MP2, thus completing the high-order sign bit completion.

[0055] Next, the internal structure of the low-order zero-padding unit will be introduced. For example... Figure 4 As shown, the low-order zero-padding unit 3 includes the basic unit 2 and the fourth NMOS transistor MN4; the gate of the fourth NMOS transistor MN4 is connected to the gate of the first PMOS transistor, therefore, the gate of the fourth NMOS transistor MN4 is also connected to the left shift signal TWO.

[0056] The source of the fourth NMOS transistor MN4 is grounded, and the drain of the fourth NMOS transistor MN4 is connected to the drain of the first PMOS transistor MP1 (the drain of the third NMOS transistor MN3 in the low-level zero-padding unit 3 serves as the first output node P1 of the low-level zero-padding unit, while the drain of the first PMOS transistor MP1 in the low-level zero-padding unit 3 serves as the first output node P0 of the low-level zero-padding unit).

[0057] When the left shift signal TWO is high, the fourth NMOS transistor MN is turned on, which pulls the potential of the second output node P0 of the low-order zero-padding unit low to 0, thus completing the low-order zero-padding operation.

[0058] The following section introduces the basic operations of the storage and computing module.

[0059] Regarding the hold operation, such as Figure 5 As shown. During hold operation, the word line WL is low (WL=0), transistors MN7 and MN8 are off, the first storage node Q is not connected to the bit line BL, and the second storage node QB is not connected to the bit line other than BLB. The stability of the data in the storage cells is maintained through a positive feedback mechanism in the internal circuitry.

[0060] Regarding read operations, for example Figure 6 This diagram illustrates reading a "1". The initial state for reading "1" is: Q is "1", QB is "0", transistors MN7 and MN8 are off, and the memory cell is isolated from the bit line. Before the read operation, BL and BLB are pre-charged to a high level to ensure the bit line is in a known high-level state, preparing for subsequent voltage difference detection. After pre-charging, the word line is activated, WL remains high (WL=1), transistors MN7 and MN8 are turned on, and memory nodes Q (high level 1) and QB (low level 0) are connected to BL and BLB respectively. Since QB is low, a low-impedance path is formed between the bit line BLB and ground through MN8, causing BLB to discharge, as shown by the red arrow in the diagram. MN8 turns off, and the small voltage difference between BL (high level) and BLB (low level) is rapidly amplified by a sensitive amplifier. The amplified signal is converted into a digital logic "1" and output to the data bus.

[0061] Regarding write operations, set WL to a high level, i.e., WL=1. If you write 1, BL=1 and BLB=0; if you write 0, BL=0 and BLB=1. Figure 7This is a schematic diagram of writing a 0. Initially, Q=1 and QB=0. After writing a 1, the bit lines are activated, and MN7 and MN8 are both in the on state. The internal node Q starts discharging through BL, and BLB charges QB, as shown by the red arrow in the diagram. Positive feedback is formed through the cross-coupled inverter. When Q discharges below the flip-flop level of the coupled inverter, the data stored in the cell will flip, the QB node becomes 1, and Q becomes 0, completing the write operation. Since the 6T memory cell has a completely symmetrical structure, when Q and QB are 0 and 1 respectively, the read and write operations are similar to the above process, and will not be described again.

[0062] Specifically, the base 4 Bus encoder encodes the 8-bit multiplier A[7:0] in a “3-bit group, 1-bit overlap” manner, and outputs NEG and TWO signals to control the storage and calculation module to generate four partial products: W, 2W, -W, and -2W.

[0063] Taking 8-bit data processing as an example, the storage and calculation module consists of one high-order extension unit, six basic units, and one low-order zero-padding unit cascaded together, storing weights. .

[0064] For example, Figure 8 , Figure 9 and Figure 10 The complete circuit diagram of an 8-bit storage and computing module, and Figure 8 , Figure 9 and Figure 10 Each is a part of the storage computing module.

[0065] refer to Figure 8 , Figure 9 and Figure 10 It can be seen that the high-order extension unit, multiple basic units, and low-order zero-padding units in a storage computing module share a set of bit lines BL and non-BLB. Bit lines BL and non-BLB serve as read and write channels for weight data, used to synchronously load or update the weight data W [7:0] in the basic units, and are also multiplexed as transmission channels for the invert signal NEG and the left shift signal TWO, without the need for separate wiring for these two control signals; it should be noted that the inverted complementary signal NNEG is transmitted through a dedicated control signal line independent of bit lines BL and non-BLB. There is only one dedicated control signal line, with no other additional control signals, which greatly reduces the wiring pressure through signal multiplexing design.

[0066] The reason for this design is that in traditional independent routing schemes, control signals and bit lines need to occupy routing resources separately, resulting in excessively high chip routing density and increased layout difficulty. However, this invention adopts a hybrid design that multiplexes NEG and TWO signals with BL / BLB bit lines for transmission and separate routing for NNEG signals. Without affecting the functionality, it reduces the number of dedicated control signal lines, significantly reduces routing pressure, and avoids the resource waste caused by independent routing of multiple signals.

[0067] The core advantage of this design lies in its simpler and more efficient routing: by multiplexing bit lines and core control signals (NEG, TWO), the number of wires is reduced, lowering the complexity of chip layout and the risk of signal interference. At the same time, the separate routing of the NNEG signal ensures the stability of the inverted complementary logic. With the coordinated work of the high-bit extension unit, the low-bit zero-padding unit, and the basic unit, the partial product generation is completed simultaneously with the high-bit sign extension and the low-bit zero-padding. This avoids the secondary delay of "first calculating the basic partial product and then padding the bit width with an additional module" in traditional solutions. While optimizing routing, it also takes into account the computational efficiency, significantly improving the overall performance of the storage computing chip.

[0068] Next, the reconfigurable functionality of the SRAM storage computing structure will be explained. This reconfigurable functionality includes the partial product generation function analyzed above, as well as shifting and inversion functions, etc.

[0069] Based on the design of the reconfiguration function, it should be noted that the SRAM storage computing structure also includes a mode controller and a Booth encoder; the mode controller is connected to the Booth encoder to form a signal selection control link, the mode controller outputs a 2-bit mode control signal, and the mode controller determines the generation source of the inverted signal NEG and the left shift signal TWO through the signal selection control link.

[0070] When the mode control signal is 00, the mode controller selects the Bus encoder as the source of the invert signal and the left shift signal. The invert signal NEG and the left shift signal TWO are dynamically generated by the Bus encoder according to the input data to realize the partial product generation function. When the mode control signal is 01, 10 or 11, the mode controller disables the Bus encoder and selects itself as the source of the invert signal and the left shift signal. The mode controller directly outputs the fixed invert signal NEG and the left shift signal TWO. When the mode control signal is 01, the mode controller outputs an inverted signal at a high level and a left shift signal at a low level, thus realizing the inverted calculation function; When the mode control signal is 10, the inverted signal output by the mode controller is low and the left shift signal is high, thus realizing the arithmetic left shift function. When the mode control signal is 11, the inverted signal output by the mode controller is low and the left shift signal is low, thus realizing the arithmetic right shift function.

[0071] In the partial product generation mode, the above 8-bit storage and computation module generates the 9-bit complete partial product through the following four cases: Case 1: The complete partial product includes the first complete partial product; the first complete partial product is the original value of the stored weights. ; When the mode control signal is 00, the left shift signal TWO generated by the Bus encoder is low and the inverted signal NEG is low (i.e., TWO=0 and NEG=0), the first PMOS transistor MP1 is turned on, the second PMOS transistor MP2 is turned on, the third NMOS transistor MN3 is turned off, the first NMOS transistor MN1 is turned on and the second NMOS transistor MN2 is turned off. The first node A outputs the potential of the first storage node Q, the high-order extension unit completes the high-order sign bit and outputs the first complete partial product.

[0072] The operation of padding the high-order sign bit in the high-order extension unit refers to adding an extension bit to the high-order side of the original multi-bit output data. Based on the sign extension rule of signed numbers, the potential of the extension bit is made equal to the potential of the original highest bit.

[0073] The high-order extension unit implements this completion operation through an additional second PMOS transistor MP2. The specific circuit principle is as follows: the gate of the second PMOS transistor MP2 is connected to the left-shift signal TWO, its source is connected to the first node A, and its drain is connected to the first output node of the high-order extension unit. (The drain of the third NMOS transistor MN3) is connected; when the left shift signal TWO is low, the second PMOS transistor MP2 is turned on, making The potential and the second output node of the high-order extension unit (The drain of the first PMOS transistor MP1) remains consistent (i.e.) );and It is connected to the first output node of the adjacent basic unit, corresponding to the highest bit of the weight data. Therefore, the high-order sign bit is copied and completed by the conduction of MP2, which conforms to the signed number extension rule.

[0074] For example, in the expansion of 8-bit data, an extension bit is added to the high-order side of the 8-bit output data. Based on the sign extension rule for signed numbers, let the extension bits... The potential is equal to the original highest bit. The potential is used to pad the 8-bit basic partial product to a complete 9-bit partial product while ensuring that the value remains unchanged.

[0075] Specifically, the output nodes of the 8 units arrive The output is the original stored weight value. , that is The high-order extension unit adds one bit of data to the left of the most significant bit of the original 8-bit data. and make the new data Equal to the original highest bit data (because correspond The output is equivalent to copying the sign bit of 8 bits of data. For example, when (8-bit binary: 00000101, → When positive number), The final 9-bit partial product is 000000101, still a value of +5. If this rule is not followed, the hardware may misjudge the data attribute due to bit width mismatch, leading to calculation errors. Therefore, by... The sign extension, the final output of the first complete partial product is This satisfies the bit width requirement of 9 bits for the partial product in multiplication operations while ensuring the accuracy of the numerical value.

[0076] The high-order extension unit is padded with the sign bit in the high-order bits, and Therefore, the final output of the first complete partial product is .

[0077] Case 2: The complete partial product includes the second complete partial product; the second complete partial product is the inverse of the stored weights. ; When the mode control signal is 00, the left shift signal TWO generated by the Bus encoder is low, and the inverted signal NEG is high (i.e., TWO=0 and NEG=1), the first PMOS transistor MP1 is turned on, the second PMOS transistor MP2 is turned on, the third NMOS transistor MN3 is turned off, the first NMOS transistor MN1 is turned off, and the second NMOS transistor MN2 is turned on. The first node A outputs the potential of the second storage node QB, and the high-order extension unit completes the high-order sign bit and outputs the second complete partial product. The operation of completing the high-order sign bit of the high-order extension unit is the same as described above and will not be repeated here.

[0078] Specifically, the output nodes P7 to P0 of the 8 units output the opposite values ​​of the original stored weights. The high-order extension unit adds one bit of data to the left of the most significant bit of the original 8-bit inverted data. and make the new data Equal to the original highest bit data (Because P7 corresponds to the output of QB7, it is equivalent to copying the sign bit of the 8-bit inverted data). For example, when W=+5, its inverted value QB in 8-bit binary is 11111010 (QB7=1 → corresponding to a negative number), at this time... The final 9-bit partial product is 111111010, which, after subsequent +1 compensation, becomes -5, consistent with the target opposite value W; therefore, through (Right now The sign expansion of ) results in the final output of the second complete partial product as shown below: This satisfies the 9-bit width requirement for the partial product in multiplication operations while also ensuring the accuracy of the inverse value.

[0079] Case 3: The complete partial product includes the third complete partial product; the third complete partial product is twice the storage weight, i.e., 2W; When the mode control signal is 00, the left shift signal TWO generated by the Bus encoder is high and the invert signal NEG is low (i.e., TWO=1 and NEG=0), the first PMOS transistor MP1 is cut off, the third NMOS transistor MN3 is turned on, the fourth NMOS transistor MN4 is turned on, the first NMOS transistor MN1 is turned on and the second NMOS transistor MN2 is cut off. The first node A outputs the potential of the first storage node Q, the low-bit zero-padding unit fills in the low-bit zeros and outputs the third complete partial product.

[0080] The low-bit zero-padding operation of the low-bit zero-padding unit refers to adding a zero-padding bit to the low-bit side of the original multi-bit output data. Based on the bit width adaptation rule of the left shift operation, the potential of the zero-padding bit is fixed at 0.

[0081] For example, in the expansion after left shifting 8-bit data, after the original 8-bit output data is shifted left by 1 bit, a 1-bit gap will be formed on the low-order side. The low-order zero-padding unit adds a zero-padding bit at the gap position, and fixes the potential of the zero-padding bit to 0, thereby filling the 8-bit basic partial product after left shifting to a complete 9-bit partial product, and ensuring that the numerical multiplication relationship corresponding to the left shift operation remains unchanged.

[0082] Specifically, the output nodes of the 8 units arrive The output is the result of shifting the original stored weight value one bit to the left. (Shifting left by 1 bit is equivalent to multiplying the original value by 2), that is The result after left shifting. The low-order zero-padding unit fills the low-order gaps created after the original 8-bit data is left-shifted with 0, i.e. (Because the lower bits need to be padded with 0s after a left shift to maintain bit width integrity, this is equivalent to the standard logic of a left shift operation.) For example, when (8-bit binary: 00000101, When the result is a positive number, shifting it left by 1 bit yields 0000101. After padding the lower bits with 0, the final 9-bit partial product is 000001010, with a value of +10, which is exactly twice the original weight W. If this rule is not followed and zeros are not added, the width of the partial product after shifting left is only 8 bits. arrive The subsequent addition of this data with other 9-bit portions can lead to value misalignment due to bit width mismatch, causing calculation errors. Therefore, low-bit padding is used to correct this. The operation ultimately outputs the third complete part product as... This satisfies the bit width requirement of 9-bit partial product for multiplication operations while ensuring the accuracy of the values ​​corresponding to left shift operations.

[0083] Case 4: The complete partial product includes the fourth complete partial product; the fourth complete partial product is the negative of twice the stored weight. ; When the mode control signal is 00, the left shift signal TWO generated by the Bus encoder is high and the invert signal NEG is high (i.e., TWO=1 and NEG=1), the first PMOS transistor MP1 is cut off, the third NMOS transistor MN3 is turned on, the fourth NMOS transistor MN4 is turned on, the first NMOS transistor MN1 is cut off and the second NMOS transistor MN2 is turned on. The first node A outputs the potential of the second storage node QB, the low-bit zero-padding unit fills in the low-bit 0 and outputs the fourth complete partial product.

[0084] The operation of padding low-order zeros in the low-order zero-padding unit is the same as described above and will not be repeated here. For example, in the expansion after left shifting 8-bit inverted data, after the original 8-bit inverted output data is shifted left by 1 bit, a 1-bit gap will be formed on the low-order side. The low-order zero-padding unit adds a zero-padding bit P0 at the gap position, and fixes the potential of P0 to 0, thereby padding the 8-bit basic partial product after left shifting to a complete 9-bit partial product, while ensuring that the numerical multiplication relationship corresponding to the left shift operation remains unchanged from the inversion logic.

[0085] Specifically, the output nodes P8 to P1 of the 8 units are the result of shifting the original stored weight inverted value one bit to the left. (Shifting left by 1 bit after inversion is equivalent to inverting the original value and then multiplying it by 2), which is the result of shifting left after inversion of W.

[0086] The low-order zero-padding unit fills the low-order gaps created after the original 8-bit inverted data is shifted left, i.e. (Because the lower bits need to be padded with 0s after a left shift to maintain bit width integrity, this is equivalent to copying the standard logic of a left shift operation, while simultaneously using an inversion operation to achieve the numerical logic of -2W). For example, when When (8-bit binary: 00000101, Q7=0 → positive number), its inverted value QB in 8-bit binary is 11111010 ( →corresponding to a negative number), shifting left by 1 bit yields 1111010. After padding the lower bits with 0, the final 9-bit complete partial product is 111110100. After subsequent +1 compensation, the value is -10, which is exactly twice the negative value of the original weight W. If zeros are not padded according to this rule, the bit width of the inverted partial product after left shifting is only 8 bits. arrive When adding the product to other 9-bit parts, the bit width mismatch can cause misalignment in negative number operations, leading to calculation errors. Therefore, by padding the lower bits with P0=0, the final output of the fourth complete part product is... This satisfies the bit width requirement of 9-bit partial product for multiplication operations while ensuring the accuracy of the numerical values ​​corresponding to the inverted left shift operation.

[0087] Furthermore, when the mode control signal is 01, the mode controller masks the base 4 Bus encoder logic, and the operating mode is the inverted mode. The mode controller forces the output of fixed control signals NEG=1 and TWO=0. At this time, the first PMOS transistor MP1 is turned on, the second PMOS transistor MP2 is turned on, the third NMOS transistor MN3 is turned off, the first NMOS transistor MN1 is turned off and the second NMOS transistor MN2 is turned on. The first node A outputs the potential of the second storage node QB, and the output result is... The lower 8 bits The result is directly used as the inverse, and then connected. The output node can then be used to perform the inversion function.

[0088] When the mode control signal is 10, the mode controller disables the 4-bit encoder logic, and the operating mode is arithmetic left shift mode. The mode controller forces the output of fixed control signals NEG=0 and TWO=1. At this time, the first PMOS transistor MP1 is off, the third NMOS transistor MN3 is on, the fourth NMOS transistor MN4 is on, the first NMOS transistor MN1 is on, and the second NMOS transistor MN2 is off. The first node A outputs the potential of the first storage node Q, and the low-bit zero-padding unit fills the low bits with 0. The output result is... The lower 8 bits Directly used as the result of a left shift, through docking The output node can then perform the arithmetic left shift function.

[0089] When the mode control signal is 11, the mode controller disables the 4-bit encoder logic, and the operating mode is arithmetic right shift mode. The mode controller forces the output of fixed control signals NEG=0 and TWO=0. At this time, the first PMOS transistor MP1 is turned on, the second PMOS transistor MP2 is turned on, the third NMOS transistor MN3 is turned off, the first NMOS transistor MN1 is turned on and the second NMOS transistor MN2 is turned off. The first node A outputs the potential of the first storage node Q, and the high-order extension unit completes the high-order sign bit. The output result is... The high 8 bits Directly used as the result of a right shift, through docking The output node can then perform the arithmetic right shift function.

[0090] Beneficial effects of the embodiments of the present invention: 1) Reconfigurable functionality covers all computing needs across various scenarios, significantly enhancing flexibility. Leveraging the differentiated configuration of the NEG / TWO control signals, the storage and computing module can flexibly switch between four core functions: partial product generation, arithmetic left shift, arithmetic right shift, and inversion, without requiring additional hardware reconfiguration or module replacement. Specifically, NEG=1 and TWO=0 implements the inversion function; NEG=0 and TWO=1 implements the arithmetic left shift function; NEG=0 and TWO=0 implements the arithmetic right shift function; and when NEG and TWO are controlled collaboratively, four partial product functions—W / 2W / -W / -2W—are generated. This perfectly adapts to the diverse intermediate operation requirements in multiplication and accumulation operations, eliminating the need for dedicated circuits for different functions and greatly improving the chip's functional adaptability and resource utilization.

[0091] 2) Reduced transistor count in computing units, resulting in significant advantages in area and power consumption. Compared to existing technologies that require at least 6 transistors per computing unit, this invention adds only 4 computing transistors to a standard 6TSRAM memory cell, forming a 10T minimum storage computing unit, thus reducing the number of transistors per computing unit. Since the storage computing array consists of thousands to tens of thousands of minimum cells, this reduction in transistor count directly lowers static power consumption and significantly reduces the overall chip area overhead, making it more suitable for the large-scale array integration requirements of storage computing chips and giving it a significant competitive advantage in area and power consumption optimization.

[0092] 3) Partial product generation and padding are completed simultaneously, resulting in significant low latency. While generating the partial product, the high-order sign is extended synchronously through the high-order extension unit, and the low-order padding is completed synchronously through the low-order zero-padding unit. The two padding operations require only 2 transistors and do not rely on subsequent additional sign extension or zero-padding modules. This completely avoids the secondary latency caused by generating the basic partial product first and then padding the bit width through additional modules, significantly improving the efficiency of multiply-accumulate operations. Moreover, the hardware overhead is far lower than that of the multi-selector padding design in traditional schemes.

[0093] 4) Precise sign extension and zero-padding logic ensures high reliability in negative number operations. The high-order sign extension strictly follows the signed number extension rule of P8=P7, while low-order zero-padding is achieved by grounding the fourth NMOS transistor to achieve P0=0. Both padding operations are completed synchronously with the partial product generation. This design avoids numerical deviations caused by the disconnect between padding logic and partial product generation in existing technologies. Especially for negative partial products, the complete chain of "inversion, sign extension, and subsequent compensation" ensures the accuracy of negative number operations, avoids calculation errors caused by improper padding, and perfectly adapts to all scenarios of 8-bit signed number multiplication.

[0094] 5) The unit cascading logic is clear, and the bit width expansion compatibility is excellent. The high-bit extension unit, basic unit, and low-bit zero-padding unit are cascaded in order from high to low bits. The output nodes are sequentially connected to form a continuous 9-bit partial product. Furthermore, the cascaded structure can be adapted to data processing with different bit widths (such as 16-bit and 32-bit) by increasing or decreasing the number of basic units. This design not only ensures the continuous bit width of the partial product in the current 8-bit scenario but also provides a unified hardware architecture for subsequent expansion to higher bit widths without requiring reconstruction of the core cascading logic, thus improving the scalability and versatility of the technical solution.

[0095] 6) Deep integration of storage and computing reduces data transfer losses: The basic unit integrates 6T storage units and 4T computing transistors. The high-order expansion unit and low-order zero-padding unit add a small number of dedicated transistors to the basic unit, realizing an integrated design of storage, computing, and zero-padding functions. Data does not need to be frequently transferred between storage units and independent computing units and zero-padding modules, reducing the time and power consumption losses caused by data transfer. This further aligns with the core goal of in-memory computing—"less data transfer and breaking through the memory wall"—significantly improving the chip's energy efficiency ratio.

[0096] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings, the disclosure, and the appended claims in carrying out the claimed invention. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality.

[0097] Although the invention has been described in conjunction with specific features and embodiments, it is obvious that various modifications and combinations can be made therein without departing from the spirit and scope of the invention. Accordingly, this specification and drawings are merely exemplary descriptions of the invention as defined by the appended claims, and are considered to cover any and all modifications, variations, combinations, or equivalents within the scope of the invention. Clearly, those skilled in the art can make various alterations and modifications to the invention without departing from its spirit and scope. Thus, if such modifications and modifications of the invention fall within the scope of the claims and their equivalents, the invention is also intended to include such modifications and modifications.

Claims

1. An SRAM storage computing structure, characterized in that, include: Multiple storage and computing modules; Each storage computing module includes a high-order extension unit, at least one basic unit, and a low-order zero-padding unit; A transistor is added to the base unit in the high-order extension unit; a transistor is added to the base unit in the low-order zero-padding unit; Each of the basic units includes 6T of memory cells and computing transistors.

2. The SRAM storage computing structure according to claim 1, characterized in that, The 6T storage unit has a first storage node and a second storage node; the first storage node and the second storage node are connected to the computing transistor; The computing transistors include a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a first PMOS transistor.

3. The SRAM storage computing structure according to claim 2, characterized in that, The gate of the first NMOS transistor is connected to the first memory node; the gate of the second NMOS transistor is connected to the second memory node. The drain of the first NMOS transistor and the drain of the second NMOS transistor are connected to the first node; The source of the second NMOS transistor is connected to an inverted signal; The source of the first NMOS transistor is connected to an inverted complementary signal; The gate of the third NMOS transistor is connected to a left-shift signal, the source of the third NMOS transistor is connected to the first node, and the drain of the third NMOS transistor serves as the first output node of the basic unit. The gate of the first PMOS transistor is connected to the left shift signal, the source of the first PMOS transistor is connected to the first node, and the drain of the first PMOS transistor serves as the second output node of the basic unit.

4. The SRAM storage and computing structure according to claim 3, characterized in that, The high-level expansion unit includes the basic unit and the second PMOS transistor; The gate of the second PMOS transistor is connected to the gate of the third NMOS transistor, the source of the second PMOS transistor is connected to the first node, and the drain of the second PMOS transistor is connected to the drain of the third NMOS transistor.

5. The SRAM storage and computing structure according to claim 4, characterized in that, The low-order zero-padding unit includes the basic unit and the fourth NMOS transistor; The gate of the fourth NMOS transistor is connected to the gate of the first PMOS transistor, the source of the fourth NMOS transistor is grounded, and the drain of the fourth NMOS transistor is connected to the drain of the first PMOS transistor.

6. The SRAM storage computing structure according to claim 5, characterized in that, It also includes a mode controller and a Booth encoder; the mode controller is connected to the Booth encoder to form a signal selection control link, the mode controller outputs a 2-bit mode control signal, and the mode controller determines the generation source of the inverted signal and the left shift signal through the signal selection control link; When the mode control signal is 00, the mode controller selects the Bus encoder as the source of the inverted signal and the left shift signal. The inverted signal and the left shift signal are dynamically generated by the Bus encoder to realize the partial product generation function. When the mode control signal is 01, 10 or 11, the mode controller disables the Bus encoder and directly outputs the fixed invert signal and the left shift signal. When the mode control signal is 01, the invert signal output by the mode controller is high and the left shift signal is low, thereby realizing the invert calculation function; When the mode control signal is 10, the inverted signal output by the mode controller is low and the left shift signal is high, thereby realizing the arithmetic left shift function; When the mode control signal is 11, the inverted signal output by the mode controller is low and the left shift signal is low, thereby realizing the arithmetic right shift function.

7. The SRAM storage computing structure according to claim 6, characterized in that, When the mode control signal is 00, the left shift signal generated by the Bus encoder is low, and the invert signal is low, the first PMOS transistor is turned on, the second PMOS transistor is turned on, the third NMOS transistor is turned off, the first NMOS transistor is turned on, and the second NMOS transistor is turned off. The first node outputs the potential of the first storage node, and the high-order extension unit completes the high-order sign bit and outputs the first complete partial product.

8. The SRAM storage computing structure according to claim 6, characterized in that, When the mode control signal is 00, the left shift signal generated by the Bus encoder is low, and the invert signal NEG is high, the first PMOS transistor is turned on, the second PMOS transistor is turned on, the third NMOS transistor is turned off, the first NMOS transistor is turned off and the second NMOS transistor is turned on, the first node outputs the potential of the second storage node, and the high-order extension unit completes the high-order sign bit and outputs the second complete partial product.

9. The SRAM storage computing structure according to claim 6, characterized in that, When the mode control signal is 00, the left shift signal generated by the Bus encoder is high and the invert signal is low, the first PMOS transistor is off, the third NMOS transistor is on, the fourth NMOS transistor is on, the first NMOS transistor is on and the second NMOS transistor is off, the first node outputs the potential of the first storage node, and the low-bit zero-padding unit fills in the low bits with 0 and outputs the third complete partial product.

10. The SRAM storage computing structure according to claim 6, characterized in that, When the mode control signal is 00, the left shift signal generated by the Bus encoder is high, and the invert signal is high, the first PMOS transistor is off, the third NMOS transistor is on, the fourth NMOS transistor is on, the first NMOS transistor is off, and the second NMOS transistor is on. The first node outputs the potential of the second storage node, and the low-bit zero-padding unit fills in the low bits with 0 and outputs the fourth complete partial product.

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