Semiconductor devices for providing chip kill

Abstract

This disclosure relates to a semiconductor device for providing a chip kill. A memory device includes a plurality of stacked shard chips. The plurality of shard chips are electrically connected to each other through a plurality of vias, and when a chip kill occurs in one of the plurality of shard chips, operation of the plurality of shard chips is determined by correcting the shard ID in each of the plurality of shard chips. Furthermore, among the shard chips in the plurality of shard chips where a chip kill has not occurred, the shard chip at the lowest layer and the shard chip at the highest layer can be determined to be operational.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Application No. 10-2024-0171537, filed with the Korean Intellectual Property Office on November 26, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Some embodiments of this disclosure relate to storage devices that provide chip-kill functionality. Background Technology

[0004] Recently, stacked memory systems, such as high-bandwidth memory (HBM) devices, have gained widespread adoption due to their excellent bandwidth and energy efficiency. Unlike traditional memory systems that use parallel data buses, stacked memory systems consist of stacked memory devices, which include a base chip and multiple memory chips interconnected via through-silicon vias (TSVs). The stacked memory devices include physical interfaces, such as a physical layer for communicating with a processor. This physical layer is designed for high-speed data transfer and efficient communication.

[0005] Storage devices can correct and recover errors contained in data. Techniques for error correction and recovery include techniques for correcting bit-level errors using error correction codes (ECC) and Chip Kill, which provides more robust error correction capabilities to recover data even if the storage chip itself fails. Summary of the Invention

[0006] This disclosure provides a storage device including a plurality of stacked slice chips. The plurality of slice chips are electrically interconnected through a plurality of vias, and when one slice chip experiences a chip kill, operation of the plurality of slice chips is determined by correcting the slice ID in each slice chip. Furthermore, among the slice chips that have not experienced a chip kill, the lowest-layer slice chip and the highest-layer slice chip can be determined to be operational.

[0007] Furthermore, this disclosure provides a storage device including a first shard chip, a second shard chip stacked on top of the first shard chip, a third shard chip stacked on top of the second shard chip, and a fourth shard chip stacked on top of the third shard chip. When the second shard chip experiences a chip kill, the first and fourth shard chips can be configured to operate, while the second and third shard chips can be configured to stop operating. Attached Figure Description

[0008] Figure 1A storage device according to an embodiment of the present disclosure is shown.

[0009] Figure 2 An embodiment of a first shard chip included in a storage device is shown.

[0010] Figure 3 An embodiment of the slice ID calibration circuit included in the first slice chip is shown.

[0011] Figure 4 An embodiment of a corrected fragment ID generation circuit included in a fragment ID calibration circuit is shown.

[0012] Figure 5 It is a table that identifies the signals transmitted during the operation of generating the first slice ID in the first slice chip.

[0013] Figure 6 It is a table that identifies the signals transmitted during the operation of generating the first inverted signal in the segment ID calibration circuit.

[0014] Figure 7 It is a table that identifies the signals transmitted during the operation of generating the first correction fragment ID in the first correction fragment ID generation circuit.

[0015] Figure 8 An embodiment of a second shard chip included in a storage device is shown.

[0016] Figure 9 An embodiment of the shard ID calibration circuit included in the second shard chip is shown.

[0017] Figure 10 An embodiment of a corrected fragment ID generation circuit included in a fragment ID calibration circuit is shown.

[0018] Figure 11 It is a table that identifies the signals transmitted during the operation of generating the second slice ID in the second slice chip.

[0019] Figure 12 It is a table that identifies the signals transmitted during the operation of generating the second inverted signal in the segment ID calibration circuit.

[0020] Figure 13 It is a table that identifies the signals transmitted during the operation of generating the second correction fragment ID in the second correction fragment ID generation circuit.

[0021] Figure 14 An embodiment of a third-slice chip included in a storage device is shown.

[0022] Figure 15 An embodiment of the slice ID calibration circuit included in the third slice chip is shown.

[0023] Figure 16 An embodiment of a corrected fragment ID generation circuit included in a fragment ID calibration circuit is shown.

[0024] Figure 17 It is a table that identifies the signals transmitted during the operation of generating the third slice ID in the third slice chip.

[0025] Figure 18 It is a table that identifies the signals transmitted during the operation of generating the third inverted signal in the segment ID calibration circuit.

[0026] Figure 19 It is a table that identifies the signals transmitted during the operation of generating the third correction fragment ID in the third correction fragment ID generation circuit.

[0027] Figure 20 An embodiment of a fourth chip included in a storage device is shown.

[0028] Figure 21 An embodiment of a slice ID calibration circuit included in the fourth slice chip is shown.

[0029] Figure 22 An embodiment of a corrected fragment ID generation circuit included in a fragment ID calibration circuit is shown.

[0030] Figure 23 It is a table that identifies the signals transmitted during the operation of generating the fourth slice ID in the fourth slice chip.

[0031] Figure 24 It is a table that identifies the signals transmitted during the operation of generating the fourth inverted signal in the segment ID calibration circuit.

[0032] Figure 25 It is a table that identifies the signals transmitted during the operation of generating the fourth correction segment ID in the fourth correction segment ID generation circuit.

[0033] Figures 26 to 28 This illustrates a memory device that performs an operation to generate a corrected fragment ID from the fragment ID when a chip-kill occurs in each fragment chip contained in the memory device.

[0034] Figure 29 This is a block diagram illustrating a stacked storage system according to an embodiment of the present disclosure.

[0035] Figure 30 This is a block diagram illustrating a stacked storage system according to another embodiment of the present disclosure. Detailed Implementation

[0036] In the following description of the embodiments, when a parameter is referred to as “predetermined,” the value of the parameter can be predetermined when the parameter is used in a process or algorithm. The value of the parameter can be determined at the start of the process or algorithm, or it can be determined during a period of execution of the process or algorithm.

[0037] Although the terms “first,” “second,” “third,” etc., are used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another and are not intended to imply the order or number of elements. Therefore, a first element in some embodiments may be referred to as a second element in other embodiments without departing from the teachings of this disclosure.

[0038] When a component is referred to as "connected" or "coupled" to another component, the component may be directly connected or coupled to the other component, or there may be intermediate components. When a component is referred to as "directly connected" or "directly coupled" to another component, there are no intermediate components.

[0039] Logic "high" and logic "low" levels can be used to describe the logic levels of electrical signals. A signal at a logic "high" level is distinct from a signal at a logic "low" level. For example, when a signal at a first voltage level corresponds to a signal at a logic "high" level, a signal at a second voltage level corresponds to a signal at a logic "low" level. In embodiments, a logic "high" level can be a voltage level higher than a logic "low" level. The logic levels of signals can differ or be reversed depending on the embodiment. For example, a signal at a logic "high" level in one embodiment may be at a logic "low" level in another embodiment, and vice versa.

[0040] Various embodiments of the present disclosure are described in more detail with reference to the accompanying drawings. These embodiments are for illustrative purposes only and are not intended to limit the scope of the disclosure.

[0041] Figure 1 A storage device 10 according to an embodiment of the present disclosure is shown.

[0042] like Figure 1 As shown, the storage device 10 includes a first segmented chip 101, a second segmented chip 102, a third segmented chip 103, and a fourth segmented chip 104. The first segmented chip 101 and the second segmented chip 102 are electrically connected to each other through a first through-hole 111 and a second through-hole 113. The second segmented chip 102 and the third segmented chip 103 are electrically connected to each other through a third through-hole 121 and a fourth through-hole 123. The third segmented chip 103 and the fourth segmented chip 104 are electrically connected to each other through a fifth through-hole 131 and a sixth through-hole 133.

[0043] The first slice chip 101 receives a first synthesized chip-kill signal SCKILL1 through a first via 111. The first synthesized chip-kill signal SCKILL1 is activated when one of the second slice chip 102, the third slice chip 103, or the fourth slice chip 104 performs a chip-kill. The first slice chip 101 can be designated as a master chip, controlling the operation of the slave chips, including the second slice chip 102, the third slice chip 103, and the fourth slice chip 104. The first slice chip 101 can be configured not to perform a chip-kill. The first slice chip 101 is configured to generate a first slice ID SID1 with a preset binary bit set. For example, the first slice chip 101 can be configured to generate a first slice ID SID1<1:0> with a binary bit set "01". The first slice chip 101 transmits the first slice ID SID1 to the second slice chip 102 through a second via 113. The first slice chip 101 is configured to generate a first corrected slice ID with a preset binary bit set (e.g., Figure 2 (CSID1<1:0> in the code). For example, the first slice chip 101 can be configured to generate a first corrected slice ID with a binary bit set "00". The first slice chip 101 is configured to operate regardless of whether a chip kill occurs in one of the second slice chip 102, the third slice chip 103, and the fourth slice chip 104.

[0044] The second slice chip 102 receives the second synthesized chip-kill signal SCKILL2 through the third via 121. The second synthesized chip-kill signal SCKILL2 is activated when one of the third slice chip 103 or the fourth slice chip 104 experiences a chip-kill. The second slice chip 102 can be designated as a slave chip operating under the control of the first slice chip 101, which is designated as the master chip. When the second slice chip 102 does not experience a chip-kill, it counts up the bit group of the first slice ID SID1 to output the second slice ID SID2. For example, when the second slice chip 102 receives the first slice ID SID1<1:0> with binary bit group "01" without experiencing a chip-kill, it can count up one bit from the binary bit group "01" of the first slice ID SID1<1:0> to generate the second slice ID SID2<1:0> with binary bit group "10". When the second slice chip 102 experiences a chip kill, it outputs the first slice ID SID1 as the second slice ID SID2. For example, when the second slice chip 102 experiences a chip kill and receives the first slice ID SID1<1:0> with a binary bit group "01", the second slice chip 102 can generate a second slice ID SID2<1:0> with the same binary bit group "01" as the first slice ID SID1. The second slice chip 102 transmits the second slice ID SID2 to the third slice chip 103 through the fourth via 123. The second slice chip 102 is configured to generate a second corrected slice ID with a preset binary bit group when the second slice chip 102 experiences a chip kill (e.g., ...). Figure 8 (CSID2<1:0> in the code). For example, when a chip kill occurs in the second slice chip 102, the second slice chip 102 can generate a second corrected slice ID with a preset binary bit group "11". The second slice chip 102 is configured to generate a second corrected slice ID with a preset binary bit group when a chip kill occurs in one of the third slice chip 103 and the fourth slice chip 104. For example, when a chip kill occurs in one of the third slice chip 103 and the fourth slice chip 104, the second slice chip 102 can generate a second corrected slice ID with a preset binary bit group "10". The second slice chip 102 is configured to stop operating when a chip kill occurs in one of the second slice chip 102, the third slice chip 103, and the fourth slice chip 104.

[0045] The third slice chip 103 receives the third synthesized chip-kill signal SCKILL3 through the fifth via 131. The third synthesized chip-kill signal SCKILL3 is activated when the fourth slice chip 104 performs a chip-kill. The third slice chip 103 can be designated as a slave chip operating under the control of the first slice chip 101, which is designated as the master chip. When the third slice chip 103 does not perform a chip-kill, it counts up the bit group of the second slice ID SID2 to output the third slice ID SID3. For example, when the third slice chip 103 receives the second slice ID SID2<1:0> with binary bit group "10" without performing a chip-kill, it can count up one bit of the binary bit group of the second slice ID SID2<1:0> to generate the third slice ID SID3<1:0> with binary bit group "11". When the third slice chip 103 experiences a chip kill, it outputs the second slice ID SID2 as the third slice ID SID3. For example, when the third slice chip 103 experiences a chip kill and receives the second slice ID SID2<1:0> with a binary bit group "10", the third slice chip 103 can generate a third slice ID SID3<1:0> with the same binary bit group "10" as the second slice ID SID2. The third slice chip 103 transmits the third slice ID SID3 to the fourth slice chip 104 through the sixth via 133. The third slice chip 103 is configured to generate a third corrected slice ID with a preset binary bit group when the third slice chip 103 experiences a chip kill (e.g., ...). Figure 14(CSID3<1:0> in the code). For example, when the third slice chip 103 experiences a chip kill, it can generate a third corrected slice ID with a preset binary bit group "11". When one of the second slice chip 102 or the fourth slice chip 104 experiences a chip kill, the third slice chip 103 is configured to generate a third corrected slice ID with a preset binary bit group. For example, when the second slice chip 102 experiences a chip kill, the third slice chip 103 can generate a third corrected slice ID with a preset binary bit group "10", while when the fourth slice chip 104 experiences a chip kill, the third slice chip 103 can generate a third corrected slice ID with a preset binary bit group "01". The third slice chip 103 is configured to stop operating based on the third corrected slice ID when one of the second slice chip 102 or the third slice chip 103 experiences a chip kill. The third chip 103 is configured to operate when the fourth chip 104 experiences a chip kill.

[0046] The fourth slice chip 104 can be designated as a slave chip operating under the control of the first slice chip 101, which is designated as the master chip. When the fourth slice chip 104 does not experience a chip-kill, it counts up the bit group of the third slice ID SID3 to output the fourth slice ID SID4. For example, when the fourth slice chip 104 receives the third slice ID SID3<1:0> with a binary bit group "11" without experiencing a chip-kill, it can count up one bit of the binary bit group of the third slice ID SID3<1:0> to generate the fourth slice ID SID4<1:0> with a binary bit group "00". When the fourth slice chip 104 experiences a chip-kill, it outputs the third slice ID SID3 as the fourth slice ID SID4. For example, when the fourth slice chip 104 experiences a chip kill and receives the third slice ID SID3<1:0> with a binary bit group of "11", the fourth slice chip 104 can generate a fourth slice ID SID4<1:0> with the same binary bit group of "11" as the third slice ID SID3. The fourth slice chip 104 is configured to generate a fourth corrected slice ID with a preset binary bit group when the fourth slice chip 104 experiences a chip kill (e.g., Figure 20(CSID4<1:0> in the code). For example, when the fourth slice chip 104 experiences a chip kill, the fourth slice chip 104 can generate a fourth corrected slice ID with a preset binary bit group "11". When the fourth slice chip 104 experiences a chip kill and the fourth corrected slice ID has a binary bit group "11", the fourth slice chip 104 is set to stop operation. The fourth slice chip 104 is configured to generate a fourth corrected slice ID with a preset binary bit group when one of the second slice chip 102 and the third slice chip 103 experiences a chip kill. For example, when one of the second slice chip 102 and the third slice chip 103 experiences a chip kill, the fourth slice chip 104 can generate a fourth corrected slice ID with a preset binary bit group "01". When one of the second slice chip 102 and the third slice chip 103 experiences a chip kill and the fourth corrected slice ID has a binary bit group "01", the fourth slice chip 104 is set to operate.

[0047] Figure 2 Examples of such storage devices included in the storage device according to the present disclosure are shown. Figure 1 An embodiment of the first slice chip 101 shown.

[0048] like Figure 2 As shown, the first slice chip 101 includes NMOS transistors 201-1 and 201-2, buffers 202-1 and 202-2, inverter 203, slice ID generation circuit (SID GEN) 205, and slice ID calibration circuit (SID CAL) 207.

[0049] NMOS transistor 201-1 operates as a driver to drive node nd201-1 to a logic "low" level. NMOS transistor 201-2 operates as a driver to drive node nd201-2 to a logic "low" level. Nodes nd201-1 and nd201-2 can be initialized to a logic "low" level.

[0050] Buffer 202-1 buffers the signal of node nd201-1 to generate the second bit SIDP of the pre-fragment ID. <1> Buffer 202-2 buffers the signals of node nd201-2 to generate the first bit of the pre-fragment ID, SIDP. <0> The pre-fragment ID SIDP<1:0> is set and initialized by buffers 202-1 and 202-2 with a binary bit set of "00". A pre-fragment ID SIDP<1:0> set to a binary bit set of "00" means that the second bit of the pre-fragment ID is SIDP. <1> and the first bit of the pre-shard ID SIDP <0> All are set to logic "low".

[0051] The fragment ID generation circuit 205 receives the pre-fragment ID SIDP<1:0> through buffers 202-1 and 202-2 electrically connected to it. The fragment ID generation circuit 205 receives the first chip-kill signal CKILL-S1 through the first input terminal F and the inverted signal of the first chip-kill signal CKILL-S1 inverted by the inverter 203 through the second input terminal D. The first chip-kill signal CKILL-S1 is activated when the first fragment chip 101 experiences a chip-kill. The fragment ID generation circuit 205 generates the first fragment ID SID1<1:0> from the pre-fragment ID SIDP<1:0> based on the first chip-kill signal CKILL-S1, so as to pass... Figure 1 The second via 113 outputs the first slice ID SID1<1:0>. When the first slice chip 101 does not experience a chip kill and the deactivated first chip kill signal CKILL-S1 is received, the slice ID generation circuit 205 counts up on the pre-slice ID SIDP<1:0> to generate the first slice ID SID1<1:0>. For example, when the deactivated first chip kill signal CKILL-S1 is received, the slice ID generation circuit 205 can count up one bit on the pre-slice ID SIDP<1:0>, which is set to have a binary bit group "00", to generate the first slice ID SID1<1:0>, which is set to have a binary bit group "01". When the first slice chip 101 experiences a chip kill and the activated first chip kill signal CKILL-S1 is received, the slice ID generation circuit 205 generates the first slice ID SID1<1:0> with the same binary bit group as the pre-slice ID SIDP<1:0>. For example, when the first chip-kill signal CKILL-S1 is received, the fragment ID generation circuit 205 can generate a first fragment ID SID1<1:0> with the same binary bit group "00" as the pre-fragment ID SIDP<1:0>.

[0052] The slice ID calibration circuit 207 receives the pre-slice ID SIDP<1:0> through buffers 202-1 and 202-2 electrically connected to it. The slice ID calibration circuit 207 generates a first corrected slice ID CSID1<1:0> from the pre-slice ID SIDP<1:0> based on the first synthesized chip-kill signal SCKILL1, the first chip-kill signal CKILL-S1, and the first lower slice signal SL-DN1. Since the first lower slice signal SL-DN1 is activated when the first slice chip 101 is at the bottom layer, the slice ID calibration circuit 207 receives the activated first lower slice signal SL-DN1. When the activated first lower slice signal SL-DN1 is received, the slice ID calibration circuit 207 is configured to generate the first corrected slice ID CSID1<1:0> with a preset binary bit group, regardless of the first synthesized chip-kill signal SCKILL1 and the first chip-kill signal CKILL-S1. For example, when the first sub-slice signal SL-DN1 is received, the slice ID calibration circuit 207 can be configured to generate a first corrected slice ID CSID1<1:0> with the same binary bit group "00" as the pre-slice ID SIDP<1:0>.

[0053] Figure 3 Examples are shown, such as Figure 2 An embodiment of the slice ID calibration circuit 207 included in the first slice chip is shown.

[0054] like Figure 3 As shown, the segment ID calibration circuit 207 includes an inverting signal generation circuit (INV GEN) 301 and a corrected segment ID generation circuit (CSID GEN) 303.

[0055] The inverting signal generation circuit 301 generates a first inverted signal INV1 based on the first chip-kill signal CKILL-S1, the first synthesized chip-kill signal SCKILL1, and the first slice signal SL-DN1. The first chip-kill signal CKILL-S1 is deactivated to set the first slice chip 101 to not be chip-killed. The inverting signal generation circuit 301 receives the activated first slice signal SL-DN1 to generate the first inverted signal INV1, which is deactivated regardless of the first synthesized chip-kill signal SCKILL1 and the first chip-kill signal CKILL-S1. Each bit contained in the first inverted signal INV1 can be set to be deactivated at a logic "low" level; however, this is merely an example and the disclosure is not limited thereto.

[0056] The corrected fragment ID generation circuit 303 receives a first inverted signal INV1 from an inverted signal generation circuit 301 electrically connected to it. The corrected fragment ID generation circuit 303 generates a first corrected fragment ID CSID1 based on a first chip-kill signal CKILL-S1 and the first inverted signal INV1. The corrected fragment ID generation circuit 303 receives both the first chip-kill signal CKILL-S1 and the first inverted signal INV1, both of which are deactivated, to generate a first corrected fragment ID CSID1 set to have the same binary bit set as the pre-fragment ID SIDP. For example, the corrected fragment ID generation circuit 303 can generate a first corrected fragment ID CSID1<1:0> with a binary bit set of "00".

[0057] Figure 4 Examples are shown, such as Figure 3 The embodiment of the correction segment ID generation circuit 303 shown is illustrated.

[0058] like Figure 4 As shown, the correction fragment ID generation circuit 303 includes a first correction fragment ID generation circuit 311 and a second correction fragment ID generation circuit 313.

[0059] The first correction segment ID generation circuit 311 generates an ID based on the first chip-kill signal CKILL-S1 deactivated at a logic "low" level and the first bit of the inverted signal INV1. <0> SIDP for the first bit of the pre-fragment ID <0> Buffering is performed to generate the first bit of CSID1 at a logic "low" level. <0> .

[0060] The second correction segment ID generation circuit 313 generates IDs based on the first chip-kill signal CKILL-S1 deactivated at a logic "low" level and the second bit INV1 of the first inverted signal INV1. <1> SIDP for the second bit of the pre-fragment ID <1> Buffering is performed to generate the second bit of CSID1 at a logic "low" level for the first corrected fragment ID CSID1. <1> .

[0061] The correction fragment ID generation circuit 303 buffers the pre-fragment ID SIDP<1:0> with binary bit set "00" according to the first chip-kill signal CKILL-S1 and the first inverted signal INV1<1:0> which are deactivated at the logic "low" level, to generate the first correction fragment ID CSID1<1:0> with binary bit set "00".

[0062] Figure 5 To identify in, for example Figure 2The table showing the signals transmitted during the operation of generating the first slice ID SID1<1:0> in the first slice chip 101 shown. Figure 6 To identify in, for example Figure 3 The table shown represents the signals transmitted during the operation of generating the first inverted signal INV1<1:0> in the segmented ID calibration circuit 207, while... Figure 7 To identify in, for example Figure 4 The table shows the signals transmitted during the operation of generating the first correction slice ID CSID1<1:0> in the first slice chip 101 shown.

[0063] refer to Figure 2 and Figure 5 The slice ID generation circuit 205 of the first slice chip 101 counts up by 1 bit on the pre-slice ID SIDP<1:0> set to have a binary bit set of "00" according to the first chip-kill signal CKILL-S1 which is deactivated at a logic "low" level "L" to generate a first slice ID SID1<1:0> set to have a binary bit set of "01". The first slice ID SID1<1:0> being set to have a binary bit set of "01" means that the second bit of the first slice ID SID1... <1> Set to logic "low" level "L" and the first bit of the first fragment ID is SID1. <0> It is set to the logic "high" level "H".

[0064] refer to Figure 3 and Figure 6 The inverting signal generation circuit 301 of the slice ID calibration circuit 207 receives the first lower slice signal SL-DN1 activated at a logic "high" level to generate a first inverted signal INV1<1:0> set to have a binary bit group of "00", regardless of the first synthesized chip-kill signal SCKILL1, the first chip-kill signal CKILL1, and the pre-slice ID SIDP. The first inverted signal INV1<1:0> being set to have a binary bit group of "00" means that the second bit of the first inverted signal INV1... <1> The first bit of the first inverted signal, INV1 <0> All are set to logic "low" level "L".

[0065] refer to Figure 3 , Figure 4 and Figure 7The corrected fragment ID generation circuit 303 generates a first corrected fragment ID CSID1<1:0> with the same binary bit group "00" as the pre-fragment ID SIDP<1:0>, based on the first chip-kill signal CKILL-S1 deactivated to a logic "low" level "L" and the first inverted signal INV1<1:0> set to have a binary bit group "00". The first corrected fragment ID CSID1 being set to have a binary bit group "00" means that the second bit of the first corrected fragment ID CSID1 is... <1> and the first bit of the first corrected fragment ID, CSID1 <0> All are set to logic "low" level "L".

[0066] Figure 8 Examples of such storage devices included in the storage device according to the present disclosure are shown. Figure 1 An embodiment of the second chip 102 shown.

[0067] like Figure 8 As shown, the second chip 102 includes NMOS transistors 211-1 and 211-2, buffers 212-1 and 212-2, inverter 213, chip ID generation circuit (SID GEN) 215, chip ID calibration circuit (SID CAL) 217, and synthesized chip-kill signal generation circuit (SCKILL GEN) 219.

[0068] NMOS transistor 211-1 operates as a driver to drive node nd211-1 to a logic "low" level. NMOS transistor 211-2 operates as a driver to drive node nd211-2 to a logic "low" level. Both nodes nd211-1 and nd211-2 can be initialized to a logic "low" level using NMOS transistors 211-1 and 211-2. The logic level of node nd211-1 can be determined via... Figure 1 The second through-hole 113 receives the second bit SID1 of the first fragment ID. <1> The logic level of node nd211-2 can be configured via the first bit SID1 of the first fragment ID received through the second via 113. <0> set up.

[0069] Buffer 212-1 buffer node nd211-1 signals to output the second bit SID1 of the first fragment ID. <1> Buffer 212-2 buffers the signals of node nd211-2 to output the first bit of the first fragment ID, SID1<1:0>. For example, buffer 212-1 can buffer and output the first fragment ID, SID1<1:0>, which is input with a binary bit group "01". Setting the first fragment ID, SID1<1:0>, to have a binary bit group "01" means the second bit of the first fragment ID, SID1. <1> Set to logic "low", while the first bit of the first fragment ID, SID1. <0> It is set to a logic "high" level.

[0070] The segment ID generation circuit 215 receives the first segment ID SID1<1:0> through buffers 212-1 and 212-2 electrically connected to it. The segment ID generation circuit 215 receives the second chip-kill signal CKILL-S2 through the first input terminal F, and receives the inverted signal of the second chip-kill signal CKILL-S2 inverted by inverter 213 through the second input terminal D. The second chip-kill signal CKILL-S2 is activated when the second segment chip 102 experiences a chip-kill. The segment ID generation circuit 215 generates the second segment ID SID2<1:0> from the first segment ID SID1<1:0> based on the second chip-kill signal CKILL-S2, and then... Figure 1The fourth via 123 outputs the second slice ID SID2<1:0>. When the second slice chip 102 does not experience a chip-kill and the deactivated second chip-kill signal CKILL-S2 is received, the slice ID generation circuit 215 counts up on the first slice ID SID1<1:0> to generate the second slice ID SID2<1:0>. For example, when the deactivated second chip-kill signal CKILL-S2 is received, the slice ID generation circuit 215 can count up one bit on the first slice ID SID1<1:0>, which is set to have a binary bit group "01", to generate the second slice ID SID2<1:0>, which is set to have a binary bit group "10". When the second slice chip 102 experiences a chip-kill and the activated second chip-kill signal CKILL-S2 is received, the slice ID generation circuit 215 generates the second slice ID SID2<1:0>, which has the same binary bit group as the first slice ID SID1<1:0>. For example, when the activated second chip-kill signal CKILL-S2 is received, the slice ID generation circuit 215 can generate a second slice ID SID2<1:0> with the same binary bit group "01" as the first slice ID SID1<1:0>.

[0071] Slice ID calibration circuit 217 receives a first slice ID SID1<1:0> via buffers 212-1 and 212-2 electrically connected to it. Slice ID calibration circuit 217 generates a second corrected slice ID CSID2<1:0> from the first slice ID SID1<1:0> based on the second synthesized chip-kill signal SCKILL2, the second chip-kill signal CKILL-S2, and the second lower slice signal SL-DN2. Since the second lower slice signal SL-DN2 is activated when the second slice chip 102 is at the bottom layer, slice ID calibration circuit 217 receives the deactivated second lower slice signal SL-DN2. Slice ID calibration circuit 217 is configured to generate a second corrected slice ID CSID2<1:0> with binary bit groups based on the second synthesized chip-kill signal SCKILL2 and the second chip-kill signal CKILL-S2 when the deactivated second lower slice signal SL-DN2 is received. For example, when the activated second chip-kill signal CKILL-S2 is received, the slice ID calibration circuit 217 can be configured to generate a second corrected slice ID CSID2<1:0> with a binary bit group of "11". The second corrected slice ID CSID2<1:0> being set to have a binary bit group of "11" means that the second bit of the second corrected slice ID CSID2... <1> The first bit of the second corrected fragment ID, CSID2 <0> All are set to logic "high" level. As another example, the slice ID calibration circuit 217 can be configured to generate a second corrected slice ID CSID2<1:0> with a binary bit group of "10" when the activated second synthetic chip-kill signal SCKILL2 is received. The second corrected slice ID CSID2<1:0> being set to have a binary bit group of "10" means that the second bit of the second corrected slice ID CSID2... <1> Set to logic "high" and the first bit of the second corrected fragment ID, CSID2. <0> It is set to a logic "low" level.

[0072] The chip-kill signal generation circuit 219 generates a first synthetic chip-kill signal SCKILL1 based on a second synthetic chip-kill signal SCKILL2 and a second chip-kill signal CKILL-S2. The circuit generates the first synthetic chip-kill signal SCKILL1, which is activated when one of the second synthetic chip-kill signals SCKILL2 and CKILL-S2 is activated. The circuit generates the activated first synthetic chip-kill signal SCKILL1 when a chip-kill occurs in the second chip chip 102 and the activated second chip-kill signal CKILL-S2 is received, or when a chip-kill occurs in one of the third chip chip 103 and the fourth chip chip 104 and the activated second synthetic chip-kill signal SCKILL2 is received. Therefore, the chip-kill signal generation circuit 219 generates the first synthetic chip-kill signal SCKILL1, which is activated when one of the second chip chip 102, the third chip chip 103, and the fourth chip chip 104 experiences a chip-kill.

[0073] Figure 9 Examples are shown Figure 8 An embodiment of the shard ID calculation circuit 217 included in the second shard chip shown.

[0074] like Figure 9 As shown, the segment ID calculation circuit 217 includes an inverting signal generation circuit (INV GEN) 321 and a corrected segment ID generation circuit (CSID GEN) 323.

[0075] The inverting signal generation circuit 321 generates a second inverted signal INV2 based on the second synthesized chip-kill signal SCKILL2, the second chip-kill signal CKILL-S2, and the second lower slice signal SL-DN2. The inverting signal generation circuit 321 receives the deactivated second lower slice signal SL-DN2 to generate a second inverted signal INV2 having binary bit groups set according to the second synthesized chip-kill signal SCKILL2 and the second chip-kill signal CKILL-S2. For example, when both the second synthesized chip-kill signal SCKILL2 and the second chip-kill signal CKILL-S2 are received and deactivated, the inverting signal generation circuit 321 can generate a second inverted signal INV2<1:0> set to have binary bit groups "00". As another example, when the activated second chip-kill signal CKILL-S2 is received, the inverting signal generation circuit 321 can generate a second inverted signal INV2<1:0> set to have binary bit groups in an "irrelevant" state "X". Setting the second inverted signal INV2<1:0> to a "non-existent" state with binary bit groups means that the binary bit groups of the second inverted signal INV2<1:0> are generated to have one of the binary bit groups "00", "01", "10", and "11". As another example, when the activated second synthetic chip-kill signal SCKILL2 is received, the inverted signal generation circuit 321 can generate the second inverted signal INV2<1:0> set to have binary bit group "11".

[0076] The corrected fragment ID generation circuit 323 receives a second inverted signal INV2 from an inverted signal generation circuit 321 electrically connected to it. Based on the second chip-kill signal CKILL-S2 and the second inverted signal INV2, the corrected fragment ID generation circuit 323 generates a second corrected fragment ID CSID2 according to the first fragment ID SID1. The corrected fragment ID generation circuit 323 receives both the deactivated second chip-kill signal CKILL-S2 and the second inverted signal INV2 to generate a second corrected fragment ID CSID2 set to have the same binary bit group as the first fragment ID SID1. For example, when the first fragment ID SID1 with binary bit group "01" is received, the corrected fragment ID generation circuit 323 can generate a second corrected fragment ID CSID2 with binary bit group "01". When the activated second chip-kill signal CKILL-S2 is received, the corrected fragment ID generation circuit 323 generates a second corrected fragment ID CSID2 set to have a preset binary bit group. For example, when the activated second chip-kill signal CKILL-S2 is received, the corrected fragment ID generation circuit 323 can generate a second corrected fragment ID CSID2<1:0> with a binary bit group of "11". When the deactivated second chip-kill signal CKILL-S2, the activated second synthesized chip-kill signal SCKILL2, and the activated second inverted signal INV2 are received, the corrected fragment ID generation circuit 323 inverts the first fragment ID SID1 to generate the second corrected fragment ID CSID2. For example, when the deactivated second chip-kill signal CKILL-S2 and the activated second inverted signal INV2 are received, the corrected fragment ID generation circuit 323 can invert the first fragment ID SID1 with a binary bit group of "01" to generate a second corrected fragment ID CSID2 with a binary bit group of "10".

[0077] Figure 10 Examples are shown, such as Figure 9 The embodiment of the correction segment ID generation circuit 323 shown is illustrated.

[0078] like Figure 10 As shown, the correction fragment ID generation circuit 323 includes a first correction fragment ID generation circuit 331 and a second correction fragment ID generation circuit 333.

[0079] When the second chip-kill signal CKILL-S2, which is activated at a logic "high" level, is received, the first correction segment ID generation circuit 331 generates the first bit CSID2 of the second correction segment ID, which is set to a logic "high" level. <0> The first correction segment ID generation circuit 331 generates the second chip-kill signal CKILL-S2, which is deactivated at a logic "low" level, and the first bit of the second inverted signal INV2. <0> For the first bit SID1 of the first fragment ID <0> Buffering is performed to generate the first bit CSID2 of the second corrected fragment ID. <0> The first correction segment ID generation circuit 331 generates the ID based on the second chip-kill signal CKILL-S2, which is deactivated at a logic "low" level, and the first bit INV2, which is activated at a logic "high" level, and the second inverted signal. <0> For the first bit SID1 of the first fragment ID <0> Perform an inverted buffer to generate the first bit CSID2 of the second corrected fragment ID. <0> .

[0080] When the second chip-kill signal CKILL-S2, which is activated at a logic "high" level, is received, the second correction segment ID generation circuit 333 generates the second bit CSID2 of the second correction segment ID, which is set to a logic "high" level. <1> The second correction segment ID generation circuit 333 generates the second chip-kill signal CKILL-S2, which is deactivated at a logic "low" level, and the second bit of the second inverted signal INV2. <1> For the second bit SID1 of the first fragment ID <1> Buffering is performed to generate the second bit CSID2 of the second corrected fragment ID. <1> The second correction segment ID generation circuit 333 generates the second chip-kill signal CKILL-S2, which is deactivated at a logic "low" level, and the second bit INV2, which is activated at a logic "high" level, based on the second bit of the second inverted signal CKILL-S2, which is deactivated at a logic "low" level. <1> For the second bit SID1 of the first fragment ID <1> Perform an inverted buffer to generate the second bit CSID2 of the second corrected fragment ID. <1> .

[0081] The correction segment ID generation circuit 323 buffers the first segment ID SID1<1:0> with binary bit group "01" based on the second chip-kill signal CKILL-S2, which is deactivated at logic "low" level, and the second inverted signal INV2<1:0>, to generate a second correction segment ID CSID2<1:0> with binary bit group "01". When the second chip-kill signal CKILL-S2, which is activated at logic "high" level, is received, the correction segment ID generation circuit 323 generates the second correction segment ID CSID2<1:0> with binary bit group "11". The correction segment ID generation circuit 323 buffers the first segment ID SID1<1:0> with binary bit group "11" based on the second chip-kill signal CKILL-S2, which is deactivated at logic "low" level, and the second bit INV2, which is activated at logic "high" level, based on the second chip-kill signal CKILL-S2, which is deactivated at logic "low" level, and the second bit INV2, which is activated at logic "high" level. <1> The first fragment ID SID1<1:0> with binary bit group "01" is inverted and buffered to generate the second corrected fragment ID CSID2<1:0> with binary bit group "10".

[0082] Figure 11 To identify in, for example Figure 8 The table showing the signals transmitted during the operation of generating the second slice ID SID2<1:0> in the second slice chip 102 shown. Figure 12 To identify in, for example Figure 9 The table shows the signals transmitted during the operation of the segmented ID calibration circuit 217 that generates the second inverted signal INV2<1:0>, while... Figure 13 To identify in, for example Figure 10 The table shows the signals transmitted during the operation of generating the second correction slice ID CSID2<1:0> in the second slice chip 102 shown.

[0083] refer to Figure 8 and Figure 11 In the first line, based on the second chip-kill signal CKILL-S2 deactivated at a logic "low" level "L", the slice ID generation circuit 215 of the second slice chip 102 counts up one bit on the first slice ID SID1<1:0>, which is set to have a binary bit group "01", to generate a second slice ID SID2<1:0>, which is set to have a binary bit group "10". The second slice ID SID2<1:0> being set to have a binary bit group "10" means that the second bit of the first slice ID SID1 <1> Set to logic "high" level "H", while the first bit of the first fragment ID, SID1. <0> Set to logic "low" level "L". See also Figure 8 and Figure 11In the second row, the slice ID generation circuit 215 of the second slice chip 102 generates a second slice ID SID2<1:0> based on the second chip-kill signal CKILL-S2, which is activated to a logic "high" level "H". The second slice ID SID2<1:0> is set to have the same binary bit group "01" as the first slice ID SID1<1:0>.

[0084] See Figure 9 and Figure 12 In the first line, when the second lower segmentation signal SL-DN2, the second synthesized chip-kill signal SCKILL2, and the second chip-kill signal CKILL-S2, which are all deactivated at the logic "low" level "L", are received, the inverting signal generation circuit 301 of the segmentation ID calibration circuit 217 generates a second inverted signal INV2<1:0> set to have a binary bit group of "00". (Refer to...) Figure 9 and Figure 12 In the second line, when the second chip-kill signal CKILL-S2, activated at logic "high" level "H," and the second lower-segment signal SL-DN2, both deactivated at logic "low" level "L," and the second combined chip-kill signal SCKILL2 are received, the inverting signal generation circuit 301 generates a second inverted signal INV2<1:0> set to the binary bit group "irrelevant" state "XX." (Refer to...) Figure 9 and Figure 12 In the third line, when the second synthesized chip-kill signal SCKILL2, which is activated at the logic "high" level "H", and the second lower segment signal SL-DN2, which is deactivated at the logic "low" level "L", and the second chip-kill signal CKILL-S2 are received, the inverting signal generation circuit 301 generates a second inverted signal INV2<1:0> set to have a binary bit group "11".

[0085] Reference Figure 9 , Figure 10 and Figure 13In the first line, the corrected slice ID generation circuit 217 generates a second corrected slice ID SID2<1:0> with the same binary bit group "01" as the first slice ID SID1<1:0>, based on the second chip-kill signal CKILL-S2 deactivated at a logic "low" level, the second synthesized chip-kill signal SCKILL2, and the second inverted signal INV2<1:0> set to have a binary bit group "00". The second corrected slice ID SID2 being set to have a binary bit group "01" means that the second bit of the second corrected slice ID SID2 is CSID2. <1> Set to logic "low" level "L", while the first bit of the second correction fragment ID, CSID2, is... <0> Set to logic "high" level "H". (See reference) Figure 9 , Figure 10 and Figure 13 In the second line, when the second chip-kill signal CKILL-S2, activated at a logic "high" level, is received, the correction slice ID generation circuit 217 generates a second correction slice ID CSID2<1:0> with a preset binary bit group "11", regardless of the second inverted signal INV2<1:0>. The second correction slice ID CSID2 being set to have a binary bit group "11" means that the second bit of the second correction slice ID CSID2... <1> The first bit of the second corrected fragment ID, CSID2 <0> All are set to logic "high" level "H". (Reference) Figure 9 , Figure 10 and Figure 13 In the third line, when the second chip-kill signal CKILL-S2, which is deactivated at the logic "low" level "L", and the second composite chip-kill signal SCKILL2, which is activated at the logic "high" level "H", and the second inverted signal INV2<1:0> are received, the correction slice ID generation circuit 217 will be set to invert the first slice ID SID1<1:0> with binary bit group "01" to generate the second correction slice ID CSID2<1:0>, which is set to have binary bit group "10".

[0086] Figure 14 The storage device includes, for example, such as Figure 1 The embodiment of the third chip 103 shown.

[0087] like Figure 14As shown, the third chip 103 includes NMOS transistors 221-1 and 221-2, buffers 222-1 and 222-2, inverter 223, chip ID generation circuit (SID GEN) 225, chip ID calibration circuit (SID CAL) 227, and synthesized chip-kill signal generation circuit (SCKILL GEN) 229.

[0088] NMOS transistor 221-1 operates as a driver to drive node nd221-1 to a logic "low" level. NMOS transistor 221-2 operates as a driver to drive node nd221-2 to a logic "low" level. Both nodes nd221-1 and nd221-2 can be initialized to a logic "low" level using NMOS transistors 221-1 and 221-2. The logic level of node nd221-1 can be determined via... Figure 1 The second bit SID2 of the second fragment ID received by the fourth through-hole 123 <1> To configure. The logic level of node nd221-2 can be set via the first bit SID2 of the second fragment ID received through the fourth via 123. <0> To set it up.

[0089] Buffer 221-1 buffers the signal of node nd221-1 to output the second bit SID2 of the second fragment ID. <1> Buffer 222-2 buffers the signal from node nd221-2 to output the first bit SID2 of the second fragment ID. <0> For example, buffers 222-1 and 222-2 can buffer and output the second fragment ID SID2<1:0>, which is input with a binary bit group "10". The second fragment ID SID2<1:0> being set to have a binary bit group "10" means that the second bit of the second fragment ID, SID2, is... <1> Set to logic "high" level, and the first bit of the second fragment ID, SID2. <0> It is set to a logic "low" level.

[0090] The slice ID generation circuit 225 receives the second slice ID SID2<1:0> through buffers 222-1 and 222-2 electrically connected to it. The slice ID generation circuit 225 receives the third chip-kill signal CKILL-S3 through the first input terminal F, and receives the inverted third chip-kill signal CKILL-S3 inverted by inverter 223 through the second input terminal D. The third chip-kill signal CKILL-S3 is activated when the third slice chip 103 experiences a chip-kill. The slice ID generation circuit 225 generates the third slice ID SID3<1:0> from the second slice ID SID2<1:0> based on the third chip-kill signal CKILL-S3, so as to pass... Figure 1 The sixth via 133 outputs the third slice ID SID3<1:0>. When the third slice chip 103 does not experience a chip kill and the deactivated third chip kill signal CKILL-S3 is received, the slice ID generation circuit 225 counts up on the second slice ID SID2<1:0> to generate the third slice ID SID3<1:0>. For example, when the deactivated third chip kill signal CKILL-S3 is received, the slice ID generation circuit 225 can count up one bit on the second slice ID SID2<1:0>, which is set to have a binary bit group "10", to generate the third slice ID SID3<1:0>, which is set to have a binary bit group "11". When the third slice chip 103 experiences a chip kill and the activated third chip kill signal CKILL-S3 is received, the slice ID generation circuit 225 generates the third slice ID SID3<1:0>, which has the same binary bit group as the second slice ID SID2<1:0>. For example, when the activated third chip-kill signal CKILL-S3 is received, the slice ID generation circuit 225 can generate a third slice ID SID3<1:0> with the same binary bit group "10" as the second slice ID SID2<1:0>.

[0091] Slice ID calibration circuit 227 receives the second slice ID SID2<1:0> via buffers 221-1 and 222-2 electrically connected to it. Slice ID calibration circuit 227 generates a third corrected slice ID CSID3<1:0> from the second slice ID SID2<1:0> based on the third synthesized chip-kill signal SCKILL3, the third chip-kill signal CKILL3, and the third lower slice signal SL-DN3. Since the third lower slice signal SL-DN3 is activated when the third slice chip 103 is at the lowest layer, slice ID calibration circuit 227 receives the deactivated third lower slice signal SL-DN3. Slice ID calibration circuit 227 is configured to generate a third corrected slice ID CSID3<1:0> with binary bit groups based on the third synthesized chip-kill signal SCKILL3 and the third chip-kill signal CKILL-S3 when the deactivated third lower slice signal SL-DN3 is received. For example, the slice ID calibration circuit 227 can be configured to generate a third corrected slice ID CSID3<1:0> with binary bit groups when the activated third chip-kill signal CKILL-S3 is received. As another example, the slice ID calibration circuit 227 can be configured to invert a second slice ID SID2<1:0> with binary bit groups "10" when the activated third composite chip-kill signal SCKILL3 is received, to generate a third corrected slice ID CSID3<1:0> with binary bit groups "01".

[0092] The chip-kill signal generation circuit 229 generates a second synthetic chip-kill signal SCKILL2 based on the third synthetic chip-kill signal SCKILL3 and the third chip-kill signal CKILL-S3. The circuit generates the second synthetic chip-kill signal SCKILL2, which is activated when one of the third synthetic chip-kill signals SCKILL3 or CKILL-S3 is activated. The circuit generates the activated second synthetic chip-kill signal SCKILL2 when a chip-kill occurs in the third chip 103 and the activated third chip-kill signal CKILL-S3 is received, or when a chip-kill occurs in the fourth chip 104 and the activated third synthetic chip-kill signal SCKILL3 is received. Therefore, the chip-kill signal generation circuit 229 generates the second synthetic chip-kill signal SCKILL2, which is activated when one of the third chip 103 or the fourth chip 104 experiences a chip-kill.

[0093] Figure 15 Examples are shown, such as Figure 14 An embodiment of the segmented ID calibration circuit 227 is shown.

[0094] like Figure 15 As shown, the slice ID calibration circuit 227 includes an inverting signal generation circuit (INV GEN) 341 and a corrected slice ID generation circuit (CSID GEN) 343.

[0095] The inverting signal generation circuit 341 generates a third inverted signal INV3 based on the third synthesized chip-kill signal SCKILL3, the third chip-kill signal CKILL-S3, and the third lower slice signal SL-DN3. The inverting signal generation circuit 341 receives the deactivated third lower slice signal SL-DN3 to generate a third inverted signal INV3 having a binary bit set according to the third synthesized chip-kill signal SCKILL3 and the third chip-kill signal CKILL-S3. For example, when both the third synthesized chip-kill signal SCKILL3 and the third chip-kill signal CKILL-S3 are deactivated, the inverting signal generation circuit 341 generates a third inverted signal INV3<1:0>, which is set to have a binary bit set of "00". As another example, when the activated third chip-kill signal CKILL-S3 is received, the inverting signal generation circuit 341 can generate a third inverted signal INV3<1:0>, which is set to a binary bit group "irrelevant" state "X". As another example, when the activated third synthetic chip-kill signal SCKILL3 is received, the inverting signal generation circuit 341 can generate a third inverted signal INV3<1:0>, which is set to a binary bit group "11".

[0096] The corrected fragment ID generation circuit 343 receives a third inverted signal INV3 from an inverted signal generation circuit 341 electrically connected to it. Based on the third chip-kill signal CKILL-S3 and the third inverted signal INV3, the corrected fragment ID generation circuit 343 generates a third corrected fragment ID CSID3 according to the second fragment ID SID2. The corrected fragment ID generation circuit 343 receives the third chip-kill signal CKILL-S3 and the third inverted signal INV3, both of which are deactivated, to generate a third corrected fragment ID CSID3 configured to have the same binary bit set as the second fragment ID SID2. For example, when the second fragment ID SID2 with binary bit set "10" is received, the corrected fragment ID generation circuit 343 can generate a third corrected fragment ID CSID3 with binary bit set "10". When the activated third chip-kill signal CKILL-S3 is received, the corrected fragment ID generation circuit 343 generates a third corrected fragment ID CSID3 with a preset binary bit group. For example, when the activated third chip-kill signal CKILL-S3 is received, the corrected fragment ID generation circuit 343 can generate a third corrected fragment ID CSID3<1:0> with a binary bit group "11". When the deactivated third chip-kill signal CKILL-S3, the activated third composite chip-kill signal SCKILL3, and the activated third inverted signal INV3 are received, the corrected fragment ID generation circuit 343 inverts the second fragment ID SID2 to generate the third corrected fragment ID CSID3. For example, when the deactivated third chip-kill signal CKILL-S3, the activated third composite chip-kill signal SCKILL3, and the activated third inverted signal INV3 are received, the corrected slice ID generation circuit 343 can invert the second slice ID SID2 with binary bit group "10" to generate the third corrected slice ID CSID3 with binary bit group "01".

[0097] Figure 16 Examples are shown, such as Figure 15 The embodiment of the correction fragment ID generation circuit 343 shown is illustrated.

[0098] like Figure 16 As shown, the correction fragment ID generation circuit 343 includes a first correction fragment ID generation circuit 351 and a second correction fragment ID generation circuit 353.

[0099] When the third chip-kill signal CKILL-S3, which is activated at a logic "high" level, is received, the first correction segment ID generation circuit 351 generates the first bit CSID3 of the third correction segment ID, which is set to a logic "high" level. <0> The first correction segment ID generation circuit 351 is based on the third chip-kill signal CKILL-S3, which is deactivated at a logic "low" level, and the first bit of the third inverted signal INV3. <0> For the first bit SID2 of the second fragment ID <0> Buffering is performed to generate the first bit of the third corrected fragment ID, CSID3. <0> Based on the third chip-kill signal CKILL-S3 being deactivated at a logic "low" level and the first bit INV3 of the third inverted signal being activated at a logic "high" level. <0> The first correction segment ID generation circuit 351 generates the first bit SID2 of the second segment ID. <0> Invert the phase to generate the first bit CSID3 of the third corrected fragment ID. <0> .

[0100] When the third chip-kill signal CKILL3, which is activated at a logic "high" level, is received, the second correction segment ID generation circuit 353 generates the second bit CSID3 of the third correction segment ID, which is set to a logic "high" level. <2> The second correction segment ID generation circuit 353 generates the third chip-kill signal CKILL-S3, which is deactivated at a logic "low" level, and the second bit of the third inverted signal INV3. <1> For the second bit SID2 of the second fragment ID <1> Buffering is performed to generate the second bit CSID3 of the third corrected fragment ID. <1> Based on the third chip-kill signal CKILL-S3 being deactivated at a logic "low" level and the second bit INV3 of the third inverted signal being activated at a logic "high" level. <1> The second correction segment ID generation circuit 353 generates the second bit SID2 of the second segment ID. <1> Perform an inverted buffer to generate the second bit CSID3 of the third corrected fragment ID. <1> .

[0101] Figure 17 It is an identifier in such as Figure 14 The table showing the signals transmitted during the operation of generating the third slice ID SID3<1:0> in the third slice chip 103 shown. Figure 18 It is an identifier in such as Figure 15 The table shows the signals transmitted during the operation of the segmented ID calibration circuit 227 that generates the third inverted signal INV3<1:0>, while... Figure 19 It is an identifier in such as Figure 16 The table shows the signals transmitted during the operation of generating the third correction slice ID CSID3<1:0> in the third slice chip 103 shown.

[0102] refer to Figure 14 and Figure 17 In the first row, the slice ID generation circuit 225 of the third slice chip 103, based on the third chip-kill signal CKILL-S3 which is deactivated at a logic "low" level "L", counts up one bit from the second slice ID SID2<1:0>, which is set to have a binary bit set of "01", to generate the third slice ID SID3<1:0>, which is set to a binary bit set of "10". (Reference) Figure 14 and Figure 17 In the second line, the slice ID generation circuit 225 of the third slice chip 103 generates a third slice ID SID3<1:0> based on the third chip-kill signal CKILL3, which is activated at a logic "high" level "H". This third slice ID is set to have the same binary bit group "01" as the second slice ID SID2<1:0>. (See reference) Figure 14 and Figure 17 In the third line, the slice ID generation circuit 225 of the third slice chip 103, based on the third chip-kill signal CKILL3 which is deactivated to a logic "low" level "L", counts up by 1 bit on the second slice ID SID2<1:0>, which is set to have a binary bit set of "10", to generate the third slice ID SID3<1:0>, which is set to have a binary bit set of "11". (See reference) Figure 14 and Figure 17 In the fourth line, the slice ID generation circuit 225 of the third slice chip 103 generates a third slice ID SID3<1:0> that is set to have the same binary bit group "10" as the second slice ID SID2<1:0> according to the third chip-kill signal CKILL3 that is activated to a logic "high" level "H".

[0103] refer to Figure 15 and Figure 18 In the first line, when the inverted signal generation circuit 301 of the slice ID calibration circuit 227 receives the third lower slice signal SL-DN3, the third synthesized chip-kill signal SCKILL3, and the third chip-kill signal CKILL-S3, all of which are deactivated at the logic "low" level "L", it generates a third inverted signal INV3<1:0>, which is set to have a binary bit group "00". (Reference) Figure 15 and Figure 18In the second line, when the third chip-kill signal CKILL-S3, activated at logic "high" level "H," and the third lower-slice signal SL-DN3, deactivated at logic "low" level "L," and the third synthesized chip-kill signal SCKILL3 are received, the inverting signal generation circuit 301 generates a third inverted signal INV3<1:0> set to the binary bit group "irrelevant" state "XX." See also... Figure 15 and Figure 18 In the third line, when the third synthesized chip-kill signal SCKILL3, which is activated to a logic "high" level "H", and the third lower segment signal SL-DN3 and the third chip-kill signal CKILL-S3, which are both deactivated to a logic "low" level "L", are received, the inverting signal generation circuit 301 generates a third inverted signal INV3<1:0> set to have a binary bit group "11".

[0104] refer to Figure 15 , Figure 16 and Figure 19 In the first line, the corrected slice ID generation circuit 227 generates a third corrected slice ID CSID3<1:0> with the same binary bit group "01" as the second slice ID SID2<1:0>, based on the third chip-kill signal CKILL-S3 deactivated at a logic "low" level, the third synthesized chip-kill signal SCKILL3, and the third inverted signal INV3<1:0> set to have binary bit group "00". (See reference) Figure 15 , Figure 16 and Figure 19 In the second line, when the third chip-kill signal CKILL-S3, activated at logic "high" level "H," is received, the correction slice ID generation circuit 227 generates a third correction slice ID CSID3<1:0> with a preset binary bit group "11," regardless of the third inverted signal INV3<1:0>. (See reference...) Figure 15 , Figure 16 and Figure 19 In the third line, when the third chip-kill signal CKILL-S3, which is deactivated at logic "low" level "L," and the third synthesized chip-kill signal SCKILL3, which is fully activated at logic "high" level "H," and the third inverted signal INV3<1:0> are received, the corrected slice ID generation circuit 227 will be set to invert the first slice ID SID1<1:0> with binary bit group "01" to generate the third corrected slice ID CSID3<1:0> with binary bit group "01." (Reference) Figure 15 , Figure 16 and Figure 19 In the fourth line, based on the third chip-kill signal CKILL-S3 and the third synthesized chip-kill signal SCKILL3 deactivated at logic "low" level "L" and the third inverted signal INV3<1:0> set to have binary bit groups "00", the corrected slice ID generation circuit 227 generates a third corrected slice ID CSID3<1:0> with the same binary bit groups as the first slice ID SID1<1:0> with binary bit groups "10". (See reference) Figure 15 , Figure 16 and Figure 19 In the fifth line, when the third chip-kill signal CKILL-S3, activated at logic "high" level "H," is received, the correction slice ID generation circuit 227 generates a third correction slice ID CSID3<1:0> with a preset binary bit group "11," regardless of the third inverted signal INV3<1:0>. See also Figure 15 , Figure 16 and Figure 19 In the sixth line, when the third chip-kill signal CKILL-S3, which is deactivated at logic "low" level "L", and the third composite chip-kill signal SCKILL3, which is fully activated at logic "high" level "H", and the third inverted signal INV3<1:0> are received, the correction slice ID generation circuit 227 will be set to invert the first slice ID SID1<1:0> with binary bit group "10" to generate the third correction slice ID CSID3<1:0>, which is set to binary bit group "01".

[0105] Figure 20 Examples are shown, such as Figure 1 The embodiment of the fourth chip 104 shown.

[0106] like Figure 20 As shown, the fourth chip 104 includes NMOS transistors 231-1 and 231-2, buffers 232-1 and 232-2, inverter 233, chip ID generation circuit (SID GEN) 235, chip ID calibration circuit (SID CAL) 237, and synthesized chip-kill signal generation circuit (SCKILL GEN) 239.

[0107] NMOS transistor 231-1 operates as a driver to drive node nd231-1 to a logic "low" level. NMOS transistor 231-2 operates as a driver to drive node nd231-2 to a logic "low" level. Both nodes nd231-1 and nd231-2 can be initialized to a logic "low" level using NMOS transistors 231-1 and 231-2, respectively. The logic level of node nd231-1 can be... Figure 1 The logic level of node nd231-2 can be set via the sixth via 133. The logic level of node nd231-2 can be set via the first bit SID3 of the third fragment ID received by the sixth via 133. <0> To set it up.

[0108] Buffer 232-1 buffer node nd231-1 signals to output the second bit SID3 of the third fragment ID. <1> The signal of buffer node nd231-2 in buffer 232-2 is used to output the first bit SID3 of the third fragment ID. <0> For example, buffers 232-1 and 232-2 can buffer and output the third fragment ID SID3<1:0>, which is input with a binary bit group "11". The third fragment ID SID3<1:0> being set to have a binary bit group "11" means that the second bit of the third fragment ID is SID3. <1> and the first bit of the third fragment ID, SID3 <0> It is set to a logic "high" level.

[0109] The slice ID generation circuit 235 receives the third slice ID SID3<1:0> through buffers 232-1 and 232-2 electrically connected to it. The slice ID generation circuit 235 receives the fourth chip-kill signal CKILL-S4 through the first input terminal F and the inverted fourth chip-kill signal CKILL-S4 (inverted by inverter 233) through the second input terminal D. The fourth chip-kill signal CKILL-S4 is activated when the fourth slice chip 104 experiences a chip-kill. Based on the fourth chip-kill signal CKILL-S4, the slice ID generation circuit 235 generates the fourth slice ID SID4<1:0> from the third slice ID SID3<1:0>. When the fourth slice chip 104 does not experience a chip-kill and the deactivated fourth chip-kill signal CKILL-S4 is received, the slice ID generation circuit 235 counts up on the third slice ID SID3<1:0> to generate the fourth slice ID SID4<1:0>. For example, when the deactivated fourth chip-kill signal CKILL-S4 is received, the slice ID generation circuit 235 can count up one bit from the third slice ID SID3<1:0> with binary bit group "11" to generate a fourth slice ID SID4<1:0> set to binary bit group "00". When the fourth slice chip 104 performs a chip-kill and the activated fourth chip-kill signal CKILL-S4 is received, the slice ID generation circuit 235 generates a fourth slice ID SID4<1:0> with the same binary bit group as the third slice ID SID3<1:0>. For example, when the activated fourth chip-kill signal CKILL-S4 is received, the slice ID generation circuit 235 can generate a fourth slice ID SID4<1:0> with the same binary bit group "11" as the third slice ID SID3<1:0>.

[0110] The slice ID calibration circuit 237 receives the third slice ID SID3<1:0> via buffers 232-1 and 232-2 electrically connected to it. The slice ID calibration circuit 237 generates a fourth corrected slice ID CSID4<1:0> from the third slice ID SID3<1:0> based on the fourth chip-kill signal CKILL-S4 and the fourth lower slice signal SL-DN4. Since the fourth lower slice signal SL-DN4 is activated when the fourth slice chip 104 is at the lowest layer, the slice ID calibration circuit 237 receives the deactivated fourth lower slice signal SL-DN4. The slice ID calibration circuit 237 is configured to generate a fourth corrected slice ID CSID4<1:0> with binary bit groups based on the fourth chip-kill signal CKILL-S4 when the deactivated fourth lower slice signal SL-DN4 is received. For example, the slice ID calibration circuit 237 can be configured to generate a fourth corrected slice ID CSID4<1:0> with a binary bit group "11" when the activated fourth chip-kill signal CKILL-S4 is received. As another example, the slice ID calibration circuit 237 can be configured to generate a fourth corrected slice ID CSID4<1:0> with a binary bit group "irrelevant" state "XX" when the deactivated fourth chip-kill signal CKILL-S4 is received.

[0111] The chip-kill signal generation circuit 239 generates a third synthetic chip-kill signal SCKILL3 based on the fourth chip-kill signal CKILL-S4. The chip-kill signal generation circuit 239 generates the third synthetic chip-kill signal SCKILL3, which is activated when the fourth chip-kill signal CKILL-S4 is activated. When the fourth chip 104 is damaged and the activated fourth chip-kill signal CKILL-S4 is received, the chip-kill signal generation circuit 239 generates the activated third synthetic chip-kill signal SCKILL3.

[0112] Figure 21 Examples are shown, such as Figure 20 An embodiment of the segmented ID calibration circuit 237 is shown.

[0113] like Figure 21 As shown, the slice ID calibration circuit 237 includes an inverting signal generation circuit (INV GEN) 361 and a corrected slice ID generation circuit (CSID GEN) 363.

[0114] The inverting signal generation circuit 361 generates a fourth inverted signal INV4 based on the fourth chip-kill signal CKILL-S4 and the fourth lower slice signal SL-DN4. The inverting signal generation circuit 361 receives the deactivated fourth lower slice signal SL-DN4 to generate the fourth inverted signal INV4 having a binary bit group set according to the fourth synthesized chip-kill signal SCKIIL4. For example, when the deactivated fourth chip-kill signal CKILL-S4 is received, the inverting signal generation circuit 361 can generate the fourth inverted signal INV4 set to a binary bit group "irrelevant" state "X".

[0115] The corrected fragment ID generation circuit 363 receives a fourth inverted signal INV4 from an inverted signal generation circuit 361 electrically connected to it. Based on the fourth chip-kill signal CKILL-S4 and the fourth inverted signal INV4, the corrected fragment ID generation circuit 363 generates a fourth corrected fragment ID CSID4 according to the third fragment ID SID3. The corrected fragment ID generation circuit 363 receives the fourth chip-kill signal CKILL-S4 and the fourth inverted signal INV4, both of which are deactivated, to generate a fourth corrected fragment ID CSID4 set to have the same binary bit set as the third fragment ID SID3. For example, when the third fragment ID SID3 with binary bit set "10" is received, the corrected fragment ID generation circuit 363 can generate a fourth corrected fragment ID CSID4 with binary bit set "10". When the activated fourth chip-kill signal CKILL-S4 is received, the correction fragment ID generation circuit 363 generates a fourth correction fragment ID CSID4 with a preset binary bit group. For example, when the activated fourth chip-kill signal CKILL-S4 is received, the correction fragment ID generation circuit 363 can generate a fourth correction fragment ID CSID4<1:0> with a binary bit group "11".

[0116] Figure 22 Examples are shown, such as Figure 21 The embodiment of the correction fragment ID generation circuit 363 shown is illustrated.

[0117] like Figure 22 As shown, the correction fragment ID generation circuit 363 includes a first correction fragment ID generation circuit 371 and a second correction fragment ID generation circuit 373.

[0118] When the fourth chip-kill signal CKILL-S4, activated at a logic "high" level, is received, the first correction segment ID generation circuit 371 generates the first bit CSID4 of the fourth correction segment ID, set to a logic "high" level. <0> Based on the fourth chip-kill signal CKILL-S4, which is deactivated to a logic "low" level, and the first bit of the fourth inverted signal INV4... <0> The first correction segment ID generation circuit 371 generates the first bit SID3 of the third segment ID. <0> Buffering is performed to generate the first bit of the fourth corrected fragment ID, CSID4. <0> Based on the fourth chip-kill signal CKILL-S4 being deactivated at a logic "low" level and the first bit INV4 of the fourth inverted signal being activated at a logic "high" level. <0> The first correction segment ID generation circuit 371 generates the first bit SID3 of the third segment ID. <0> Perform an inverted buffer to generate the first bit CSID4 of the fourth corrected fragment ID. <0> .

[0119] When the fourth chip-kill signal CKILL-S4, activated at a logic "high" level, is received, the second correction segment ID generation circuit 373 generates the second bit CSID4 of the fourth correction segment ID, which is set to a logic "high" level. <1> Based on the fourth chip-kill signal CKILL-S4, which is deactivated to a logic "low" level, and the second bit of the fourth inverted signal INV4<1:0>, INV4... <1> The second correction segment ID generation circuit 373 generates the second bit SID3 of the third segment ID. <1> Buffering is performed to generate the second bit CSID4 of the fourth corrected fragment ID. <1> Based on the fourth chip-kill signal CKILL-S4 being deactivated at a logic "low" level and the second bit INV4 of the fourth inverted signal INV4<1:0> being activated at a logic "high" level. <1> The second correction segment ID generation circuit 373 generates the second bit SID3 of the third segment ID. <1> Perform an inverted buffer to generate the second bit CSID4 of the fourth corrected fragment ID. <1> .

[0120] Figure 23 To identify in, for example Figure 20 The signal table transmitted during the operation of generating the fourth slice ID SID4<1:0> in the fourth slice chip 104 shown. Figure 24 To identify in, for example Figure 21 The table shows the signals transmitted during the operation of the segmented ID calibration circuit 237, which generates the fourth inverted signal INV4<1:0>. Figure 25 To identify in, for example Figure 22The table shows the signals transmitted during the operation of generating the fourth correction slice ID SID4<1:0> in the fourth slice chip 104 shown.

[0121] refer to Figure 20 and Figure 23 In the first row, the slice ID generation circuit 235 of the fourth slice chip 104, based on the fourth chip-kill signal CKILL-S4 which is deactivated at a logic "low" level "L", counts up one bit from the third slice ID SID3<1:0>, which is set to have a binary bit set of "01", to generate a fourth slice ID SID4<1:0>, which is set to have a binary bit set of "10". (Reference) Figure 20 and Figure 23 In the second line, the slice ID generation circuit 235 of the fourth slice chip 104 generates a fourth slice ID SID4<1:0> based on the fourth chip-kill signal CKILL-S4, which is activated at a logic "high" level "H". This fourth slice ID is set to have the same binary bit group "01" as the third slice ID SID3<1:0>. See also... Figure 20 and Figure 23 In the third line, the slice ID generation circuit 235 of the fourth slice chip 104, based on the fourth chip-kill signal CKILL-S4 which is deactivated to a logic "low" level "L", counts up by 1 bit on the third slice ID SID3<1:0>, which is set to have a binary bit set of "10", to generate the fourth slice ID SID4<1:0>, which is set to have a binary bit set of "11". See also Figure 20 and Figure 23 In the fourth line, the slice ID generation circuit 235 of the fourth slice chip 104 generates a fourth slice ID SID4<1:0> based on the fourth chip-kill signal CKILL-S4, which is activated at a logic "high" level "H". This fourth slice ID is set to have the same binary bit group "10" as the third slice ID SID3<1:0>. See also... Figure 20 and Figure 23 In the fifth line, the slice ID generation circuit 235 of the fourth slice chip 104, based on the fourth chip-kill signal CKILL-S4 which is deactivated to a logic "low" level "L", counts up by 1 bit on the third slice ID SID3<1:0>, which is set to have a binary bit set of "11", to generate the fourth slice ID SID4<1:0>, which is set to have a binary bit set of "00". See also Figure 20 and Figure 23In the sixth line, the slice ID generation circuit 235 of the fourth slice chip 104 generates a fourth slice ID SID4<1:0> which is set to have the same binary bit group "11" as the third slice ID SID3<1:0> according to the fourth chip-kill signal CKILL-S4 which is activated to a logic "high" level "H".

[0122] See Figure 21 and Figure 24 In the first line, when the fourth lower slice signal SL-DN4 and the fourth chip-kill signal CKILL-S4, both deactivated to logic "low" level "L", are received, the inverting signal generation circuit 301 of the slice ID calibration circuit 237 generates a fourth inverted signal INV4<1:0> set to have binary bit groups "00". See also... Figure 21 and Figure 24 In the second line, when the fourth chip-kill signal CKILL-S4, which is activated to a logic "high" level "H", and the fourth lower slice signal SL-DN4, which is deactivated to a logic "low" level "L", are received, the inverting signal generation circuit 301 generates a fourth inverted signal INV4<1:0> with a binary bit group set to an "irrelevant" state "XX".

[0123] refer to Figure 21 , Figure 23 and Figure 25 In the first line, based on the fourth chip-kill signal CKILL-S4 deactivated at logic "low" level "L" and the fourth inverted signal INV4<1:0> set to have a binary bit set of "00", the corrected slice ID generation circuit 363 of the slice ID calibration circuit 237 generates a fourth corrected slice ID CSID4 with the same binary bit set of "01" as the third slice ID SID3. (See reference) Figure 21 , Figure 23 and Figure 25 In the second line, when the fourth chip-kill signal CKILL-S4, activated at logic "high" level "H," is received, the corrected slice ID generation circuit 363 generates a fourth corrected slice ID CSID4 with a binary bit group of "11," regardless of the fourth inverted signal INV4<1:0>. (Reference) Figure 21 , Figure 23 and Figure 25In the third line, based on the fourth chip-kill signal CKILL-S4 deactivated at logic "low" level "L" and the fourth inverted signal INV4<1:0> set to have binary bit group "00", the correction slice ID generation circuit 363 generates a fourth correction slice ID CSID4 with the same binary bit group "10" as the third slice ID SID3. (See reference) Figure 21 , Figure 23 and Figure 25 In the fourth line, when the fourth chip-kill signal CKILL-S4, activated at logic "high" level "H," is received, the correction slice ID generation circuit 363 generates a fourth correction slice ID CSID4 with a preset binary bit group "11," regardless of the fourth inverted signal INV4<1:0>. (Reference) Figure 21 , Figure 23 and Figure 25 In the fifth line, based on the fourth chip-kill signal CKILL-S4, which is deactivated to a logic "low" level "L", and the fourth inverted signal INV4<1:0>, which is set to binary bit group "00", the correction slice ID generation circuit 363 generates a fourth correction slice ID CSID4 with the same binary bit group "11" as the third slice ID SID3. (Refer to...) Figure 21 , Figure 23 and Figure 25 In the sixth line, when the fourth chip-kill signal CKILL-S4, which is activated to a logic "high" level "H", is received, the correction slice ID generation circuit 363 generates a fourth correction slice ID CSID4 with a preset binary bit group "11", regardless of the fourth inverted signal INV4<1:0>.

[0124] Figures 26 to 28 Examples of embodiments according to this disclosure are shown. Figure 1 The storage device 10 shown is a storage device that generates a corrected slice ID when a chip kill occurs in the second slice chip 102, the third slice chip 103, and the fourth slice chip 104.

[0125] refer to Figure 26 It describes the operation of generating the first to fourth corrected slice IDs CSID1<1:0>, CSID2<1:0>, CSID3<1:0> and CSID4<1:0> respectively in the first slice chip 101, the second slice chip 102, the third slice chip 103 and the fourth slice chip 104 when the second slice chip 102 performs a chip kill.

[0126] First, since the first chip-kill signal CKILL-S1 in the first slice chip 101 is deactivated to a logic "low" level "L", the pre-slice ID SIDP<1:0>, set to have a binary bit group of "00", is counted up by one bit, and the first slice ID SID1<1:0>, set to have a binary bit group of "01", is generated. Furthermore, based on the first inverted signal INV1<1:0> in the first slice chip 101, set to have a binary bit group of "00", a first corrected slice ID CSID1<1:0>, set to have the same binary bit group of "00" as the pre-slice ID SIDP<1:0>, is generated. The first slice chip 101 can continue operating based on the first corrected slice ID CSID1<1:0>, set to have a binary bit group of "00".

[0127] Next, since the second chip-kill signal CKILL-S2 is activated to a logic "high" level "H" in the second slice chip 102, a second slice ID SID2<1:0> is generated with the same binary bit group "01" as the first slice ID SID1<1:0>. Furthermore, regardless of the second inverting signal INV2<1:0>, a second corrected slice ID CSID2<1:0> with binary bit group "11" is generated in the second slice chip 102. The second slice chip 102 can stop operating based on the second corrected slice ID CSID2<1:0> with binary bit group "11".

[0128] Next, since the third chip-kill signal CKILL-S3 in the third-slice chip 103 is deactivated to a logic "low" level "L", the second slice ID SID2<1:0>, which is set to have a binary bit group "01", counts up one bit, and a third slice ID SID3<1:0>, which is set to have a binary bit group "10", is generated. Furthermore, in the third-slice chip 103, the second slice ID SID2<1:0>, which is set to have a binary bit group "01", is inverted by the third inverted signal INV3<1:0>, which is set to have a binary bit group "11", and a third corrected slice ID CSID3<1:0>, which is set to have a binary bit group "10", is generated. The third-slice chip 103 can stop operating based on the third corrected slice ID CSID3<1:0>, which is set to have a binary bit group "10".

[0129] Next, since the fourth chip-kill signal CKILL-S4 in the fourth slice chip 104 is deactivated to a logic "low" level "L", the third slice ID SID3<1:0>, set to have a binary bit set of "10", is counted up by 1 bit to generate the fourth slice ID SID4<1:0>, set to have a binary bit set of "11". Additionally, in the fourth slice chip 103, the third slice ID SID2<1:0>, set to have a binary bit set of "10", is inverted by the fourth inverted signal INV4<1:0>, set to have a binary bit set of "11", and the fourth corrected slice ID CSID4<1:0>, set to have a binary bit set of "01", is generated. The fourth slice chip 103 can maintain operation via the fourth corrected slice ID CSID4<1:0>, set to have a binary bit set of "01".

[0130] As described above, the storage device 10 is configured to operate only on the first shard chip 101 at the lowest level and the fourth shard chip 104 at the highest level based on the first to fourth corrected shard IDs CSID1<1:0>, CSID2<1:0>, CSID3<1:0> and CSID4<1:0> when the second shard chip 102 experiences a chip kill, thereby enabling the storage device 10 to maintain stable operation even after a chip kill.

[0131] See Figure 27 It describes the operation of generating first to fourth corrected fragment IDs CSID1<1:0>, CSID2<1:0>, CSID3<1:0> and CSID4<1:0> respectively in the first fragment chip 101, the second fragment chip 102, the third fragment chip 103 and the fourth fragment chip 104 when the third fragment chip 103 performs a chip kill.

[0132] First, since the first chip-kill signal CKILL-S1 in the first slice chip 101 is deactivated to a logic "low" level "L", the pre-slice ID SIDP<1:0>, set to have a binary bit group "00", is counted up by one bit, and the first slice ID SID1<1:0>, set to have a binary bit group "01", is generated. Furthermore, in the first slice chip 101, a first corrected slice ID CSID1<1:0>, set to have the same binary bit group "00" as the pre-slice ID SIDP<1:0>, is generated based on the first inverted signal INV1<1:0>, set to have a binary bit group "00". The first slice chip 101 can continue operating based on the first corrected slice ID CSID1<1:0>, set to have a binary bit group "00".

[0133] Next, since the second chip-kill signal CKILL-S2 in the second slice chip 102 is deactivated to a logic "low" level "L", the first slice ID SID1<1:0>, configured with binary bit group "01", is counted up by one bit to generate a second slice ID SID2<1:0> configured with binary bit group "10". Additionally, in the second slice chip 102, the first slice ID SID1<1:0> configured with binary bit group "01" is inverted by the second inverted signal INV2<1:0> configured with binary bit group "11" to generate a second corrected slice ID CSID2<1:0> configured with binary bit group "10". The third slice chip 103 can stop operating based on the second corrected slice ID CSID2<1:0> configured with binary bit group "10".

[0134] Next, since the third chip-kill signal CKILL-S3 in the third chip chip 103 is activated to a logic "high" level "H", a third chip ID SID3<1:0> with the same binary bit group "10" as the second chip ID SID2<1:0> is generated. Furthermore, a third corrected chip ID CSID3<1:0> with binary bit group "11" is generated, regardless of the third inverted signal INV3<1:0> in the third chip chip 103. The third chip chip 103 can stop operating based on the third corrected chip ID CSID3<1:0> with binary bit group "11".

[0135] Next, since the fourth chip-kill signal CKILL-S4 in the fourth slice chip 104 is deactivated to a logic "low" level "L", the third slice ID SID3<1:0>, set to have a binary bit set of "10", is counted up by 1 bit to generate the fourth slice ID SID4<1:0>, set to have a binary bit set of "11". Furthermore, in the fourth slice chip 104, the third slice ID SID3<1:0>, set to have a binary bit set of "10", is inverted by the fourth inverted signal INV4<1:0>, set to have a binary bit set of "11", to generate the fourth corrected slice ID CSID4<1:0>, set to have a binary bit set of "01". The fourth slice chip 103 can continue operating based on the fourth corrected slice ID CSID4<1:0>, set to have a binary bit set of "01".

[0136] As described above, the storage device 10 is configured to operate only on the first shard chip 101 at the lowest level and the fourth shard chip 104 at the highest level based on the first to fourth corrected shard IDs CSID1<1:0>, CSID2<1:0>, CSID3<1:0> and CSID4<1:0> when the third shard chip 103 experiences a chip kill, thereby enabling the storage device 10 to maintain stable operation even after a chip kill.

[0137] See Figure 28 It describes the operation of generating the first to fourth corrected fragment IDs CSID1<1:0>, CSID2<1:0>, CSID3<1:0> and CSID4<1:0> respectively in the first fragment chip 101, the second fragment chip 102, the third fragment chip 103 and the fourth fragment chip 104 when the fourth fragment chip 104 performs a chip kill.

[0138] First, since the first chip-kill signal CKILL-S1 in the first slice chip 101 is deactivated to a logic "low" level "L", the pre-slice ID SIDP<1:0>, set to have a binary bit set of "00", is counted up by one bit to generate a first slice ID SID1<1:0> set to have a binary bit set of "01". Furthermore, in the first slice chip 101, a first corrected slice ID CSID1<1:0>, set to have a binary bit set of "00", is generated based on the first inverted signal INV1<1:0>, set to have a binary bit set of "00". The first slice chip 101 can continue operating based on the first corrected slice ID CSID1<1:0>, set to have a binary bit set of "00".

[0139] Next, since the second chip-kill signal CKILL-S2 in the second slice chip 102 is deactivated to a logic "low" level, the first slice ID SID1<1:0>, configured with binary bit group "01", is counted up by one bit to generate the second slice ID SID2<1:0>, configured with binary bit group "10". Additionally, in the second slice chip 102, the first slice ID SID1<1:0>, configured with binary bit group "01", is inverted by the second inverted signal INV2<1:0>, configured with binary bit group "11", to generate the second corrected slice ID CSID2<1:0>, configured with binary bit group "10". The third slice chip 103 can stop operating based on the second corrected slice ID CSID2<1:0>, configured with binary bit group "10".

[0140] Next, since the third chip-kill signal CKILL-S3 in the third slice chip 103 is deactivated to a logic "low" level "L", the second slice ID SID2<1:0>, which is set to have a binary bit set of "10", is counted up by one bit to generate the third slice ID SID3<1:0>, which is set to have a binary bit set of "11". Furthermore, in the third slice chip 103, the second slice ID SID2<1:0>, which is set to have a binary bit set of "10", is inverted by the third inverted signal INV3<1:0>, which is set to have a binary bit set of "11", to generate the third corrected slice ID CSID3<1:0>, which is set to have a binary bit set of "01". The third slice chip 103 can continue to operate based on the third corrected slice ID CSID3<1:0>, which is set to have a binary bit set of "01".

[0141] Next, since the fourth chip-kill signal CKILL-S4 in the fourth slice chip 104 is activated to a logic "high" level "H", a fourth slice ID SID4<1:0> with the same binary bit group "11" as the third slice ID SID3<1:0> is generated. Furthermore, in the fourth slice chip 104, regardless of the fourth inverting signal INV4<1:0>, a fourth corrected slice ID CSID4<1:0> with binary bit group "11" is generated. The fourth slice chip 104 can stop operating based on the fourth corrected slice ID CSID4<1:0> with binary bit group "11".

[0142] As described above, the storage device 10 is configured to operate only on the first shard chip 101 at the lowest level and the third shard chip 103 at the highest level where no chip-kill has occurred, based on the first to fourth corrected shard IDs CSID1<1:0>, CSID2<1:0>, CSID3<1:0> and CSID4<1:0>, thereby allowing the storage device 10 to maintain stable operation even after a chip-kill.

[0143] Figure 29 This is a block diagram illustrating a stacked storage system 3 according to an embodiment of the present disclosure. Figure 29 As shown, the stacked storage system 3 includes a first stacked storage device 3100, a second stacked storage device 3200, a processor 3300, an interposer layer 3400, and a substrate 3500.

[0144] An interposer layer 3400 is disposed on a substrate 3500, and a first stacked storage device 3100, a second stacked storage device 3200, and a processor 3300 are disposed on the interposer layer 3400. The processor 3300 is disposed between the first stacked storage device 3100 and the second stacked storage device 3200. The interposer layer 3400 is used to electrically connect the substrate 3500, the first stacked storage device 3100, the second stacked storage device 3200, and the processor 3300 to each other. Because the spacing between the first stacked storage device 3100, the second stacked storage device 3200, and the processor 3300 varies greatly, an interposer layer 3400 including various formed wirings can be used to electrically connect the first stacked storage device 3100, the second stacked storage device 3200, and the processor 3300 to each other.

[0145] Processor 3300 includes a first controller 3310 for controlling a first stacked storage device 3100 and a first processing interface circuit 3320 electrically connecting the first stacked storage device 3100 and the first controller 3310 to each other. Processor 3300 also includes a second controller 3330 for controlling a second stacked storage device 3200 and a second processing interface circuit 3340 electrically connecting the second stacked storage device 3200 and the second controller 3330 to each other. Processor 3300 provides signals including commands and addresses for controlling various internal operations of the first stacked storage device 3100 to the first stacked storage device 3100 via the first processing interface circuit 3320, and receives signals from the first stacked storage device 3100 via the first processing interface circuit 3320. Processor 3300 provides signals including commands and addresses for controlling various internal operations of the second stacked storage device 3200 to the second stacked storage device 3200 via the second processing interface circuit 3340, and receives signals from the second stacked storage device 3200 via the second processing interface circuit 3340.

[0146] The first stacked storage device 3100 includes a first base chip 3110 and first core chips 3120, 3130, 3140, and 3150. The first core chips 3120, 3130, 3140, and 3150 are sequentially stacked on top of the first base chip 3110 and receive various signals from the first base chip 3110 through vias. The first stacked storage device 3100 is configured to include four first core chips 3120, 3130, 3140, and 3150, but can be configured to include various numbers of core chips, such as four, eight, or sixteen core chips, depending on the embodiment. The first stacked storage device 3100 can be used as... Figure 1 The storage device 10 shown is used to implement this.

[0147] The first base chip 3110 includes a first core interface circuit 3111. The first core interface circuit 3111 is configured to communicate with the first processing interface circuit 3320 to receive signals sent from the processor 3300 and to apply signals generated from the first core chips 3120, 3130, 3140 and 3150 to the processor 3300.

[0148] The second stacked storage device 3200 includes a second base chip 3210 and second core chips 3220, 3230, 3240, and 3250. The second core chips 3220, 3230, 3240, and 3250 are sequentially stacked on top of the second base chip 3210 and receive various signals from the second base chip 3210 through vias. The second stacked storage device 3200 is configured to include four second core chips 3220, 3230, 3240, and 3250, but according to embodiments, it can be configured to include various numbers of core chips, such as four, eight, or sixteen core chips. The second stacked storage device 3200 can be used as follows: Figure 1 The storage device 10 shown is used to implement this.

[0149] The second base chip 3210 includes a second core interface circuit 3211. The second core interface circuit 3211 is configured to communicate with the second processing interface circuit 3330 to receive signals sent from the processor 3300 and to apply signals generated from the second core chips 3220, 3230, 3240 and 3250 to the processor 3300.

[0150] Figure 30 This is a block diagram illustrating a stacked storage system 4 according to another embodiment of the present disclosure. Figure 30 The stacked storage system 4 shown includes a first stacked storage device 4100, a second stacked storage device 4200, a system control device 4300, a substrate 4400, and a motherboard 4500.

[0151] A substrate 4400 is mounted on a motherboard 4500, and a system control device 4300 is mounted on the substrate 4400. A first stacked storage device 4100 and a second stacked storage device 4200 are mounted on the system control device 4300. The system control device 4300 includes a processor 4310, a first controller 4320, a first processing interface circuit 4330, a second controller 4340, and a second processing interface circuit 4350.

[0152] Processor 4310 is electrically connected to a first controller 4320 that controls various internal operations of the first stacked storage device 4100. Processor 4310 provides signals including commands and addresses for controlling various internal operations of the first stacked storage device 4100 to the first stacked storage device 4100 via a first processing interface circuit 4330, and receives signals from the first stacked storage device 4100 via the first processing interface circuit 4330. Processor 4310 is electrically connected to a second controller 4340 to control various internal operations of the second stacked storage device 4200. Processor 4310 provides signals including commands and addresses for controlling various internal operations of the second stacked storage device 4100 to the second stacked storage device 4200 via a second processing interface circuit 4350, and receives signals from the second stacked storage device 4200 via the second processing interface circuit 4350.

[0153] The first stacked storage device 4100 includes a first base chip 4110 and first core chips 4120, 4130, 4140, and 4150. The first core chips 4120, 4130, 4140, and 4150 are sequentially stacked on top of the first base chip 4110 and receive various signals from the first base chip 4110 through vias. The first stacked storage device 4100 is configured to include four first core chips 4120, 4130, 4140, and 4150, but can be configured to include various numbers of core chips, such as four, eight, or sixteen core chips, depending on the embodiment. The first stacked storage device 4100 can be used... Figure 1 The storage device 10 shown is used to implement this.

[0154] The first base chip 4110 includes a first core interface circuit 4111. The first core interface circuit 4111 is configured to communicate with the first processing interface circuit 4330 to receive signals sent from the processor 4310 and to apply signals generated from the first core chips 4120, 4130, 4140 and 4150 to the processor 4310.

[0155] The second stacked storage device 4200 includes second core chips 4210, 4230, 4230, and 4240. The second core chips 4210, 4230, 4230, and 4240 are sequentially stacked and receive various signals through vias. The second stacked storage device 4200 is configured to include four second core chips 4210, 4230, 4230, and 4240, but can be configured to include various numbers of stacked core chips, such as four, eight, or sixteen core chips, depending on the embodiment. The second stacked storage device 4200 can be formed by stacking core chips without a base chip. The second stacked storage device 4200 can be used as... Figure 1 The storage device 10 shown is used to implement this.

[0156] The second stacked storage device 4200 is configured to communicate with the second processing interface circuit 4350 to receive signals sent from the processor 4310 and to apply signals generated from the second core chips 4210, 4230, 4230 and 4240 to the processor 4310.

[0157] The concepts have been disclosed in conjunction with various examples and embodiments. Those skilled in the art will understand that various modifications, additions, and substitutions can be made without departing from the scope and technical concepts of this disclosure. The embodiments disclosed in this specification should be considered illustratively and not restrictively. The scope of this disclosure is not limited to the description, and all unique features within the equivalent scope should be interpreted as included in this disclosure. All variations within the equivalent meaning and scope of the claims are included within the scope of the claims.

Claims

1. A storage device, comprising: Multiple stacked chip shards, The multiple chip slicings are electrically connected to each other through multiple vias. Specifically, when one of the plurality of chip slices experiences a chip kill, the operation of the plurality of chip slices is determined by correcting the slice ID in each of the plurality of chip slices. Among the multiple chip shards that did not experience chip kill, the chip shard at the lowest layer and the chip shard at the highest layer are determined to be operated.

2. The storage device according to claim 1, wherein, The chip segment at the lowest layer includes: A fragment ID generation circuit that generates the fragment ID from a pre-fragment ID based on a chip-kill signal; and The shard ID calibration circuit generates a corrected shard ID from the pre-shard ID based on the lower shard signal.

3. The storage device according to claim 2, wherein, The chip-kill signal is deactivated in the chip segment at the lowest layer.

4. The storage device according to claim 2, wherein, The fragment ID generation circuit: Count the initialized pre-shard IDs to generate the shard IDs, and The fragment ID is transmitted through the via to the fragment chip stacked on top of the fragment chip at the lowest layer.

5. The storage device according to claim 2, wherein, The fragment ID calibration circuit receives the activated lower fragment ID to generate a pre-fragment ID configured to have the same group of binary bits as the pre-fragment ID.

6. The storage device according to claim 1, wherein, Each of the shard chips stacked on top of the shard chips at the lowest layer includes: A fragment ID generation circuit that generates a second fragment ID from a first fragment ID based on a chip-kill signal; and The slice ID calibration circuit generates a corrected slice ID from the first slice ID based on the chip-kill signal, the synthesized chip-kill signal, and the next slice signal.

7. The storage device according to claim 6, wherein, The fragment ID generation circuit: When the chip-kill signal is deactivated, the first fragment ID is counted to generate the second fragment ID, and When the chip-kill signal is activated, a second slice ID is generated, which is configured to have the same group of binary bits as the first slice ID.

8. The storage device according to claim 7, in, The fragment ID generation circuit is included in the first fragment chip. The second chip is stacked on top of the first chip, and The shard ID generation circuit transmits the second shard ID to the shard chip stacked on top of the first shard chip through the via.

9. The storage device according to claim 6, wherein, The shard ID calibration circuit receives the synthetic chip-kill signal that is activated when one of the shard chips experiences a chip-kill.

10. The storage device according to claim 6, wherein, When the chip-kill signal is activated and the synthetic chip-kill signal is deactivated, the fragment ID calibration circuit generates a corrected fragment ID configured with a preset first binary bit group.

11. The storage device according to claim 10, wherein, When the synthetic chip-kill signal is activated and the chip-kill signal is deactivated, the fragment ID calibration circuit generates the corrected fragment ID configured to have a preset second binary bit group.

12. A storage device, comprising: First chip segment; The second chip is stacked on top of the first chip. The third chip is stacked on top of the second chip; as well as The fourth chip is stacked on top of the third chip. Specifically, when the second chip segment experiences a chip kill, the first and fourth chip segments operate, while the second and third chip segments cease operation.

13. The storage device according to claim 12, wherein, When the third chip kill occurs, the first and fourth chips operate, while the second and third chips stop operating.

14. The storage device according to claim 12, wherein, When the fourth chip segment experiences a chip kill, the first and third chip segments continue operating, while the second and fourth chip segments cease operation.

15. The storage device according to claim 12, wherein, The first slice chip includes: The fragment ID generation circuit generates fragment IDs from pre-fragment IDs based on the chip-kill signal; and The shard ID calibration circuit generates a corrected shard ID from the pre-shard ID based on the lower shard signal.

16. The storage device according to claim 15, wherein, The chip-kill signal is deactivated in the first chip segment.

17. The storage device according to claim 15, wherein, The fragment ID generation circuit: Count the initialized pre-shard IDs to generate the shard IDs, and The fragment ID is transmitted to the fragment chip stacked on top of the first fragment chip via a via.

18. The storage device according to claim 15, wherein, The fragment ID calibration circuit receives the activated lower fragment ID to generate the pre-fragment ID, which is set to have the same group of binary bits as the pre-fragment ID.

19. The storage device according to claim 12, wherein, Each of the second, third, and fourth shard chips includes: A fragment ID generation circuit that generates a second fragment ID from a first fragment ID based on a chip-kill signal; and The slice ID calibration circuit generates a corrected slice ID from the first slice ID based on the chip-kill signal, the synthesized chip-kill signal, and the next slice signal.

20. The storage device according to claim 19, wherein, The fragment ID generation circuit: When the chip-kill signal is deactivated, the first fragment ID is counted to generate the second fragment ID, and When the chip-kill signal is activated, a second slice ID is generated, which is configured to have the same group of binary bits as the first slice ID.

21. The storage device according to claim 19, wherein, When the chip-kill signal is activated and the synthetic chip-kill signal is deactivated, the fragment ID calibration circuit generates a corrected fragment ID configured with a preset first binary bit group.

22. The storage device according to claim 19, wherein, When the synthetic chip-kill signal is activated and the chip-kill signal is deactivated, the fragment ID calibration circuit generates the corrected fragment ID configured to have a preset second binary bit group.

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