A host computer-based LPDDR chip testing system and method

Abstract

This application discloses a host computer-based LPDDR chip testing system and method, relating to the field of chip testing technology. The system includes: a host computer, a switch, multiple SLT test units, and multiple LPDDR chips under test. The host computer is connected to the switch and is used to send test commands to the multiple SLT test units and receive test result information. The switch is connected to the host computer and the multiple SLT test units for TCP / IP communication. The multiple LPDDR chips under test are installed in the multiple SLT test units, which are used to test the LPDDR chips installed on the SLT test units according to the test commands and send the test result information to the host computer through the switch. This solves the problems of low testing efficiency, poor test consistency, low resource utilization, and lack of intelligent scheduling mechanism in traditional LPDDR testing.

Description

Technical Field

[0001] This application relates to the field of chip testing technology, and more specifically, to an LPDDR chip testing system and method based on a host computer. Background Technology

[0002] With the increasing demand for high-performance, low-power memory in mobile devices, LPDDR, as the mainstream memory standard, is widely used in terminal devices such as smartphones and tablets. In order to ensure the stability of LPDDR during application, it is usually necessary to perform SLT (System Level Test) on LPDDR chips during the production process to verify their electrical performance and stability.

[0003] Traditional LPDDR testing typically employs manual frequency switching or fixed-frequency automated testing systems. However, manual frequency switching suffers from low efficiency (requiring manual intervention or configuration changes for different frequency levels, hindering batch parallel testing) and poor consistency (human error can lead to inconsistent test conditions, affecting the accuracy of yield assessment). While fixed-frequency automated testing systems can improve efficiency, they often only support a single frequency or require pre-set fixed test sequences, failing to dynamically adjust test parameters based on the actual capabilities of the tested chips. This results in low resource utilization (the same hardware platform cannot dynamically adapt to the testing needs of different LPDDR frequencies, leading to idle testing equipment) and a lack of intelligent scheduling mechanisms (the absence of a unified management and task allocation strategy results in complex testing processes and high error rates).

[0004] There is currently no effective solution to at least one of the aforementioned problems in existing LPDDR testing methods. Summary of the Invention

[0005] The main purpose of this application is to provide a host computer-based LPDDR chip testing system and method to solve the problems of low testing efficiency, poor testing consistency, low resource utilization and lack of intelligent scheduling mechanism in traditional LPDDR testing.

[0006] To achieve the above objectives, according to one aspect of the embodiments of this application, an LPDDR chip testing system based on a host computer is proposed, comprising: a host computer, a switch, multiple SLT test units, and multiple LPDDR chips under test; wherein, the host computer is connected to the switch and is used to send test commands to the multiple SLT test units and receive test result information through the switch; the switch is connected to the host computer and the multiple SLT test units to implement TCP / IP communication; the multiple LPDDR chips under test are installed in the multiple SLT test units, and the multiple SLT test units are used to test the LPDDR chips under test installed in the SLT test units according to the test commands, and send the test result information to the host computer through the switch.

[0007] Optionally, each of the above SLT test units includes multiple SLT boards, which correspond to multiple initial particle grades of the LPDDR particles under test. The LPDDR particles under test are installed on the SLT boards, and the SLT boards are used to perform multi-stage testing on the LPDDR particles under test installed on the SLT boards.

[0008] Optionally, the above multi-stage test includes: preload test, used to test the voltage and current of the LPDDR chip under test at the target test frequency; performance test, used to test the stability and electrical characteristics of the LPDDR chip under test at the target test frequency; and stress test, used to test the performance of the LPDDR chip under test at the target test frequency.

[0009] Optionally, the SLT test unit further includes: a support fixture for providing stable support and precise positioning for multiple components within the SLT test unit; and a power board, mounted on the support fixture with multiple screws for distributing power to multiple components within the SLT test unit. The power board includes multiple pins, and each SLT board includes multiple sockets. Each SLT board is mounted on the power board through multiple sockets and multiple pins.

[0010] Optionally, the SLT test unit further includes: multiple pressure heads, each pressure head corresponding to one LPDDR chip under test, the pressure heads being used to fix the LPDDR chip under test onto the SLT board; a power adapter for powering the SLT test unit; and multiple LEDs, each LED corresponding to one SLT board, the LEDs being used to test the contact status of the SLT board after the power adapter powers the SLT test unit.

[0011] Optionally, the aforementioned LPDDR particle testing system also includes a test control unit deployed on a host computer. The test control unit includes a particle information acquisition module, an intelligent frequency division decision module, and a test task scheduling module. The particle information acquisition module is used to collect particle information and testing requirements of multiple LPDDR particles to be tested. The intelligent frequency division decision module is used to determine testing rules for LPDDR particles of different particle grades to be tested based on particle information and testing requirements. The test task scheduling module is used to generate test instructions corresponding to the testing rules and send the test instructions to multiple SLT test units through a switch.

[0012] According to another aspect of the embodiments of this application, a host computer-based LPDDR chip testing method is also provided, comprising: acquiring test unit information of multiple SLT test units, chip information of multiple LPDDR chips to be tested, and test requirements, wherein the test unit information includes connection status information of each SLT test unit and board information of multiple SLT boards installed in the SLT test unit; using the host computer to determine the target detection rules for each LPDDR chip to be tested based on the multiple chip information, multiple test unit information, and test requirements, generating multiple detection instructions based on the multiple target detection rules, and sending the multiple detection instructions to the target SLT board corresponding to the detection instructions based on the multiple test unit information; using the multiple SLT boards to perform multi-stage tests on the multiple LPDDR chips to be tested according to the multiple detection instructions, obtaining test result information, and sending the test result information to the host computer; and using the host computer to determine whether each LPDDR chip to be tested passes the target chip level test based on the test result information.

[0013] According to another aspect of the embodiments of this application, a host computer-based LPDDR chip testing device is also provided, comprising: an information acquisition unit, used to acquire test unit information of multiple SLT test units, chip information of multiple LPDDR chips to be tested, and test requirements, wherein the test unit information includes connection status information of each SLT test unit and board information of multiple SLT boards installed in the SLT test unit; a detection instruction generation unit, used to use the host computer to determine the target detection rules for each LPDDR chip to be tested according to the multiple chip information, multiple test unit information, and test requirements, generate multiple detection instructions according to the multiple target detection rules, and send the multiple detection instructions to the target SLT board corresponding to the detection instructions according to the multiple test unit information; a multi-stage testing unit, used to use multiple SLT boards to perform multi-stage tests on multiple LPDDR chips to be tested according to the multiple detection instructions, obtain test result information, and send the test result information to the host computer; and a result determination unit, used to use the host computer to determine whether each LPDDR chip to be tested passes the target chip level test based on the test result information.

[0014] Optionally, the aforementioned detection instruction generation unit includes: a primary particle level determination subunit, used to determine the initial particle level of each LPDDR particle to be tested based on particle information and test requirements; a target particle level determination subunit, used to determine the target particle level corresponding to each LPDDR particle to be tested based on multiple test unit information; and a target detection rule acquisition subunit, used to acquire the target detection rules corresponding to the multiple target particle levels from multiple reference detection rules.

[0015] Optionally, the multi-stage testing unit includes: a first test frequency determination subunit, used to determine any one of the multiple test instructions as the current test instruction, determine the LPDDR chip under test corresponding to the current test instruction as the target chip, and determine the highest test frequency among the test instructions as the first test frequency; a reference test result acquisition subunit, used to perform preload testing, performance testing, and stress testing on the target chip according to the first test frequency, and obtain reference test result information corresponding to the first test frequency; and a result information determination subunit, used to determine test result information according to the reference test result information and the test instructions.

[0016] Optionally, the above-mentioned result information determination subunit includes: an information determination subunit, used to determine the reference test result information as test result information when the reference test result information indicates that the test has passed; a frequency confirmation subunit, used to determine whether a second test frequency exists, wherein the second test frequency is lower than the first test frequency, according to the test instruction when the reference test result information indicates that the test has failed; a first determination subunit, used to determine the reference test result information as test result information when the test instruction indicates that there is no second test frequency; and a second determination subunit, used to determine the second test frequency as the first test frequency when the test instruction indicates that there is a second test frequency.

[0017] According to another aspect of the embodiments of this application, a computer-readable storage medium is provided, which stores computer instructions for causing a computer to perform the above-described host computer-based LPDDR chip testing method.

[0018] According to another aspect of the embodiments of this application, an electronic device is also provided, the electronic device including: at least one processor, and a memory communicatively connected to the at least one processor; wherein, the memory stores a computer program executable by the at least one processor, the computer program being executed by the at least one processor to cause the at least one processor to perform the above-described host computer-based LPDDR particle testing method.

[0019] The technical solutions provided by the embodiments of this application may include the following beneficial effects:

[0020] In this application, the above-mentioned host computer-based LPDDR chip testing system and method solve the problems of low testing efficiency, poor testing consistency, low resource utilization, and lack of intelligent scheduling mechanism in traditional LPDDR testing. Attached Figure Description

[0021] The accompanying drawings, which form part of this application, are used to provide a further understanding of the application and to make other features, objects, and advantages of the application more apparent. The illustrative embodiments and descriptions of this application are used to explain the application and do not constitute an undue limitation of the application. In the drawings: Figure 1 A structural diagram of an optional host computer-based LPDDR chip testing system provided for this application; Figure 2 A hardware side view of an optional host computer-based LPDDR chip testing system provided for this application; Figure 3 A top-down view of another optional host computer-based LPDDR chip testing system provided for this application; Figure 4 A flowchart of another optional host computer-based LPDDR chip testing method provided in this application; Figure 5 A schematic diagram of an optional host computer-based LPDDR chip testing device provided for this application; Figure 6 A schematic diagram of an optional electronic device provided in this application.

[0022] ( Figure 2 , Figure 3 In the middle, 1-SLT board; 2-Support fixture; 3-Power board; 4-Pin; 5-Pressure head; 6-LED light; 7-LPDDR chip under test) Detailed Implementation To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0023] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus. Without conflict, the embodiments and features in the embodiments of this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0024] To address the issues of low testing efficiency, poor test consistency, low resource utilization, and lack of intelligent scheduling mechanisms in traditional host computer-based LPDDR (Low Power Double Data Rate) chip testing, this application provides a host computer-based LPDDR chip testing system and method (Note: LPDDR is a low-power memory standard designed for mobile devices and embedded systems, developed by JEDEC (Solid State Technology Association). It significantly reduces operating voltage and power consumption while maintaining a high data transfer rate, making it suitable for scenarios sensitive to battery life).

[0025] As an alternative implementation method, please refer to Figure 1 This document illustrates a structural diagram of a host computer-based LPDDR chip testing system according to an embodiment of this application. The system includes: a host computer, a switch, multiple SLT test units, and multiple LPDDR chips to be tested. 1. The host computer connects to the switch and is used to send test commands to multiple SLT test units and receive test result information through the switch; 2. The switch connects to the host computer and multiple SLT test units to implement TCP / IP communication; 3. Multiple LPDDR chips under test are installed in multiple SLT test units. The multiple SLT test units are used to test the LPDDR chips under test installed in the SLT test units according to the test instructions, and send the test result information to the host computer through the switch.

[0026] The aforementioned host computer is equipped with test control software, which performs functions including sending test commands, receiving test results, and executing intelligent frequency division logic.

[0027] In the aforementioned SLT test unit, SLT (Sort Line Test) refers to the functional and performance verification of each chip after packaging to determine its qualification and applicable frequency level. In the multiple LPDDR SLT test units mentioned above, each LPDDR SLT test unit contains an independent test circuit board, supports LPDDR signal driving and response detection, and each test circuit board can connect to multiple LPDDR chips and can receive test commands from the host computer through a network interface.

[0028] The aforementioned LPDDR chips include Low-Power Double Data Rate Synchronous Dynamic Random Access Memory (Low-Power Double Data Rate SDRAM) chips, which are typically in chip form. The chip types supported by the aforementioned LPDDR chips include LPDDR3, LPDDR4, and LPDDR5.

[0029] With the structure of the above-described host computer-based LPDDR chip testing system, the system can uniformly manage and schedule multiple SLT test units through the host computer. The system integrates an intelligent frequency division algorithm, which can automatically plan the optimal test path based on LPDDR chips with different nominal frequencies (such as 4266, 3733, and 3200MT / s), thereby achieving efficient and accurate automated testing. In addition, the system supports networked deployment and parallel operation of multiple devices, which significantly improves testing efficiency and result consistency, and is suitable for the SLT testing stage in large-scale chip production.

[0030] The above-described embodiments of this application solve the problems of low testing efficiency, poor testing consistency, low resource utilization, and lack of intelligent scheduling mechanism in traditional LPDDR testing.

[0031] As an optional implementation, each of the above SLT test units includes multiple SLT boards, which correspond to multiple initial particle grades of the LPDDR particles to be tested. The LPDDR particles to be tested are installed on the SLT boards, and the SLT boards are used to perform multi-stage testing on the LPDDR particles to be tested installed on the SLT boards.

[0032] The aforementioned SLT board is the core hardware carrier in System Level Testing (SLT), primarily used for: 1. Mounting and Installation: Physically mounting and connecting the LPDDR chip under test. 2. Test Interface: Providing electrical connections and signal channels, enabling the test unit to apply test signals, supply power, and read the response from the LPDDR chip under test. 3. Test Execution: As the specific execution level of test commands, it performs multi-stage testing on the LPDDR chip under test mounted on the SLT board.

[0033] The SLT board in this application corresponds to the initial chip grade of the LPDDR chip under test. If a new type of LPDDR chip with a higher grade than the current highest grade appears in the future, the test system can be made compatible with future products by replacing the existing SLT board with a board that supports the new higher grade.

[0034] The aforementioned initial particle level refers to the pre-classification or grouping of the LPDDR particles under test based on preliminary, basic test parameters (such as basic speed range, voltage standard, or early screening results). This allows the test system to install the LPDDR particles under test onto the corresponding boards based on their initial particle level, providing a more targeted and efficient starting point for subsequent "multi-stage testing".

[0035] The above-mentioned installation method for LPDDR chips under test, by equipping them with dedicated SLT boards for different initial chip grades, enables categorized and multi-stage parallel testing within a single test unit. This improves the overall efficiency and management precision of the test system. The correspondence between the SLT boards and the initial chip grades of the LPDDR chips under test effectively extends the technical lifecycle of the entire test platform, avoiding the overall obsolescence of equipment due to technological iterations.

[0036] As an optional implementation, the above multi-stage test includes: Phase 1: Preload test, used to test the voltage and current of the LPDDR chip under test at the target test frequency; Phase 2: Performance testing, used to test the stability and electrical characteristics of the LPDDR chip under test at the target test frequency; Phase 3: Stress test, used to test the performance of the LPDDR chip under test at the target test frequency.

[0037] In Phase 1 above, the purpose of this phase is to verify the basic electrical and key timing parameters of the LPDDR chip under test. The test content includes not only the operating voltage and current at the target test frequency, but also the detection of whether the core timing parameters (such as TRCD, TRP, TRAS, TWR and other timing parameters) are within the normal range.

[0038] In stage 2 above, read and write operations are performed on the particle at the target test frequency to comprehensively evaluate its function and performance. The test objectives include systematically detecting whether the particle under test has defects in terms of functional correctness, operational stability, timing compliance, and electrical characteristics.

[0039] In stage 3 above, this stage can simulate high-load real-world application scenarios to evaluate the performance of the chip under extreme conditions, such as simulating the working state and performance of the LPDDR chip under test in an operating system (OS) environment when the memory capacity utilization is high.

[0040] As an optional implementation, the SLT test unit described above further includes: Support fixtures are used to provide stable support and precise positioning for multiple components within the SLT test unit; The power board, mounted on a support fixture with multiple screws, is used to distribute power to multiple components within the SLT test unit. The power board includes multiple pins, and each SLT board includes multiple sockets. Each SLT board is mounted on the power board via multiple sockets and multiple pins.

[0041] The aforementioned support fixture is a base used for mechanical fixation and positioning. Its core functions include providing rigid and stable physical support for all components within the SLT test unit, such as the power board and SLT circuit board, and ensuring precise relative positioning between the components. The aforementioned pins are standardized metal conductive connection terminals on the power board. Their core function is to mate with the sockets on the SLT circuit board to form a quick-plug electrical connection interface.

[0042] The aforementioned support fixtures and power boards work together to form a stable, reliable, and easy-to-maintain modular hardware platform in the SLT test unit.

[0043] As an optional implementation, the SLT test unit described above further includes: Multiple pressure heads, each corresponding to one LPDDR chip to be tested, are used to fix the LPDDR chip to be tested onto the SLT board; Power adapter for powering the SLT test unit; Multiple LEDs, each corresponding to an SLT board, are used to test the contact status of the SLT board after the power adapter powers the SLT test unit.

[0044] The aforementioned pressure head and LED lights ensure reliable contact between internal components, while the aforementioned power adapter ensures a stable, clean, and compliant power input during testing, avoiding the risk of interference or fluctuations caused by shared power.

[0045] For example, combined Figure 2 , Figure 3 As shown, in the specific implementation process, the overall installation process of the above-mentioned LPDDR chip testing system based on the host computer includes: 1. Place the power board 3 onto the support fixture 2 (it can be fixed at the edge or other positions by screws or other means); 2. Insert the SLT board 1 into the corresponding pins 4 on the power board 3. Figure 3 Taking four SLT boards 1 as an example, when inserting the SLT boards 1, it is important to ensure that the sockets of each SLT board 1 are aligned with the pins of the power board 3. 3. Place the LPDDR chip to be tested (7) onto the SLT board 1, and clamp and tighten it using the clamping head 5. Note the following when placing the LPDDR chip to be tested: 1) The LPDDR chip 7 under test is aligned with the corresponding position on the SLT board 1; 2) When installing the pressure head 5, the two protruding steel columns under the pressure head 5 should be inserted into the round holes on the test plate accordingly; 3) When installing the pressure head 5, after clamping the SLT board 1, tighten the pressure head 5 clockwise to ensure good contact between the LPDDR chip 7 to be tested and the SLT board 1.

[0046] Note: If there is poor contact, the purple LED 6 on the test board will not light up after the test starts, and the test result feedback will be 08, indicating that the test has failed. If all four LPDDR chips under test are in a normal contact state, the purple LED 6 will light up to indicate that the contact is good. 4. Plug in the network cable and power adapter.

[0047] It should be noted that during the test, the system's communication path includes: LPDDR chip under test 7 - parallel bus - SLT board 1 - parallel bus - power board 3 - serial port (to Ethernet) - host computer.

[0048] As an optional implementation, the above-mentioned LPDDR particle testing system also includes a test control unit deployed on a host computer. The test control unit includes a particle information acquisition module, an intelligent frequency division decision module, and a test task scheduling module. The particle information acquisition module is used to collect particle information and testing requirements of multiple LPDDR particles to be tested. The intelligent frequency division decision module is used to determine testing rules for LPDDR particles of different particle grades to be tested based on particle information and testing requirements. The test task scheduling module is used to generate test instructions corresponding to the testing rules and send the test instructions to multiple SLT test units through a switch.

[0049] The above-mentioned particle information includes relevant data of the LPDDR particle under test itself, such as basic attributes such as model, nominal frequency, capacity, and production batch; the testing requirements include the specific requirements and objectives for testing the LPDDR particle under test, such as the speed range to be tested (e.g., 4266MT / s), the scope of test items, and the severity level of the test; the testing rules include the specific test basis and procedures dynamically generated by the system.

[0050] The aforementioned test control unit, through its particle information acquisition module, intelligent frequency division decision module, and test task scheduling module, can centrally manage particle data, dynamically formulate test strategies, and accurately schedule tasks, achieving a high degree of intelligence and standardization in the test process and significantly improving the efficiency, accuracy, and consistency of large-scale testing.

[0051] The effects achieved by the above-described host computer-based LPDDR chip testing system of this application include: 1. Intelligent frequency division decision mechanism: Based on the nominal specifications of the particles and their actual performance, the optimal test path is automatically generated to reduce invalid test time; 2. Multi-device collaborative scheduling: The host computer manages multiple SLT devices in a unified manner, enabling parallel processing of tasks and improving overall throughput; 3. Dynamic frequency adaptation: Supports seamless switching between three typical frequencies: 4266 / 3733 / 3200, without manual intervention; 4. Closed-loop feedback control: Test results feed back into the frequency division strategy, gradually optimizing subsequent test processes; 5. Networked architecture design: Remote control is achieved based on the TCP / IP protocol, which is easy to integrate into the production line MES system.

[0052] According to another aspect of the present invention, a host computer-based LPDDR chip testing method is also provided for the above-described host computer-based LPDDR chip testing system, such as... Figure 4 As shown, the host computer-based LPDDR chip testing method includes: S402, acquiring test unit information of multiple SLT test units, chip information of multiple LPDDR chips to be tested, and test requirements. The test unit information includes the connection status information of each SLT test unit and the board information of multiple SLT boards installed in the SLT test unit; S404, using the host computer to determine the target detection rules for each LPDDR chip to be tested based on the multiple chip information, multiple test unit information, and test requirements, generating multiple detection commands based on the multiple target detection rules, and sending the multiple detection commands to the target SLT board corresponding to the detection commands based on the multiple test unit information; S406, using multiple SLT boards to perform multi-stage tests on multiple LPDDR chips to be tested according to the multiple detection commands, obtaining test result information, and sending the test result information to the host computer; S408, using the host computer to determine whether each LPDDR chip to be tested passes the target chip level test based on the test result information.

[0053] It should be noted that the above-mentioned host computer-based LPDDR chip testing method can be deployed on the host computer of the host computer-based LPDDR chip testing system.

[0054] The aforementioned board information includes the hardware attributes and configuration parameters of each SLT board installed inside the SLT test unit. This information forms the basis for task scheduling by the host computer and ensures that test commands can be sent to the appropriate hardware. The test unit information includes the overall status report of the SLT test unit, including whether its connection with the host computer is normal, and a summary of information on all SLT boards installed inside it. The test result information includes the raw data and result reports generated by the SLT board after receiving commands from the host computer and performing multi-stage tests on the LPDDR chip under test. This information can be used as a basis for judging the chip quality. The target chip grade includes predefined performance and quality standards for judging whether the LPDDR chip is qualified. The host computer will compare the "test result information" with these standards to make a "pass" or "fail" judgment.

[0055] The above-mentioned S402 to S408 achieve a fully automated and standardized LPDDR particle testing process by centrally acquiring information, intelligently formulating rules, scheduling instructions, and analyzing results through a host computer. This significantly improves the efficiency and accuracy of multi-particle parallel testing, while ensuring the consistency and manageability of the testing process and reducing manual operation costs and errors.

[0056] Optionally, the above-mentioned method of using a host computer to determine the target detection rules for each LPDDR chip under test based on multiple chip information, multiple test unit information, and test requirements includes: S1, determine the initial particle level of each LPDDR particle to be tested based on particle information and testing requirements; S2, determine the target particle level corresponding to each LPDDR particle to be tested based on multiple test unit information; S3, obtain the target detection rules corresponding to multiple target particle levels from multiple reference detection rules.

[0057] The above-mentioned S1 provides a clear starting point for classifying the LPDDR chips to be tested by determining the initial chip level; the above-mentioned S2 determines the target chip level to ensure the best match between the test task and hardware resources; the above-mentioned S3 generates a customized test plan for each LPDDR chip to be tested through target detection rules. The above-mentioned S1-S3 can dynamically generate the most suitable detection rules according to the individual differences of the chips to be tested and the real-time status of the test system, thereby greatly improving the targeting and accuracy of the test and optimizing resource utilization.

[0058] Optionally, the above-mentioned method utilizes multiple SLT boards to perform multi-stage tests on multiple LPDDR chips under test according to multiple detection commands, obtaining test result information, including: S1, determine any one of the multiple detection commands as the current detection command, determine the LPDDR chip to be tested corresponding to the current detection command as the target chip, and determine the highest test frequency in the test command as the first test frequency; S2, perform pre-loading test, performance test and stress test on the target particle according to the first test frequency, and obtain reference test result information corresponding to the first test frequency; S3 determines the test result information based on the reference test result information and the test instructions.

[0059] The aforementioned maximum test frequency includes the highest preset speed level in the test scheme required by the current detection command, and belongs to the frequency point used to verify the closest to the nominal performance limit of the LPDDR chip under test. The above S1-S3 form an intelligent test path that judges based on the test results at the highest test frequency, quickly screening out unqualified chips that cannot work stably at the nominal limit, thereby saving test time and resources.

[0060] Optionally, the above-mentioned determination of test result information based on reference test result information and test instructions includes: S3-1, If ​​the reference test result information indicates that the test has passed, the reference test result information shall be determined as the test result information; S3-2, if the reference test result information indicates that the test has failed, determine whether there is a second test frequency according to the test instruction, and the second test frequency is lower than the first test frequency; S3-3, if the test instruction indicates that there is no second test frequency, the reference test result information shall be determined as the test result information; S3-4, if the test instruction indicates the existence of a second test frequency, the second test frequency is determined as the first test frequency.

[0061] The aforementioned second test frequency can be understood as a lower and more conservative test frequency level relative to the first test frequency (for example, when the first test frequency is 4266MT / s, the second test frequency may be 3733MT / s), which is used to provide LPDDR chips that fail the test with an opportunity to "downgrade and retry".

[0062] The above S3-1 to S3-4 implement a stepped performance verification mechanism. After the LPDDR chip fails the high-frequency test, the system can automatically judge and switch to a lower preset frequency for retesting, thereby optimizing the efficiency of the test process and the overall yield of the chip while ensuring basic quality.

[0063] It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and although a logical order is shown in the flowchart, in some cases the steps shown or described may be executed in a different order than that shown here.

[0064] The following is an example of the LPDDR chip testing method based on a host computer provided in this application: A manufacturer purchased a batch of LPDDR4 chips with nominal frequencies of 4266MT / s and 3733MT / s, respectively.

[0065] 1. After the host computer starts up, it finds three SLT devices online, numbered SLT-A, SLT-B and SLT-C respectively; 2. The operator inserts a 4266MT / s particle into SLT-A; 3. After receiving the particle information, the host computer triggers the intelligent frequency division process and first issues a 4266MT / s test task; 4. If the test fails, the host computer will automatically reduce the frequency to 3733MT / s and send the data to SLT-A to continue the test. 5. Successfully passed, the particle is marked as "3733MT / s qualified product"; 6. Meanwhile, another 3733MT / s particle was inserted into SLT-B and the 3733 test was performed directly, which passed successfully; 7. At the same time, another 3733MT / s particle was inserted into SLT-C and the 3733 test was performed directly, but the test failed; 8. If the test fails, the host computer will automatically reduce the frequency to 3200MT / s and send the data to the SLT-C to continue the test. 9. If the test fails, mark the particle as "non-conforming". 10. After the test, the system generated a report showing that a total of 3 samples were tested, with a yield rate of 66.67%. Two samples were rated as "qualified products with a yield rate of 3733MT / s" and one was rated as "unqualified product". The average test time was 120 seconds.

[0066] The effects achieved by the host computer-based LPDDR chip testing system and method provided in this application include: 1. Significantly improves testing efficiency and shortens production cycle: Traditional SLT testing requires manual frequency switching or batch processing of particles of different frequency levels. However, this invention automatically identifies the nominal frequency of the particles and dynamically generates test paths (e.g., 4266→3733→3200MT / s) through a host computer, achieving "one-time loading, multi-frequency verification"; it supports parallel scheduling of multiple SLT devices, automatic task allocation, and separates the test tasks of each SLT device, avoiding equipment idleness or bottlenecks, and improving the overall test throughput by 30%~50%; it intelligently skips inapplicable frequencies (e.g., 3200 particles are not tested on 4266), reducing invalid test time and reducing the average test time per particle by more than 20%.

[0067] 2. Improved testing accuracy and yield assessment precision: ZQ-Long-Calibration (a key impedance matching and drive strength calibration mechanism in LPDDR series memory, used to ensure signal integrity, reduce power consumption, and improve system stability) is automatically triggered after each frequency switch to ensure that the drive impedance and termination match the signal integrity requirements of the current frequency, avoiding misjudgments caused by impedance mismatch; a "high-then-low" step-down frequency reduction strategy is adopted to truly reflect the highest stable operating frequency of the chip and accurately classify performance levels (e.g., "4266 qualified", "3733 only qualified", "unqualified"); all test parameters are uniformly configured by software to eliminate human operation differences, and the test consistency reaches over 99.9%.

[0068] 3. Reduced testing costs and hardware dependence: The same SLT hardware platform is compatible with LPDDR chips of various frequency levels, eliminating the need for dedicated test fixtures or firmware for different frequencies; centralized management by the host computer reduces the number of on-site operators, thereby reducing labor costs and training complexity.

[0069] 4. Enhanced system flexibility and scalability: Based on TCP / IP network architecture, it supports remote monitoring, batch task import, and cloud synchronization of test data, making it easy to integrate into intelligent manufacturing systems such as MES / ERP; the intelligent frequency division algorithm can be connected to AI models (such as predicting the optimal test path based on historical data), and has the potential for continuous optimization.

[0070] 5. Promoting the evolution of SLT testing towards intelligence and automation: For the first time, the "frequency sensing + dynamic calibration + closed-loop feedback" mechanism is introduced into the LPDDRSLT process, filling the technological gap in the field of automated graded testing of high-frequency low-power memory in the industry; providing reliable screening assurance for application scenarios that are sensitive to memory performance, such as high-end mobile SoCs and AIoT chips; and meeting the core requirements of Industry 4.0 for semiconductor testing of "high efficiency, high precision, and traceability".

[0071] According to another aspect of the present invention, an apparatus for applying the above-described host computer-based LPDDR chip testing method is also provided, such as... Figure 5 As shown, the device includes: an information acquisition unit 502, used to acquire test unit information of multiple SLT test units, particle information of multiple LPDDR particles to be tested, and test requirements. The test unit information includes connection status information of each SLT test unit and board information of multiple SLT boards installed in the SLT test unit; a detection instruction generation unit 504, used to use a host computer to determine the target detection rules for each LPDDR particle to be tested based on the multiple particle information, multiple test unit information, and test requirements, generate multiple detection instructions based on the multiple target detection rules, and send the multiple detection instructions to the target SLT board corresponding to the detection instructions based on the multiple test unit information; a multi-stage testing unit 506, used to use multiple SLT boards to perform multi-stage tests on multiple LPDDR particles to be tested according to the multiple detection instructions, obtain test result information, and send the test result information to the host computer; and a result determination unit 508, used by the host computer to determine whether each LPDDR particle to be tested passes the target particle level test based on the test result information.

[0072] The specific methods of execution of each unit in the above device embodiments have been described in detail in the embodiments related to the method, and will not be elaborated further here.

[0073] According to another aspect of the present invention, an electronic device for implementing a host computer-based LPDDR chip testing method is also provided. This electronic device may be as follows: Figure 6 The terminal device or server (host computer) shown. This embodiment uses the electronic device as an example for illustration, such as... Figure 6 As shown, the electronic device includes: at least one processor 604; and a memory 602 communicatively connected to the at least one processor 604; wherein the memory 602 stores a computer program executable by the at least one processor 604, the computer program being executed by the at least one processor 604 to cause the at least one processor 604 to perform the steps in any of the above method embodiments. The electronic device may be located in at least one of a plurality of network devices in a computer network. The processor may be configured to execute a host computer-based LPDDR chip testing method via a computer program.

[0074] Alternatively, as those skilled in the art will understand, Figure 6The structure shown is for illustrative purposes only. The electronic device (host computer) can also be an industrial computer, a smartphone (such as an Android phone, an iOS phone, etc.), a tablet computer, a handheld computer, and a mobile internet device (MID), PAD, and other terminal devices. Figure 6 This does not limit the structure of the aforementioned electronic devices. For example, electronic devices may also include components that are more... Figure 6 The more or fewer components shown (such as network interfaces, etc.) or having the same Figure 6 The different configurations shown.

[0075] The memory 602 can be used to store software programs and modules, such as the program instructions / modules corresponding to the host computer-based LPDDR chip testing method in this embodiment of the invention. The processor 604 executes various functional applications and data processing by running the software programs and modules stored in the memory 602, thereby realizing the aforementioned host computer-based LPDDR chip testing method. The memory 602 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 602 may further include memory remotely located relative to the processor 604, and these remote memories can be connected to the terminal via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof. As an example, such as Figure 6 As shown, the memory 602 described above may include, but is not limited to, the information acquisition unit 502, the detection instruction generation unit 504, the multi-stage testing unit 506, and the result determination unit 508 found in the host computer-based LPDDR chip testing device. Furthermore, it may include, but is not limited to, other module units in the aforementioned host computer-based LPDDR chip testing device, which will not be elaborated upon in this example.

[0076] Optionally, the aforementioned transmission device 606 is used to receive or send data via a network. Specific examples of the network may include wired and wireless networks. In one example, the transmission device 606 includes a Network Interface Controller (NIC), which can be connected to other network devices and a router via a network cable to communicate with the Internet or a local area network. In another example, the transmission device 606 is a Radio Frequency (RF) module used for wireless communication with the Internet. Furthermore, the aforementioned electronic device also includes a display 608 and a connection bus 610 for connecting the various module components within the electronic device.

[0077] Obviously, those skilled in the art should understand that the various units or steps of this application described above can be implemented using general-purpose computing devices. They can be centralized on a single computing device or distributed across a network of multiple computing devices. Optionally, they can be implemented using computer-executable program code, thereby storing them in a storage device for execution by a computing device, or fabricating them separately as individual integrated circuit modules, or fabricating multiple modules or steps into a single integrated circuit module. Thus, this application is not limited to any particular combination of hardware and software.

[0078] The above are merely preferred embodiments of this application and are not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A host computer-based LPDDR chip testing system, characterized in that, include: The system includes a host computer, a switch, multiple SLT test units, and multiple LPDDR chips under test; among them, The host computer is connected to the switch and is used to send test commands to multiple SLT test units and receive test result information through the switch. The switch is connected to the host computer and multiple SLT test units to implement TCP / IP communication; Multiple LPDDR chips under test are installed in multiple SLT test units. The multiple SLT test units are used to test the LPDDR chips under test installed in the SLT test units according to the test instructions, and send the test result information to the host computer through the switch.

2. The system according to claim 1, characterized in that, Each SLT test unit includes multiple SLT boards, each SLT board corresponding to an initial particle level of multiple LPDDR particles under test. The LPDDR particles under test are mounted on the SLT boards, and the SLT boards are used to perform multi-stage testing on the LPDDR particles under test mounted on the SLT boards.

3. The system according to claim 2, characterized in that, Multi-stage testing includes: Preload test is used to test the voltage and current of the LPDDR chip under test at the target test frequency; Performance testing is used to test the stability and electrical characteristics of the LPDDR chip under test at the target test frequency; Stress testing is used to test the performance of the LPDDR chip under test at the target test frequency.

4. The system according to claim 3, characterized in that, The SLT test unit also includes: A support fixture is used to provide stable support and precise positioning for multiple components within the SLT test unit; The power board is mounted on the support fixture by multiple screws and is used to distribute power to multiple components in the SLT test unit. The power board includes multiple pins, and each SLT board includes multiple sockets. Each SLT board is mounted on the power board through multiple sockets and multiple pins.

5. The system according to claim 2, characterized in that, The SLT test unit also includes: Multiple pressure heads, each pressure head corresponding to one LPDDR chip to be tested, the pressure head being used to fix the LPDDR chip to be tested onto the SLT board; A power adapter for supplying power to the SLT test unit; Multiple LEDs, each corresponding to one SLT board, are used to test the contact status of the SLT board after the power adapter powers the SLT test unit.

6. The system according to claim 1, characterized in that, The LPDDR particle testing system further includes a test control unit deployed on the host computer. The test control unit includes a particle information acquisition module, an intelligent frequency division decision module, and a test task scheduling module. The particle information acquisition module is used to collect particle information and testing requirements of multiple LPDDR particles under test. The intelligent frequency division decision module is used to determine testing rules for LPDDR particles of different particle levels under test based on the particle information and the testing requirements. The test task scheduling module is used to generate test instructions corresponding to the testing rules and send the test instructions to multiple SLT test units through the switch.

7. A method for testing LPDDR chips based on a host computer, characterized in that, An LPDDR chip testing system based on a host computer, applicable to any one of claims 1 to 6, comprising: Acquire test unit information of multiple SLT test units, chip information of multiple LPDDR chips to be tested, and test requirements. The test unit information includes connection status information of each SLT test unit and board information of multiple SLT boards installed in the SLT test unit. The host computer determines the target detection rules for each LPDDR chip to be tested based on multiple chip information, multiple test unit information and the test requirements. It generates multiple detection instructions based on the multiple target detection rules and sends the multiple detection instructions to the target SLT board corresponding to the detection instructions based on the multiple test unit information. Multiple SLT boards are used to perform multi-stage tests on multiple LPDDR chips under test according to multiple detection commands, and test result information is obtained and sent to the host computer. The host computer uses the test results to determine whether each LPDDR chip under test has passed the target chip level test.

8. The method according to claim 7, characterized in that, The host computer determines the target detection rules for each LPDDR particle to be tested based on multiple particle information, multiple test unit information, and the test requirements, including: The initial particle level of each LPDDR particle to be tested is determined based on the particle information and the test requirements. The target particle level corresponding to each LPDDR particle under test is determined based on the information from multiple test units. Target detection rules corresponding to the multiple target particle levels are obtained from multiple reference detection rules.

9. The method according to claim 7, characterized in that, Using multiple SLT boards, multiple LPDDR chips under test are subjected to multi-stage testing according to multiple detection commands to obtain test result information, including: Any one of the multiple detection commands is determined as the current detection command, the LPDDR chip to be tested corresponding to the current detection command is determined as the target chip, and the highest test frequency in the test command is determined as the first test frequency. Based on the first test frequency, the target particle is subjected to pre-loading test, performance test and stress test to obtain reference test result information corresponding to the first test frequency; The test result information is determined based on the reference test result information and the test instructions.

10. The method according to claim 9, characterized in that, The test result information is determined based on the reference test result information and the test instruction, including: If the reference test result information indicates that the test has passed, the reference test result information shall be determined as the test result information; If the reference test result information indicates that the test has failed, it is determined whether there is a second test frequency, which is lower than the first test frequency, according to the test instruction. If the test instruction indicates that the second test frequency does not exist, the reference test result information shall be determined as the test result information; If the test instruction indicates the existence of the second test frequency, the second test frequency is determined as the first test frequency.

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