Heap memory analysis method and device, computer device, chip and chip module

Abstract

The application relates to a heap memory analysis method and device, computer equipment, a chip and a chip module. The method comprises the following steps: in response to a heap memory processing instruction for a to-be-analyzed heap memory, determining the array identifier of a preset array corresponding to the to-be-analyzed heap memory according to the heap memory address corresponding to the heap memory processing instruction; updating the array information of the preset array according to the heap memory processing instruction and the array identifier, to obtain the updated array information of the preset array; and generating a memory analysis report corresponding to the to-be-analyzed heap memory based on the updated array information. The method can improve the analysis efficiency of the heap memory.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a heap memory analysis method, apparatus, computer equipment, chip, chip module, computer-readable storage medium, and computer program product. Background Technology

[0002] Currently, in order to meet the real-time requirements of embedded real-time operating systems, it is crucial to be able to quickly analyze the system's heap memory.

[0003] In traditional techniques, heap memory analysis typically involves traversing the entire linked list of memory; however, this method is time-consuming and results in low efficiency. Summary of the Invention

[0004] Therefore, it is necessary to provide a heap memory analysis method, apparatus, computer equipment, chip, chip module, computer-readable storage medium, and computer program product that can improve the analysis efficiency of heap memory in response to the above-mentioned technical problems.

[0005] Firstly, this application provides a heap memory analysis method, including:

[0006] In response to a heap memory processing instruction for the heap memory to be analyzed, the array identifier of the preset array corresponding to the heap memory to be analyzed is determined according to the heap memory address corresponding to the heap memory processing instruction.

[0007] Based on the heap memory processing instructions and the array identifier, the array information of the preset array is updated to obtain the updated array information of the preset array;

[0008] Based on the updated array information, a memory analysis report is generated corresponding to the heap memory to be analyzed.

[0009] In one embodiment, determining the array identifier of the preset array corresponding to the heap memory to be analyzed based on the heap memory address corresponding to the heap memory processing instruction includes:

[0010] The heap memory address corresponding to the heap memory processing instruction is hashed to obtain the hash value corresponding to the heap memory address.

[0011] Based on the hash value, the array identifier of the preset array corresponding to the heap memory to be analyzed is obtained.

[0012] In one embodiment, hashing the heap memory address corresponding to the heap memory processing instruction to obtain the hash value corresponding to the heap memory address includes:

[0013] Obtain the aligned byte count of the heap memory address;

[0014] The hash value corresponding to the heap memory address is obtained based on the ratio between the heap memory address and the number of aligned bytes.

[0015] In one embodiment, updating the array information of the preset array according to the heap memory processing instructions and the array identifier to obtain the updated array information of the preset array includes:

[0016] When the heap memory processing instruction is a heap memory request instruction for the heap memory to be analyzed, it is determined whether the target array information identified by the array exists in the preset array;

[0017] If the target array information is not present in the preset array, the array information of the preset array is updated according to the target array information to obtain the updated array information of the preset array;

[0018] or,

[0019] If the target array information exists in the preset array, a memory allocation error message for the array identifier is generated, and the array information of the preset array is updated according to the memory allocation error message to obtain the updated array information of the preset array.

[0020] In one embodiment, updating the array information of the preset array according to the heap memory processing instructions and the array identifier to obtain the updated array information of the preset array includes:

[0021] When the heap memory processing instruction is a heap memory release instruction for the heap memory to be analyzed, it is determined whether the target array information identified by the array exists in the preset array;

[0022] If the target array information exists in the preset array, the target array information is deleted from the array information of the preset array to obtain the updated array information of the preset array;

[0023] or,

[0024] If the target array information is not present in the preset array, a memory release error message for the array identifier is generated, and the array information of the preset array is updated according to the memory release error message to obtain the updated array information of the preset array.

[0025] In one embodiment, before determining the array identifier of the preset array corresponding to the heap memory to be analyzed based on the heap memory address corresponding to the heap memory processing instruction in response to the heap memory to be analyzed, the method further includes:

[0026] Obtain the maximum heap memory address corresponding to the heap memory to be analyzed;

[0027] Based on the maximum heap memory address, determine the upper bound of the preset array;

[0028] Based on the upper bound value, the preset array is constructed.

[0029] Secondly, this application also provides a heap memory analysis apparatus, comprising:

[0030] The identifier determination module is used to determine the array identifier of the preset array corresponding to the heap memory to be analyzed based on the heap memory address corresponding to the heap memory to be analyzed in response to the heap memory processing instruction for the heap memory to be analyzed.

[0031] The information update module is used to update the array information of the preset array according to the heap memory processing instructions and the array identifier, so as to obtain the updated array information of the preset array;

[0032] The report generation module is used to generate a memory analysis report corresponding to the heap memory to be analyzed based on the updated array information.

[0033] Thirdly, this application also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to perform the following steps:

[0034] In response to a heap memory processing instruction for the heap memory to be analyzed, the array identifier of the preset array corresponding to the heap memory to be analyzed is determined according to the heap memory address corresponding to the heap memory processing instruction.

[0035] Based on the heap memory processing instructions and the array identifier, the array information of the preset array is updated to obtain the updated array information of the preset array;

[0036] Based on the updated array information, a memory analysis report is generated corresponding to the heap memory to be analyzed.

[0037] Fourthly, this application also provides a chip, including a processor and a communication interface, wherein the processor is configured to cause the chip to perform:

[0038] In response to a heap memory processing instruction for the heap memory to be analyzed, the array identifier of the preset array corresponding to the heap memory to be analyzed is determined according to the heap memory address corresponding to the heap memory processing instruction.

[0039] Based on the heap memory processing instructions and the array identifier, the array information of the preset array is updated to obtain the updated array information of the preset array;

[0040] Based on the updated array information, a memory analysis report is generated corresponding to the heap memory to be analyzed.

[0041] Fifthly, this application also provides a chip module, including a communication module, a power module, a storage module, and a chip, wherein:

[0042] The power module is used to provide power to the chip module;

[0043] The storage module is used to store data and instructions;

[0044] The communication module is used for internal communication within the chip module, or for communication between the chip module and external devices.

[0045] The chip is used to perform the steps of the method provided in the first aspect above.

[0046] Sixthly, this application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, performs the following steps:

[0047] In response to a heap memory processing instruction for the heap memory to be analyzed, the array identifier of the preset array corresponding to the heap memory to be analyzed is determined according to the heap memory address corresponding to the heap memory processing instruction.

[0048] Based on the heap memory processing instructions and the array identifier, the array information of the preset array is updated to obtain the updated array information of the preset array;

[0049] Based on the updated array information, a memory analysis report is generated corresponding to the heap memory to be analyzed.

[0050] In a seventh aspect, this application also provides a computer program product, including a computer program that, when executed by a processor, performs the following steps:

[0051] In response to a heap memory processing instruction for the heap memory to be analyzed, the array identifier of the preset array corresponding to the heap memory to be analyzed is determined according to the heap memory address corresponding to the heap memory processing instruction.

[0052] Based on the heap memory processing instructions and the array identifier, the array information of the preset array is updated to obtain the updated array information of the preset array;

[0053] Based on the updated array information, a memory analysis report is generated corresponding to the heap memory to be analyzed.

[0054] The aforementioned heap memory analysis method, apparatus, computer equipment, chip, chip module, computer-readable storage medium, and computer program product first respond to a heap memory processing instruction for the heap memory to be analyzed, determine the array identifier of the preset array corresponding to the heap memory to be analyzed based on the heap memory address corresponding to the heap memory processing instruction, then update the array information of the preset array based on the heap memory processing instruction and the array identifier to obtain the updated array information of the preset array, and finally generate a memory analysis report corresponding to the heap memory to be analyzed based on the updated array information. In this way, when analyzing heap memory, the preset array identifier corresponding to the heap memory to be analyzed can be directly located through the heap memory address associated with the heap memory processing instructions. There is no need to perform a full traversal and retrieval of the entire heap memory, which greatly reduces the addressing time in the early stage of heap memory analysis. Furthermore, the array information of the preset array is updated in a targeted manner based on the instructions and array identifier, avoiding indiscriminate memory data processing. The update of array information always revolves around the heap memory to be analyzed, which improves the efficiency of data processing. Moreover, the memory analysis report is generated directly based on the updated dedicated array information, eliminating the step of filtering and sorting effective information from massive heap memory data. This achieves targeted optimization of the entire process of heap memory analysis from addressing, data processing to report generation. It avoids the shortcomings of traditional techniques that use the method of traversing the entire memory linked list for analysis, which is prone to consuming a lot of time and resulting in low efficiency of heap memory analysis. This is conducive to improving the efficiency of heap memory analysis. Attached Figure Description

[0055] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0056] Figure 1 This is a flowchart illustrating a heap memory analysis method in one embodiment;

[0057] Figure 2 This is a flowchart illustrating the heap memory analysis method in another embodiment;

[0058] Figure 3 This is a schematic diagram of the structure of an embedded real-time operating system heap memory analysis method in one embodiment;

[0059] Figure 4 This is a flowchart illustrating an embedded real-time operating system heap memory analysis method in one embodiment;

[0060] Figure 5 This is a structural block diagram of a heap memory analysis device in one embodiment;

[0061] Figure 6 This is an internal structural diagram of a computer device in one embodiment;

[0062] Figure 7 This is an internal structure diagram of a chip module in one embodiment. Detailed Implementation

[0063] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0064] It should be noted that the terms "first," "second," etc., used in this application can be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from the second element. The terms "comprising" and "having," and any variations thereof, used in this application, are intended to cover non-exclusive inclusion. The term "multiple" used in this application refers to two or more. The term "and / or" used in this application refers to one of the embodiments, or any combination of multiple embodiments.

[0065] With the rapid development of Internet of Things (IoT) technology, the number of IoT devices worldwide is growing exponentially. Most of these IoT devices run real-time operating systems (RTOS). In these embedded ROS, heap memory management algorithms are crucial for system performance. Therefore, many excellent memory allocation algorithms for ROS have emerged, such as TLSF (Two-Level Segregate Fit). However, these algorithms focus on efficient memory management but lack corresponding memory analysis tools. Currently common memory analysis tools are limited by the following: processor architecture support; and resource constraints in embedded ROS (low computing power, small storage space), making deployment difficult. Therefore, this application provides a heap memory analysis method that can improve the efficiency of heap memory analysis.

[0066] In one exemplary embodiment, such as Figure 1As shown, a heap memory analysis method is provided. This embodiment illustrates the method by applying it to a server. It is understood that this method can also be applied to terminals, systems including terminals and servers, and is implemented through interaction between the terminal and server. It can also be applied to communication equipment, terminal equipment, base stations, network-side equipment, chips, and chip modules. The terminal can be, but is not limited to, various personal computers, laptops, smartphones, and tablets; the server can be a standalone physical server, a server cluster or distributed system composed of multiple physical servers, or a cloud server providing cloud computing services. In this embodiment, the method includes the following steps:

[0067] Step S101: In response to the heap memory processing instruction for the heap memory to be analyzed, determine the array identifier of the preset array corresponding to the heap memory to be analyzed based on the heap memory address corresponding to the heap memory processing instruction.

[0068] Among them, the heap memory to be analyzed refers to the heap memory region in the embedded real-time operating system that needs to be analyzed.

[0069] Among them, heap memory processing instructions refer to the operation instructions for allocating or releasing heap memory.

[0070] The heap memory address is used to indicate the specific memory location of the heap memory to be analyzed, which is targeted by the processing operation of the heap memory processing instruction.

[0071] The preset array refers to a pre-constructed contiguous storage structure used to store the allocation status of the heap memory to be analyzed.

[0072] The array identifier can refer to the index value of a preset array.

[0073] For example, the server obtains a data packet containing heap memory processing instructions for the heap memory to be analyzed, and performs unpacking and decompression processing on the data packet to obtain the heap memory processing instructions for the heap memory to be analyzed; then, in response to the heap memory processing instructions for the heap memory to be analyzed, based on the heap memory address of the heap memory to be analyzed carried by the heap memory processing instructions, it queries the correspondence between the heap memory address and the array identifier to obtain the array identifier of the preset array corresponding to the heap memory to be analyzed.

[0074] Step S102: Update the array information of the preset array according to the heap memory processing instructions and array identifier to obtain the updated array information of the preset array.

[0075] Among them, array information refers to the information related to the memory allocation status of the heap memory to be analyzed stored in the preset array, including the allocation status information corresponding to each heap memory address in the heap memory to be analyzed, including at least the memory allocation size corresponding to the heap memory address, and may also include the request thread number, request function line number, request timestamp, etc. corresponding to the heap memory address.

[0076] The updated array information represents the overall data state after the array information under the corresponding array identifier in the preset array has been modified in response to the heap memory processing instructions.

[0077] For example, the server updates the local information under the array identifier of the preset array according to the heap memory processing instructions to obtain the updated information under the array identifier of the preset array; then, according to the updated information, the array information of the preset array is updated to obtain the updated array information of the preset array.

[0078] Step S103: Based on the updated array information, generate a memory analysis report corresponding to the heap memory to be analyzed.

[0079] Among them, the memory analysis report refers to a structured report that comprehensively reflects the overall usage status of the heap memory to be analyzed.

[0080] For example, the server inputs the updated array information into a trained information extraction model designed for an embedded real-time operating system. Through the trained information extraction model, the server extracts the number of allocated bytes, the number of allocated blocks, the number of free bytes, memory allocation error information, memory release error information, current memory allocation information, memory allocation record information, and memory release record information corresponding to the heap memory to be analyzed from the updated array information. The server then adds the above report content information to the corresponding position in a preset memory analysis report template adapted to the heap memory analysis requirements of the embedded real-time operating system, thereby obtaining the memory analysis report corresponding to the heap memory to be analyzed.

[0081] In the above heap memory analysis method, firstly, in response to the heap memory processing instruction for the heap memory to be analyzed, the array identifier of the preset array corresponding to the heap memory to be analyzed is determined according to the heap memory address corresponding to the heap memory processing instruction. Then, according to the heap memory processing instruction and the array identifier, the array information of the preset array is updated to obtain the updated array information of the preset array. Finally, based on the updated array information, a memory analysis report corresponding to the heap memory to be analyzed is generated. In this way, when analyzing heap memory, the preset array identifier corresponding to the heap memory to be analyzed can be directly located through the heap memory address associated with the heap memory processing instructions. There is no need to perform a full traversal and retrieval of the entire heap memory, which greatly reduces the addressing time in the early stage of heap memory analysis. Furthermore, the array information of the preset array is updated in a targeted manner based on the instructions and array identifier, avoiding indiscriminate memory data processing. The update of array information always revolves around the heap memory to be analyzed, which improves the efficiency of data processing. Moreover, the memory analysis report is generated directly based on the updated dedicated array information, eliminating the step of filtering and sorting effective information from massive heap memory data. This achieves targeted optimization of the entire process of heap memory analysis from addressing, data processing to report generation. It avoids the shortcomings of traditional techniques that use the method of traversing the entire memory linked list for analysis, which is prone to consuming a lot of time and resulting in low efficiency of heap memory analysis. This is conducive to improving the efficiency of heap memory analysis.

[0082] In an exemplary embodiment, step S101 above, which determines the array identifier of the preset array corresponding to the heap memory to be analyzed based on the heap memory address corresponding to the heap memory processing instruction, specifically includes the following: performing hash processing on the heap memory address corresponding to the heap memory processing instruction to obtain the hash value corresponding to the heap memory address; and obtaining the array identifier of the preset array corresponding to the heap memory to be analyzed based on the hash value.

[0083] The hash value is used to represent the hash value corresponding to the heap memory address.

[0084] For example, the server inputs the heap memory address corresponding to the heap memory processing instruction into a preset hash algorithm that matches the embedded real-time operating system. The preset hash algorithm is used to hash the heap memory address corresponding to the heap memory processing instruction to obtain the hash value corresponding to the heap memory address. Then, the hash value is used as the array identifier of the preset array corresponding to the heap memory to be analyzed.

[0085] For example, the hash value corresponding to a heap memory address can be calculated using the following formula:

[0086] Equation (1)

[0087] in, Indicates the heap memory address. Represents a hash function. This represents the hash value.

[0088] In this embodiment, a unique hash value is obtained by hashing the heap memory address corresponding to the heap memory processing instruction, and the array identifier of the preset array is obtained by mapping the hash value. This can effectively avoid the address location conflict problem, ensure that the heap memory address corresponds to the storage location of the preset array, and lay a solid foundation for subsequent accurate and efficient updating of the array information of the preset array.

[0089] In an exemplary embodiment, the heap memory address corresponding to the heap memory processing instruction is hashed to obtain the hash value corresponding to the heap memory address. Specifically, this includes: obtaining the number of aligned bytes of the heap memory address; and obtaining the hash value corresponding to the heap memory address based on the ratio between the heap memory address and the number of aligned bytes.

[0090] The alignment byte count is a fixed number of bytes used to determine the granularity of heap memory address allocation, and is usually a power of 2 (such as 4 bytes, 8 bytes, or 16 bytes).

[0091] For example, the server reads the number of aligned bytes that matches the heap memory to be analyzed from the preset heap memory configuration parameters of the embedded real-time operating system, and uses it as the number of aligned bytes for the heap memory address. Then, it performs a validity check on the heap memory address corresponding to the heap memory processing instruction to obtain the verification result of the heap memory address. For example, if it is determined that the heap memory address belongs to the address range of the heap memory to be analyzed and the value of the heap memory address is an integer multiple of the number of aligned bytes, the verification result is determined to be that the heap memory address verification is successful. If the verification result indicates that the heap memory address verification is successful, an integer division operation is performed on the heap memory address and the number of aligned bytes to obtain the ratio between the heap memory address and the number of aligned bytes, and the ratio between the heap memory address and the number of aligned bytes is used as the hash value corresponding to the heap memory address.

[0092] For example, the hash value corresponding to a heap memory address can be calculated using the following formula:

[0093] Equation (2)

[0094] in, Indicates the heap memory address. This represents the division operation. This indicates the number of bytes aligned to the heap memory address. In embedded real-time operating systems, Common values ​​for are 4, 8, or 16.

[0095] In this embodiment, the number of aligned bytes of the heap memory to be analyzed is obtained directly from the system configuration, and the integer ratio of the heap memory address to the number of aligned bytes is used as the hash value. This eliminates the need for complex hash operations and conflict resolution mechanisms, greatly simplifying the hash value calculation process and meeting the requirements of embedded real-time operating systems for low computing power and high response.

[0096] In an exemplary embodiment, step S102, which updates the array information of a preset array according to the heap memory processing instruction and the array identifier to obtain the updated array information of the preset array, specifically includes the following: when the heap memory processing instruction is a heap memory allocation instruction for the heap memory to be analyzed, determining whether there is target array information of the array identifier in the preset array; when there is no target array information in the preset array, updating the array information of the preset array according to the target array information to obtain the updated array information of the preset array; or, when there is target array information in the preset array, generating memory allocation error information of the array identifier, and updating the array information of the preset array according to the memory allocation error information to obtain the updated array information of the preset array.

[0097] Among them, the heap memory allocation instruction refers to the operation instruction in the embedded real-time operating system that requests the allocation of a specified size of memory space from the heap memory to be analyzed.

[0098] Among them, the target array information refers to the memory allocation information under the array identifier in the preset array that matches the heap memory processing instructions.

[0099] Among them, memory allocation error information refers to the abnormal information generated when the heap memory allocation instruction is executed because the target array information with the corresponding array identifier already exists in the preset array (i.e., the heap memory address has been allocated and occupied), and it is determined that the same heap memory address is being requested repeatedly.

[0100] For example, the server judges the heap memory processing instruction; if the heap memory processing instruction is a heap memory allocation instruction for the heap memory to be analyzed, it determines whether there is target array information with array identifier in the preset array; if there is no target array information in the preset array, the target array information and the array information of the preset array are integrated to obtain the updated array information of the preset array; or, if there is target array information in the preset array, the array identifier is input into the corresponding position in the preset memory allocation error information template to obtain the memory allocation error information with array identifier, and the memory allocation error information and the array information of the preset array are integrated to obtain the updated array information of the preset array.

[0101] In this embodiment, by verifying whether target array information exists under the corresponding array identifier in the preset array, the accurate identification and control of repeated heap memory allocation behavior is achieved, avoiding problems such as memory leaks and address conflicts caused by the same heap memory address being allocated multiple times, and providing accurate data support for the subsequent generation of a complete memory analysis report.

[0102] In an exemplary embodiment, step S102, which updates the array information of a preset array according to the heap memory processing instruction and the array identifier to obtain the updated array information of the preset array, specifically includes the following: when the heap memory processing instruction is a heap memory release instruction for the heap memory to be analyzed, determining whether there is target array information of the array identifier in the preset array; when the target array information exists in the preset array, deleting the target array information from the array information of the preset array to obtain the updated array information of the preset array; or, when the target array information does not exist in the preset array, generating memory release error information of the array identifier, and updating the array information of the preset array according to the memory release error information to obtain the updated array information of the preset array.

[0103] Among them, the heap memory release instruction refers to the operation instruction in the embedded real-time operating system that initiates a request to release the allocated memory space to the heap memory to be analyzed.

[0104] Among them, memory release error information refers to the abnormal information generated when the heap memory release instruction is executed because the target array information with the corresponding array identifier does not exist in the preset array (that is, the heap memory address has not been requested or has been released), and it is judged as invalid release or duplicate release.

[0105] For example, the server judges the heap memory processing instruction; if the heap memory processing instruction is a heap memory release instruction for the heap memory to be analyzed, it determines whether there is target array information with an array identifier in the preset array; if the target array information exists in the preset array, the target array information is deleted from the array information of the preset array to obtain the array information after deleting the target array information, which is used as the updated array information of the preset array; or, if the target array information does not exist in the preset array, the array identifier is input into the corresponding position in the preset memory release error information template to obtain the memory release error information of the array identifier, and the memory release error information and the array information of the preset array are integrated and processed to obtain the updated array information of the preset array.

[0106] In this embodiment, by verifying whether target array information exists under the corresponding array identifier in the preset array, the system can accurately identify and control violations such as invalid release and duplicate release of heap memory, avoid memory management chaos and system crashes caused by invalid release operations, and greatly improve the processing efficiency of heap memory release instructions.

[0107] In an exemplary embodiment, before determining the array identifier of the preset array corresponding to the heap memory to be analyzed based on the heap memory address corresponding to the heap memory processing instruction for the heap memory to be analyzed in response to the heap memory processing instruction, step S101 specifically includes the following: obtaining the maximum heap memory address corresponding to the heap memory to be analyzed; determining the upper bound of the preset array based on the maximum heap memory address; and constructing the preset array based on the upper bound.

[0108] The maximum heap memory address refers to the upper limit of the range of heap memory addresses to be analyzed (the lower limit is the starting address of the heap memory to be analyzed).

[0109] The upper bound value refers to the integer threshold used to limit the capacity of the preset array.

[0110] For example, the server obtains the configuration parameters corresponding to the heap memory to be analyzed, inputs the configuration parameters corresponding to the heap memory to be analyzed into the trained information extraction model, and extracts the maximum heap memory address corresponding to the heap memory to be analyzed from the configuration parameters of the heap memory to be analyzed; then, it obtains the number of aligned bytes that match the heap memory to be analyzed, and uses the ratio between the maximum heap memory address and the number of aligned bytes as the upper bound of the preset array; then, it uses the upper bound as the maximum valid value of the array identifier of the preset array, and constructs the preset array based on the maximum valid value of the array identifier of the preset array.

[0111] In this embodiment, the upper bound of the preset array is determined by obtaining the maximum heap memory address of the heap memory to be analyzed, and the preset array is constructed based on the upper bound. This allows the capacity of the preset array to accurately match the address range of the heap memory to be analyzed, avoiding the waste of embedded system memory resources caused by an excessively large array capacity, and also avoiding the problem that the array capacity is insufficient to cover all heap memory addresses.

[0112] In one exemplary embodiment, such as Figure 2 As shown, another method for heap memory analysis is provided. Taking the application of this method to a server as an example, the specific steps include:

[0113] Step S201: Obtain the maximum heap memory address corresponding to the heap memory to be analyzed.

[0114] Step S202: Determine the upper bound of the preset array corresponding to the heap memory to be analyzed based on the maximum heap memory address.

[0115] Step S203: Based on the upper bound value, construct a preset array corresponding to the heap memory to be analyzed.

[0116] Step S204: In response to a heap memory processing instruction for the heap memory to be analyzed, obtain the number of aligned bytes of the heap memory address.

[0117] Step S205: Based on the ratio between the heap memory address and the number of aligned bytes, obtain the hash value corresponding to the heap memory address.

[0118] Step S206: Based on the hash value, obtain the array identifier of the preset array corresponding to the heap memory to be analyzed.

[0119] Step S207: Update the array information of the preset array according to the heap memory processing instructions and array identifier to obtain the updated array information of the preset array.

[0120] Step S208: Based on the updated array information, generate a memory analysis report corresponding to the heap memory to be analyzed.

[0121] In the aforementioned heap memory analysis method, when analyzing heap memory, the preset array identifier corresponding to the heap memory to be analyzed is directly located through the heap memory address associated with the heap memory processing instructions. This eliminates the need for a full traversal and retrieval of the entire heap memory, significantly reducing the addressing time in the early stages of heap memory analysis. Furthermore, the array information of the preset array is updated specifically based on the instructions and array identifier, avoiding indiscriminate memory data processing. This ensures that the update of array information always revolves around the heap memory to be analyzed, improving data processing efficiency. Additionally, the memory analysis report is generated directly based on the updated, dedicated array information, eliminating the need to filter and organize effective information from massive heap memory data. This achieves targeted optimization of the entire process of heap memory analysis, from addressing and data processing to report generation. It avoids the drawback of traditional techniques that use traversing the entire memory linked list for analysis, which is time-consuming and leads to low efficiency in heap memory analysis. This method is beneficial for improving the efficiency of heap memory analysis.

[0122] In an exemplary embodiment, to more clearly illustrate the heap memory analysis method provided by the embodiments of this application, the following specific embodiment will be used to describe the heap memory analysis method in detail. In one embodiment, this application also provides a heap memory analysis method for an embedded real-time operating system. Specifically, it includes the following:

[0123] Figure 3 This is a schematic diagram of the structure of an embedded real-time operating system heap memory analysis method provided in this embodiment.

[0124] like Figure 4The diagram shown is a flowchart of an embedded real-time operating system heap memory analysis method provided in this embodiment. The specific steps are as follows:

[0125] Step 1, Information Acquisition: When the embedded program requests memory, the acquisition module can collect the following information: the allocated memory address, the allocated size, the address of the called function, the filename of the called function, the line number of the file containing the called function, and the current thread number. The allocated memory address and allocated size are mandatory; the remaining information is optional (depending on the performance of the embedded device). When the embedded program releases memory, the acquisition module collects the following information: the released memory address, the address of the called function, the filename of the called function, the line number of the file containing the called function, and the current thread number. The released memory address is mandatory; the remaining information is optional (depending on the performance of the embedded device).

[0126] Step 2: Place the collected data into a queue, and the transmission module will process it.

[0127] Step 3, Data Packaging: This refers to compressing and encapsulating the data in the queue to improve data transmission efficiency and security. Compression is an optional step (depending on the performance of the embedded device).

[0128] Step 4, Data Transmission: This refers to transmitting the packaged data to the analysis module through a specific physical channel, such as a serial port or USB (Universal Serial Bus).

[0129] Step 5, Data Unpacking: After receiving the data, the analysis module unpacks and decompresses it. Unpacking is the reverse operation of the encapsulation step in Step 3. Decompression is the reverse operation of the compression step in Step 3. Decompression is an optional step, depending on Step 3.

[0130] Step 6: Calculate the hash value based on the address, as shown in formula (1). Among these, common... The function expression is shown in formula (2). Through The function and analysis module can quickly locate memory information.

[0131] Step 7, Adding and Deleting Records: During initialization, the analysis module creates an array whose upper bound is the value obtained in Step 6. The maximum value of the array is used to ensure that the array does not go out of bounds; this array is denoted as... .

[0132] If the data in step 5 is memory allocation information, the analysis module will add a record, and the index of this record in the array will be the one obtained in step 6. .if There is already a record indicating that a memory allocation error occurred. If No record found. A new record will be added.

[0133] If the data in step 5 is memory release information, the analysis module will delete a record. The index of this record in the array is obtained in step 6. .if If a record already exists, it will be deleted. No record indicates an error occurred during memory release.

[0134] Step 8: Analyze the data and generate a report. The analysis module iterates through the array. Based on the information recorded in the array, a memory report is generated. The report includes: the number of bytes allocated, the number of allocated blocks, the number of free bytes, whether there are memory allocation or deallocation errors, detailed information on currently allocated memory, and a history of memory allocation and deallocation.

[0135] In the above embodiments, when analyzing heap memory, the preset array identifier corresponding to the heap memory to be analyzed is directly located through the heap memory address associated with the heap memory processing instructions. This eliminates the need for a full traversal and retrieval of the entire heap memory, significantly reducing the addressing time in the early stages of heap memory analysis. Furthermore, the array information of the preset array is updated specifically based on the instructions and array identifier, avoiding indiscriminate memory data processing. This ensures that the update of array information always revolves around the heap memory to be analyzed, improving data processing efficiency. Additionally, a memory analysis report is generated directly based on the updated, dedicated array information, eliminating the need to filter and organize effective information from massive heap memory data. This achieves targeted optimization of the entire process of heap memory analysis, from addressing and data processing to report generation. It avoids the drawback of traditional techniques that use traversing the entire memory linked list for analysis, which is time-consuming and results in low efficiency in heap memory analysis. This approach is beneficial for improving the efficiency of heap memory analysis.

[0136] It should be understood that although the steps in the flowcharts of the above embodiments are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the above embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages in other steps. It is understood that the steps in different embodiments can be freely combined as needed, and all non-contradictory solutions formed by such combinations are within the scope of protection of this application.

[0137] Based on the same inventive concept, this application also provides a heap memory analysis apparatus for implementing the heap memory analysis method described above. This apparatus can be applied to or integrated into a chip or chip module, for example. The solution provided by this apparatus is similar to the implementation scheme described in the above method; therefore, the specific limitations in one or more heap memory analysis apparatus embodiments provided below can be found in the limitations of the heap memory analysis method above, and will not be repeated here.

[0138] In one exemplary embodiment, such as Figure 5 As shown, a heap memory analysis device is provided, including: an identifier determination module 501, an information update module 502, and a report generation module 503, wherein:

[0139] The identifier determination module 501 is used to determine the array identifier of the preset array corresponding to the heap memory to be analyzed based on the heap memory address corresponding to the heap memory processing instruction for the heap memory to be analyzed in response to the heap memory processing instruction.

[0140] The information update module 502 is used to update the array information of the preset array according to the heap memory processing instructions and the array identifier, so as to obtain the updated array information of the preset array.

[0141] The report generation module 503 is used to generate a memory analysis report for the heap memory to be analyzed based on the updated array information.

[0142] In an exemplary embodiment, the identifier determination module 501 is further configured to perform hash processing on the heap memory address corresponding to the heap memory processing instruction to obtain the hash value corresponding to the heap memory address; and based on the hash value, obtain the array identifier of the preset array corresponding to the heap memory to be analyzed.

[0143] In an exemplary embodiment, the identifier determination module 501 is further configured to obtain the number of aligned bytes of the heap memory address; and obtain the hash value corresponding to the heap memory address based on the ratio between the heap memory address and the number of aligned bytes.

[0144] In an exemplary embodiment, the information update module 502 is further configured to: determine whether target array information of an array identifier exists in the preset array when the heap memory processing instruction is a heap memory allocation instruction for the heap memory to be analyzed; update the array information of the preset array according to the target array information when the target array information does not exist in the preset array to obtain the updated array information of the preset array; or generate memory allocation error information of an array identifier when the target array information exists in the preset array, and update the array information of the preset array according to the memory allocation error information to obtain the updated array information of the preset array.

[0145] In an exemplary embodiment, the information update module 502 is further configured to: determine whether target array information of an array identifier exists in a preset array when the heap memory processing instruction is a heap memory release instruction for the heap memory to be analyzed; if target array information exists in the preset array, delete the target array information from the array information of the preset array to obtain the updated array information of the preset array; or, if target array information does not exist in the preset array, generate memory release error information of the array identifier, and update the array information of the preset array according to the memory release error information to obtain the updated array information of the preset array.

[0146] In an exemplary embodiment, the heap memory analysis device further includes an array construction module, used to obtain the maximum heap memory address corresponding to the heap memory to be analyzed; determine the upper bound of a preset array based on the maximum heap memory address; and construct the preset array based on the upper bound.

[0147] Regarding the modules / units included in the various devices and products described in the above embodiments, they can be software modules / units, hardware modules / units, or a combination of both. For example, for various devices and products applied to or integrated into a chip, all of their modules / units can be implemented using hardware methods such as circuits, or at least some modules / units can be implemented using software programs that run on a processor integrated within the chip, while the remaining (if any) modules / units can be implemented using hardware methods such as circuits; for various devices and products applied to or integrated into a chip module, all of their modules / units can be implemented using hardware methods such as circuits, and different modules / units can be located in the same component (e.g., chip, circuit module, etc.) or different components of the chip module, or at least some modules / units can be implemented using hardware methods such as circuits. The components can be implemented using software programs that run on the processor integrated within the chip module. The remaining (if any) modules / units can be implemented using hardware methods such as circuits. For various devices and products applied to or integrated into the terminal, each of its components / units can be implemented using hardware methods such as circuits. Different modules / units can be located in the same component (e.g., chip, circuit module, etc.) or in different components within the terminal. Alternatively, at least some modules / units can be implemented using software programs that run on the processor integrated within the terminal, while the remaining (if any) modules / units can be implemented using hardware methods such as circuits.

[0148] In one exemplary embodiment, a computer device is provided, which may be a server, and its internal structure diagram may be as follows: Figure 6As shown, this computer device includes a processor, memory, input / output interfaces (I / O), and a communication interface. The processor, memory, and I / O interfaces are connected via a system bus, and the communication interface is also connected to the system bus via the I / O interfaces. The processor provides computational and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and a database. The internal memory provides the environment for the operating system and computer programs stored in the non-volatile storage media. The database stores data such as heap memory addresses and array identifiers. The I / O interfaces are used for exchanging information between the processor and external devices. The communication interface is used for communication with external terminals via a network connection. When executed by the processor, the computer program implements a heap memory analysis method.

[0149] Those skilled in the art will understand that Figure 6 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0150] In one embodiment, a computer device is also provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps in the above method embodiments.

[0151] Based on the same inventive concept, this application also provides a chip, including a processor coupled to a memory, for executing a computer program or instructions stored in the memory, and implementing the steps in the above method embodiments when the processor executes the computer program or instructions.

[0152] It is understood that the chip involved in the embodiments of this application may be a field-programmable gate array (FPGA), may include an application-specific integrated circuit (ASIC), may be a system on chip (SoC), may be a central processor unit (CPU), may be a network processor (NP), may be a digital signal processor (DSP), may be a microcontroller unit (MCU), may be a programmable logic device (PLD), or other integrated chips, etc.

[0153] Based on the same inventive concept, this application also provides a chip module, such as... Figure 6 As shown, the chip module includes a communication module, a power module, a storage module, and a chip. Among them:

[0154] The power module is used to provide power to the chip module; the storage module is used to store data and instructions; the communication module is used for internal communication within the chip module, or for communication between the chip module and external devices; this chip corresponds to the chip in the above chip embodiment.

[0155] The implementation method of this chip module can be found in the relevant content of the above chip embodiment, and will not be repeated here.

[0156] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon that, when executed by a processor, implements the steps in the above method embodiments.

[0157] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps in the above method embodiments.

[0158] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of the relevant data must comply with relevant regulations.

[0159] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.

[0160] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0161] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A heap memory analysis method, characterized in that, The method includes: In response to a heap memory processing instruction for the heap memory to be analyzed, the array identifier of the preset array corresponding to the heap memory to be analyzed is determined according to the heap memory address corresponding to the heap memory processing instruction. Based on the heap memory processing instructions and the array identifier, the array information of the preset array is updated to obtain the updated array information of the preset array; Based on the updated array information, a memory analysis report is generated corresponding to the heap memory to be analyzed.

2. The method according to claim 1, characterized in that, The step of determining the array identifier of the preset array corresponding to the heap memory to be analyzed based on the heap memory address corresponding to the heap memory processing instruction includes: The heap memory address corresponding to the heap memory processing instruction is hashed to obtain the hash value corresponding to the heap memory address. Based on the hash value, the array identifier of the preset array corresponding to the heap memory to be analyzed is obtained.

3. The method according to claim 2, characterized in that, The step of hashing the heap memory address corresponding to the heap memory processing instruction to obtain the hash value corresponding to the heap memory address includes: Obtain the aligned byte count of the heap memory address; The hash value corresponding to the heap memory address is obtained based on the ratio between the heap memory address and the number of aligned bytes.

4. The method according to claim 1, characterized in that, The step of updating the array information of the preset array according to the heap memory processing instructions and the array identifier to obtain the updated array information of the preset array includes: When the heap memory processing instruction is a heap memory request instruction for the heap memory to be analyzed, it is determined whether the target array information identified by the array exists in the preset array; If the target array information is not present in the preset array, the array information of the preset array is updated according to the target array information to obtain the updated array information of the preset array; or, If the target array information exists in the preset array, a memory allocation error message for the array identifier is generated, and the array information of the preset array is updated according to the memory allocation error message to obtain the updated array information of the preset array.

5. The method according to claim 1, characterized in that, The step of updating the array information of the preset array according to the heap memory processing instructions and the array identifier to obtain the updated array information of the preset array includes: When the heap memory processing instruction is a heap memory release instruction for the heap memory to be analyzed, it is determined whether the target array information identified by the array exists in the preset array; If the target array information exists in the preset array, the target array information is deleted from the array information of the preset array to obtain the updated array information of the preset array; or, If the target array information is not present in the preset array, a memory release error message for the array identifier is generated, and the array information of the preset array is updated according to the memory release error message to obtain the updated array information of the preset array.

6. The method according to any one of claims 1 to 5, characterized in that, Before determining the array identifier of the preset array corresponding to the heap memory to be analyzed based on the heap memory address corresponding to the heap memory processing instruction in response to the heap memory to be analyzed, the method further includes: Obtain the maximum heap memory address corresponding to the heap memory to be analyzed; Based on the maximum heap memory address, determine the upper bound of the preset array; Based on the upper bound value, the preset array is constructed.

7. A heap memory analysis device, characterized in that, The device includes: The identifier determination module is used to determine the array identifier of the preset array corresponding to the heap memory to be analyzed based on the heap memory address corresponding to the heap memory to be analyzed in response to the heap memory processing instruction for the heap memory to be analyzed. The information update module is used to update the array information of the preset array according to the heap memory processing instructions and the array identifier, so as to obtain the updated array information of the preset array; The report generation module is used to generate a memory analysis report corresponding to the heap memory to be analyzed based on the updated array information.

8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 6.

9. A chip, characterized in that, The device includes a processor and a communication interface, wherein the processor is configured to cause the chip to perform the steps of the method described in any one of claims 1 to 6.

10. A chip module, characterized in that, This includes communication modules, power modules, storage modules, and chips, among which: The power module is used to provide power to the chip module; The storage module is used to store data and instructions; The communication module is used for internal communication within the chip module, or for communication between the chip module and external devices. The chip is used to perform the steps of the method according to any one of claims 1 to 6.

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