A method and system for predicting high-frequency impedance characteristics of cables based on the network tearing method.

Abstract

This invention proposes a method and system for predicting high-frequency impedance characteristics of cables based on the network tearing method. First, a high-precision cascaded model of the minimum circuit units of a multi-conductor cable is established. Then, based on the finite element simulation results of cable parasitic parameters, the parameters of the minimum circuit unit model are tuned. Next, the entire circuit is torn according to the connection form of the minimum circuit units, resulting in several retained sub-networks and torn branches. Then, based on the network topology, the correlation matrix, branch admittance matrix, component admittance matrix, and controlled branch matrix of each retained sub-network are listed, and the complete network matrix equation is determined based on the connection relationships between the retained sub-networks. Finally, M frequency points are selected within the key frequency band, and the network matrix equation at each frequency point is solved to obtain the complete impedance curve of the cable. This invention achieves rapid prediction of high-frequency impedance characteristics of cables and has advantages such as high accuracy, strong versatility, and high numerical robustness.

Description

Technical Field

[0001] This invention belongs to the field of high-frequency modeling technology for cables, and specifically relates to a method and system for predicting the high-frequency impedance characteristics of cables. Background Technology

[0002] In variable frequency speed control motor systems, cables play a crucial role in efficiently and reliably transmitting electrical energy from the power electronic converter to the motor. However, under the influence of the high-voltage slew rate (PWM) voltage of the power electronic converter, the transmission line effect of the cable becomes significant. High-frequency voltage spikes appear at the motor winding terminals due to impedance mismatch between the cable and the motor windings. In severe cases, the amplitude of the voltage spike at the motor winding terminals can reach twice the DC bus voltage. The amplitude and frequency of this voltage spike are closely related to the high-frequency impedance characteristics of the cable. Therefore, rapidly predicting the high-frequency impedance curve of the cable during the design phase is of great significance for assessing the potential overvoltage risk at the motor terminals and designing dv / dt filters for system impedance matching. Reference 1 (S. Sundeep, “Peak voltage stress in inverter-fed machines and its mitigation measures,” Ph.D. dissertation, Dept. Electron. Elect. Eng., Univ. Sheffield, Sheffield, UK, 2022.) proposes a time-domain simulation method for the equivalent circuit of a cable based on segmented multi-conductor cascades. This method can predict the impedance characteristics of the cable during the design phase. However, the number of components in the cable equivalent circuit increases significantly with the increase of cable length and driver slew rate, resulting in a substantial increase in time-domain simulation time. To ensure that the resolution of the predicted impedance curve is high enough to accurately predict the resonant frequency of the cable, this method requires time-domain simulation at least several hundred frequency points in the key frequency band, and post-processing calculations of impedance amplitude and phase based on each voltage and current simulation waveform, which is cumbersome and time-consuming. When the cable length reaches several meters, the calculation time of this method will reach several days, making it difficult to accurately and quickly assess the potential overvoltage risk of motor terminals and perform corresponding system matching optimization during the design phase. Summary of the Invention

[0003] The technical problem to be solved by this invention is to propose a high-precision and fast method for predicting the high-frequency impedance characteristics of cables, which solves the problem that existing methods are difficult to balance accuracy and computational efficiency, and has the advantages of strong versatility and high numerical robustness.

[0004] To solve the above-mentioned technical problems, the present invention adopts the following technical solution:

[0005] First, this invention proposes a method for predicting the high-frequency impedance characteristics of cables based on the network tearing method, applicable to m-phase n-core cables, including the following steps:

[0006] Step 1: Construct a cascaded model of the minimum circuit units of a multi-conductor cable;

[0007] Step 2: Based on the network tearing method, the cascaded model is decomposed into multiple preserved sub-networks and tearing branches connecting these sub-networks;

[0008] Step 3: Based on the impedance prediction type, connect the input and output ports of the model in common-mode or differential-mode configuration;

[0009] Step 4: Write the network matrix equations based on the circuit topology;

[0010] Step 5: Select multiple frequency points within the target frequency band to solve for the impedance frequency characteristic curve of the cable.

[0011] Further, in step 1, the multi-conductor minimum circuit unit cascade model is composed of N (N>1) cascaded sub-networks with the same structure; each sub-network is a 2n-terminal network, containing n input ports and n output ports; each sub-network is composed of n line self-impedances, n×(n-1) line mutual impedances, and all line-to-line (including to ground) capacitances based on the cable structure; wherein, the number of cascades N is determined according to the total cable length and the preset minimum unit length, and the minimum unit length must be less than the minimum wavelength of the frequency corresponding to the rising edge of the PWM voltage.

[0012] Further, in step 2, the specific implementation of the network tearing method is as follows: the connection branch between each smallest circuit unit and its next level unit is torn in the middle, half of the torn series impedance is assigned to the previous unit to form a "reserved sub-network", and the other half is used as an independent "torn branch"; each reserved sub-network is an independent module containing a complete mutual impedance and capacitance network; a reserved node is designated as a reference node in each reserved sub-network for the subsequent writing of network equations.

[0013] Furthermore, in step 3, when predicting the common-mode impedance, all phase lines at the input terminal are shorted, and all phase lines at the output terminal are shorted; when predicting the differential-mode impedance, the corresponding differential-mode connection is adopted.

[0014] Furthermore, in step 4, the method for writing the network matrix equation specifically includes:

[0015] (1) List the correlation matrix:

[0016] List the node-branch incidence matrix A of a single retained subnetwork, and then combine them to obtain the overall incidence matrix A of all retained subnetworks.r Among them, the correlation matrix A of the first and last subnetworks r1 and A rN External connection constraints of inputs and outputs need to be considered;

[0017] List the correlation matrix A between the torn branch and all preserved sub-network nodes (excluding the reference node). d It is a (7N-4)×(4N-4) matrix;

[0018] List the correlation matrix between the torn branch and all reference nodes. It is an (N-1)×(4N-4) matrix;

[0019] List the association matrix between all reference nodes and reserved subnetwork nodes. It is an (N-1)×(10N-5) matrix.

[0020] (2) Write out the admittance matrix and impedance matrix:

[0021] Write the branch admittance matrix Y of a single retained subnetwork, which is derived from the self-admittance matrix Y. em (Corresponding to self-impedance and capacitance) and the controlled branch matrix R m (Corresponding to mutual impedance) constitutes, and then combines to obtain the branch admittance matrix Y composed of all retained subnetworks. r Among them, the branch admittance matrix Y of the first and last subnetworks r1 and Y rN External connection constraints of inputs and outputs need to be considered.

[0022] List the impedance matrix Z of all the tear branches. d .

[0023] (3) Constructing system equations:

[0024] Based on Kirchhoff's laws and the above matrix, a system matrix equation is established with node voltages and tear branch currents as variables. Its form is as follows:

[0025] ;

[0026] J n U is the excitation vector of the node current source. no For the voltage of all reserved sub-network nodes, where U no (1,1) represents the voltage at node 1 of the input terminal; I d For all torn branch circuits; U nc Reserve the reference node voltage for all.

[0027] Further, in step 5, the method for solving the impedance curve is as follows: select M frequency points (M can usually be 500) within the target frequency band (e.g., 10kHz to 100MHz); for each frequency point, substitute the component parameters at that frequency and update the system matrix; by setting a unit excitation (e.g., a common-mode current source), solve the system equation to directly obtain the input impedance amplitude and phase at that frequency; after traversing all frequency points, the complete impedance amplitude-frequency and phase-frequency characteristic curves are obtained.

[0028] In step 5, when calculating the common-mode impedance, the first element of the node current source excitation vector can be set to a unit current, and the rest to 0, i.e., J n =1, calculate the 1-node voltage U under this excitation. no The common-mode impedance amplitude and phase of the cable can be obtained by (1,1), which simplifies the calculation and shortens the solution time.

[0029] Secondly, the present invention also proposes a prediction apparatus for implementing the method described herein, comprising:

[0030] Model building unit, used to build a cascaded model of the minimum circuit units of a multi-conductor cable;

[0031] Branch decomposition unit, used to decompose the cascaded model into multiple retained sub-networks and tearing branches connecting these sub-networks based on the network tearing method;

[0032] Port connection unit, used to connect the input and output ports of the model in common mode or differential mode according to the impedance prediction type;

[0033] The network matrix equation writing unit is used to write network matrix equations based on circuit topology.

[0034] The impedance frequency characteristic solving unit is used to select multiple frequency points within the target frequency band for solving and obtain the impedance frequency characteristic curve of the cable.

[0035] Furthermore, the present invention also proposes an electronic system comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform the steps of the method described in the present invention.

[0036] Finally, the present invention provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the method described in the present invention.

[0037] The present invention adopts the above technical solution and has the following technical effects compared with the prior art:

[0038] This invention reconstructs the cascaded model of the minimum circuit units of a multi-conductor cable using the network tearing method and solves for impedance based on the circuit network equations. Compared with existing methods such as time-domain simulation of the equivalent circuit of a cable based on segmented multi-conductor cascades, it has the following significant advantages:

[0039] (1) The present invention avoids the tedious and time-consuming operations of the existing method, such as complex circuit modeling in circuit simulation software and post-processing the voltage and current obtained from the simulation to calculate the impedance amplitude and phase. The modeling and solution process is significantly simplified.

[0040] (2) This invention improves the calculation efficiency of high-frequency impedance characteristics of cables by thousands of times while ensuring high prediction accuracy. For typical power electronic drive applications with cable lengths less than 10 meters, high-precision prediction of impedance characteristics across the entire frequency band can be completed within 3 minutes, greatly meeting the needs of rapid iteration in the design phase and achieving an order-of-magnitude improvement in calculation efficiency.

[0041] The network matrix constructed in this invention has a low condition number and is less affected by changes in cable length, resulting in good system equation behavior. Even under long cable or high-frequency operating conditions, it maintains high numerical solution accuracy, ensuring the reliability and stability of the method in different scenarios, and exhibiting excellent numerical robustness and accuracy. Attached Figure Description

[0042] Figure 1 This is a flowchart illustrating the prediction of high-frequency impedance characteristics of cables according to the present invention.

[0043] Figure 2 This is a schematic diagram of a cable model initially established in this invention, consisting of cascaded subnetworks of multi-conductor minimum circuit unit models.

[0044] Figure 3 This is a schematic diagram of the cable cascading model based on the network tearing method that was finally established in this invention.

[0045] Figure 4 The circuit diagram (using a three-phase four-core cable as an example) constructed for this invention is used to describe the nodes and branches of the reserved sub-network.

[0046] Figure 5 The diagram shows the input / output port connections corresponding to the common-mode impedance prediction of the cable in this invention (taking a three-phase four-core cable as an example).

[0047] Figure 6 To compare the results of the common-mode impedance obtained from the present invention with existing methods and experimental tests (taking a 2m three-phase four-core cable as an example).

[0048] Figure 7 The total calculation time of the present invention and the existing method is compared at 500 sampling points for different cable lengths (taking a three-phase four-core cable as an example).

[0049] Figure 8 The condition number is the network matrix solved by this invention under 100MHz operating conditions for different cable lengths (taking a three-phase four-core cable as an example). Detailed Implementation

[0050] The present invention will now be described in detail with reference to the accompanying drawings. The following embodiments are for illustrative purposes only and do not constitute a limitation thereof. The overall flowchart of the implementation of the present invention is as follows: Figure 1 As shown.

[0051] Example 1: This example illustrates the prediction of the common-mode impedance characteristics of a three-phase four-core cable. The specific steps are as follows:

[0052] Step 1, construct the cascade model of the minimum circuit unit of the cable multi-conductor:

[0053] like Figure 2 As shown, a high-frequency equivalent model of the cable is first constructed, consisting of N identical cascaded subnetworks. Each subnetwork is a multi-conductor minimum circuit unit, which is an 8-terminal network containing 4 input ports and 4 output ports. It consists of 4 line self-impedances, 12 line mutual impedances, and 6 line-to-line (including to ground) capacitances. The model parameters such as impedance and capacitance can be obtained from the cable datasheet or calculated through finite element simulation. The number of cascaded subnetworks, N, is determined by the total cable length and the minimum unit length. The minimum unit length must be less than the minimum wavelength corresponding to the rising frequency of the PWM, typically taken as 0.1m. For a 2m cable, N=20.

[0054] Step 2, reconstruct the circuit model based on the network tearing method:

[0055] The network tearing method is used to process the above cascaded model to reconstruct the circuit model. First, the connection branches (i.e., the series impedances of each phase and ground) between each smallest unit and its next-level unit are torn in the middle. After tearing, half of the original impedance is incorporated into the "reserved sub-network" of the previous unit, and the other half forms an independent "torn branch." Each independent "reserved sub-network" contains a complete network of mutual impedances and capacitances. For ease of subsequent analysis, a connection point (usually the ground input point) is designated as the reference node in each reserved sub-network and defined as the reserved node. Figure 3 In the middle, Z 11 ~Z 44 For the self-impedance of each phase-retaining subnetwork, C 11 ~C 33 For each phase retaining subnetwork interphase capacitance, Z 12 ~Z 43 To preserve the mutual impedance in the subnetwork.

[0056] Step 3, determine the impedance measurement connection method:

[0057] Based on the predicted requirements (common-mode or differential-mode impedance), the input and output ports of the cable cascade model are connected in the corresponding manner. Figure 4 The connection method used to predict common-mode impedance is shown: all phase lines at the input are shorted, and all phase lines at the output are shorted.

[0058] Step 4, Write the circuit network matrix equations:

[0059] This step aims to establish system equations describing the entire post-tear circuit.

[0060] 1) List the relationship matrix describing the established cable cascade model circuit based on the network tearing method, following these steps:

[0061] First, list the association matrix A, which describes the relationships between nodes and branches within the preserved subnetwork. Figure 3 The circuit topology diagram of the preserved subnetwork is shown below, including the circuit lines containing nodes and branches, as follows: Figure 4 As shown, the nodes of the retained subnetwork are first numbered ①-⑦, and the branches are numbered 1-10. Then, the element A(i, j) in A represents the connection relationship between node i and branch j in the circuit diagram. The incidence matrix A of a single retained subnetwork can be represented as follows:

[0062] (1)

[0063] Furthermore, the correlation matrix formed by all retained subnetworks can be calculated. The correlation matrix A r1 and A rN To consider the input and output connection structure of the common-mode impedance circuit (reference) Figure 5 As shown, the three-phase signal line start nodes 1-3 of the three-phase four-core cable are shorted, the protective ground wire start node 4 of the three-phase four-core cable is grounded, the three-phase line ends are shorted, and the ground wire is left floating. This is an additional constraint.

[0064] Secondly, based on the circuit topology, construct the correlation matrix A describing the connection relationships between the torn branch and all retained sub-network nodes (excluding the retained nodes). d The correlation matrix A can be obtained. d It is a (7N-4)×(4N-4) matrix, and satisfies:

[0065] (2)

[0066] All other elements are equal to 0.

[0067] Similarly, based on the circuit topology, an association matrix describing the connection relationships between the torn branch and all retained nodes is then constructed. The correlation matrix can be obtained. It is an (N-1)×(4N-4) matrix that satisfies:

[0068] (3)

[0069] All other elements are equal to 0.

[0070] Finally, list the correlation matrix describing the connections between all reserved nodes and reserved sub-network nodes. The correlation matrix can be obtained. It is an (N-1)×(10N-5) matrix that satisfies:

[0071] (4)

[0072] All other elements are equal to 0.

[0073] The above four correlation matrices , , , The entire cable cascade circuit model based on the network tearing method is described.

[0074] 2) Obtain the admittance matrix of the circuit branch. The specific steps are as follows:

[0075] The branch admittance matrix Y of each retained subnetwork is listed below:

[0076] (5)

[0077] Furthermore, the branch admittance matrix formed by all retained subnetworks can be calculated. The branch admittance matrix Y r1 and Y rN To consider the input and output connection structure of the common-mode impedance circuit ( Figure 5 Listed as additional constraints.

[0078] in The self-admittance matrix, corresponding to the self-impedance and interphase capacitance in the retained subnetwork, can be expressed as follows:

[0079] (6)

[0080] in The controlled branch matrix, corresponding to the mutual impedances in the reserved subnetwork, can be expressed as follows:

[0081] (7)

[0082] Next, list the impedance matrix of the torn branch. , can be represented as follows:

[0083] (8)

[0084] 3) Furthermore, based on Ohm's law and Kirchhoff's voltage and current laws for circuits, the voltage and current equations for the circuit can be derived as follows:

[0085] (9)

[0086] J n U is a 1×(12N-9) matrix representing the input current source excitation of the retained sub-network nodes; no For the voltage of all reserved sub-network nodes, where U no (1,1) represents the voltage at node 1 of the input terminal; I d For all torn branch circuits; U nc For all reserved node voltages; the first matrix element on the left is calculated from the previously obtained relation matrix and admittance / impedance matrix.

[0087] Step 5, solve for the cable impedance characteristics:

[0088] Impedance is determined based on the excitation-response method, i.e., the total node voltage and current of the circuit under different excitations can be obtained through (10), thereby obtaining the impedance. In particular, when determining the common-mode impedance, a unit common-mode current source excitation input can be set, i.e.:

[0089] (10)

[0090] All other elements are 0.

[0091] Calculate the input node voltage U under this excitation. no (1,1) gives the common-mode impedance amplitude and phase of the cable.

[0092] Typically, the frequency band of interest is selected within 10k~100MHz. A sufficient number of frequency points are chosen (generally 500). The admittance / impedance values ​​at different frequencies are substituted into (5)~(8), and further substituted into (9) to obtain the common-mode impedance amplitude and phase at different frequencies. Plotting the impedance characteristics of all frequency points yields the complete common-mode impedance characteristic curve.

[0093] Figure 6The prediction results of the common-mode impedance of a 2m three-phase four-core cable presented in this invention are compared with those of an existing method (based on segmented multi-conductor cascade time-domain simulation). It can be seen that the predicted common-mode impedance results of the two methods are basically the same, and both have high accuracy compared with the measured results. The predicted common-mode resonant frequency is 16.08MHz, while the measured result is 15.42MHz, with an error of only 4.3%. This verifies the high accuracy of the present invention in predicting the high-frequency impedance characteristics of cables.

[0094] Figure 7 A comparison of the total calculation time for impedance at 500 frequency points using the present invention and an existing method (based on segmented multi-conductor cascade time-domain simulation) is presented for different cable lengths. For a 10m cable, the total calculation time of the present invention is reduced from tens of hours to less than 3 minutes, representing a several-thousand-fold improvement in computational efficiency. This verifies the rapid accuracy of the present invention in predicting the high-frequency impedance characteristics of cables.

[0095] Figure 8 The condition number of the network matrix solved by this invention under 100MHz operating conditions for different cable lengths is given. For all different cable lengths, the condition number of this invention is less than 10. 6 The order of magnitude, for a typical computer, the numerical resolution using floating-point operations is 10^10. -16 The magnitude is so large that the present invention has a ten-digit numerical accuracy under 100MHz conditions for different cable lengths, which verifies the good numerical robustness of the method.

[0096] Furthermore, as can be seen from the embodiments of the present invention, the present invention avoids the tedious modeling in circuit simulation software and the post-processing of the voltage and current obtained from the simulation to calculate the impedance amplitude and phase, which facilitates the high-precision and rapid prediction of the high-frequency impedance characteristics of the cable in the motor system design stage, thereby guiding the matching design and overvoltage risk assessment of the system.

[0097] Example 2: This example proposes a prediction device for implementing the method described in Example 1 of the present invention, comprising:

[0098] Model building unit, used to build a cascaded model of the minimum circuit units of a multi-conductor cable;

[0099] Branch decomposition unit, used to decompose the cascaded model into multiple retained sub-networks and tearing branches connecting these sub-networks based on the network tearing method;

[0100] Port connection unit, used to connect the input and output ports of the model in common mode or differential mode according to the impedance prediction type;

[0101] The network matrix equation writing unit is used to write network matrix equations based on circuit topology.

[0102] The impedance frequency characteristic solving unit is used to select multiple frequency points within the target frequency band for solving and obtain the impedance frequency characteristic curve of the cable.

[0103] Example 3: This example proposes an electronic system, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform the method steps of the present invention.

[0104] It should be noted that the electronic system can use terminal devices such as desktop computers, laptops, or cloud servers. Furthermore, terminal devices include, but are not limited to, processors and memory. For example, terminal devices can also include input / output devices, network access devices, and buses.

[0105] Furthermore, the processor can be a central processing unit (CPU). Of course, depending on the actual use, other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), off-the-shelf programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. can also be used. The general-purpose processor can be a microprocessor or any conventional processor, etc., and this application does not limit it in this regard.

[0106] Furthermore, the memory can be an internal storage unit of the terminal device, such as the hard disk or RAM of the terminal device, or an external storage device of the terminal device, such as a plug-in hard disk, smart memory card (SMC), secure digital card (SD), or flash memory card (FC) equipped on the terminal device. In addition, the memory can also be a combination of the internal storage unit and the external storage device of the terminal device. The memory is used to store computer programs and other programs and data required by the terminal device. The memory can also be used to temporarily store data that has been output or will be output. This application does not limit this.

[0107] Furthermore, through this electronic system, any one of the methods described in the above embodiments can be stored in the memory of the electronic system and loaded and executed on the processor of the terminal device for convenient use.

[0108] Example 4: This example proposes a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the steps of the method described in this invention.

[0109] It should be noted that the processing flows of embodiments 2, 3, and 4 correspond to the specific steps of the method provided in the embodiments of the present invention, and possess the corresponding functional modules and beneficial effects of the method. Technical details not described in detail in this embodiment can be found in the method provided in the embodiments of the present invention.

[0110] It should also be noted that the various specific technical features described in the above embodiments can be combined in any suitable manner without contradiction. To avoid unnecessary repetition, the present invention will not describe the various possible combinations separately.

Claims

1. A method for predicting the high-frequency impedance characteristics of cables based on the network tearing method, applicable to m-phase n-core cables, characterized in that, Includes the following steps: Construct a cascaded model of minimum circuit units for multiple conductors in a cable; Based on the network tearing method, the cascaded model is decomposed into multiple preserved sub-networks and tearing branches connecting these sub-networks; Depending on the impedance prediction type, the input and output ports of the model are connected in common-mode or differential-mode configurations. Write the network matrix equations based on the circuit topology; Multiple frequency points within the target frequency band are selected for solution to obtain the impedance-frequency characteristic curve of the cable. Specifically, the method for writing the network matrix equation includes: (1) List the correlation matrix: List the node-branch incidence matrix A of a single retained subnetwork, and then combine them to obtain the overall incidence matrix A of all retained subnetworks. r Among them, the correlation matrix A of the first and last subnetworks r1 and A rN External connection constraints of the input and output need to be considered, where N is the number of subnetworks; Write the correlation matrix A between the torn branch and all retained subnetwork nodes except the reference node. d It is a (7N-4)×(4N-4) matrix; List the correlation matrix between the torn branch and all reference nodes. It is an (N-1)×(4N-4) matrix; List the association matrix between all reference nodes and reserved subnetwork nodes. It is an (N-1)×(10N-5) matrix; (2) Write out the admittance matrix and impedance matrix: Write the branch admittance matrix Y of a single retained subnetwork, which is composed of the self-admittance matrices Y corresponding to the self-impedance and capacitance. em and the controlled branch matrix R corresponding to the mutual impedance m This is used to construct and combine the branch admittance matrix Y, which consists of all the retained subnetworks. r Among them, the branch admittance matrix Y of the first and last subnetworks r1 and Y rN External connection constraints of inputs and outputs need to be considered; List the impedance matrix Z of all the tear branches. d ; (3) Constructing system equations: Based on Kirchhoff's laws and the above matrix, a system matrix equation is established with node voltages and tear branch currents as variables. Its form is as follows: ； J n U is the excitation vector of the node current source. no For the voltage of all reserved sub-network nodes, U no (1,1) represents the voltage at node 1 of the input terminal; I d For all torn branch circuits; U nc Reserve the reference node voltage for all.

2. The method according to claim 1, characterized in that, The multi-conductor minimum circuit unit cascade model consists of N cascaded sub-networks with identical structures; each sub-network is a 2n-terminal network, containing n input ports and n output ports; each sub-network consists of n line self-impedances, n×(n-1) line mutual impedances, and all line-to-line capacitances based on the cable structure; wherein, the number of cascades N is determined according to the total cable length and the preset minimum unit length, and the minimum unit length must be less than one-tenth of the minimum wavelength of the frequency corresponding to the upper limit of the effective spectrum of the rising edge of the PWM voltage.

3. The method according to claim 1, characterized in that, The network tearing method specifically involves tearing the connection branch between each smallest circuit unit and its next-level unit in the middle. Half of the torn series impedance is incorporated into the previous unit to form a reserved sub-network, and the other half is used as an independent tearing branch. Each reserved sub-network is an independent module containing a complete mutual impedance and capacitance network. In each reserved sub-network, a reserved node is designated as a reference node for subsequent network equation writing.

4. The method according to claim 1, characterized in that, When predicting common-mode impedance, short-circuit all phase lines at the input and all phase lines at the output; when predicting differential-mode impedance, use the corresponding differential-mode connection.

5. The method according to claim 1, characterized in that, The method for solving the impedance frequency response curve is as follows: Select M frequency points within the target frequency band. For each frequency point, substitute the component parameters at that frequency and update the system matrix. By setting a unit excitation, solve the system equation to directly obtain the input impedance amplitude and phase at that frequency. After traversing all frequency points, the complete impedance amplitude-frequency and phase-frequency response curves are obtained.

6. The method according to claim 5, characterized in that, When determining the common-mode impedance, the first element of the node current source excitation vector is set to unit current, and the rest are set to 0, i.e., J n =1, calculate the 1-node voltage U under this excitation. no (1,1) gives the common-mode impedance amplitude and phase of the cable.

7. A prediction apparatus for implementing the method of any one of claims 1-6, characterized in that, include: Model building unit, used to build a cascaded model of the minimum circuit units of a multi-conductor cable; Branch decomposition unit, used to decompose the cascaded model into multiple retained sub-networks and tearing branches connecting these sub-networks based on the network tearing method; Port connection unit, used to connect the input and output ports of the model in common mode or differential mode according to the impedance prediction type; The network matrix equation writing unit is used to write network matrix equations based on circuit topology. The impedance frequency characteristic solving unit is used to select multiple frequency points within the target frequency band for solving and obtain the impedance frequency characteristic curve of the cable.

8. An electronic system comprising: At least one processor; And a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, characterized in that the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1-6.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, it implements the method as described in any one of claims 1 to 6.

Images