A deep reinforcement learning based anti-radiation layout optimization method

Abstract

The application provides an anti-radiation layout optimization method based on deep reinforcement learning, extracts a global state vector from a design file to constitute a multi-modal state space; models an optimization problem of an initial layout as a Markov decision process, deploys two agents as layout and wiring optimizers respectively, adjusts actions under the guidance of a reward by perceiving a layout state, optimizes the layout of sensitive devices and redundant structures, then performs wiring optimization to obtain an optimized layout of a current round, finally implements multi-objective joint verification on the optimized layout, and generates a reward signal feedback to the two agents to drive them to perform closed-loop iterative optimization to obtain a final layout. The application constructs an end-to-end deep reinforcement learning process, effectively coordinates the conflict between anti-radiation reinforcement requirements and complex process rules with the help of a fuse reward mechanism and intelligent decision-making throughout the whole process, realizes automatic generation of anti-radiation layout under FinFET process compliance, and significantly improves design efficiency and layout quality.

Description

Technical Field

[0001] This application belongs to the field of integrated circuit electronic design automation technology, specifically relating to a radiation-resistant layout optimization method based on deep reinforcement learning. Background Technology

[0002] Integrated circuit layout design is a crucial step in transforming a logic netlist into a physical geometry. Essentially, it's a combinatorial optimization problem involving finding the optimal solution within an extremely constrained solution space. As semiconductor manufacturing processes have evolved to the 16nm and below FinFET (Fin Field-Effect Transistor) node, the constraints and complexity of layout design have significantly increased. Furthermore, the radiation resistance requirements of chips in special applications such as aerospace and nuclear industries further complicate layout design.

[0003] The current mainstream practice in the industry is to use traditional EDA (Electronic Design Automation) tools, based on simulated annealing or genetic algorithms, to generate an initial layout, followed by manual or script-based post-processing adjustments. However, this traditional method has significant performance bottlenecks and application scenario limitations in practical applications: (1) Traditional algorithms rely on random search or fixed heuristic rules. In the discrete resolution space of FinFET process (such as coordinates needing to be integer multiples of fin pitch and unidirectional wiring of metal layer), the search process has a lot of redundant iterations, resulting in a long layout optimization cycle. Especially for large-scale integrated circuits, it often takes several days or even weeks to complete the optimization. (2) Traditional methods divide layout and wiring into independent stages for sequential optimization, lacking global collaborative prediction capabilities. For example, in order to pursue compact area, the devices are densely arranged in the layout stage, which will make it difficult to insert radiation shielding layer in the subsequent wiring stage, or the bottom metal (M1) will have DRC violations that are difficult to repair. The final layout's line length, congestion and other indicators are not good. (3) When additional constraints such as radiation resistance need to be added on the basis of the existing layout, traditional methods are difficult to dynamically balance the conflict between the new constraints and the original process rules and circuit performance. They often need to be manually adjusted repeatedly, which not only further extends the design cycle, but also makes it difficult to guarantee the consistency and reliability of the optimization results.

[0004] While traditional methods can generate initial layouts that meet basic manufacturability requirements, they are no longer sufficient to meet the demands of advanced processes and high-reliability scenarios in terms of optimization efficiency, layout quality, and adaptability to additional constraints. Therefore, there is an urgent need for a highly efficient optimization algorithm that can achieve precise optimization of placement and routing based on the initial layout generated by traditional methods through intelligent decision-making. Simultaneously, it should efficiently adapt to additional constraints such as radiation resistance, significantly improving the reliability and performance of the layout while ensuring process compliance. Summary of the Invention

[0005] To address the aforementioned problems in the existing technology, this application provides a radiation-resistant layout optimization method based on deep reinforcement learning. The technical problem to be solved by this application is achieved through the following technical solution: A radiation-resistant layout optimization method based on deep reinforcement learning includes: S100, Input the initial layout design file and extract the global state vector from the design file; S200, using the global state vector as the multimodal state space, and defining the optimization action space and a hierarchical reward function with a circuit breaker mechanism, the optimization problem of the initial layout is modeled as a Markov decision process; wherein, the optimization action space includes optimization actions for layout adjustment and routing optimization; S300, Deploy the first reinforcement learning agent as a layout optimizer, so that it perceives the initial layout from the multimodal state space, and based on the initial layout and guided by the hierarchical reward function, selects and executes optimization actions for layout adjustment from the optimization action space, adjusts the positions of sensitive devices and redundant structures in the initial layout and satisfies the constraints, and generates the layout-optimized layout. S400, deploy a second reinforcement learning agent as a routing optimizer, enabling it to perceive the initial routing from the multimodal state space, and select and execute optimization actions for routing optimization from the optimization action space according to the guidance of the hierarchical reward function, so as to optimize the routing of the layout after optimization to obtain the optimized layout of the current round. S500, perform multi-objective joint verification on the optimized layout of the current round to obtain the verification result, and use the verification result and the hierarchical reward function to generate a reward signal, which is fed back to the first reinforcement learning agent and the second reinforcement learning agent to drive the first reinforcement learning agent and the second reinforcement learning agent to perform closed-loop iterative optimization until the final layout that satisfies all preset constraints is output.

[0006] Beneficial effects: 1. This application uses an initial layout generated by traditional methods as a basis, avoiding blind searching from scratch. The intelligent agent accurately locates the defects and optimization space of the initial layout through multimodal state perception. The efficient strategy iteration of the PPO algorithm shortens the optimization cycle by more than 50%, reducing the optimization time of large-scale integrated circuits from several weeks to several days, significantly improving optimization efficiency. 2. This application designs a full-line collaborative optimization process, breaking down the independent optimization barriers between layout and routing. The intelligent agent can predict the impact of optimization actions on subsequent stages, and achieve reasonable layout of sensitive devices, accurate alignment of redundant structures, and efficient repair of routing violations based on the initial layout, thereby shortening the layout lines and reducing congestion. 3. This application addresses the additional constraint of radiation resistance by employing targeted strategies such as collaborative generation of shielding layers, isolation of sensitive devices, and insertion of virtual devices. This achieves an improvement in radiation resistance performance without compromising the compliance of the initial layout process, and can dynamically balance radiation resistance requirements with circuit performance without manual intervention. 4. This application designs a tiered reward function with a circuit breaker mechanism, strictly prohibits new process violations, and always bases the optimization process on the compliance of the initial layout, ensuring that the final output layout has zero DRC violations, a 100% LVS verification pass rate, and full assurance of manufacturability.

[0007] The present application will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0008] Figure 1 This is a flowchart illustrating a radiation-resistant layout optimization method based on deep reinforcement learning provided in this application; Figure 2 This is a schematic diagram illustrating the process of a radiation-resistant layout optimization method based on deep reinforcement learning provided by the present invention; Figure 3 This is a flow graph of the multimodal state-sensing data in this invention; Figure 4 This is a flowchart of the reward calculation based on the circuit breaker mechanism in this invention; Figure 5 This is a schematic diagram of the intelligent layout and wiring optimization strategy in this invention. Detailed Implementation

[0009] The present application will be described in further detail below with reference to specific embodiments, but the implementation of the present application is not limited thereto.

[0010] like Figure 1 As shown, this application provides a radiation-resistant layout optimization method based on deep reinforcement learning, including: S100, Input the initial layout design file and extract the global state vector from the design file; This application addresses the initial layout of advanced process node (16nm and below FinFET) integrated circuits generated using traditional methods. The input consists of a gate-level netlist after logic synthesis and a FinFET process design file. The output is a GDSII layout free of DRC violations and meeting radiation resistance specifications, i.e., the final layout. This application transforms the complex layout design problem into a mathematical state perceptible to an intelligent agent. To simultaneously capture the logical connections of the circuit and the physical space constraints of the layout, a multimodal feature extraction network can be used to propose a global state vector.

[0011] S200, using the global state vector as the multimodal state space, and defining the optimization action space and a hierarchical reward function with a circuit breaker mechanism, the optimization problem of the initial layout is modeled as a Markov decision process; wherein, the optimization action space includes optimization actions for layout adjustment and routing optimization; S300, Deploy the first reinforcement learning agent as a layout optimizer, so that it perceives the initial layout from the multimodal state space, and based on the initial layout and guided by the hierarchical reward function, selects and executes optimization actions for layout adjustment from the optimization action space, adjusts the positions of sensitive devices and redundant structures in the initial layout and satisfies the constraints, and generates the layout-optimized layout. S400, deploy a second reinforcement learning agent as a routing optimizer, enabling it to perceive the initial routing from the multimodal state space, and select and execute optimization actions for routing optimization from the optimization action space according to the guidance of the hierarchical reward function, so as to optimize the routing of the layout after optimization to obtain the optimized layout of the current round. S500, perform multi-objective joint verification on the optimized layout of the current round to obtain the verification result, and use the verification result and the hierarchical reward function to generate a reward signal, which is fed back to the first reinforcement learning agent and the second reinforcement learning agent to drive the first reinforcement learning agent and the second reinforcement learning agent to perform closed-loop iterative optimization until the final layout that satisfies all preset constraints is output.

[0012] In one specific embodiment of this application, S100 includes: S110, Input the initial layout design file; S120, using a graph neural network to extract topological feature vectors from the circuit netlist of the design file and using a convolutional neural network to extract geometric feature vectors from the design file; For the circuit netlist in the design document, a graph neural network (GNN) is used to extract topological features. The netlist is then parsed into a directed graph. ,in Represents standard units (such as NAND gates and flip-flops). This represents a signal connection. For each node in the diagram... Initialize a feature vector This vector encodes the device type, driving capability, area, and whether it is a radiation-sensitive node. Subsequently, the GraphSAGE algorithm is used for... Layer neighborhood aggregation, the first Layer node embedding vector The calculation formula is as follows: ; in, Represents a node The set of neighboring nodes, It is the average aggregation function. For a trainable weight matrix, This is a non-linear activation function. After... After layer aggregation, a topological feature vector is generated. It contains contextual information about the device in the circuit logic, including information related to node function, connectivity, sensitivity, and triple modular redundancy (TMR) structure.

[0013] For the physical layout, this application employs a deep convolutional neural network (CNN) to extract geometric features. The current layout region is discretized into a resolution of [resolution value missing]. Multichannel tensors The tensor channels are designed as follows: channels 1 to 3 represent the mask distribution of fins, polysilicon, and active areas (OD), respectively; channels 4 to 10 represent the wiring occupancy of layers Metal-1 to Metal-7, respectively; and channel 11 is a congestion heatmap. The system uses ResNet-18 as the backbone network to process this tensor and outputs a geometric feature vector. This geometric feature vector includes fin distribution density, fin alignment deviation, M1 layer metal mask distribution, and potential shielding layer coverage area, used to characterize the physical space constraints and optimization potential of the initial layout.

[0014] S120, the topological feature vector and the geometric feature vector are fused into a global state vector through an attention mechanism.

[0015] This application uses a multi-head attention mechanism to fuse the topological feature vector output by the GNN with the geometric feature vector output by the CNN to generate a global state vector. This global state vector serves as the input to the reinforcement learning policy network, enabling the agent to simultaneously perceive both the logical structural defects and physical congestion issues of the initial layout, thus providing support for precise optimization.

[0016] In one specific embodiment of this application, S200 includes: S210, Define the global state vector as a multimodal state space; S220 defines layout optimization actions and routing optimization actions, and combines the two into an optimization action space; This application addresses the characteristics of incremental optimization by designing the optimization action space as a discretized fine-tuning instruction set, rather than continuous coordinate regression, to reduce the search difficulty. Layout optimization actions: .

[0017] Cabling optimization actions: .

[0018] In the above formula, Move the component slightly within the layout. , This indicates the distance traveled in the horizontal direction. This indicates the distance moved in the vertical direction. This indicates that components are aligned to the layout grid, which is typically used to maintain a neat layout and reduce wiring conflicts. This indicates the insertion of a virtual node or placeholder, often used to reserve space or assist in subsequent wiring. This indicates that an existing section of wiring has been removed in order to allow for rewiring. This indicates the addition of a shielding layer or protection for the traces, often used to reduce signal interference (such as crosstalk and electromagnetic interference). This indicates the insertion of a jumper (crossover) to resolve wiring conflicts or optimize signal paths. This indicates the location for fine-tuning the wiring path, typically used to optimize wiring density or avoid obstacles.

[0019] S230 defines a tiered reward function with a circuit breaker mechanism; To resolve the strong conflict between the hard constraints of FinFET process and the soft constraints of radiation resistance, this application designs a hierarchical dynamic reward function with a circuit breaker mechanism. The hierarchical reward function with a circuit breaker mechanism comprises two levels: a first level is a hard constraint circuit breaker layer, and a second level is a soft constraint guiding layer. The operating logic of the hard constraint circuit breaker layer is as follows: for each optimization action, it checks whether the optimization action causes the initial layout to introduce new process rules; if so, the hierarchical reward function outputs a truncation penalty reward. (Can be set to -100), and force termination or rollback of the optimization action to ensure that the optimization process does not count as a violation; the process rules are: whether the device coordinates are not aligned with the fin grid, whether the M1 layer violates the unidirectional horizontal routing rule, and whether the metal spacing is less than the minimum value defined by the process. .

[0020] The mathematical expression for truncated punishment-reward is: ; In the formula, This indicates the number of Design Rule Check (DRC) violations added to the initial layout after the optimization action is executed.

[0021] The operating logic of the soft constraint guidance layer is as follows: for each optimization action, if the optimization action does not cause the initial layout to have new process rules and conforms to the original process rules, then a positive guidance reward is calculated based on the radiation resistance index and circuit performance index, and fed back to the optimization action.

[0022] Only when At that time, the system calculates a positive guidance reward, which is a weighted average of radiation resistance and circuit performance indicators: ; in This indicates a positive incentive or reward. Initial map line length Optimized total wiring length These are weighting coefficients, which can be used to optimize specific metrics. This indicates the actual spacing between redundant components in the TMR structure. This represents the safety spacing threshold for redundant devices in a TMR structure. This indicates the compliance factor of the shielding layer for sensitive signal lines. (Setting) Prioritize radiation resistance.

[0023] S240, based on the multimodal state space, the optimized action space, and the hierarchical reward function with a circuit breaker mechanism, the optimization problem of the initial layout is modeled as a Markov decision process.

[0024] In one specific embodiment of this application, S300 includes: S310, Deploy the first reinforcement learning agent as a layout optimizer, enabling it to perceive the initial layout from the multimodal state space; S320, based on the initial layout, the near-end strategy optimization algorithm, guided by the hierarchical reward function, selects and executes optimization actions for the layout from the optimization action space, thereby performing sensitive device directional migration, redundant device alignment, and virtual device insertion on the initial layout to obtain the layout-optimized layout.

[0025] This application utilizes a placement agent and employs the Proximal Policy Optimization (PPO) algorithm to perform minor adjustments based on the initial placement. The agent adjusts the placement based on the global state vector. Output action probability distribution And sample and execute corresponding optimization actions.

[0026] The operation logic of the directed migration is as follows: the sensitive devices in the initial layout are migrated to a designated area with lower radiation interference; the operation logic of the redundant device alignment is as follows: for device groups with redundant design, they are forcibly constrained to a position that meets the process grid alignment requirements, and the spacing between devices is ensured to meet the radiation isolation requirements; the operation logic of the virtual device insertion is as follows: near the predicted high-risk circuit nodes, virtual isolation or buffer structures are inserted to enhance anti-interference capability.

[0027] Specifically, the agent executes a strategy combining macroscopic partitioning and microscopic adsorption. For macroscopic placement, based on sensitivity markers in the input state, the agent's output action migrates critical sensitive devices to a low-radiation interference region in the center of the layout. For microscopic placement, the agent executes strict grid adsorption. Let the fin pitch of the FinFET process be... The polycrystalline silicon pitch is The coordinates output by the agent The mandatory constraint is: ; In the formula, Represents a set of integers.

[0028] For the identified triple modular redundancy (TMR) device group, the agent performs a group alignment action, which involves determining the coordinates of the three redundant units at once. and enforce constraints At the same time, constraints (Meets radiation protection requirements). , They represent the first The circuit unit and the first The horizontal coordinates of each circuit unit This indicates the safe isolation distance, which is a preset parameter.

[0029] In one specific embodiment of this application, S400 includes: S410, Deploy a second reinforcement learning agent as a wiring optimizer, enabling it to perceive the initial wiring from the multimodal state space; S420, based on the initial routing, the near-end strategy optimization algorithm, guided by the hierarchical reward function, selects and executes optimization actions for the routing from the optimization action space, thereby performing key masking and violation increment repair on the layout after optimization, and obtaining the optimized layout of the current round.

[0030] The critical shielding operation logic is as follows: when planning the routing path for critical sensitive signal lines, a grounded shielding layer is simultaneously planned and generated on adjacent routing tracks or metal layers; if the shielding layer causes via violations, the geometry of the shielding layer and the local routing path of the signal lines are dynamically adjusted. The operational logic for incremental violation repair is as follows: For the bottom metal layer constrained by unidirectional routing rules, if there is a design rule violation, rerouting repair is performed within the local area of ​​the violation point. This rerouting repair includes inserting jumpers, track shifting, and shortening the line tail. The operation logic for inserting jumpers is as follows: vias are generated at both ends of the violation line segment to jump the signal upwards to the second layer, which allows vertical routing, thus avoiding the directional restrictions of the first metal layer. The operation logic for track shifting is as follows: the entire line segment is shifted to an adjacent empty horizontal track. The operation logic for shortening the line tail is as follows: the redundant portion of the line segment is shortened.

[0031] During the cabling phase, the cabling agent is responsible for signal interconnection and incremental repair based on the initial cabling. The first step is collaborative planning of signals and shielding. When the agent plans a path for a signal line marked as sensitive... At the same time, it not only searches for connected paths, but also simultaneously detects adjacent tracks (Track IDs) along that path. The availability of the signal line is assessed. The agent's policy network outputs a composite action instructing the generation of a grounded shielded metal wire on an adjacent track while simultaneously laying the signal line metal. If an adjacent track on the direct path is blocked, the agent will automatically explore an alternative path, sacrificing some line length for the integrity of the shielding structure. This directly responds to the reward function. The setting with higher weight.

[0032] Because FinFET technology requires the underlying metal (M1) to be strictly unidirectional, traditional maze routing algorithms are prone to vertical violations at pin access points. The agent of this invention does not adopt a complete dismantling and rewiring approach, but instead adopts an incremental repair strategy. When a non-horizontal line segment is detected in the M1 layer, the agent defines a local observation window (such as a 5×5 grid) centered on the violation point and performs a minimally invasive action sequence within this window. The action sequence includes: (1) Inserting a jumper: generating vias at both ends of the violation line segment to jump the signal upwards to the M2 layer, which allows vertical routing, thus avoiding the directional restrictions of the M1 layer; (2) Track translation: translating the entire line segment to an adjacent free horizontal track. The agent uses reinforcement learning to try and find the action combination that can eliminate DRC violations and introduce the minimum parasitic parameters. (3) Shortening the line tail. All repair actions do not destroy the overall connectivity of the initial routing.

[0033] In one specific embodiment of this application, S500 includes: S510 performs process design rule checks, circuit consistency checks, radiation resistance verification, and parasitic parameter verification on the optimized layout in parallel to obtain verification results; S520, if there are residual violations in the verification results, the type and physical location information of the residual violations are converted into strong negative reward signals and fed back to the first reinforcement learning agent or the second reinforcement learning agent, so that it can automatically lock the violation area and initiate a new round of incremental violation repair. S530, repeatedly drive the first reinforcement learning agent and the second reinforcement learning agent until the final layout that satisfies all preset constraints is output.

[0034] The entire optimization process in this application employs the Proximal Policy Optimization (PPO) algorithm for end-to-end training. An experience replay buffer is maintained to record the quadruplets at each time step. .in, Indicates that the agent is in the first... The optimized action vector is taken step by step. This represents the reward value for environmental feedback. Indicates the first The global state vector for each execution. After the first step, the advantage function is calculated using generalized advantage estimation (GAE). And update the policy network parameters by maximizing the following objective function. : ; in, This represents the objective function of PPO. Represents the expectation operator within a finite time step. The ratio of the old to the new strategies. This indicates the cutoff range hyperparameter. This represents the truncation function.

[0035] Through this online feedback mechanism, the agent can quickly converge from early random exploration to a stable optimal strategy. The training termination condition is set as follows: the average reward value tends to stabilize after 100 consecutive rounds, the number of DRC violations in the generated layout is zero, and the radiation resistance index meets the design specifications. The final output is a final layout file conforming to the GDSII standard, which can be directly used for subsequent physical verification (LVS / DRC) and tape-out without manual modification.

[0036] This application provides a radiation-hardened layout optimization method based on deep reinforcement learning. It extracts global state vectors from the design file to construct a multimodal state space. The optimization problem of the initial layout is modeled as a Markov decision process, deploying two agents as placement and routing optimizers, respectively. By perceiving the layout state and performing adjustment actions under reward guidance, the agents optimize the placement of sensitive devices and redundant structures. Subsequently, routing optimization is performed to obtain the optimized layout for the current round. Finally, multi-objective joint verification is performed on the optimized layout, generating reward signals that are fed back to the two agents to drive them to perform closed-loop iterative optimization to obtain the final layout. This invention constructs an end-to-end deep reinforcement learning process. With the help of a circuit breaker reward mechanism and intelligent decision-making throughout the process, it effectively coordinates the conflict between radiation hardening requirements and complex process rules, achieving automated generation of radiation-hardened layouts under FinFET process compliance, significantly improving design efficiency and layout quality.

[0037] It is worth noting that the terms "first" and "second" in this application are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0038] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of this application and should not be construed as limiting the specific implementation of this application to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of this application, and all such modifications or substitutions should be considered within the scope of protection of this application.

Claims

1. A radiation-resistant layout optimization method based on deep reinforcement learning, characterized in that, include: S100, Input the initial layout design file and extract the global state vector from the design file; S200, using the global state vector as the multimodal state space, and defining the optimization action space and a hierarchical reward function with a circuit breaker mechanism, the optimization problem of the initial layout is modeled as a Markov decision process; wherein, the optimization action space includes optimization actions for layout adjustment and routing optimization; S300, Deploy the first reinforcement learning agent as a layout optimizer, so that it perceives the initial layout from the multimodal state space, and based on the initial layout and guided by the hierarchical reward function, selects and executes optimization actions for layout adjustment from the optimization action space, adjusts the positions of sensitive devices and redundant structures in the initial layout and satisfies the constraints, and generates the layout-optimized layout. S400, deploy a second reinforcement learning agent as a routing optimizer, enabling it to perceive the initial routing from the multimodal state space, and select and execute optimization actions for routing optimization from the optimization action space according to the guidance of the hierarchical reward function, so as to optimize the routing of the layout after optimization to obtain the optimized layout of the current round. S500, perform multi-objective joint verification on the optimized layout of the current round to obtain the verification result, and use the verification result and the hierarchical reward function to generate a reward signal, which is fed back to the first reinforcement learning agent and the second reinforcement learning agent to drive the first reinforcement learning agent and the second reinforcement learning agent to perform closed-loop iterative optimization until the final layout that satisfies all preset constraints is output.

2. The radiation-resistant layout optimization method based on deep reinforcement learning according to claim 1, characterized in that, S100 includes: S110, Input the initial layout design file; S120, using a graph neural network to extract topological feature vectors from the circuit netlist of the design file and using a convolutional neural network to extract geometric feature vectors from the design file; S120, the topological feature vector and the geometric feature vector are fused into a global state vector through an attention mechanism.

3. The radiation-resistant layout optimization method based on deep reinforcement learning according to claim 1, characterized in that, S200 includes: S210, Define the global state vector as a multimodal state space; S220 defines layout optimization actions and routing optimization actions, and combines the two into an optimization action space; S230, Define a hierarchical reward function with a circuit breaker mechanism. The hierarchical reward function with a circuit breaker mechanism includes two levels: the first level is a hard constraint circuit breaker layer, and the second level is a soft constraint guiding layer. S240, based on the multimodal state space, the optimized action space, and the hierarchical reward function with a circuit breaker mechanism, the optimization problem of the initial layout is modeled as a Markov decision process.

4. The radiation-resistant layout optimization method based on deep reinforcement learning according to claim 3, characterized in that, The operating logic of the hard-constraint circuit breaker layer is as follows: For each optimization action, it is checked whether the optimization action causes the initial layout to have new process rules. If so, the hierarchical reward function outputs a truncated penalty reward and forcibly terminates or rolls back the optimization action to ensure that the optimization process is not counted as a violation. The operating logic of the soft constraint guidance layer is as follows: For each optimization action, if the optimization action does not result in the introduction of new process rules in the initial layout and conforms to the original process rules, a positive guidance reward is calculated based on the radiation resistance index and circuit performance index and fed back to the optimization action.

5. The radiation-resistant layout optimization method based on deep reinforcement learning according to claim 1, characterized in that, The S300 includes: S310, Deploy the first reinforcement learning agent as a layout optimizer, enabling it to perceive the initial layout from the multimodal state space; S320, based on the initial layout, the near-end strategy optimization algorithm, guided by the hierarchical reward function, selects and executes optimization actions for the layout from the optimization action space, thereby performing sensitive device directional migration, redundant device alignment, and virtual device insertion on the initial layout to obtain the layout-optimized layout.

6. The radiation-resistant layout optimization method based on deep reinforcement learning according to claim 5, characterized in that, The operation logic of the targeted migration is as follows: sensitive devices in the initial layout are migrated to designated areas with lower radiation interference; the operation logic of the redundant device alignment is as follows: for device groups with redundant designs, they are forcibly constrained to positions that meet the process grid alignment requirements, and the spacing between devices is ensured to meet the radiation isolation requirements; the operation logic of the virtual device insertion is as follows: near the predicted high-risk circuit nodes, virtual isolation or buffer structures are inserted to enhance anti-interference capabilities.

7. The radiation-resistant layout optimization method based on deep reinforcement learning according to claim 1, characterized in that, The S400 includes: S410, Deploy a second reinforcement learning agent as a wiring optimizer, enabling it to perceive the initial wiring from the multimodal state space; S420, based on the initial routing, the near-end strategy optimization algorithm, guided by the hierarchical reward function, selects and executes optimization actions for the routing from the optimization action space, thereby performing key masking and violation increment repair on the layout after optimization, and obtaining the optimized layout of the current round.

8. The radiation-resistant layout optimization method based on deep reinforcement learning according to claim 7, characterized in that, The critical shielding operation logic is as follows: when planning the routing path for critical sensitive signal lines, a grounded shielding layer is simultaneously planned and generated on adjacent routing tracks or metal layers; if the shielding layer causes via violations, the geometry of the shielding layer and the local routing path of the signal lines are dynamically adjusted. The operation logic of the incremental repair of violations is as follows: For the bottom metal layer constrained by the unidirectional wiring rule, if there is a violation of the design rule, the rerouting repair is performed in the local area of ​​the violation point; wherein, the rerouting repair includes inserting jumpers, track translation and shortening the tail of the line.

9. The radiation-resistant layout optimization method based on deep reinforcement learning according to claim 8, characterized in that, The operation logic of the inserted jumper is as follows: through holes are generated at both ends of the non-compliant wire segment to jump the signal upward to the second layer of transmission that allows vertical wiring, thus avoiding the directional restriction of the first metal layer; The operational logic for track translation is as follows: the entire line segment is translated to an adjacent empty horizontal track; The operating logic for shortening the line tail is: shorten the redundant part of the line segment.

10. The radiation-resistant layout optimization method based on deep reinforcement learning according to claim 7, characterized in that, The S500 includes: S510 performs process design rule checks, circuit consistency checks, radiation resistance verification, and parasitic parameter verification on the optimized layout in parallel to obtain verification results; S520, if there are residual violations in the verification results, the type and physical location information of the residual violations are converted into strong negative reward signals and fed back to the first reinforcement learning agent or the second reinforcement learning agent, so that it can automatically lock the violation area and initiate a new round of incremental violation repair. S530, repeatedly drive the first reinforcement learning agent and the second reinforcement learning agent until the final layout that satisfies all preset constraints is output.

Images