Chip top layer design method and device, storage medium and electronic equipment

Abstract

A chip top layer design method and device, a storage medium and an electronic device are disclosed, and relate to the field of chips. The method comprises the following steps: determining position information of a plurality of hardware units in a chip top layer according to layout design information of the chip; determining a level fixed node and connection configuration information of the chip top layer according to function implementation information of the chip; determining a wiring mode of the plurality of hardware units of the chip top layer according to the level fixed node, the connection configuration information and the position information of the plurality of hardware units in the chip top layer; and generating a top layer design code of the chip according to the wiring mode and the position information of the plurality of hardware units in the chip top layer. The disclosure can improve the efficiency of designing the chip top layer based on Top free.

Description

Technical Field

[0001] This disclosure relates to the field of chips, specifically to a top-level design method and apparatus for chips, a storage medium, and an electronic device. Background Technology

[0002] In the field of chip design, top-level design, as the core link connecting chip functional modules with physical implementation and system verification, directly determines the chip's R&D cycle through its code generation efficiency. Currently, when designing chip top-level structures based on the "top-free" requirement, efficiency is generally low, making it difficult to meet the needs of rapid chip iteration. Summary of the Invention

[0003] To address the aforementioned technical issues, this disclosure provides a top-free top-level design method to improve the efficiency of designing chip top-level structures based on top-free requirements.

[0004] A first aspect of this disclosure provides a top-level design method for a chip, comprising: determining the location information of multiple hardware units in the top layer of the chip based on the chip's layout design information; determining the level-fixed nodes and connection configuration information of the top layer of the chip based on the chip's functional implementation information; determining the routing method of the multiple hardware units in the top layer of the chip based on the level-fixed nodes, connection configuration information, and the location information of the multiple hardware units in the top layer of the chip; and generating the top-level design code of the chip based on the routing method and the location information of the multiple hardware units in the top layer of the chip.

[0005] A second aspect of this disclosure provides a top-level design apparatus for a chip, comprising: The first determining module is used to determine the position information of multiple hardware units in the top layer of the chip based on the chip layout design information; The second determining module is used to determine the level fixed node and connection configuration information of the chip's top layer based on the chip's functional implementation information; The third determining module is used to determine the wiring method of multiple hardware units at the top layer of the chip based on the level fixed node, connection configuration information and the location information of multiple hardware units; The generation module is used to generate the top-level design code of the chip based on the wiring method and the location of multiple hardware units.

[0006] A third aspect of this disclosure provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the top-level design method of the chip described in the first aspect.

[0007] A fourth aspect of this disclosure provides an electronic device comprising: a processor; a memory for storing processor-executable instructions; and a top-level design method for the processor to read the executable instructions from the memory and execute the instructions to implement a chip according to the first aspect of this disclosure.

[0008] A fifth aspect of this disclosure provides a computer program product that, when executed by an instruction processor, performs a top-level design method for a chip according to the first aspect of this disclosure.

[0009] The technical solution provided in this disclosure can determine the position information of multiple hardware units in the top layer of the chip based on the chip layout design information; then, based on the chip's functional implementation information, it can determine the level fixing nodes and connection configuration information of the top layer of the chip; based on the level fixing nodes, connection configuration information, and the position information of multiple hardware units in the top layer of the chip, it can determine the routing method of multiple hardware units in the top layer of the chip; finally, based on the routing method and the position information of multiple hardware units in the top layer of the chip, it can generate the top-level design code of the chip. Therefore, this disclosure can realize an automated chip top-level design process, avoiding the tedious process of manually adjusting the position of hardware units, level fixing nodes, and routing, effectively shortening the design cycle of the top-level design code and meeting the needs of rapid chip iteration. Attached Figure Description

[0010] Figure 1 This is a schematic diagram of the top layer of the chip in the publicly disclosed "Top Free" implementation scheme.

[0011] Figure 2 This is a schematic flowchart of a top-level design method for a chip provided in an exemplary embodiment of this disclosure.

[0012] Figure 3 This is a schematic diagram of multiple functional areas at the top layer of the chip.

[0013] Figure 4 This is a flowchart illustrating a top-level design method for a chip provided in another exemplary embodiment of this disclosure.

[0014] Figure 5 This is a schematic diagram of the setting of level fixed nodes in the top-level design method of a chip provided by an exemplary embodiment of this disclosure.

[0015] Figure 6A This is a schematic diagram showing the connection between two physically adjacent hardware units in the top-level design method of a chip provided by an exemplary embodiment of this disclosure.

[0016] Figure 6B This is a schematic diagram showing the connection between two hardware units that are not physically adjacent in the top-level design method of a chip provided by an exemplary embodiment of this disclosure.

[0017] Figure 7 This is a schematic diagram illustrating the connection of hardware units in a one-to-many connection scenario in the top-level design method of a chip provided by an exemplary embodiment of this disclosure.

[0018] Figure 8 This is a flowchart illustrating a top-level design method for a chip provided in yet another exemplary embodiment of this disclosure.

[0019] Figure 9 This is a flowchart illustrating a top-level design method for a chip provided in yet another exemplary embodiment of this disclosure.

[0020] Figure 10 This is a flowchart illustrating a top-level design method for a chip provided in yet another exemplary embodiment of this disclosure.

[0021] Figure 11 This is a schematic diagram illustrating the connection relationship between multiple hardware units in an example of a top-level chip design method provided in another exemplary embodiment of this disclosure.

[0022] Figure 12 This is a flowchart illustrating a top-level design method for a chip provided in yet another exemplary embodiment of this disclosure.

[0023] Figure 13 This is a flowchart illustrating a top-level design method for a chip provided in yet another exemplary embodiment of this disclosure.

[0024] Figure 14 This is a schematic diagram of various wiring methods in the top-level design method of a chip provided in yet another exemplary embodiment of this disclosure.

[0025] Figure 15 This is a flowchart illustrating a top-level design method for a chip provided in yet another exemplary embodiment of this disclosure.

[0026] Figure 16 This is a schematic diagram illustrating how a chip top-level design method, provided by another exemplary embodiment of this disclosure, divides multiple functional modules in the top level to obtain multiple hardware units.

[0027] Figure 17 This is a schematic diagram of the structure of a top-level design device for a chip provided in an exemplary embodiment of this disclosure.

[0028] Figure 18 This is a structural diagram of an electronic device provided in an exemplary embodiment of this disclosure. Detailed Implementation

[0029] To explain this disclosure, exemplary embodiments of the disclosure will now be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the disclosure, and not all of them. It should be understood that the disclosure is not limited to exemplary embodiments.

[0030] It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of this disclosure.

[0031] Application Overview In related technologies, the physical floor plan of a chip is a multi-level structure, including a root level and at least one lower level below the root level. The root level is the foundation and framework for the entire physical floor plan planning. Chip-level global constraints (area, power consumption, timing, packaging adaptation, etc.) and resource allocation (power backbone, cross-area interconnect channels, etc.) are all determined by the root level and passed down from top to bottom to all lower levels, which are nested within the physical boundaries of the root level. In other words, the root level establishes a unified definition standard and implementation framework for the chip's physical planning. Based on the attributes of the root level, it is referred to as the top level of the chip.

[0032] As chip scale continues to increase, a "Top-Free" implementation scheme has been proposed to reduce chip iteration cycles, improve area utilization, and enhance feasibility. The core idea of ​​"Top-Free" is that the top layer of the chip no longer includes any logic circuits, but serves only as a physical interconnect and integration platform. All logical functions are implemented in pre-designed and verified hardware units (i.e., "Harden"). In this scenario, the top layer includes all lower-level hardware units, but the top layer itself does not directly define or host any hardware units (i.e., lower-level hardware units are subdivided entities within the top-level physical framework). The function of the top layer is strictly limited to physically connecting and globally routing the hardware units within it (i.e., all lower-level hardware units). Therefore, quickly obtaining top-level design code that meets the "Top-Free" requirements becomes crucial for shortening chip iteration cycles.

[0033] In practice, manually completing the physical assembly of hardware units and the routing logic requires designers with extensive chip design experience and a significant amount of time for repeated debugging and verification. This is not only labor-intensive but also prone to human error, making it difficult to meet the demands of rapid chip iteration. This disclosure provides a top-level chip design method and apparatus, a storage medium, and an electronic device. It enables the rapid generation of top-level chip design code through an automated process, automating the physical assembly of hardware units and global routing planning, thus providing strong support for rapid chip iteration.

[0034] Exemplary System Figure 1 This is a schematic diagram of the top layer of the chip in the "Top Free" implementation scheme.

[0035] like Figure 1 As shown, in the physical layout of the chip, the top layer 101 includes multiple hardware units 1011, which include all the hardware units of the lower levels in the physical layout.

[0036] The function of the top-level unit 101 is strictly limited to the physical interconnection and global routing of multiple hardware units 1011 within the top level. All logical functions (such as combinational and sequential logic) are encapsulated in the hardware units of lower levels. From a hierarchical perspective, the top-level unit 101 is a structural level responsible only for physical interconnection, while logical operations are entirely implemented in the hardware units of lower levels. Therefore, the top-level unit 101 does not contain logic circuits, nor does it contain level-fixed nodes that provide level inputs for logic circuits.

[0037] Hardware unit 1011 is a unit that is pre-designed, verified, and solidified (with fixed form and function, and cannot be changed in subsequent processes) into a physical entity in chip design, possessing independent functional logic and physical boundaries. Hardware unit 1011 can be a processor core, interface controller, memory, accelerator, input / output buffer, interrupt controller, direct memory access (DMA) controller, etc.

[0038] For example, the processor core may be a central processing unit (CPU) core, a graphics processing unit (GPU) core, a digital signal processor (DSP) core, etc.

[0039] For example, the interface controller may be a Universal Serial Bus (USB) controller, a Serial Peripheral Interface (SPI) controller, an Inter-Integrated Circuit (I2C) controller, an Ethernet controller, a Universal Asynchronous Receiver / Transmitter (UART) controller, etc.

[0040] For example, the memory may be static random-access memory (SRAM), dynamic random-access memory (DRAM), flash memory, etc.

[0041] For example, an accelerator may be a neural network processor (NPU), a tensor processing unit (TPU), a cryptographic accelerator, etc., used to accelerate specific types of computing tasks.

[0042] Exemplary methods Figure 2 This is a schematic flowchart of a top-level chip design method provided in an exemplary embodiment of this disclosure. This embodiment can be applied to servers or terminals, such as... Figure 2 As shown, the method includes the following steps S210~S240.

[0043] S210: Based on the chip layout design information, determine the location information of multiple hardware units in the top layer of the chip.

[0044] Chip layout design information can include information related to chip layout, such as the chip's physical boundaries, functional partitions, and the physical dimensions of hardware units.

[0045] For example, in chip layout design information, physical boundaries are typically defined by the coordinate range of rectangles or polygons, representing the maximum physical size of the chip's top layer; functional partitions can be regions that carry different functions, obtained by dividing the top layer according to the chip's application scenarios and performance requirements. For example, the computing core area (such as...) Figure 3 Functional area A), storage area (such as...) Figure 3 Functional area B), interface area (such as...) Figure 3 Functional area C), and power management area (such as Figure 3 Functional areas (such as D) can be integrated into each functional area. For example, the computing core area can house high-performance computing hardware units such as CPU cores and / or GPU cores; the storage area can house storage hardware units such as SRAM and / or DRAM; the interface area can house interface controller hardware units such as USB controllers and / or Ethernet controllers; and the power management area can house power management units (PMUs) and / or level conversion units, etc., for power and level adaptation.

[0046] The physical dimensions of a hardware unit can include physical parameters such as its length and width. When determining the location information of multiple hardware units in the top layer of the chip, the physical dimensions of the hardware can be used to ensure a reasonable arrangement of different hardware units within their corresponding functional areas. For example, if the hardware unit to be housed in the computing core area is a CPU core, and the location of the computing core area in the layout design information is limited to the central region of the top layer, and the area of ​​this central region must meet the placement requirements of at least two CPU cores, then two CPU cores are allocated to this central region, and the position coordinate range of each of the two CPU cores is determined based on the length and width of the central region and the physical dimensions of the CPU cores.

[0047] Layout design information can also include the priority weights of hardware units. When determining the location of multiple hardware units in the top layer of the chip, their priority weights can also be used to determine their location. For example, the CPU core in the computing core area has strict timing latency requirements, so its priority weight can be set to the highest level. When determining the location of multiple hardware units in the top layer of the chip, the CPU core can be preferentially allocated to the core area with the least signal interference and the shortest interconnect path within the physical boundary of the top layer, based on its priority weight. Other hardware units in the computing core area can then be allocated sequentially to the associated areas around the CPU core according to their priority weights, from high to low, ensuring the interconnection efficiency and stability of the hardware units.

[0048] Layout design information can also include the minimum spacing between hardware units to avoid manufacturing risks such as photolithography errors and metal layer short circuits caused by overly compact hardware units. When determining the position information of multiple hardware units in the top layer of the chip, the positions of the hardware units can be adjusted according to the minimum spacing between them, so that the distance between any two hardware units is less than the minimum spacing, thus avoiding the aforementioned manufacturing risks. For example, the CPU core and SRAM interact frequently and need to be laid out close together to reduce data transmission latency. After determining the position of the CPU core in the computing core area and the position of the SRAM in the storage area based on the close-distance layout, the distance between the CPU core and SRAM can be detected. If the distance is less than the minimum spacing, the position coordinates of the CPU core and / or SRAM can be automatically adjusted to increase the distance between the CPU core and SRAM to above the minimum spacing, while ensuring that the adjusted positions of the CPU core and SRAM are still within their respective functional partitions and do not affect the layout space of other hardware units.

[0049] When determining the location information of multiple hardware units in the top layer of the chip, if the physical size of a hardware unit exceeds the remaining space of the functional partition corresponding to that hardware unit, the available space can be freed up by adjusting the arrangement direction of the hardware unit in the functional partition (such as rotating it 90 degrees) or reducing the spacing between other hardware units in the functional partition. This allows the remaining space of the functional partition to fit the physical size of the hardware unit as much as possible. Otherwise, the functional area can be re-divided or the hardware unit can be moved to another functional partition to achieve a non-overlapping, high-density layout of hardware units in the top layer, avoiding a decrease in the utilization rate of the top layer area due to wasted space.

[0050] Chip layout design information can be, for example, a chip layout plan (Floor Plan).

[0051] S220: Based on the chip's functional implementation information, determine the level fixed node and connection configuration information of the chip's top layer.

[0052] The functional implementation information of a chip may include: interface definitions of hardware units, and logical function connection information, as well as other information related to the functional implementation of the chip.

[0053] The interface definition of a hardware unit may include, for example, information related to the hardware unit's interface, such as the input pins, output pins, number of pins, pin electrical characteristics (e.g., high-level threshold, low-level threshold, drive capability, etc.), and pin function descriptions. Logical function connection information may include, for example, information related to logical function connections, such as the signal flow direction between hardware units, connection information, and control logic links. For instance, the signal flow direction between hardware units may include the signal input direction and output direction between hardware units; for example, hardware unit A's output pin OUT1 outputs signal 1, hardware unit B's input pin IN1 receives signal 1, and so on. Connection information may include the physical connection relationship between hardware units; for example, hardware unit C's control pin is connected to hardware unit D's status pin. Control logic links may include the control signal transmission path between hardware units; for example, hardware unit G's reset signal is transmitted to hardware unit H and hardware unit I through the control logic link.

[0054] A fixed-level node is a physical node in the top layer of a chip used to provide a stable voltage level (such as high level VDD or low level VSS). The voltage level of a fixed-level node remains constant during chip operation.

[0055] Based on the interface definitions and logic function connection information of the hardware units described above, the level-fixed nodes in the top layer can be determined. For example, if the interface definition of a hardware unit contains a pin that always needs to be kept high, and this pin is not level-fixed internally by logic circuitry, then a corresponding level-fixed node needs to be configured for this pin in the top layer. This level-fixed node connects the power supply voltage (such as VDD) and the pin, and is used to continuously output a high level for this pin. Similarly, if the interface definition of a hardware unit contains a pin that always needs to be kept low, and this hardware unit does not implement level-fixing internally, then a level-fixed node connected to a low voltage (such as VSS) needs to be configured for this pin in the top layer, and this level-fixed node is used to continuously output a low level for this pin. For example, the interface definition of the hardware unit includes a mode selection pin. The mode selection pin needs to be kept high after the chip is powered on to enter a specific working mode. If the hardware unit does not implement the logic for fixing this level, then the corresponding level fixing node is configured. The interface definition of the hardware unit also includes an enable pin. In some scenarios, it needs to be kept low to disable a specific function of the unit. In this case, the corresponding low-level fixing node needs to be configured for the enable pin to ensure the stability of the function-disabled state.

[0056] The connection configuration information includes connection-related information between the top-level hardware unit and the level-fixed node that controls the level of that hardware unit, as well as connection-related information between multiple hardware units. For example, it includes which hardware units are configured as connected in the chip's functional implementation information, and the connection methods (e.g., pin interconnection relationships) of the connected hardware units. Based on the interface definitions and logical function connection information of the hardware units described above, the connection configuration information can be determined. For example, if the power supply pin VDD_P1 of hardware unit P is connected to the top-level fixed-level node VDD_TOP1, then the connection configuration information records the connection relationship between the power supply pin VDD_P1 of hardware unit P and the fixed-level node VDD_TOP1, indicating that the level provided by the fixed-level node VDD_TOP1 is high. Similarly, if the logic function connection information includes the output pin OUT1 of hardware unit A1 outputting signal 1 and the input pin IN1 of hardware unit B1 receiving signal 1, then the connection configuration information will record the physical pin numbers of OUT1 and IN1, and establish a corresponding connection relationship between the output pin OUT1 of hardware unit A1 and the input pin IN1 of hardware unit B1. If the logic function connection information includes the interrupt request pin IRQ1 of hardware unit C being connected to the interrupt receive pin IRQ_RCV1 of hardware unit D and the interrupt receive pin IRQ_RCV2 of hardware unit E, then the connection configuration information will record the one-to-many connection relationship between the interrupt request pin IRQ1, the interrupt receive pin IRQ_RCV1, and the interrupt receive pin IRQ_RCV2.

[0057] It should be noted that the connection configuration information does not involve the definition of any logic circuits; all logic functions are encapsulated within the hardware unit.

[0058] S230: Determine the wiring method of multiple hardware units at the top layer of the chip based on the level fixed node, connection configuration information, and the position information of multiple hardware units in the top layer of the chip.

[0059] A fixed-level node is configured in a hardware unit at the top layer of the chip, and this hardware unit is different from the hardware unit controlled by the fixed-level node. This ensures that the top layer of the chip does not contain a fixed-level node, satisfying the requirement of a "Top-Free" implementation where the top layer has no fixed-level nodes. Simultaneously, a connection is established between the hardware unit configuring the fixed-level node and the hardware unit controlled by it to ensure that the level control function of the fixed-level node can still be implemented normally.

[0060] After configuring level-fixed nodes in the corresponding hardware units, the connection relationships between multiple hardware units can be determined based on the connection relationships between the hardware unit configuring the level-fixed node and the hardware units controlled by that level-fixed node, as well as the connection configuration information. Based on the connection relationships of multiple hardware units and the position information of each hardware unit in the top layer, the routing of the chip's top layer is planned, resulting in the routing method of multiple hardware units in the chip's top layer. In the routing method, two hardware units can be connected one-to-one via pins, that is, the output pin of one hardware unit is directly connected to the input pin of another hardware unit, satisfying the pin-to-pin requirement of the "Top Free" implementation scheme.

[0061] S240: Generates the top-level design code of the chip based on the wiring method and the location information of multiple hardware units in the top layer of the chip.

[0062] Based on the syntax rules of Hardware Description Language (HDL), the wiring methods of multiple hardware units and the location information of multiple hardware units can be transformed into structured code logic to obtain the top-level design code of the chip.

[0063] For example, for any one of multiple hardware units, instantiation parameters of that hardware unit can be defined in the code based on its location information. These instantiation parameters may include the hardware unit's position coordinates in the top layer, its size parameters, and its port mapping relationships. Then, according to the routing method, corresponding interconnection statements are added to the code, including direct pin connection statements between multiple hardware units, global bus definition and access statements, and connection statements for configuring hardware units with fixed-level nodes and the hardware units controlled by those fixed-level nodes, thereby obtaining the chip's top-level design code. Syntax checks and logical consistency verification are performed on this code to ensure that the instantiation parameters of all hardware units and the interconnection statements between them conform to the syntax rules of the hardware description language, and that the location and connection relationships of the hardware units fully match the constraints of the "Top Free" scheme, thus guaranteeing the correctness and validity of the top-level design code. Finally, the top-level design code is output, thereby completing the automated generation of the chip's top-level design code.

[0064] The chip top-level design method provided in this disclosure can determine the position information of multiple hardware units in the chip top layer based on the chip layout design information; then, based on the chip's functional implementation information, determine the level fixed nodes and connection configuration information of the chip top layer; based on the level fixed nodes, connection configuration information, and the position information of multiple hardware units in the chip top layer, determine the routing method of multiple hardware units in the chip top layer; finally, based on the routing method and the position information of multiple hardware units in the chip top layer, generate the chip top-level design code. Therefore, this disclosure can automate the chip top-level design process, avoiding the tedious process of manually adjusting the position of hardware units, level nodes, and routing, effectively shortening the design cycle of the top-level design code and meeting the needs of rapid chip iteration.

[0065] In some embodiments, such as Figure 4 As shown, the execution process of S230 may include the following S410~S430.

[0066] S410: Based on the connection configuration information, determine the first connection relationship between the level fixed node and the first hardware unit among the multiple hardware units, and determine the second connection relationship among the multiple hardware units.

[0067] The first connection is between a fixed-level node and the hardware unit it directly controls. The second connection is a signal interaction connection established between multiple hardware units based on logical functional requirements.

[0068] Based on the connection configuration information, the hardware unit controlled by the fixed-level node is determined, and this hardware unit is identified as the first hardware unit corresponding to the fixed-level node. Therefore, the first connection relationship between the fixed-level node and the first hardware unit is determined. For example, if the connection configuration information records the connection relationship between the power supply pin VDD_P1 of hardware unit P and the fixed-level node VDD_TOP1, then the first hardware unit corresponding to the fixed-level node VDD_TOP1 is hardware unit P, and the first connection relationship between the fixed-level node VDD_TOP1 and hardware unit P is determined.

[0069] Based on the connection configuration information, the signal interaction connections configured for multiple hardware units are determined, thereby obtaining the second connection relationship between these multiple hardware units.

[0070] S420: Based on the location information of multiple hardware units and the first connection relationship, the level fixed node is set in the second hardware unit among the multiple hardware units, and a third connection relationship is established between the first hardware unit and the second hardware unit.

[0071] Based on the location information of multiple hardware units and the first connection relationship, the hardware unit that is physically closer to the first hardware unit is identified as the second hardware unit. For example, one hardware unit within a set distance range from the first hardware unit can be identified as the second hardware unit, or one hardware unit within a set number of hardware units separated from the first hardware unit can be identified as the second hardware unit. This shortens the transmission path of the level signal and reduces signal attenuation and interference. After identifying the second hardware unit, a third connection relationship is established between the first and second hardware units, enabling the level-fixed node to control the level of the first hardware unit through the second hardware unit.

[0072] For example, such as Figure 5 As shown in (a), the level-fixed node 50 is connected to hardware unit A2. This connection corresponds to the first connection relationship described above. Hardware unit B2 is determined based on the location information of multiple hardware units and the first connection relationship, as follows: Figure 5 As shown in (b), the level fixed node 50 is set in hardware unit B2 to establish a third connection relationship between hardware unit A2 and hardware unit B2. Figure 5 The arrows in (a) and (b) indicate the direction of signal transmission.

[0073] S430: Determine the routing method of multiple hardware units based on their location information, second connection relationship, and third connection relationship in the top layer of the chip.

[0074] Based on the location information and second connection relationship of multiple hardware units in the top layer of the chip, when two hardware units to be connected are physically adjacent, a direct wiring method is used to directly connect the corresponding pins on the two hardware units. When the two hardware units to be connected are not physically adjacent, an indirect wiring method is used through at least one intermediate hardware unit between the two hardware units to be connected, connecting the two hardware units to be connected and two physically adjacent hardware units in the at least one intermediate hardware unit between the two hardware units to be connected. For any hardware unit among multiple hardware units, if one pin on the hardware unit is simultaneously connected to two or more other hardware units, the pin connection relationship on the hardware unit is modified to a one-to-one connection relationship, so that the pin connection relationship of multiple hardware units meets the pin-to-pin wiring requirements of the "Top Free" scheme, ensuring that the wiring method of all hardware units complies with the constraints of the "Top Free" scheme.

[0075] For example, such as Figure 6A As shown, hardware unit 61 and hardware unit 62 are physically adjacent, so a direct wiring method can be used to wire hardware unit 61 and hardware unit 62, connecting the corresponding pins on hardware unit 61 and hardware unit 62. Figure 6A (Pin not shown) are directly connected via wires to form a one-to-one direct connection. Figure 6A The arrows in the diagram indicate the direction of signal transmission.

[0076] For example, such as Figure 6B As shown, hardware unit 61 and hardware unit 64 are not physically adjacent. Hardware unit 62 and hardware unit 63 are sequentially adjacent to hardware unit 61 and hardware unit 64. Therefore, an indirect routing method is used to route hardware unit 61 and hardware unit 64, connecting the corresponding pins on hardware unit 61 and hardware unit 62. Figure 6B (Pin not shown) are connected by wires to the corresponding pins on hardware unit 62 and hardware unit 63. Figure 6B (Pin not shown) are connected by wires to the corresponding pins on hardware unit 63 and hardware unit 64. Figure 6B (Pin not shown) are connected by wires to realize signal transmission between hardware unit 61 and hardware unit 64. Figure 6B The arrows in the diagram indicate the direction of signal transmission.

[0077] For example, in the case where one pin of each of a plurality of hardware units is simultaneously connected to pins of two or more other hardware units among the plurality of hardware units, for example... Figure 7As shown in part (a), one pin on hardware unit 71 is simultaneously connected to one pin of hardware unit 70, one pin of hardware unit 72, and one pin of hardware unit 73. Hardware units 70, 71, 72, and 73 are sequentially adjacent, but hardware units 71 and 73 are not adjacent. Figure 7 (a) and (b) only show the connection logic of hardware units 70 to 73, and do not show the actual location arrangement of hardware units 70 to 73. During the above direct wiring or indirect conversion wiring process, the pin connection relationship on the hardware units can be modified to a one-to-one connection relationship. For example... Figure 7 As shown in section (b), one pin of hardware unit 71 is connected to one pin of hardware unit 70, another pin of hardware unit 71 is connected to one pin of hardware unit 72, and another pin of hardware unit 72 is connected to one pin of hardware unit 73. This transforms the one-to-many connection relationship between hardware unit 71 and hardware units 70, 72, and 73 into a one-to-one connection relationship between hardware unit 70 and hardware unit 71, hardware unit 71 and hardware unit 72, and hardware unit 72 and hardware unit 73, thus satisfying the pin-to-pin wiring requirements of the "Top Free" scheme. Figure 7 The pins on the hardware unit are not shown in the diagram. Figure 7 The arrows in (a) and (b) indicate the direction of signal transmission. This method avoids signal conflicts or excessive load caused by connecting multiple hardware units to the same pin simultaneously, ensuring the stability and reliability of signal transmission.

[0078] Based on S410~S430 above, the hardware unit that is physically closer to the first hardware unit can be identified as the second hardware unit according to the location information of multiple hardware units and the first connection relationship. This effectively shortens the transmission path of the level signal, reduces signal attenuation and interference during transmission, and ensures the stability of level control. When determining the routing method, a direct connection or indirect conversion routing strategy is adopted for hardware units with different physical location relationships. This not only meets the functional connection requirements between hardware units, but also strictly follows the pin-to-pin routing requirements of the "Top Free" scheme through the adjustment of the one-to-one pin connection, further improving the standardization and reliability of the chip's top-level design.

[0079] In some embodiments, such as Figure 8 As shown, the execution process of S420 may include the following S810~S830.

[0080] S810: Based on the location information of multiple hardware units, determine at least one adjacent hardware unit that is adjacent to the location of the first hardware unit among the multiple hardware units.

[0081] Based on the location information of multiple hardware units, at least one adjacent hardware unit that is physically adjacent to the first hardware unit can be identified among the multiple hardware units. This can initially eliminate hardware units that are far away from the first hardware unit, avoiding excessive signal transmission delay or loss due to excessive physical distance. At the same time, due to the Pin to Pin wiring requirements in the "Top Free" scheme, the wiring between adjacent hardware units and the first hardware unit does not need to be connected through at least one intermediate hardware unit, making it easier to meet the Pin to Pin wiring requirements.

[0082] S820: Determine the second hardware unit based on at least one adjacent hardware unit.

[0083] Any one of the at least one adjacent hardware units that is adjacent to the first hardware unit can be designated as the second hardware unit. In cases where at least one adjacent hardware unit comprises multiple adjacent hardware units, the adjacent hardware unit closest to the first hardware unit among these multiple adjacent hardware units can also be designated as the second hardware unit to further shorten the transmission path of the level signal and minimize signal attenuation.

[0084] S830: Set the level fixed node corresponding to the first connection relationship in the second hardware unit to establish a third connection relationship between the first hardware unit and the second hardware unit.

[0085] The first connection relationship is a direct connection between the first hardware unit and the level-fixed node that controls the first hardware unit. After determining the second hardware unit, the level-fixed node corresponding to the first connection relationship is set in the second hardware unit, establishing a third connection relationship between the first and second hardware units. This allows the level signal of the level-fixed node to be transmitted to the first hardware unit via the second hardware unit, thereby achieving level control of the first hardware unit.

[0086] In this embodiment, through steps S810-S830, a hardware unit directly connected to the first hardware unit can be selected from multiple hardware units as the second hardware unit. This avoids the signal delay and interference risks that may be introduced by transferring through an intermediate hardware unit, further ensuring the stability and timeliness of level control. Simultaneously, since the second hardware unit and the first hardware unit are adjacent, the direct pin connection between them fully complies with the pin-to-pin wiring requirements of the "Top Free" scheme, eliminating the need for additional wiring topology adjustments and effectively simplifying the wiring design process.

[0087] In some embodiments, such as Figure 9 As shown, the execution process of S830 may include the following S910~S920.

[0088] S910: Determine the distance information between the first hardware unit and each adjacent hardware unit.

[0089] The physical distance between the first hardware unit and each adjacent hardware unit can be calculated. The method for calculating the physical distance between the first hardware unit and each adjacent hardware unit can be set by those skilled in the art according to the actual situation, and the embodiments disclosed herein do not limit this.

[0090] S920: The adjacent hardware unit with the smallest distance value in the distance information is determined as the second hardware unit.

[0091] Based on the distance information obtained from S910, the physical distances between each adjacent hardware unit and the first hardware unit are sorted, and the adjacent hardware unit with the smallest distance value is selected as the second hardware unit.

[0092] In this embodiment of the present disclosure, through S910~S920, the adjacent hardware unit that is closest to the first hardware unit in terms of physical distance can be accurately selected as the second hardware unit. This ensures that the level fixed node is set in the hardware unit that is closest to the first hardware unit in terms of physical distance, thereby compressing the transmission path of the level signal to the shortest possible length, minimizing the attenuation and interference probability of the signal during transmission, and ensuring that the level control signal can be transmitted to the first hardware unit accurately and stably.

[0093] In some embodiments, such as Figure 10 As shown, the execution process of S430 may include the following S1010~S1030.

[0094] S1010: Determine the hardware unit routing relationship based on the location information of multiple hardware units; wherein, the hardware unit routing relationship is used to represent the connection relationship between two hardware units that are adjacent in location among the multiple hardware units.

[0095] Based on the location information of multiple hardware units, it can be determined whether at least one intermediate hardware unit is provided between any two hardware units. If no intermediate hardware unit is provided between two hardware units, the connection between the two hardware units is marked as a direct connection routing relationship; if at least one intermediate hardware unit is provided between two hardware units, the connection between the two hardware units is marked as an indirect connection routing relationship via the intermediate hardware unit. When multiple intermediate hardware units are arranged between two hardware units, the intermediate hardware units can be sorted according to the transmission direction of the signal between the two hardware units, based on the order in which the signal flows through the multiple intermediate hardware units, and the sorting result of the multiple intermediate hardware units is recorded. The hardware unit routing relationship can include the recorded direct connection routing relationship, indirect connection routing relationship, and the sorting result of multiple intermediate hardware units in the indirect connection routing relationship.

[0096] It should be noted that the signal transmission direction between two hardware units includes two transmission directions. For example, if one of the two hardware units is the first target hardware unit and the other is the second target hardware unit, the signal can be transmitted from the first target hardware unit to the second target hardware unit, or vice versa. In this case, the sorting results of multiple intermediate hardware units can be arranged in either forward or reverse order according to the signal transmission direction, depending on the different transmission directions between the two hardware units. When recording the sorting results of multiple intermediate hardware units, the first target hardware unit can be designated as the signal source hardware unit for outputting the signal, and the second target hardware unit can be designated as the signal receiving hardware unit for receiving the signal, corresponding to one sorting result of multiple intermediate hardware units. Conversely, designating the second target hardware unit as the signal source hardware unit for outputting the signal and the first target hardware unit as the signal receiving hardware unit for receiving the signal corresponds to another sorting result of multiple intermediate hardware units. This bidirectional recording method incorporates the sorting results of multiple intermediate hardware units obtained from two hardware units into the hardware unit routing relationship. It can fully cover the bidirectional signal transmission scenario between hardware units, accurately reflect the connection path between hardware units under different transmission directions, provide a comprehensive routing basis for the selection of subsequent wiring methods, and avoid the problem of missing routes due to different transmission directions.

[0097] In some examples, hardware unit routing relationships can be presented as a list. This list could be, for example, a hardware unit routing table as shown in Table 1. In the hardware unit routing table, the hardware units in the header row can represent signal source hardware units used to output signals, and the hardware units in the header columns can represent signal receiving hardware units used to receive signals. The cell at the intersection of the row containing the signal source hardware unit and the column containing the signal receiving hardware unit records the sequence of intermediate hardware units between the signal source hardware unit and the signal receiving hardware unit (the sequence of intermediate hardware units that the signal must pass through sequentially from the signal source hardware unit before reaching the signal receiving hardware unit).

[0098] Table 1

[0099] In Table 1, “×” indicates that there is no intermediate hardware unit, and n is a positive integer.

[0100] For example, if the multiple hardware units include four hardware units, namely hardware unit 1, hardware unit 2, hardware unit 3, and hardware unit 4, the physical positional relationship of hardware unit 1 to hardware unit 4 is as follows: Figure 11 As shown in Table 2, the hardware unit routing table can be configured as follows.

[0101] Table 2

[0102] S1020: Update the second connection relationship based on the hardware unit routing relationship to obtain the fourth connection relationship between multiple hardware units.

[0103] Based on the sequence of intermediate hardware units between the signal source hardware unit and the signal receiving hardware unit recorded in the hardware unit routing relationship, two hardware units with a connection relationship in the second connection relationship can be connected.

[0104] For example, if the two hardware units recorded in the hardware unit routing relationship are directly connected (i.e., there is no intermediate hardware unit), the connection relationship between the two hardware units in the second connection relationship is directly retained; if the two hardware units recorded in the hardware unit routing relationship are indirectly connected (i.e. there is at least one intermediate hardware unit), based on the sequence of intermediate hardware units in the hardware unit routing relationship and the transmission direction of the signal in the two hardware units, the connection relationship of the two hardware units in the second connection relationship is updated to an indirect connection relationship where the two hardware units are connected through an intermediate hardware unit, forming a connection relationship in which the signal source hardware unit, the intermediate hardware unit, and the signal receiving hardware unit are connected in sequence.

[0105] By updating the second connection relationship, it can be ensured that the connection between all hardware units follows the rule of connecting hardware units that are physically adjacent in sequence, and complies with the pin-to-pin wiring requirements in the "Top Free" scheme.

[0106] S1030: Determine the wiring method for multiple hardware units based on the third and fourth connection relationships.

[0107] Taking the first and second hardware units as adjacent hardware units in the third connection relationship as an example, the corresponding pins of the first and second hardware units are directly connected by wiring to complete the wiring of the third connection method; the corresponding pins of the adjacent hardware units in the fourth connection relationship are directly connected by wiring to complete the wiring of the fourth connection method, and finally a complete wiring topology between multiple hardware units is formed.

[0108] In some embodiments, such as Figure 12 As shown, the execution process of S1020 may also include the following S1210~S1230.

[0109] S1210: Based on the second connection relationship, a third hardware unit is determined among the plurality of hardware units, and at least one fourth hardware unit connected to the third hardware unit is determined among the plurality of hardware units.

[0110] S1220: Based on the hardware unit routing relationship, the third hardware unit, and at least one fourth hardware unit, determine the matching connection relationship between any two adjacent hardware units among the multiple hardware units.

[0111] When at least one fourth hardware unit includes a fourth hardware unit, the signal source hardware unit and the signal receiving hardware unit are determined in the third and fourth hardware units according to the signal transmission direction between the third and fourth hardware units. For example, if the signal transmission direction is from the third hardware unit to the fourth hardware unit, then the third hardware unit is the signal source hardware unit and the fourth hardware unit is the signal receiving hardware unit; if the signal transmission direction is from the fourth hardware unit to the third hardware unit, then the fourth hardware unit is the signal source hardware unit and the third hardware unit is the signal receiving hardware unit. Based on the determination of the signal source hardware unit and the signal receiving hardware unit in the third and fourth hardware units, the corresponding intermediate hardware unit sequence for connecting the third and fourth hardware units is determined in the hardware unit routing relationship. For any two physically adjacent hardware units in the third hardware unit, the fourth hardware unit, and the intermediate hardware unit sequence, a connection relationship is established between the two physically adjacent hardware units to obtain a matching connection relationship.

[0112] In cases where at least one fourth hardware unit comprises multiple fourth hardware units, the third hardware unit is connected to the multiple fourth hardware units one-to-one via pin connections. All available pins of the third hardware unit can be traversed, and each fourth hardware unit is assigned a unique corresponding pin on the third hardware unit based on its functional connection requirements. Following this, similar to the case where at least one fourth hardware unit comprises one fourth hardware unit, for each fourth hardware unit, a signal source hardware unit and a signal receiving hardware unit are determined within both the third and fourth hardware units. Then, based on the determination of the signal source and signal receiving hardware units within both the third and fourth hardware units, a sequence of intermediate hardware units corresponding to the connection between the third and fourth hardware units is determined. For any two physically adjacent hardware units in the third, fourth, and intermediate hardware unit sequences, a connection is established between these two physically adjacent hardware units to obtain a matching connection relationship.

[0113] S1230: Based on the matching connection relationship, update the second connection relationship to obtain the fourth connection relationship between multiple hardware units.

[0114] The direct connection between the third hardware unit and at least one fourth hardware unit in the second connection relationship is replaced with the connection relationship in the matching connection relationship in which the signal source hardware unit, the intermediate hardware unit sequence, and the signal receiving hardware unit are connected in sequence, thus obtaining the fourth connection relationship between multiple hardware units.

[0115] Based on S1210~S1230, the signal transmission direction between the third and fourth hardware units can be accurately identified. Combined with the intermediate hardware unit sequence in the hardware unit routing relationship, the previously possible cross-hardware unit connections are transformed into sequential connections between adjacent units, strictly adhering to the Pin-to-Pin wiring constraints of the "Top Free" scheme. By updating the second connection relationship through matching connections, the connection topology of all hardware units can perfectly conform to the adjacency rules of physical locations, forming a standardized wiring framework of "adjacent direct connection, indirect transfer," effectively reducing the complexity of subsequent wiring implementation.

[0116] In some embodiments, such as Figure 13 As shown, the execution process of S1030 may also include the following S1310~S1320.

[0117] S1310: Based on the third connection relationship and the fourth connection relationship, at least one connection method of the plurality of hardware units is determined; wherein, when at least one fourth hardware unit includes a plurality of fourth hardware units, in response to the third hardware unit connecting the plurality of fourth hardware units through a first pin, a plurality of second pins are determined among the plurality of pins corresponding to the third hardware unit, and the plurality of fourth hardware units are respectively connected through the plurality of second pins.

[0118] In the third and fourth connection relationships, the third hardware unit among the multiple hardware units is connected to at least one fourth hardware unit.

[0119] In cases where at least one fourth hardware unit comprises multiple fourth hardware units (i.e., the third hardware unit is simultaneously connected to multiple fourth hardware units), if the third hardware unit is connected to multiple fourth hardware units via a first pin, the pin resources of the third hardware unit can be detected to select multiple unused second pins that match the function of the first pin (e.g., level compatibility, signal transmission rate adaptation). For example, if the first pin is a 3.3V general-purpose input / output pin, a pin of the same type can be selected from the free pins of the third hardware unit as the second pin, ensuring that the electrical characteristics of each second pin are consistent with the signal requirements of the corresponding fourth hardware unit. Then, following the "one-to-one mapping" principle, each second pin is connected to a corresponding pin of a fourth hardware unit, achieving a precise one-to-one pin-to-pin connection between the third hardware unit and multiple fourth hardware units. This ensures both electrical compatibility of signal transmission and efficient use of the pin resources of the third hardware unit.

[0120] When making pin connections, if at least one fourth hardware unit comprises multiple fourth hardware units, and connections are made only based on hardware units with a connection relationship, the wiring between two hardware units may be redundant after connecting multiple hardware units, since the fourth hardware unit may be the third connection unit in other connection relationships. For example... Figure 7 When the hardware unit 71 shown is the third hardware unit, multiple fourth hardware units include hardware unit 70, hardware unit 72, and hardware unit 73. By connecting hardware unit 71 with hardware units 70, 72, and 73, the following can be obtained: Figure 14 The wiring method is as follows: However, when hardware unit 72 is used as a third hardware unit, it is possible to perform wiring again between hardware units 71 and 72, and / or between hardware units 72 and 73, resulting in the following: Figure 14 The four wiring methods shown have different numbers of wires in three of them (e.g., wiring method 1, wiring method 2, and wiring method 4, or wiring method 1, wiring method 3, and wiring method 4).

[0121] S1320: Determine the wiring method based on the number of wires corresponding to at least one connection method.

[0122] When at least one connection method includes one connection method, the connection method is determined to be a wiring method.

[0123] When at least one connection method includes multiple connection methods, the number of wires for each connection method is obtained, resulting in multiple wire quantities corresponding to each connection method. The connection method corresponding to the smallest wire quantity among these multiple wire quantities is determined as the wiring method, thereby achieving optimal utilization of wiring resources. While meeting the connection requirements of all hardware units, the goal is to minimize wiring length and crossover probability, thereby improving the space utilization and signal transmission stability of the chip's top-level wiring.

[0124] In some embodiments, such as Figure 15 As shown, when determining the location information of multiple hardware units in the top layer of the chip based on the chip layout design information, the following steps S1510~S1530 can be executed.

[0125] S1510: Based on the chip layout design information, determine the initial position information of multiple functional modules in the top layer of the chip.

[0126] The initial position information of multiple functional modules in the top layer of the chip can be the pre-planned position information of functional modules in the chip layout design information.

[0127] S1520: Perform functional segmentation on the functional module to obtain multiple hardware units included in the functional module.

[0128] The functions within a functional module can be further subdivided to obtain a more granular functional division result. Each independent functional unit in the functional division result is identified as a hardware unit, thus obtaining multiple hardware units included in the functional module.

[0129] For example, if the functional module is a processor module, and the processor module includes sub-functions such as arithmetic, storage, and control, then the circuit units corresponding to the arithmetic sub-function can be divided into arithmetic hardware units, the circuit units corresponding to the storage sub-function into storage hardware units, the circuit units corresponding to the control sub-function into control hardware units, and so on, completing the functional division of the processor module into multiple hardware units. During the functional division process, it is necessary to ensure the functional independence and integrity of each hardware unit to avoid functional overlap or omissions.

[0130] In some examples, such as Figure 16As shown in (a) and (b), the chip top layer 101 initially includes multiple functional modules, including functional module A01, functional module B01, functional module C01, and functional module D01. The functions in functional modules A01, B01, C01, and D01 are further subdivided. For example, the function of functional module A is divided into four independent functions: function A-H0, function A-H1, function A-H2, and function A-H3, resulting in the functional unit A-H0 corresponding to function A-H0 (corresponding to...). Figure 16 (b) shows hardware unit A-H00, and functional unit A-H1 corresponding to function A-H1. Figure 16 (b) shows hardware unit A-H01, and functional unit A-H2 corresponding to function A-H2. Figure 16 Hardware unit A-H02 shown in (b) and functional unit A-H3 corresponding to function A-H3 (corresponding to) Figure 16 Hardware unit A-H03 is shown in (b) above; similarly, the functions of functional module B are divided into functions B-H0, B-H1, B-H2 and B-H3, resulting in corresponding functional units B-H0 to B-H3 (corresponding to...). Figure 16 (b) shows hardware units B-H00 to B-H03; the functions of functional module C are divided into functions C-H0, C-H1, C-H2, and C-H3, resulting in corresponding functional units C-H0 to C-H3 (corresponding to...). Figure 16 (as shown in (b) of the diagram, hardware units C-H00 to C-H03) are divided into functional units D-H0, D-H1, D-H2, and D-H3, resulting in corresponding functional units D-H0 to D-H3. Through the above functional segmentation operation, multiple functional modules at the top layer of the chip are decomposed into 16 independent hardware units. Each hardware unit corresponds to a functional unit after the functional module has been subdivided. This fine-grained functional segmentation not only allows the location planning of hardware units to better meet the compactness requirements of the physical layout, but also provides a more accurate basis for subsequent wiring based on adjacent hardware units, making the overall wiring topology closer to the design goal of "independent units and direct connection between adjacent units" in the "Top Free" scheme.

[0131] S1530: Determine the position information of the hardware unit in the top layer of the chip based on the functions and initial position information of the functional modules corresponding to multiple hardware units.

[0132] The physical position of each hardware unit can be adjusted based on the functions and initial position information of the functional modules corresponding to multiple hardware units (see [reference]). Figure 16As shown in (b) in the figure, this is the hardware unit after the position has been adjusted to make the layout of the top layer of the chip more reasonable.

[0133] When adjusting the physical location of hardware units, the principle of "functional similarity and physical adjacency" can be followed: the distance between hardware units with strong functional correlation (such as high data interaction frequency and strict signal transmission delay requirements) should be reduced to a smaller distance. For example, the computing hardware unit and control hardware unit cut from the processor module can be placed adjacent to each other to reduce the wiring length and signal attenuation between them. Hardware units with relatively independent functions can be flexibly arranged according to the free space on the top layer of the chip to avoid the situation of overly dense or sparse layout in some areas. At the same time, the position can also be optimized based on the power consumption characteristics of the hardware units: high-power hardware units (such as computing hardware units) can be placed near the heat dissipation channels on the top layer of the chip, while low-power hardware units (such as storage hardware units) can be placed in areas with less heat dissipation pressure to balance the overall heat distribution of the chip and improve the chip's operating stability.

[0134] Through the above position adjustment operations, the final determined hardware unit position information can achieve precise matching between functional logic and physical layout. This allows the hardware unit layout at the top level of the chip to retain the original functional module's regional division logic while achieving precise positioning at the hardware unit level, laying a solid physical foundation for the establishment of subsequent connection relationships and wiring implementation.

[0135] Exemplary device Figure 17 This is a schematic diagram of the structure of a top-level design device for a chip provided in an embodiment of this disclosure. Figure 17 As shown, the chip top-level design device 1700 includes: a first determination module 1701, a second determination module 1702, a third determination module 1703, and a generation module 1704.

[0136] The first determining module 1701 is used to determine the position information of multiple hardware units in the top layer of the chip based on the chip layout design information.

[0137] The second determining module 1702 is used to determine the level fixed node and connection configuration information of the chip top layer based on the chip's functional implementation information.

[0138] The third determining module 1703 is used to determine the wiring method of multiple hardware units at the top layer of the chip based on the level fixed node, connection configuration information and the location information of multiple hardware units.

[0139] The generation module 1704 is used to generate the top-level design code of the chip based on the wiring method and the location of multiple hardware units.

[0140] The chip top-level design apparatus provided in this disclosure can determine the position information of multiple hardware units in the chip top layer based on the chip layout design information; then, based on the chip's functional implementation information, determine the level fixed nodes and connection configuration information of the chip top layer; based on the level fixed nodes, connection configuration information, and the position information of the multiple hardware units in the chip top layer, determine the routing method of the multiple hardware units in the chip top layer; finally, based on the routing method and the position information of the multiple hardware units in the chip top layer, generate the chip top-level design code. Therefore, this disclosure can automate the chip top-level design process, avoiding the tedious process of manually adjusting the position of hardware units, level nodes, and routing, effectively shortening the design cycle of the top-level design code and meeting the needs of rapid chip iteration.

[0141] In some embodiments, the third determining module 1703 includes: First Determined Submodule ( Figure 17 (not shown in the image), used to determine the first connection relationship between the level fixed node and the first hardware unit among multiple hardware units, and to determine the second connection relationship among multiple hardware units, based on the connection configuration information; First processing submodule ( Figure 17 (not shown in the image) is used to set a level-fixed node in the second hardware unit among the multiple hardware units according to the location information of multiple hardware units and the first connection relationship, and to establish a third connection relationship between the first hardware unit and the second hardware unit. Second processing submodule ( Figure 17 (not shown in the image) is used to determine the wiring method of multiple hardware units based on their location information in the top layer of the chip, the second connection relationship, and the third connection relationship.

[0142] In some embodiments, the first processing submodule includes: First Determined Unit ( Figure 17 (not shown in the figure), used to determine at least one adjacent hardware unit that is adjacent to the position of the first hardware unit among multiple hardware units based on the position information of multiple hardware units; Second Determining Unit ( Figure 17 (not shown in the image), used to determine the second hardware unit based on at least one adjacent hardware unit; First processing unit ( Figure 17 (Not shown in the image), used to set the level fixed node corresponding to the first connection relationship in the second hardware unit, and establish a third connection relationship between the first hardware unit and the second hardware unit.

[0143] In some embodiments, the second determining unit is specifically configured to: determine distance information between the first hardware unit and each adjacent hardware unit; and determine the second hardware unit among at least one adjacent hardware unit based on the distance information.

[0144] In some embodiments, the second processing submodule includes: The third unit ( Figure 17 (Not shown in the image), used to determine the hardware unit routing relationship based on the location information of multiple hardware units; wherein, the hardware unit routing relationship is used to represent the connection relationship between two hardware units that are adjacent in location among the multiple hardware units; Update unit ( Figure 17 (Not shown in the image), used to update the second connection relationship based on the hardware unit routing relationship, and obtain the fourth connection relationship between multiple hardware units; Fourth determination unit ( Figure 17 (Not shown in the image), used to determine the wiring method of multiple hardware units based on the third connection relationship and the fourth connection relationship.

[0145] In some embodiments, the updating unit is specifically configured to: determine a third hardware unit among a plurality of hardware units and at least one fourth hardware unit connected to the third hardware unit among a plurality of hardware units according to the second connection relationship; determine a matching connection relationship between any two adjacent hardware units among the plurality of hardware units according to the hardware unit routing relationship, the third hardware unit and at least one fourth hardware unit; and update the second connection relationship according to the matching connection relationship to obtain a fourth connection relationship among the plurality of hardware units.

[0146] In some embodiments, the fourth determining unit is specifically used to: determine at least one connection method of the plurality of hardware units according to the third connection relationship and the fourth connection relationship; wherein, when at least one fourth hardware unit includes a plurality of fourth hardware units, in response to the third hardware unit connecting the plurality of fourth hardware units through a first pin, a plurality of second pins are determined among the plurality of pins corresponding to the third hardware unit, and the plurality of fourth hardware units are respectively connected through the plurality of second pins; and a wiring method is determined according to the number of wirings corresponding to the at least one connection method.

[0147] In some embodiments, the first determining module 1701 is specifically used to: determine the initial position information of multiple functional modules in the top layer of the chip according to the chip layout design information; perform functional segmentation on the functional modules to obtain multiple hardware units included in the functional modules; and determine the position information of the hardware units in the top layer of the chip according to the functions corresponding to the multiple hardware units and the initial position information of the functional modules.

[0148] The beneficial technical effects corresponding to the exemplary embodiments of this device can be found in the corresponding beneficial technical effects in the exemplary method section above, and will not be repeated here.

[0149] Exemplary electronic devices Figure 18 A structural diagram of an electronic device provided in an embodiment of this disclosure includes at least one processor 111 and a memory 112.

[0150] The processor 111 may be a central processing unit (CPU) or other form of processing unit with data processing capabilities and / or instruction execution capabilities, and may control other components in the electronic device 11 to perform desired functions.

[0151] The memory 112 may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and the processor 111 may execute one or more computer program instructions to implement the top-level design methods of the chips in the various embodiments of this disclosure above and / or other desired functions.

[0152] In one example, the electronic device 11 may also include an input device 113 and an output device 114, which are interconnected via a bus system and / or other forms of connection mechanism (not shown).

[0153] The input device 113 may also include, for example, a keyboard, a mouse, etc.

[0154] The output device 114 can output various information to the outside, including, for example, a display, a speaker, a printer, and a communication network and its connected remote output devices, etc.

[0155] Of course, for the sake of simplicity, Figure 18 Only some of the components of the electronic device 11 relevant to this disclosure are shown, omitting components such as buses, input / output interfaces, etc. In addition, the electronic device 11 may include any other suitable components depending on the specific application.

[0156] Exemplary computer program products and computer-readable storage media In addition to the methods and apparatus described above, embodiments of this disclosure may also provide a computer program product, including computer program instructions that, when executed by a processor, cause the processor to perform the steps in the top-level design methods for chips of various embodiments of this disclosure described in the "Exemplary Methods" section above.

[0157] Computer program products can be written in any combination of one or more programming languages ​​to perform the operations of embodiments of this disclosure. These programming languages ​​include object-oriented programming languages ​​such as Java and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on a user's computing device, partially on a user's computing device, as a standalone software package, partially on a user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0158] Furthermore, embodiments of this disclosure may also be computer-readable storage media storing computer program instructions thereon, which, when executed by a processor, cause the processor to perform the steps in the top-level design methods of the chip of various embodiments of this disclosure described in the "Exemplary Methods" section above.

[0159] Computer-readable storage media may take the form of any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may include, but is not limited to, systems, apparatuses, or devices that are electrical, magnetic, optical, electromagnetic, infrared, or semiconductor, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: electrical connections having one or more wires, portable disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0160] The basic principles of this disclosure have been described above with reference to specific embodiments. However, the advantages, benefits, and effects mentioned in this disclosure are merely examples and not limitations, and should not be considered as essential features of each embodiment of this disclosure. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the scope of this disclosure to the necessity of employing the aforementioned specific details for implementation.

[0161] Various modifications and variations can be made to this disclosure without departing from the spirit and scope of this application. Therefore, this disclosure is also intended to include such modifications and variations if they fall within the scope of the claims of this disclosure and their equivalents.

Claims

1. A top-level design method for a chip, comprising: Based on the chip's layout design information, the position information of multiple hardware units in the top layer of the chip is determined; Based on the functional implementation information of the chip, determine the level fixed node and connection configuration information of the top layer of the chip; Based on the fixed-level node, the connection configuration information, and the position information of the plurality of hardware units in the top layer of the chip, the wiring method of the plurality of hardware units in the top layer of the chip is determined; Based on the wiring method and the position information of the plurality of hardware units in the top layer of the chip, the top-level design code of the chip is generated.

2. The method according to claim 1, wherein, The step of determining the wiring method of the plurality of hardware units in the top layer of the chip based on the fixed-level node, the connection configuration information, and the position information of the plurality of hardware units in the top layer of the chip includes: Based on the connection configuration information, a first connection relationship is determined between the level-fixed node and the first hardware unit among the plurality of hardware units, and a second connection relationship is determined among the plurality of hardware units; Based on the location information of the plurality of hardware units and the first connection relationship, the level-fixed node is set in the second hardware unit among the plurality of hardware units, and a third connection relationship is established between the first hardware unit and the second hardware unit; The wiring method of the plurality of hardware units is determined based on the position information of the plurality of hardware units in the top layer of the chip, the second connection relationship, and the third connection relationship.

3. The method according to claim 2, wherein, The step of setting the level-fixed node in the second hardware unit according to the position information of the plurality of hardware units and the first connection relationship, and establishing a third connection relationship between the first hardware unit and the second hardware unit, includes: Based on the location information of the plurality of hardware units, at least one adjacent hardware unit that is adjacent to the location of the first hardware unit is determined among the plurality of hardware units. The second hardware unit is determined based on the at least one adjacent hardware unit; The level-fixed node corresponding to the first connection relationship is set in the second hardware unit to establish the third connection relationship between the first hardware unit and the second hardware unit.

4. The method according to claim 3, wherein, Determining the second hardware unit based on the at least one adjacent hardware unit includes: Determine the distance information between the first hardware unit and each of the adjacent hardware units; Based on the distance information, the second hardware unit is determined among the at least one adjacent hardware unit.

5. The method according to claim 2, wherein, The step of determining the wiring method of the plurality of hardware units based on the position information of the plurality of hardware units in the top layer of the chip, the second connection relationship, and the third connection relationship includes: Based on the location information of the plurality of hardware units, a hardware unit routing relationship is determined; wherein, the hardware unit routing relationship is used to represent the connection relationship between two hardware units that are adjacent in position among the plurality of hardware units; Based on the hardware unit routing relationship, the second connection relationship is updated to obtain the fourth connection relationship among the plurality of hardware units; The wiring method of the plurality of hardware units is determined based on the third connection relationship and the fourth connection relationship.

6. The method according to claim 5, wherein, The step of updating the second connection relationship based on the hardware unit routing relationship to obtain the fourth connection relationship among the plurality of hardware units includes: Based on the second connection relationship, a third hardware unit is determined among the plurality of hardware units, and at least one fourth hardware unit connected to the third hardware unit is determined among the plurality of hardware units. Based on the hardware unit routing relationship, the third hardware unit, and the at least one fourth hardware unit, determine the matching connection relationship between any two adjacent hardware units among the plurality of hardware units; Based on the matching connection relationship, the second connection relationship is updated to obtain the fourth connection relationship between the plurality of hardware units.

7. The method according to claim 5 or 6, wherein, The step of determining the wiring method of the plurality of hardware units based on the third connection relationship and the fourth connection relationship includes: Based on the third connection relationship and the fourth connection relationship, at least one connection method of the plurality of hardware units is determined; wherein, when the at least one fourth hardware unit includes a plurality of fourth hardware units, in response to the third hardware unit being connected to the plurality of fourth hardware units through a first pin, a plurality of second pins are determined from the plurality of pins corresponding to the third hardware unit, and the plurality of fourth hardware units are respectively connected through the plurality of second pins; The wiring method is determined based on the number of wires corresponding to each of the at least one connection method.

8. The method according to claim 1, wherein, The step of determining the position information of multiple hardware units in the top layer of the chip based on the chip's layout design information includes: Based on the chip's layout design information, the initial position information of multiple functional modules in the top layer of the chip is determined; The functional module is functionally divided to obtain the multiple hardware units included in the functional module; Based on the functions corresponding to the multiple hardware units and the initial position information of the functional modules, the position information of the hardware units in the top layer of the chip is determined.

9. A top-level design apparatus for a chip, comprising: The first determining module is used to determine the position information of multiple hardware units in the top layer of the chip based on the chip layout design information; The second determining module is used to determine the level fixed node and connection configuration information of the top layer of the chip based on the functional implementation information of the chip; The third determining module is used to determine the wiring method of the plurality of hardware units at the top layer of the chip based on the level fixed node, the connection configuration information and the position information of the plurality of hardware units; The generation module is used to generate the top-level design code of the chip based on the wiring method and the positions of the plurality of hardware units.

10. A computer-readable storage medium storing a computer program that, when executed by a processor, is used to implement the top-level design method of the chip according to any one of claims 1-8.

11. An electronic device, the electronic device comprising: processor; Memory used to store the processor's executable instructions; The processor is configured to read the executable instructions from the memory and execute the instructions to implement the top-level design method of the chip according to any one of claims 1-8.

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