A flash stack package optimization method, device, equipment and storage medium

Abstract

The application provides a flash memory stack package optimization method and device, equipment and a storage medium, and the method comprises the following steps: coupling simulation is performed on an initial three-dimensional package model of a flash memory stack, and a performance data set of the flash memory stack under a target workload is obtained; performance defects of the initial three-dimensional package model in terms of thermal management, power integrity and signal integrity are identified based on the performance data set, and package structure optimization parameters corresponding to each performance defect are generated respectively; and the package structure optimization parameters are integrated into the initial three-dimensional package model to obtain a target three-dimensional package model. Through coupling simulation on the initial three-dimensional package model, the performance data set is obtained, the package defects of the initial three-dimensional package model are identified based on the performance data set, and the corresponding package structure optimization parameter set is generated and integrated into the unified model, so that the accurate heat dissipation of the high heat flux density area can be improved, the impedance of the power distribution network can be effectively reduced, the crosstalk between high-speed signal paths can be suppressed, and the optimal balance of the overall performance can be achieved.

Description

Technical Field

[0001] This application relates to the field of semiconductor packaging technology, and in particular to a flash memory stack packaging optimization method, apparatus, device and storage medium. Background Technology

[0002] To meet the demands of applications such as artificial intelligence for storing massive amounts of model parameters and reading them at high speeds, flash memory has emerged that stacks 3D NAND flash chips using through-silicon via (TSV) technology and incorporates wide-bit parallel interfaces. However, this architecture faces fundamental contradictions at the packaging level: on the one hand, the multi-layered stacked NAND chips and their underlying logic control chips generate dense heat during high-speed parallel access, and traditional heat dissipation solutions struggle to effectively remove this heat from the bottom of the stack and the interior, leading to increased chip temperature and decreased data reliability; on the other hand, the dense interconnects introduced to achieve high bandwidth can cause severe signal crosstalk and power supply noise, hindering full performance. Existing packaging structures typically treat thermal management, power supply, and signal transmission as independent issues, lacking an integrated solution, resulting in inefficiency and performance bottlenecks. Summary of the Invention

[0003] This application provides a flash memory stack packaging optimization method, apparatus, device, and storage medium to solve the problems of low efficiency and performance bottleneck in the three-dimensional stacked packaging structure in related technologies.

[0004] The first aspect of this application provides a flash memory stack packaging optimization method, the flash memory stack packaging optimization method comprising: Coupled simulation is performed on the initial three-dimensional packaging model of the flash memory stack to obtain the performance dataset of the flash memory stack under the target workload; Based on the performance dataset, identify the performance defects of the initial 3D packaging model in terms of thermal management, power integrity and signal integrity, and generate packaging structure optimization parameters corresponding to each performance defect. The optimization parameters of the packaging structure are integrated into the initial three-dimensional packaging model to obtain the target three-dimensional packaging model.

[0005] Optionally, in the first implementation of the first aspect of this application, before the step of performing coupled simulation on the initial three-dimensional packaging model of the flash memory stack, the method further includes: Obtain the hierarchical description file and material library of the flash memory stack, and generate the core components of the flash memory stack based on the connection relationship configured in the hierarchical description file and the material property parameters stored in the material library; Based on the peripheral interface configuration of the core component, the wiring layer and power / ground layer of the packaging substrate are constructed to generate a substrate frame interconnected with the core component. The corresponding encapsulation filling material parameters are determined based on the gap area between the core component and the substrate frame. The core components, substrate frame, encapsulation filling material parameters, and corresponding boundary entities of the core components are combined to generate an initial three-dimensional encapsulation model.

[0006] Optionally, in the second implementation of the first aspect of this application, the step of performing coupled simulation on the initial three-dimensional packaging model of the flash memory stack to obtain the performance dataset of the flash memory stack under the target workload includes: The initial three-dimensional encapsulation model is meshed based on its geometric structure and material properties to obtain a discretized physical field model. Boundary conditions of the target workload are applied to the multiphysics discretization model to obtain the spatiotemporal distribution of temperature field, current density distribution and stress-strain distribution of the flash memory stack under transient operating conditions. Based on the spatiotemporal distribution of the temperature field, the coordinates of regions where the peak temperature exceeds the first threshold are extracted to generate a temperature distribution dataset. The impedance frequency response of the power distribution network is calculated based on the current density distribution to generate the power impedance spectrum. Based on the stress-strain distribution, a full-wave electromagnetic field simulation is performed on the discretized physical field model to extract the time-domain reflection characteristics and crosstalk parameters of the high-speed signal path, generating a signal integrity dataset.

[0007] Optionally, in a third implementation of the first aspect of this application, the step of generating heat dissipation topology parameters based on the distribution of the first region includes: Based on the temperature distribution dataset, determine the first region in the initial packaging structure model that exceeds the first temperature threshold; Based on the temperature gradient vector between the first regions, a heat-directed conduction path from the high-temperature region to the low-temperature region is generated within the silicon interposer layer of the initial three-dimensional packaging model. An asymmetric thermal conductive unit array is configured along the heat directional conduction path, and a heat conduction structure is constructed by configuring the thermal resistance gradient at the interface between adjacent units in the thermal conductive unit array. In the heat conduction structure, the micropump structure parameters are determined at the position corresponding to the center of the first region. By configuring the porosity distribution of the porous wicking material and the cross-sectional change parameters of the vapor chamber channel, a capillary pump ring is generated. The heat conduction structure and the capillary pump ring are arranged in a three-dimensional interweaving pattern to obtain the heat dissipation topology parameters.

[0008] Optionally, in the fourth implementation of the first aspect of this application, the step of determining the second region in the initial three-dimensional package model where the power supply noise exceeds the noise amplitude based on the power supply impedance spectrum, and generating the three-dimensional arrangement and aperture parameters of the power supply vias based on the distribution of the second region, includes: The power supply impedance spectrum is decomposed in the frequency domain to extract the target resonant frequency point in the second region where the impedance amplitude exceeds the noise amplitude within the target frequency range; The coordinates of the power supply noise source corresponding to the target resonant frequency point are determined based on the current phase distribution of the initial three-dimensional packaging model. In the power supply network layer of the initial three-dimensional packaging model, an annular capacitor arrangement region centered on the coordinates of the power noise source is constructed, and the annular capacitor arrangement region is divided into several capacitor arrangement sectors. Within each capacitor arrangement sector, a combination of decoupling capacitors with different capacitance values ​​is set, and a power supply via array is generated within the annular capacitor arrangement area by setting the phase offset angle of the power supply vias between adjacent sectors. Based on the current distribution characteristics of the power supply via array, the aperture size of each via in the power supply via array is configured in a gradient manner to generate the three-dimensional arrangement and aperture parameters of the power supply via.

[0009] Optionally, in a fifth implementation of the first aspect of this application, the step of generating the geometric parameters of the ring shield structure around the high-speed signal path of the initial three-dimensional encapsulation model based on the crosstalk index of the signal integrity dataset includes: The coupling strength distribution between high-speed signal paths is determined based on the crosstalk index of the signal integrity dataset, and signal path segments with coupling strength exceeding a preset strength threshold are identified based on the coupling strength distribution, generating a set of coordinates of paths to be shielded. A coaxial shielding cavity base is constructed with the high-speed signal path as the central axis, and a variable spacing shielding profile is generated by configuring the spacing gradient between the shielding cavity base and the adjacent high-speed signal path. Electromagnetic bandgap structural units are configured at the top and bottom of the shielding cavity substrate, and an electromagnetic shielding layer is constructed in the shielding cavity substrate by configuring the periodic geometric pattern of the electromagnetic bandgap structural units and the depth parameters of the metallized vias. The geometric parameters of the annular shielding structure are determined by spatially superimposing the variable-pitch shielding profile with the electromagnetic shielding layer.

[0010] Optionally, in the sixth implementation of the first aspect of this application, after the step of integrating the heat dissipation topology parameters, the three-dimensional arrangement and aperture parameters of the power supply vias, and the geometric parameters of the annular shielding structure into the initial three-dimensional packaging model to obtain the target three-dimensional packaging model, the method further includes: Based on the temperature distribution dataset and the stress-strain distribution, a third region in the initial three-dimensional packaging model where the thermomechanical stress exceeds the yield threshold is determined; Based on the stress vector distribution in the third region, design parameters for the three-dimensional interlocking microstructure at the interface between the silicon interposer and the packaging substrate are generated. Based on the heat flow path of the heat dissipation topology parameters, the arrangement density of the three-dimensional interlocking microstructure is optimized to generate high porosity arrangement parameters. The target three-dimensional packaging model is further optimized by integrating the design parameters and arrangement density parameters of the three-dimensional interlocking microstructure into the target three-dimensional packaging model.

[0011] A second aspect of this application provides a flash memory stack packaging optimization apparatus, which is used to implement a flash memory stack packaging optimization method. The flash memory stack packaging optimization apparatus includes: The simulation module is used to perform coupled simulation on the initial three-dimensional packaging model of the flash memory stack to obtain the performance dataset of the flash memory stack under the target workload. The generation module is used to identify performance defects of the initial three-dimensional packaging model in terms of thermal management, power integrity and signal integrity based on the performance dataset, and generate packaging structure optimization parameters corresponding to each performance defect respectively. An optimization module is used to integrate the optimization parameters of the packaging structure into the initial three-dimensional packaging model to obtain the target three-dimensional packaging model.

[0012] A third aspect of this application provides an electronic device, including a memory and a processor, wherein the processor is configured to execute a computer program stored in the memory, and when the processor executes the computer program, it implements the steps of the flash memory stack packaging optimization method provided in the first aspect of this application.

[0013] The fourth aspect of this application provides a computer-readable storage medium storing a computer program thereon. When the computer program is executed by a processor, it implements the steps of the flash memory stack packaging optimization method provided in the first aspect of this application.

[0014] In summary, according to the flash memory stack packaging optimization method, apparatus, device, and storage medium provided in this application, a coupled simulation is performed on the initial three-dimensional packaging model of the flash memory stack to obtain a performance dataset of the flash memory stack under a target workload. Based on the performance dataset, performance defects of the initial three-dimensional packaging model in terms of thermal management, power integrity, and signal integrity are identified, and corresponding packaging structure optimization parameters are generated for each performance defect. The packaging structure optimization parameters are integrated into the initial three-dimensional packaging model to obtain the target three-dimensional packaging model. This application obtains a performance dataset by coupled simulation of the initial three-dimensional packaging model, identifies packaging defects of the initial three-dimensional packaging model based on the performance dataset, generates a corresponding set of packaging structure optimization parameters, and integrates them into a unified model. This can improve the accurate heat dissipation of high heat flux density areas, effectively reduce the impedance of the power distribution network, suppress crosstalk between high-speed signal paths, and achieve the optimal balance of overall performance. Attached Figure Description

[0015] Figure 1 A flowchart illustrating the flash memory stack packaging optimization method provided in this application embodiment; Figure 2 A schematic diagram of the program modules of the flash memory stack packaging optimization apparatus provided in the embodiments of this application; Figure 3 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0016] To make the inventive objectives, features, and advantages of this application more apparent and understandable, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0017] To address the inefficiencies and performance bottlenecks inherent in three-dimensional stacked packaging structures in related technologies, this application provides a flash memory stack packaging optimization method, such as... Figure 1 This is a flowchart illustrating the flash memory stack packaging optimization method provided in this embodiment. The processing of this method is executed in a three-dimensional simulation software environment for thermo-mechanical-electrical multiphysics coupling. The computer processes temperature distribution data, stress-strain data, and signal integrity data within the model domain, and generates geometric parameters, arrangement parameters, and shielding structure parameters of the three-dimensional structure based on the calculation results. The content of this invention does not involve the direct manufacturing of physical hardware; the generated structure is only used as a data expression form in the simulation results to guide subsequent possible process design.

[0018] The flash memory stack packaging optimization method includes the following steps: Step 110: Perform coupled simulation on the initial three-dimensional packaging model of the flash memory stack to obtain the performance dataset of the flash memory stack under the target workload.

[0019] Specifically, the performance dataset includes a temperature distribution dataset, a power impedance spectrum, and a signal integrity dataset. During coupled simulation of the initial 3D packaging model of the flash memory stack, heat conduction, current distribution behavior, and high-speed electromagnetic propagation are simultaneously described within a unified physical solution framework. This allows for variable exchange between different physical fields under the same geometric structure, resulting in a temperature field, power distribution network response, and high-speed signal propagation state that reflect the actual operating state of the target workload. The simulation uses power consumption distribution, power input characteristics, and signal edge driving as excitations, causing the power density, current path, and electromagnetic coupling behavior within the model to evolve synchronously in time and space. During the calculation, it continuously outputs the 3D temperature distribution over time, the power impedance response curves at different frequencies, and the reflection and crosstalk waveforms of the high-speed signal path. Thus, the temperature distribution dataset, power impedance spectrum, and signal integrity dataset are formed, reflecting the thermal behavior, power stability, and signal quality within the flash memory stack.

[0020] Step 120: Identify the performance defects of the initial 3D packaging model in terms of thermal management, power integrity and signal integrity based on the performance dataset, and generate packaging structure optimization parameters corresponding to each performance defect.

[0021] Specifically, regions exceeding a first temperature threshold in the initial 3D packaging model are identified based on the temperature distribution dataset. By filtering the recorded temperature peak locations and spatial diffusion trajectories, local high-temperature clusters are clearly identified in 3D spatial coordinates. Since temperature exhibits a continuous distribution within the structure, high-temperature regions typically possess significant spatial connectivity and gradient characteristics. Therefore, based on the range where temperatures exceed the threshold, a set of paths diffusing from the hotspot center to the low-temperature region can be generated, and the heat dissipation topology parameters can be constructed accordingly. This topology is dominated by the gradient direction of the temperature field, enabling heat conduction paths to form describable connectivity within the structure and indicating the heat transfer trends in different materials and geometric layers. Regions where power supply noise exceeds the noise amplitude in the initial 3D packaging model are determined based on the power supply impedance spectrum. By examining the peaks, valleys, and abrupt changes in the impedance curves across different frequency ranges, the noise response intensity of the power supply network under electromagnetic excitation can be identified, and the spatial distribution of noise amplitudes exceeding the threshold is defined as power supply noise concentration areas. Based on this, by analyzing the relationship between this region and the power supply layer, return layer, and metallized vias, a three-dimensional arrangement of the power supply vias can be constructed. The vias are arranged in space to avoid resonance enhancement paths, and the via diameter is adjusted based on the distribution of local current density to suppress power supply noise paths. Thus, a three-dimensional via arrangement structure and aperture parameters matching the noise region can be obtained. Based on the crosstalk index in the signal integrity dataset, the geometric parameters of a ring-shaped shielding structure are generated around the high-speed signal path in the initial three-dimensional packaging model. By identifying path segments where the crosstalk amplitude exceeds the index threshold, the location of electromagnetic coupling enhancement can be determined, and a concentric layout space is constructed with the geometric centerline of the high-speed signal path as a reference. Subsequently, a surrounding body is generated along the path according to the crosstalk distribution characteristics. By adjusting the relative distance between this surrounding body and adjacent signal paths, the wall thickness distribution, and the matching relationship with the interlayer structure, the shielding structure forms a closed or semi-closed ring shape in space, thereby reducing electromagnetic leakage and coupling strength. The geometric parameters of this ring-shaped shielding structure can be optimized according to the directional distribution of crosstalk, enabling targeted protection on different signal segments.

[0022] Step 130: Integrate the heat dissipation topology parameters, the three-dimensional arrangement and aperture parameters of the power supply vias, and the geometric parameters of the annular shielding structure into the initial three-dimensional packaging model to obtain the target three-dimensional packaging model.

[0023] Specifically, the heat dissipation topology parameters, the three-dimensional arrangement and aperture parameters of the power supply vias, and the geometric parameters of the annular shielding structure are integrated into the initial three-dimensional packaging model. By coordinating the arrangement of thermal paths, power paths, and signal shielding within a unified three-dimensional framework, the target three-dimensional packaging model possesses a comprehensive structural form oriented towards thermal management, power integrity, and signal integrity. Through parameter integration, structures corresponding to different physical requirements are incorporated into the same packaging entity, thereby providing the final model foundation for subsequent performance evaluation, structural iteration, and manufacturing preparation.

[0024] In one optional implementation of this embodiment, before the step of performing coupled simulation on the initial three-dimensional packaging model of the flash memory stack, the method further includes: obtaining the hierarchical description file and material library of the flash memory stack; generating the core component of the flash memory stack based on the connection relationship configured in the hierarchical description file and the material property parameters stored in the material library; constructing the wiring layer and power / ground layer of the packaging substrate according to the peripheral interface configuration of the core component, and generating a substrate frame interconnected with the core component; determining the corresponding packaging filler material parameters according to the gap area between the core component and the substrate frame; and combining the core component, the substrate frame, the packaging filler material parameters, and the boundary entities of the corresponding core component to generate the initial three-dimensional packaging model.

[0025] In this embodiment, before performing coupled simulation on the initial 3D packaging model of the flash memory stack, a layer description file and a material library are first obtained. The layer description file describes the connection relationships, arrangement order, and spatial positioning between the layers inside the chip, while the material library stores the material property parameters of different components, including thermal conductivity, coefficient of thermal expansion, electrical conductivity, and dielectric constant. By reading the connection methods recorded in the layer description file, the spatial relationships of the flash memory chip, logic unit, and interconnect structure can be organized into assemblable structural objects, and the parameters of the material library are mapped to the corresponding components, so that each object has properties that can be used for physical analysis, thereby forming a core component with complete functionality. For example, in a multilayer flash memory stack, if a certain layer is a copper interconnect structure, its thermal conductivity and current carrying capacity will be determined according to the copper property parameters in the material library, so as to realistically reflect the heat diffusion trend and current distribution law in subsequent simulations. After obtaining the core component, the wiring layer and power / ground layer of the packaging substrate are constructed according to the peripheral interface configuration of the core component. The wiring layer refers to the wire area installed inside the substrate for transmitting data signals, while the power / ground layer includes the power plane that provides power supply path for the core component and the ground plane that serves as an electrical reference plane. By reading the number of interfaces, interface spacing, and signal type of the core components, corresponding signal traces can be arranged on the substrate. Simultaneously, ground planes can be segmented within the power and ground structure to isolate different power domains from the ground reference domain. For example, in high-speed signal regions, a continuous ground reference plane can be placed below the signal path to reduce signal coupling, while a larger power plane can be used in high-current power supply regions to maintain stable power supply. This generates a substrate frame that interconnects with the core components, enabling accurate mounting and effective electrical connection of the core components. The encapsulation filler material parameters are determined based on the gap between the core components and the substrate frame. The encapsulation filler material fills the space between components not yet occupied by the solid structure, providing sufficient mechanical support and thermal conductivity for the overall structure. If the gap is close to the heat dissipation path, an inorganic filler material with higher thermal conductivity can be selected to facilitate faster heat transfer to the outside. If the gap is located in a region prone to electromagnetic interference, a resin material with a suitable dielectric constant can be used to maintain a stable signal propagation environment. For example, when there is an irregular cavity between the top of the core component and the substrate frame, the distribution of the filler material can be adjusted according to the cavity shape to achieve a proper balance between thermal conductivity and dielectric properties in the filler structure. Finally, the core components, substrate frame, encapsulation filling material parameters, and corresponding boundary entities of the core components are combined. Boundary entities refer to the geometric boundary information used to describe the shape contour, stress range, and heat exchange interface. By geometrically superimposing and structurally associating all objects in space, an initial three-dimensional encapsulation model can be generated, giving it complete physical boundaries and material properties, and reflecting key characteristics such as connection methods, heat transfer paths, current channels, and dielectric environment.For example, during the 3D assembly process, if the core component is adjacent to the substrate frame, their boundary entities will automatically form a contact relationship, thus reflecting the changes in contact thermal resistance and local stress in subsequent simulations. The initial 3D packaging model constructed in this way has the conditions for coupled simulation and can provide a complete physical basis for thermal, electrical, and mechanical analysis.

[0026] In one optional implementation of this embodiment, the step of performing coupled simulation on the initial three-dimensional packaging model of the flash memory stack to obtain the performance dataset of the flash memory stack under the target workload includes: meshing the initial three-dimensional packaging model according to the geometry and material properties of the initial three-dimensional packaging model to obtain a physical field discretization model; loading the boundary conditions of the target workload onto the multiphysics discretization model to obtain the spatiotemporal distribution of temperature field, current density distribution, and stress-strain distribution of the flash memory stack under transient operating conditions; extracting the coordinates of the region where the peak temperature exceeds a first threshold based on the spatiotemporal distribution of temperature field to generate a temperature distribution dataset; calculating the impedance frequency response of the power distribution network based on the current density distribution to generate a power impedance spectrum; and performing full-wave electromagnetic field simulation on the physical field discretization model based on the stress-strain distribution to extract the time-domain reflection characteristics and crosstalk parameters of the high-speed signal path to generate a signal integrity dataset.

[0027] In this embodiment, the geometric domain is finely meshed based on the geometry and material properties of the initial 3D packaging model, so that the continuous physical field is approximately represented on discrete units. The size and shape of the mesh units are adaptively adjusted according to local geometric details and physical field gradients to obtain higher resolution at thermal gradients, current concentrations, and stress concentrations. Furthermore, by defining the material properties such as thermal conductivity, electrical conductivity, elastic modulus, and dielectric constant in each unit, a discretized physical field model is obtained. Then, boundary conditions representing the target workload are applied to this discretized model, including time-varying power consumption distribution as a heat source, current injection forces and potential constraints at different nodes, and mechanical constraints and external loads at the interface between the device and the substrate, to carry out transient coupling solutions. This yields the spatiotemporal distribution of the temperature field, current density field, and stress-strain field that evolve over time, reflecting heat, electricity, and force. The interaction between them; by scanning time-series data, the coordinates of the positions where the peak value in the temperature field exceeds the first threshold are extracted and the peak time point and spatial range are recorded to generate a temperature distribution dataset; and based on the experimental processing of the current density field in the frequency domain response, the method of exciting the power supply network nodes point by point within the target frequency range to measure the corresponding voltage response is adopted, so as to obtain the frequency dependence of voltage and excitation current and form the impedance frequency response curve of the power supply network, which is then summarized into the power supply impedance spectrum; based on the stress and strain distribution, the discretized geometry is deformed and the material parameters are fine-tuned, and then the corrected geometry and material properties are used as input to perform full-wave time-domain electromagnetic field simulation. By sending typical time-domain pulses in the high-speed channel and recording the reflected waveform and the induced waveform of the adjacent line pairs, the time-domain reflection characteristics and near-end / far-end crosstalk parameters are extracted, so as to generate a complete signal integrity dataset.

[0028] In one optional embodiment of this example, the step of generating heat dissipation topology parameters based on the distribution of the first region includes: determining a first region exceeding a first temperature threshold in the initial packaging structure model based on a temperature distribution dataset; generating a heat-directed conduction path from a high-temperature region to a low-temperature region within the silicon interposer of the initial three-dimensional packaging model based on the temperature gradient vector between the first regions; configuring an asymmetric thermally conductive unit array on the heat-directed conduction path and constructing a heat conduction structure by configuring the thermal resistance gradient at the interface between adjacent units in the thermally conductive unit array; determining micropump structure parameters at the position corresponding to the center of the first region in the heat conduction structure, and generating a capillary pump ring by configuring the porosity distribution of the porous wicking material and the cross-sectional change parameters of the vapor cavity channel in the micropump structure parameters; and arranging the heat conduction structure and the capillary pump ring in a three-dimensional interwoven arrangement to obtain the heat dissipation topology parameters.

[0029] In this embodiment, when processing the initial packaging structure model based on the temperature distribution dataset, regions with temperature values ​​exceeding a first temperature threshold are first identified in three-dimensional space through scanning. Since the temperature distribution dataset records the temperature changes of various parts of the material over time and location under external load, it directly reflects the way heat accumulates inside the packaging structure. The first temperature threshold refers to the temperature limit used to determine whether the material has entered a high-temperature risk state; it is set based on the characteristic temperature range where the material is prone to deformation or performance degradation under high-temperature environments. When a temperature value continuously exceeds this limit in three-dimensional space, adjacent high-temperature points in the space are clustered into a continuum and defined as the first region. If high-temperature areas exhibit multi-center distribution in certain regions, spatial connectivity analysis can be used to treat multiple related high-temperature centers as a whole to avoid misjudging local hotspots as discontinuous bodies. After determining the temperature gradient vector between the first regions, a heat-directed conduction path from the high-temperature region to the low-temperature region is generated within the silicon interposer of the initial three-dimensional packaging model based on the temperature gradient vector. The temperature gradient vector represents the direction of heat diffusion from a high-temperature location to a low-temperature location. Its magnitude reflects the local temperature change rate. By calculating the difference between discrete coordinates of the temperature field, the direction of temperature change can be obtained in three-dimensional space. Based on this temperature change direction, a continuous directional path can be drawn inside the silicon interposer, allowing the path to advance segment by segment along the gradient direction. For example, if a local high temperature occurs in the upper left region of the silicon interposer, while the temperature is lower in the lower right region, a heat conduction path extending from the upper left to the lower right can be generated based on the temperature gradient vector, aligning the path with the natural heat diffusion direction. After generating the directional heat conduction path, an array of asymmetric thermally conductive units is configured along the path. These units enhance heat transfer capabilities within localized areas, and the asymmetric structure refers to their geometry having different heat diffusion capabilities in different directions, such as a sharp cone at one end and a stepped structure at the other, making it easier for heat to advance along the gradient direction. During the configuration of the thermally conductive units, the spacing between them can be gradually reduced according to the path direction, resulting in a higher thermal conductivity density at the high-temperature end, thereby improving the efficiency of heat flow in the low-temperature direction. A thermal resistance gradient is set at the interface between adjacent heat-conducting units. This gradient refers to artificially designing different thermal resistance values ​​at different interface locations, allowing the thermal conductivity to vary controllably along the path. For example, the interface thermal resistance near the high-temperature end can be lower, making it easier for heat to flow into the array, while the thermal resistance is gradually increased in the middle of the path to regulate the heat flow rate. This constructs an overall heat conduction structure, enabling heat to propagate more stably along a directional path. After establishing the heat conduction structure, the micropump structural parameters are determined at the center of the corresponding first region. The micropump structural parameters refer to a miniature device that actively enhances heat transfer capabilities using liquid evaporation, condensation, and capillary action, forming a cyclical steam movement path through the wick and steam chamber.The porous wicking material is used to generate capillary pressure differences within the microscopic channels, enabling the liquid to spontaneously flow towards the evaporation zone. Its porosity distribution determines the liquid flow rate and absorption capacity. By setting a porosity distribution that decreases from the high-temperature region to the low-temperature region, the liquid can have a stronger replenishment capacity near the high-temperature region, thereby maintaining a stable evaporation process. Furthermore, the cross-section of the steam chamber channel is adjusted according to the heat flow direction, with a larger cross-section at the high-temperature end to release steam, and a smaller cross-section at the low-temperature end to promote steam flow towards the condensation region. For example, a wedge-shaped expansion cavity is set at the high-temperature end to allow steam to accumulate rapidly, while a convergence channel is set at the condensation end to allow condensate to drain back into the wicking material, thus forming a closed loop and generating a capillary pump ring. This transforms the heat transfer mechanism from a single diffusion mechanism to a structure jointly promoted by diffusion and phase change. After completing the construction of the heat conduction structure and the capillary pump ring, the two are arranged in a three-dimensional interwoven pattern, so that the heat conduction unit and the capillary pump ring are complementary in space. By distributing capillary pump rings on the sidewalls of the path and placing the heat-conducting unit at the center of the path, heat can be quickly guided from the heat-conducting unit to the capillary pump rings and then diffused outward through the capillary driving effect, thereby forming a three-dimensional heat dissipation topology.

[0030] In one optional embodiment of this example, the steps of determining a second region in the initial three-dimensional package model where the power supply noise exceeds the noise amplitude based on the power supply impedance spectrum, and generating the three-dimensional arrangement and aperture parameters of power supply vias based on the distribution of the second region, include: performing frequency domain feature decomposition on the power supply impedance spectrum to extract the target resonant frequency point corresponding to the second region where the impedance amplitude exceeds the noise amplitude within the target frequency range; determining the coordinates of the power supply noise source corresponding to the target resonant frequency point based on the current phase distribution of the initial three-dimensional package model; constructing an annular capacitor arrangement region centered on the power supply noise source coordinates in the power supply network layer of the initial three-dimensional package model, and dividing the annular capacitor arrangement region into several capacitor arrangement sectors; setting decoupling capacitor combinations with different capacitance values ​​in each capacitor arrangement sector, and generating a power supply via array within the annular capacitor arrangement region by setting the phase offset angle of the power supply vias between adjacent sectors; and performing gradient configuration of the aperture size of each via in the power supply via array based on the current distribution characteristics of the power supply via array to generate the three-dimensional arrangement and aperture parameters of the power supply vias.

[0031] In this embodiment, when processing the power supply impedance spectrum, frequency domain feature decomposition is performed on the impedance-frequency curve. Frequency domain feature decomposition refers to analyzing the impedance values ​​at different frequency points point by point. By comparing the relationship between the impedance amplitude and the noise amplitude at each frequency point, the region where the impedance amplitude exceeds the noise amplitude within the target frequency range is determined, and the corresponding target resonant frequency point is found within this region. The resonant frequency point refers to the location where energy concentration occurs in the power supply network, essentially reflecting the voltage fluctuation enhancement effect caused by local structures. To extract the target resonant frequency point, the amplitude of each frequency point in the impedance spectrum can be read sequentially in a frequency-by-frequency scanning manner. When the impedance of multiple consecutive frequency points increases significantly and reaches a peak at a certain point, this peak position can be taken as the target resonant frequency point. After obtaining the target resonant frequency point, the coordinates of the power supply noise source corresponding to the target resonant frequency point are determined based on the current phase distribution of the initial three-dimensional packaging model. The current phase distribution refers to the phase difference of current fluctuations at different locations within the power supply network. By analyzing the phase changes near the resonant frequency point, the location of local current phase reversal or enhancement can be located, and this location is often the noise source region causing resonance. To determine the coordinates of the noise source, the current phase can be analyzed node by node along the power supply network. When a node exhibits a significant phase shift at its resonant frequency, the location of that node can be considered the noise source. If the power supply network has a multi-layered structure with multiple branches, the noise source can be located by scanning the phase values ​​of key nodes in each layer. After determining the noise source coordinates, a ring-shaped capacitor arrangement area centered on the noise source coordinates is constructed in the power supply network layer of the initial 3D encapsulation model. The ring-shaped area refers to a concentric circular arrangement strip around the noise source, used to arrange decoupling capacitors to effectively suppress power supply ripple in this area. To enhance the ability to handle noise at different frequencies, the ring-shaped area is divided into several capacitor arrangement sectors, each covering a specific angular range. By setting different combinations of decoupling capacitors with varying capacitance values, the sectors provide different filtering capabilities in different frequency bands. Decoupling capacitors provide transient current buffering for the power supply network; larger capacitance values ​​result in stronger low-frequency filtering capabilities, while smaller capacitance values ​​provide better high-frequency response. Therefore, by combining capacitors with different capacitance values ​​within a sector, multiple frequency bands can be covered simultaneously. A power supply via array is generated between adjacent sectors by setting the phase offset angle of the vias. A power supply via refers to a metal channel connecting different power supply surfaces in the vertical direction of the substrate. The phase offset angle refers to the rotational orientation of the via relative to the capacitor placement direction within the annular region. By adjusting this angle, the vias within the annular region are arranged in a rotating, staggered pattern, thereby avoiding concentrated current paths between vias and reducing high-frequency noise caused by via coupling. Based on the current distribution characteristics of the power supply via array, the aperture size of each via in the array is configured in a gradient manner.Gradient configuration refers to gradually changing the diameter of vias from the inside to the outside of a ring-shaped region. Vias closer to noise sources have larger diameters to absorb more current fluctuations, while those farther from noise sources have smaller diameters to reduce unnecessary electromagnetic interference. For example, larger diameters can be used near the center to enhance current regulation, while smaller diameters are used on the outer ring to maintain overall structural stability. By adjusting the size and density of the vias, the three-dimensional arrangement and diameter parameters of the power supply vias can be generated, giving the power supply network layer optimized filtering capabilities in both the spatial and frequency domains, thereby effectively reducing power supply noise at the target resonant frequency.

[0032] In one optional implementation of this embodiment, the step of generating the geometric parameters of a ring shielding structure around the high-speed signal path of the initial three-dimensional encapsulation model based on the crosstalk index of the signal integrity dataset includes: determining the coupling strength distribution between high-speed signal paths based on the crosstalk index of the signal integrity dataset, identifying signal path segments with coupling strength exceeding a preset strength threshold based on the coupling strength distribution, and generating a set of coordinates of the paths to be shielded; constructing a coaxially surrounding shielding cavity base with the high-speed signal path as the central axis, and generating a variable-spacing shielding profile by configuring the spacing gradient between the shielding cavity base and adjacent high-speed signal paths; configuring electromagnetic bandgap structural units at the top and bottom of the shielding cavity base, and constructing an electromagnetic shielding layer in the shielding cavity base by configuring the periodic geometric pattern of the electromagnetic bandgap structural units and the depth parameters of the metallized vias; and spatially superimposing the variable-spacing shielding profile and the electromagnetic shielding layer to determine the geometric parameters of the ring shielding structure.

[0033] In this embodiment, when judging the coupling strength distribution between high-speed signal paths based on the crosstalk index in the signal integrity dataset, it is necessary to collect crosstalk values ​​along the length of each high-speed line in the three-dimensional encapsulation geometry and form a two-dimensional or three-dimensional matrix between adjacent conductors in order to obtain the coupling amplitude and phase relationship at each location point. The crosstalk index is used to quantify the voltage or current induction caused by a line when it sends a signal to the adjacent line. Therefore, by performing spatial interpolation and smoothing on the sampling matrix, a coupling strength field covering the entire interconnection area can be obtained. Then, based on a preset strength threshold, a threshold judgment is performed on the coupling strength field to identify continuous segments with coupling strength exceeding the threshold and extract their coordinate sequence in three-dimensional space, thereby forming a set of coordinates of the path to be shielded. This set clearly indicates the line segments and locations that need to be shielded first. For example, when two parallel conductors have a very small parallel distance and the same direction in a certain segment, resulting in a coupling peak, the coordinates of that segment will be marked into the set for accurate coverage. After establishing the coordinate set of the paths to be shielded, a coaxial shielding cavity base is constructed with each high-speed signal line to be protected as the central axis. The range of electromagnetic field activity is limited by generating a coaxially wrapped spatial strip around the signal line. The cross-sectional shape of the shielding cavity base can be deformed along the length direction according to the geometric direction of the signal line to ensure the continuity of the coverage. Furthermore, a variable spacing shielding profile is generated by setting a spacing gradient between the cavity base and adjacent high-speed signal paths. The spacing gradient refers to the controllable change of the distance between the outer wall of the cavity and the adjacent conductor along the axial direction. In this way, the spacing is reduced in areas with high coupling strength to enhance the shielding effect, while the spacing is appropriately widened in areas with low coupling to avoid occupying too much space or affecting the wiring. For example, if a certain path has extremely strong coupling due to parallel routing, the wall thickness or inner and outer diameter of the shielding cavity is locally adjusted radially in that section to shorten the electromagnetic field leakage path, thereby forming a ring-shaped coverage profile in space that both conforms to geometry and changes according to coupling requirements. Electromagnetic bandgap structural units are arranged at the top and bottom of the shielded cavity substrate to suppress lateral propagation in a specific frequency band in the frequency domain. These units are microstructures composed of periodic geometric patterns that disrupt the propagation conditions of electromagnetic waves at specific wavelengths, creating a propagation-blocking effect within a selected frequency band. To achieve this, periodic slots, perforations, or metal patches are arranged on the upper and lower surfaces of the cavity, combined with several metallized vias to establish electromagnetic coupling and blocking channels between the upper and lower layers. The depth and diameter of the metallized vias jointly determine their impedance characteristics at different frequencies. Therefore, adjusting the via depth can enhance the isolation effect of the bandgap structure within the target frequency band. To better match spatial constraints, a denser arrangement of bandgap units and appropriately increased via depth can be selected in the high-frequency sensitive band, while the period and via parameters are adjusted in the low-frequency sensitive band to achieve frequency selectivity.The variable-pitch shielding profile and the electromagnetic shielding layer are superimposed in three-dimensional space to determine the final geometric parameters of the ring shielding structure. By precisely aligning the spatial shell of the profile with the bandgap elements at the top and bottom according to coordinates, the lateral distance variation, wall shape, period of the bandgap elements, and through-hole depth work together to form a composite shield that meets both spatial coverage requirements and frequency selective suppression performance. During the superposition process, it is necessary to check the interference between the shield and the original wiring, power supply through-holes, and thermal channels, and adjust the relative positions as necessary to avoid physical conflicts. For example, in a tortuous line section, the period of the bandgap elements can be finely adjusted along the bending direction and the through-holes can be arranged in an arc shape to maintain the continuity of the bandgap effect. The final output geometric parameters include the inner and outer diameter distribution curves of the shield, the wall thickness distribution, the geometric dimensions and period of the bandgap elements, the depth of the through-holes, and the coordinate distribution on the ring.

[0034] In one optional embodiment of this example, after integrating the heat dissipation topology parameters, the three-dimensional arrangement and aperture parameters of the vias, and the geometric parameters of the annular shielding structure into the initial three-dimensional packaging model to obtain the target three-dimensional packaging model, the method further includes: determining a third region in the initial three-dimensional packaging model where the thermomechanical stress exceeds the yield threshold based on the temperature distribution dataset and stress-strain distribution; generating design parameters for the three-dimensional interlocking microstructure at the interface between the silicon interposer and the packaging substrate based on the stress vector distribution of the third region; optimizing the arrangement density of the three-dimensional interlocking microstructure based on the heat flow path of the heat dissipation topology parameters to generate high porosity arrangement parameters; and performing secondary optimization of the target three-dimensional packaging model by integrating the design parameters and arrangement density parameters of the three-dimensional interlocking microstructure into the target three-dimensional packaging model.

[0035] In this embodiment, when comparing and analyzing the initial three-dimensional encapsulation model based on the temperature distribution dataset and stress-strain distribution, the two types of field components are superimposed and mapped in the spatial coordinate system to identify stress concentration points caused by thermal load. Thermomechanical stress refers to the mechanical stress generated by the interaction between the material's thermal expansion or contraction and structural constraints. The yield threshold refers to the critical stress value at which the material transitions from elastic deformation to plastic deformation. Therefore, when the thermomechanical stress amplitude at a certain location continuously exceeds this threshold, that location is marked as a high-risk area and included in the scope determination of the third region. If multiple adjacent high-stress points exist in space, they are connected... The stress analysis is merged into continuous segments to reflect the actual failure trend. Then, the design parameters of the three-dimensional interlocking microstructure are generated based on the stress vector distribution inside the third region. The stress vector distribution represents the magnitude and direction of stress at each sampling point. The three-dimensional interlocking microstructure refers to the formation of micro-scale convex and concave units that can interlock at the interface to improve the interface's load-bearing and dispersion capabilities. The design parameters include the microstructure geometry, orientation, height, width, and chamfer form of the contact surface with the substrate. These parameters need to be oriented along the principal stress direction in order to guide concentrated stress to multiple interlocking channels for dispersion, thereby reducing local peak values. The heat flow path of the interlocking microstructure is optimized by combining the heat flow path of the previously formed heat dissipation topology parameters. The heat flow path gives the main heat transfer channel in three-dimensional space. The arrangement density is the number distribution of microstructure units per unit volume or unit area. Therefore, in areas with strong heat flow and high stress, the microstructure density can be increased to enhance the interface stiffness and fatigue life, while in areas with weak heat flow and low stress, the density can be reduced to maintain high porosity to facilitate heat flow penetration. Porosity refers to the ratio of void volume to total volume in the structure. High porosity arrangement parameters need to ensure mechanical reinforcement while minimizing the obstruction of heat conduction and fluid channels. The optimization process generates a set of arrangement parameters that takes into account both mechanical and thermal conduction characteristics by traversing different density configurations and evaluating the effects of interface stress distribution and thermal resistance. The design parameters and arrangement density parameters of the three-dimensional interlocking microstructure are integrated into the target three-dimensional packaging model for secondary optimization. The integration process includes automatically inserting interlocking units at the packaging interface according to the parameters and ensuring geometric continuity and manufacturing tolerance matching. Subsequently, the integrated overall structure is verified by mechanical and thermal simulation to confirm that the interface stress peak has been effectively suppressed and the thermal resistance change is within an acceptable range. If the verification results do not meet the design goals, the microstructure size or density is adjusted according to preset rules and the verification is repeated until the synergistic goals of mechanical reliability and thermal management performance are met. This achieves the improvement of the functionality and reliability of the target three-dimensional packaging model under thermomechanical coupling constraints.

[0036] According to the flash memory stack packaging optimization method provided in this application, a coupled simulation is performed on an initial three-dimensional packaging model of the flash memory stack to obtain a performance dataset of the flash memory stack under a target workload. Based on the performance dataset, performance defects of the initial three-dimensional packaging model in terms of thermal management, power integrity, and signal integrity are identified, and corresponding packaging structure optimization parameters are generated for each performance defect. The packaging structure optimization parameters are integrated into the initial three-dimensional packaging model to obtain the target three-dimensional packaging model. This application obtains a performance dataset by coupled simulation of the initial three-dimensional packaging model, identifies packaging defects of the initial three-dimensional packaging model based on the performance dataset, and generates a corresponding set of packaging structure optimization parameters, which are integrated into a unified model. This can improve the accurate heat dissipation of high heat flux density areas, effectively reduce the impedance of the power distribution network, suppress crosstalk between high-speed signal paths, and achieve the optimal balance of overall performance.

[0037] Figure 2 This application provides a flash memory stack packaging optimization apparatus, which can be used to implement the flash memory stack packaging optimization method described in the foregoing embodiments. For example... Figure 2 As shown, the flash memory stack packaging optimization device mainly includes: Simulation module 10 is used to perform coupled simulation on the initial three-dimensional packaging model of the flash memory stack to obtain the performance dataset of the flash memory stack under the target workload. The generation module 20 is used to identify performance defects of the initial three-dimensional packaging model in terms of thermal management, power integrity and signal integrity based on the performance dataset, and generate packaging structure optimization parameters corresponding to each performance defect. The optimization module 30 is used to integrate the packaging structure optimization parameters into the initial three-dimensional packaging model to obtain the target three-dimensional packaging model.

[0038] In an optional embodiment of this invention, the flash memory stack packaging optimization device further includes a construction module. The construction module is used to: acquire a hierarchical description file and a material library for the flash memory stack; generate core components of the flash memory stack based on the connection relationships configured in the hierarchical description file and the material property parameters stored in the material library; configure the wiring layer and power / ground layer of the packaging substrate according to the peripheral interface of the core components, and generate a substrate frame interconnected with the core components; determine the corresponding packaging filler material parameters based on the gap area between the core components and the substrate frame; and combine the core components, the substrate frame, the packaging filler material parameters, and the boundary entities of the corresponding core components to generate an initial three-dimensional packaging model.

[0039] In one optional implementation of this embodiment, the simulation module is specifically used for: meshing the initial three-dimensional packaging model according to its geometric structure and material properties to obtain a physical field discretization model; loading the boundary conditions of the target workload onto the multi-physics discretization model to obtain the spatiotemporal distribution of temperature field, current density distribution, and stress-strain distribution of the flash memory stack under transient operating conditions; extracting the coordinates of regions where the peak temperature exceeds a first threshold based on the spatiotemporal distribution of temperature field to generate a temperature distribution dataset; calculating the impedance frequency response of the power distribution network based on the current density distribution to generate a power impedance spectrum; and performing full-wave electromagnetic field simulation on the physical field discretization model based on the stress-strain distribution to extract the time-domain reflection characteristics and crosstalk parameters of the high-speed signal path to generate a signal integrity dataset.

[0040] In one optional implementation of this embodiment, the first generation module is specifically used to: generate a heat-directed conduction path from a high-temperature region to a low-temperature region within the silicon interposer layer of the initial three-dimensional packaging model based on the temperature gradient vector between the first regions; configure an asymmetric thermally conductive unit array on the heat-directed conduction path, and construct a heat conduction structure by configuring the thermal resistance gradient at the interface between adjacent units in the thermally conductive unit array; determine the micropump structure parameters at the position corresponding to the center of the first region in the heat conduction structure, and generate a capillary pump ring by configuring the porosity distribution of the porous wicking material and the cross-sectional change parameters of the vapor cavity channel in the micropump structure parameters; and arrange the heat conduction structure and the capillary pump ring in a three-dimensional interlaced arrangement to obtain the heat dissipation topology parameters.

[0041] In one optional implementation of this embodiment, the second generation module is specifically used for: performing frequency domain feature decomposition on the power supply impedance spectrum to extract the target resonant frequency point corresponding to the second region where the impedance amplitude exceeds the noise amplitude within the target frequency range; determining the power supply noise source coordinates corresponding to the target resonant frequency point based on the current phase distribution of the initial three-dimensional packaging model; constructing an annular capacitor arrangement region centered on the power supply noise source coordinates in the power supply network layer of the initial three-dimensional packaging model, and dividing the annular capacitor arrangement region into several capacitor arrangement sectors; setting decoupling capacitor combinations with different capacitance values ​​in each capacitor arrangement sector, and generating a power supply via array within the annular capacitor arrangement region by setting the phase offset angle of the power supply vias between adjacent sectors; and generating the three-dimensional arrangement and aperture parameters of the power supply vias based on the current distribution characteristics of the power supply via array and the aperture size of each via in the power supply via array is configured in a gradient manner.

[0042] In one optional implementation of this embodiment, the third generation module is specifically used to: determine the coupling strength distribution between high-speed signal paths based on the crosstalk index of the signal integrity dataset, identify signal path segments with coupling strength exceeding a preset strength threshold based on the coupling strength distribution, and generate a set of coordinates of the paths to be shielded; construct a coaxially surrounding shielding cavity substrate with the high-speed signal path as the central axis, and generate a variable spacing shielding profile by configuring the spacing gradient between the shielding cavity substrate and adjacent high-speed signal paths; configure electromagnetic bandgap structural units at the top and bottom of the shielding cavity substrate, and construct an electromagnetic shielding layer in the shielding cavity substrate by configuring the periodic geometric pattern of the electromagnetic bandgap structural units and the depth parameters of the metallized vias; The geometric parameters of the annular shielding structure are determined by spatially superimposing the variable-pitch shielding profile with the electromagnetic shielding layer.

[0043] In an optional embodiment of this example, the optimization module is further configured to: determine a third region in the initial three-dimensional packaging model where the thermomechanical stress exceeds the yield threshold based on the temperature distribution dataset and the stress-strain distribution; generate design parameters for the three-dimensional interlocking microstructure at the interface between the silicon interposer and the packaging substrate based on the stress vector distribution of the third region; optimize the arrangement density of the three-dimensional interlocking microstructure based on the heat flow path of the heat dissipation topology parameters to generate high porosity arrangement parameters; and perform secondary optimization of the target three-dimensional packaging model by integrating the design parameters and arrangement density parameters of the three-dimensional interlocking microstructure into the target three-dimensional packaging model.

[0044] According to the flash memory stack packaging optimization device provided in this application, a coupled simulation is performed on an initial three-dimensional packaging model of the flash memory stack to obtain a performance dataset of the flash memory stack under a target workload. Based on the performance dataset, performance defects of the initial three-dimensional packaging model in terms of thermal management, power integrity, and signal integrity are identified, and corresponding packaging structure optimization parameters are generated for each performance defect. The packaging structure optimization parameters are integrated into the initial three-dimensional packaging model to obtain the target three-dimensional packaging model. This application obtains a performance dataset by coupled simulation of the initial three-dimensional packaging model, identifies packaging defects of the initial three-dimensional packaging model based on the performance dataset, generates a corresponding set of packaging structure optimization parameters, and integrates them into a unified model. This can improve the accurate heat dissipation of high heat flux density areas, effectively reduce the impedance of the power distribution network, suppress crosstalk between high-speed signal paths, and achieve the optimal balance of overall performance.

[0045] According to the scheme provided in this application Figure 3 An electronic device is provided as an embodiment of this application. This electronic device can be used to implement the flash memory stack packaging optimization method of the foregoing embodiments, mainly including: The system includes a memory 301, a processor 302, and a computer program 303 stored on the memory 301 and executable on the processor 302. The memory 301 and the processor 302 are connected via communication. When the processor 302 executes the computer program 303, it implements the flash memory stack packaging optimization method described in the preceding embodiments. The number of processors can be one or more.

[0046] The memory 301 can be a high-speed random access memory (RAM) or a non-volatile memory, such as a disk storage device. The memory 301 is used to store executable program code, and the processor 302 is coupled to the memory 301.

[0047] Furthermore, embodiments of this application also provide a computer-readable storage medium, which may be disposed in the electronic device of the above embodiments, and the computer-readable storage medium may be as described above. Figure 3 The memory of the embodiment shown.

[0048] The computer-readable storage medium stores a computer program that, when executed by a processor, implements the flash memory stack packaging optimization method of the aforementioned embodiments. Furthermore, the computer-readable storage medium can also be various media capable of storing program code, such as a USB flash drive, external hard drive, read-only memory (ROM), RAM, magnetic disk, or optical disk.

[0049] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0050] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0051] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A flash memory stack packaging optimization method, characterized in that, include: Coupled simulation is performed on the initial three-dimensional packaging model of the flash memory stack to obtain the performance dataset of the flash memory stack under the target workload; Based on the performance dataset, identify the performance defects of the initial 3D packaging model in terms of thermal management, power integrity and signal integrity, and generate packaging structure optimization parameters corresponding to each performance defect. The optimization parameters of the packaging structure are integrated into the initial three-dimensional packaging model to obtain the target three-dimensional packaging model.

2. The flash memory stack packaging optimization method according to claim 1, characterized in that, Before the step of performing coupled simulation on the initial three-dimensional packaging model of the flash memory stack, the method further includes: Obtain the hierarchical description file and material library of the flash memory stack, and generate the core components of the flash memory stack based on the connection relationship configured in the hierarchical description file and the material property parameters stored in the material library; Based on the peripheral interface configuration of the core component, the wiring layer and power / ground layer of the packaging substrate are constructed to generate a substrate frame interconnected with the core component. The corresponding encapsulation filling material parameters are determined based on the gap area between the core component and the substrate frame. The core components, substrate frame, encapsulation filling material parameters, and corresponding boundary entities of the core components are combined to generate an initial three-dimensional encapsulation model.

3. The flash memory stack packaging optimization method according to claim 1, characterized in that, The performance dataset includes a temperature distribution dataset, a power supply impedance spectrum, and a signal integrity dataset. The step of performing coupled simulation on the initial three-dimensional packaging model of the flash memory stack to obtain the performance dataset of the flash memory stack under the target workload includes: The initial three-dimensional encapsulation model is meshed based on its geometric structure and material properties to obtain a discretized physical field model. Boundary conditions of the target workload are applied to the multiphysics discretization model to obtain the spatiotemporal distribution of temperature field, current density distribution and stress-strain distribution of the flash memory stack under transient operating conditions. Based on the spatiotemporal distribution of the temperature field, the coordinates of regions where the peak temperature exceeds the first threshold are extracted to generate a temperature distribution dataset. The impedance frequency response of the power distribution network is calculated based on the current density distribution to generate the power impedance spectrum. Based on the stress-strain distribution, a full-wave electromagnetic field simulation is performed on the discretized physical field model to extract the time-domain reflection characteristics and crosstalk parameters of the high-speed signal path, generating a signal integrity dataset.

4. The flash memory stack packaging optimization method according to claim 3, characterized in that, When the performance dataset is the temperature distribution dataset, the step of identifying performance defects in thermal management, power integrity, and signal integrity of the initial 3D packaging model based on the performance dataset, and generating packaging structure optimization parameters corresponding to each performance defect, includes: Based on the temperature distribution dataset, determine the first region in the initial packaging structure model that exceeds the first temperature threshold; Based on the temperature gradient vector between the first regions, a heat-directed conduction path from the high-temperature region to the low-temperature region is generated within the silicon interposer layer of the initial three-dimensional packaging model. An asymmetric thermal conductive unit array is configured along the heat directional conduction path, and a heat conduction structure is constructed by configuring the thermal resistance gradient at the interface between adjacent units in the thermal conductive unit array. In the heat conduction structure, the micropump structure parameters are determined at the position corresponding to the center of the first region. By configuring the porosity distribution of the porous wicking material and the cross-sectional change parameters of the vapor chamber channel, a capillary pump ring is generated. The heat conduction structure and the capillary pump ring are arranged in a three-dimensional interweaving pattern to obtain the heat dissipation topology parameters.

5. The flash memory stack packaging optimization method according to claim 4, characterized in that, When the performance dataset is the power impedance spectrum, the step of identifying performance defects in thermal management, power integrity, and signal integrity of the initial three-dimensional package model based on the performance dataset, and generating package structure optimization parameters corresponding to each performance defect, further includes: The power supply impedance spectrum is decomposed in the frequency domain to extract the target resonant frequency point in the second region where the impedance amplitude exceeds the noise amplitude within the target frequency range; The coordinates of the power supply noise source corresponding to the target resonant frequency point are determined based on the current phase distribution of the initial three-dimensional packaging model. In the power supply network layer of the initial three-dimensional packaging model, an annular capacitor arrangement region centered on the coordinates of the power noise source is constructed, and the annular capacitor arrangement region is divided into several capacitor arrangement sectors. Within each capacitor arrangement sector, a combination of decoupling capacitors with different capacitance values ​​is set, and a power supply via array is generated within the annular capacitor arrangement area by setting the phase offset angle of the power supply vias between adjacent sectors. Based on the current distribution characteristics of the power supply via array, the aperture size of each via in the power supply via array is configured in a gradient manner to generate the three-dimensional arrangement and aperture parameters of the power supply via.

6. The flash memory stack packaging optimization method according to claim 5, characterized in that, When the performance dataset is the signal integrity dataset, the step of identifying performance defects of the initial 3D packaging model in terms of thermal management, power integrity, and signal integrity based on the performance dataset, and generating packaging structure optimization parameters corresponding to each performance defect, further includes: The coupling strength distribution between high-speed signal paths is determined based on the crosstalk index of the signal integrity dataset, and signal path segments with coupling strength exceeding a preset strength threshold are identified based on the coupling strength distribution, generating a set of coordinates of paths to be shielded. A coaxial shielding cavity base is constructed with the high-speed signal path as the central axis, and a variable spacing shielding profile is generated by configuring the spacing gradient between the shielding cavity base and the adjacent high-speed signal path. Electromagnetic bandgap structural units are configured at the top and bottom of the shielding cavity substrate, and an electromagnetic shielding layer is constructed in the shielding cavity substrate by configuring the periodic geometric pattern of the electromagnetic bandgap structural units and the depth parameters of the metallized vias. The geometric parameters of the annular shielding structure are determined by spatially superimposing the variable-pitch shielding profile with the electromagnetic shielding layer.

7. The flash memory stack packaging optimization method according to claim 6, characterized in that, After the step of integrating the packaging structure optimization parameters into the initial three-dimensional packaging model to obtain the target three-dimensional packaging model, the method further includes: Based on the temperature distribution dataset and the stress-strain distribution, a third region in the initial three-dimensional packaging model where the thermomechanical stress exceeds the yield threshold is determined; Based on the stress vector distribution in the third region, design parameters for the three-dimensional interlocking microstructure at the interface between the silicon interposer and the packaging substrate are generated. Based on the heat flow path of the heat dissipation topology parameters, the arrangement density of the three-dimensional interlocking microstructure is optimized to generate high porosity arrangement parameters. The target three-dimensional packaging model is further optimized by integrating the design parameters and arrangement density parameters of the three-dimensional interlocking microstructure into the target three-dimensional packaging model.

8. A flash memory stack packaging optimization apparatus, characterized in that, The flash memory stack packaging optimization apparatus is used to implement the flash memory stack packaging optimization method according to claim 1, and the flash memory stack packaging optimization apparatus includes: The simulation module is used to perform coupled simulation on the initial three-dimensional packaging model of the flash memory stack to obtain the performance dataset of the flash memory stack under the target workload. The generation module is used to identify performance defects of the initial three-dimensional packaging model in terms of thermal management, power integrity and signal integrity based on the performance dataset, and generate packaging structure optimization parameters corresponding to each performance defect respectively. An optimization module is used to integrate the optimization parameters of the packaging structure into the initial three-dimensional packaging model to obtain the target three-dimensional packaging model.

9. An electronic device, characterized in that, Includes memory and processor, of which: The processor is used to execute computer programs stored in the memory; When the processor executes the computer program, it implements the steps of the flash memory stack packaging optimization method according to any one of claims 1 to 7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps of the flash memory stack packaging optimization method according to any one of claims 1 to 7.

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