Electronic device and method for generating executable files for heterogeneous computing platforms

Abstract

Disclosed are an electronic device and a method for generating an executable file of a heterogeneous computing platform. The electronic device comprises a processor configured to determine a plurality of first source codes corresponding to a neural network model and second source codes representing dependency relationships between the plurality of first source codes; determine first intermediate representations of the first source codes under a same intermediate representation framework; convert the first intermediate representations into first machine instructions suitable for execution on first hardware units matched with the first source codes, respectively; and link at least the first machine instructions based on the second source codes to generate an executable file corresponding to the neural network model. Embodiments of the present disclosure can realize training and deployment of a neural network model and pre / post processing thereof based on one-time development, thereby reducing the amount of code that needs to be developed and reducing development costs.

Description

Technical Field

[0001] This disclosure relates to compilation techniques, and in particular to an electronic device and a method for generating executable files for heterogeneous computing platforms. Background Technology

[0002] Currently, neural network models are widely used. For neural network models and their pre / post-processing, training is generally implemented in one language (such as Python), while deployment is generally implemented in another language (such as C++, which is more low-level than Python). Due to the different implementation languages, two sets of code need to be developed, resulting in very high development costs. Summary of the Invention

[0003] To address the aforementioned technical problems, this disclosure provides an electronic device and a method for generating executable files for heterogeneous computing platforms.

[0004] According to one aspect of the present disclosure, an electronic device is provided, including: a processor; the processor being configured to: Determine multiple first source codes and second source codes corresponding to the neural network model, wherein the second source code represents the dependencies between the multiple first source codes; Determine the first intermediate representation of each of the first source codes within the same intermediate representation framework; Each of the first intermediate representations is converted into a first machine instruction suitable for execution on a first hardware unit that matches the corresponding first source code. Based on the second source code, at least each of the first machine instructions is linked to generate an executable file corresponding to the neural network model.

[0005] According to another aspect of the present disclosure, a method for generating an executable file for a heterogeneous computing platform is provided, comprising: Determine multiple first source codes and second source codes corresponding to the neural network model, wherein the second source code represents the dependency relationship between the multiple first source codes; Determine the first intermediate representation of each of the first source codes within the same intermediate representation framework; Each of the first intermediate representations is converted into a first machine instruction suitable for execution on a first hardware unit that matches the corresponding first source code. Based on the second source code, at least each of the first machine instructions is linked to generate an executable file corresponding to the neural network model.

[0006] According to another aspect of the present disclosure, a computer-readable storage medium is provided, the storage medium storing a computer program that is executed by a processor to implement the above-described method for generating an executable file for a heterogeneous computing platform.

[0007] According to another aspect of the present disclosure, a computer program product is provided that, when instructions in the computer program product are executed by a processor, performs the above-described method for generating an executable file for a heterogeneous computing platform.

[0008] Based on the electronic device, method for generating executable files for heterogeneous computing platforms, medium, and program products provided in the above embodiments of this disclosure, the electronic device can determine multiple first source codes respectively under the same intermediate representation framework as first intermediate representations, and convert each first intermediate representation into first machine instructions suitable for execution on a first hardware unit matching the corresponding first source code. Based on second source code representing the dependencies between multiple first source codes, each first machine instruction is linked to generate an executable file corresponding to the neural network model. It can be seen that in the embodiments of this disclosure, when the first source code of the neural network model to be compiled includes multiple types, they can all be converted into intermediate representations under the same intermediate representation framework, the intermediate representations can be converted into machine instructions suitable for execution on the corresponding hardware unit, and the machine instructions can be linked based on the second source code to generate an executable file corresponding to the neural network model that can be deployed on a heterogeneous computing platform. Therefore, the electronic device based on the embodiments of this disclosure can further use the source code used in the neural network model training stage in the neural network model deployment stage, thereby achieving the training and deployment of the neural network model and its pre / post-processing based on a single development, thereby reducing the amount of code that needs to be developed and lowering development costs. Attached Figure Description

[0009] Figure 1 This is a system architecture diagram to which some exemplary embodiments of this disclosure apply.

[0010] Figure 2 This is a schematic diagram of the structure of an electronic device provided by some exemplary embodiments of this disclosure.

[0011] Figure 3 This is one of the flowcharts used by the processor in some exemplary electronic devices provided in this disclosure.

[0012] Figure 4 This is the second of some exemplary flowcharts of the electronic devices provided in this disclosure, illustrating how a processor implements certain processes.

[0013] Figure 5 This is the third of several exemplary flowcharts illustrating the process implemented by a processor in an electronic device provided in this disclosure.

[0014] Figure 6 This is the fourth of several exemplary flowcharts of the processes used by processors in electronic devices provided in this disclosure.

[0015] Figure 7 This is the fifth of several exemplary flowcharts of the processes used by processors in electronic devices provided in this disclosure.

[0016] Figure 8 This is a schematic diagram illustrating the principle of generating executable files corresponding to neural network models in some exemplary embodiments of this disclosure.

[0017] Figure 9 This is one of the structural schematic diagrams of an apparatus for generating executable files for heterogeneous computing platforms provided by some exemplary embodiments of this disclosure.

[0018] Figure 10 This is a second schematic diagram of an apparatus for generating executable files for heterogeneous computing platforms, provided by some exemplary embodiments of this disclosure.

[0019] Figure 11 This is the third schematic diagram of an apparatus for generating executable files for heterogeneous computing platforms provided by some exemplary embodiments of this disclosure.

[0020] Figure 12 This is the fourth schematic diagram of an apparatus for generating executable files for heterogeneous computing platforms provided by some exemplary embodiments of this disclosure.

[0021] Figure 13 This is the fifth of several exemplary embodiments of the present disclosure, showing a structural diagram of an apparatus for generating executable files for heterogeneous computing platforms.

[0022] Figure 14 This is the sixth of several schematic diagrams of an apparatus for generating executable files for heterogeneous computing platforms provided by some exemplary embodiments of this disclosure.

[0023] Figure 15 This is a schematic diagram of the structure of a heterogeneous computing platform provided by some exemplary embodiments of this disclosure.

[0024] Figure 16 This is a flowchart illustrating a method for calculating tensors provided by some exemplary embodiments of this disclosure. Detailed Implementation

[0025] To explain this disclosure, exemplary embodiments of the disclosure will now be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the disclosure, and not all of them. It should be understood that the disclosure is not limited to exemplary embodiments.

[0026] It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of this disclosure.

[0027] Application Overview Neural network models are widely used in many fields such as computer vision, natural language processing, speech recognition, autonomous driving, and industry. For example, in computer vision, neural network models can be used for image classification and recognition, video analysis, and more. In autonomous driving, neural network models can be used for environmental perception, path planning, and behavior prediction.

[0028] Neural network model preprocessing refers to the processing of data input to the neural network model to ensure that the processed data meets the input requirements of the neural network model. Preprocessing includes, but is not limited to, data format conversion, data cleaning, image resizing, data augmentation, and data normalization.

[0029] Post-processing of neural network models refers to the processing of the output data of the neural network model to make the data structured and understandable for use by downstream applications or users. Post-processing includes, but is not limited to, filtering, structured parsing, and filtering.

[0030] In the process of realizing this disclosure, the inventors discovered that for neural network models and their pre / post-processing, training is generally based on one language and deployment is generally based on another language. Due to the different implementation languages, two sets of code need to be developed, which results in very high development costs.

[0031] Exemplary System Figure 1 This is a system architecture diagram applicable to some embodiments of the present disclosure, including electronic device 110 and heterogeneous computing platform 120.

[0032] Optionally, the heterogeneous computing platform 120 can be a single packaged chip, such as, but not limited to, an intelligent driving chip, an intelligent cockpit chip, or an image processing chip. Alternatively, the heterogeneous computing platform 120 can be a chip cluster composed of multiple chips. The heterogeneous computing platform 120 can include various types of computing units, such as, but not limited to, computing units for supporting tensor computation, computing units for supporting vector computation, and computing units for supporting scalar computation and control flow computation. The computing unit for supporting tensor computation can also be called a Tensor Processing Unit (TPU), and such a computing unit can be, for example, a neural network accelerator. The computing unit for supporting vector computation can also be called a vector processing unit or a vector operation accelerator, and such a computing unit can be, for example, a Graphics Processing Unit (GPU) or a Vision Processing Unit (VPU). The computing unit for supporting scalar computation and control flow computation can be a general-purpose processor, such as a Central Processing Unit (CPU).

[0033] Optionally, electronic device 110 is a device that generates executable files for deployment on heterogeneous computing platform 120. Electronic device 110 includes, but is not limited to, terminal devices, computer systems, servers, etc. Terminal devices include, but are not limited to, personal computers, tablets, etc. Well-known examples of terminal devices, computing systems, environments, and / or configurations suitable for use with electronic devices 110, such as terminal devices, computer systems, servers, etc., include, but are not limited to: personal computer systems, server computer systems, thin clients, thick clients, handheld or laptop devices, microprocessor-based systems, set-top boxes, programmable consumer electronics, network personal computers, minicomputer systems, mainframe computer systems, and distributed cloud computing environments including any of the above systems. Terminal devices may also include in-vehicle intelligent terminals, in-vehicle infotainment terminals, in-vehicle sensing terminals, and in-vehicle computing terminals in vehicle scenarios; or robot body control terminals, robot sensing terminals, robot interaction terminals, robot execution terminals, etc. in robot scenarios.

[0034] In embodiments of this disclosure, during the compilation phase, electronic device 110 can generate an executable file corresponding to the neural network model for deployment on heterogeneous computing platform 120. Specifically, electronic device 110 can determine multiple first source codes and second source codes corresponding to the neural network model, where the second source codes represent the dependencies between the multiple first source codes; determine a first intermediate representation of each first source code within the same intermediate representation framework; convert each first intermediate representation into first machine instructions suitable for execution on a first hardware unit matching the corresponding first source code; and link at least each first machine instruction based on the second source code to generate the executable file corresponding to the neural network model. During the runtime phase, heterogeneous computing platform 120 executes the executable file corresponding to the neural network model to complete the corresponding computational tasks.

[0035] The above describes the scenario where the electronic device 110 generates an executable file, and the heterogeneous computing platform 120 executes the executable file. In some embodiments, both the generation and execution of the executable file can be achieved on the heterogeneous computing platform 120.

[0036] Exemplary electronic devices Figure 2 This is a schematic diagram of the structure of an electronic device 110 provided in some exemplary embodiments of this disclosure. For example... Figure 2 As shown, the electronic device 110 includes: Processor 210; Memory 220 for storing computer programs; Processor 210 is used to execute computer programs to generate executable files.

[0037] Optionally, the processor 210 is hardware in the electronic device 110, and the processor 210 is configured to perform at least one of the following functions: executing computer programs to generate executable files or instructions, executing instructions, processing data, coordinating and controlling other components, etc. The electronic device 110 includes one or more processors 210. For ease of understanding, the following description uses the case where the electronic device 110 includes one processor 210 as an example.

[0038] Optionally, memory 220 is the circuitry in electronic device 110 that stores instructions and data. Memory 220 includes one or more computer program products, which include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory includes, for example, random access memory (RAM) and / or cache memory. Non-volatile memory includes, for example, read-only memory (ROM), hard disk, flash memory, etc. The computer-readable storage medium can store executable instructions for processor 210, which can read from and execute the executable instructions to generate an executable file.

[0039] In some optional examples, such as Figure 2 As shown, the electronic device 110 also includes an input device 230 and an output device 240, which are interconnected via a bus system and / or other forms of connection mechanisms (not shown). The input device 230 includes, for example, a keyboard, a mouse, etc. The output device 240 includes, for example, a monitor, speakers, a printer, and a communication network and its connected remote output devices, etc., and can output various types of information.

[0040] Of course, for the sake of simplicity, Figure 2 Only some of the components of electronic device 110 relevant to this disclosure are shown, omitting components such as buses and input / output interfaces. In addition, electronic device 110 may include any other suitable components depending on the specific application.

[0041] In embodiments of this disclosure, processor 210 is configured to generate an executable file. For example, it can be executed... Figure 3 The program corresponding to the method flow shown is used to generate an executable file. Figure 3 The process shown includes steps 310, 320, 330 and 340.

[0042] Step 310: Determine multiple first source codes and second source codes corresponding to the neural network model. The second source code represents the dependencies between the multiple first source codes.

[0043] Optionally, the neural network model in step 310 can be any neural network model that needs to be compiled. The neural network model in step 310 can be compiled together with at least one of the following: a preprocessing program for the neural network model and a postprocessing program for the neural network model. The preprocessing program for the neural network model is a program used to preprocess the data to be input into the neural network model. The postprocessing program for the neural network model is a program used to postprocess the data to be output into the neural network model.

[0044] Optionally, all the multiple first source codes are abstract expressions of computational logic, and the computational logic corresponding to any two of the multiple first source codes can be different. For example, the multiple first source codes may consist of two first source codes, where one first source code corresponds to the computational logic of the pre-processing program, and the other first source code corresponds to the computational logic of the neural network model. As another example, the multiple first source codes may consist of two first source codes, where one first source code corresponds to the computational logic of the neural network model, and the other first source code corresponds to the computational logic of the post-processing program. Yet another example is that the multiple first source codes may consist of three first source codes, where one first source code corresponds to the computational logic of the pre-processing program, another first source code corresponds to the computational logic of the neural network model, and the third first source code corresponds to the computational logic of the post-processing program.

[0045] Optionally, the second source code is an abstract expression of the dependencies between multiple first source codes, which may include data dependencies. For example, if the multiple first source codes are two types, where one type corresponds to the computational logic of the preprocessing program and the other corresponds to the computational logic of the neural network model, the second source code can represent that the first source code corresponding to the computational logic of the neural network model depends on the first source code corresponding to the computational logic of the preprocessing program. Similarly, if the multiple first source codes are two types, where one type corresponds to the computational logic of the neural network model and the other corresponds to the computational logic of the postprocessing program, the second source code can represent that the first source code corresponding to the computational logic of the postprocessing program depends on the first source code corresponding to the computational logic of the neural network model.

[0046] It should be noted that the multiple first source codes and second source codes can include the program of the neural network model to be trained. The neural network model program can include a pre-processing program, a corresponding neural network model program, and a post-processing program. Specifically, the multiple first source codes and second source codes can include the program of the neural network model to be trained. That is, during the training phase, based on the multiple first source codes and second source codes, pre-processing, model inference, and post-processing can be performed sequentially, and the model parameters of the neural network model can be optimized on this basis (specific training methods can be found in relevant technologies and will not be elaborated here). Generally speaking, Python is a commonly used programming language for deep learning algorithm developers. For neural network models and their pre / post-processing, training can be implemented based on Python. Here, to better support the training of the neural network model program, the programming environment for the multiple first source codes and second source codes can be a Python environment, or both can be Python-like environments. As an example, the source codes in the embodiments of this disclosure are not limited to Domain-Specific Language (DSL) source codes, Triton source codes, Numba source codes, Python source codes, etc., which can be written in a Python environment or a Python-like environment.

[0047] Understandably, the deep learning field has various DSLs, such as, but not limited to, the embedded DSL provided by the deep learning framework PyTorch, the operator-level DSL defined by the Open Neural Network Exchange (ONNX), and the DSL for Efficient AI Programming (Leap). Triton is a GPU programming paradigm. Python is a high-level, general-purpose, interpreted programming language that supports multiple paradigms. Numba is a Just-In-Time (JIT) compiler that compiles Python functions into machine code; Numba supports a subset of Python's syntax.

[0048] Step 320: Determine the first intermediate representation of each first source code within the same intermediate representation framework.

[0049] For ease of understanding, the "same intermediate representation frame" in step 320 can also be called a preset intermediate representation frame. The preset intermediate representation frame can be a multi-level intermediate representation (MLIR) intermediate representation frame. Of course, the preset intermediate representation frame can also be other types of intermediate representation frames, and this disclosure does not limit it.

[0050] Optionally, for any one of the multiple first source codes, any feasible method can be used to convert the first source code to a preset intermediate representation framework to obtain the corresponding first intermediate representation.

[0051] Step 330: Each first intermediate representation is converted into a first machine instruction suitable for execution on a first hardware unit that matches the corresponding first source code.

[0052] Optionally, for any one of a variety of first source codes, it is possible to obtain from Figure 1 Among the computing units included in the heterogeneous computing platform 120 shown, a computing unit capable of efficiently executing the computing logic corresponding to the first source code is determined, and the determined computing unit can serve as a first hardware unit matching the first source code. Furthermore, for any one of the various first source codes, the corresponding first intermediate representation can be converted into binary machine instructions that can be efficiently executed by the first hardware unit matching the first source code, and the converted binary machine instructions can serve as first machine instructions suitable for execution on the first hardware unit matching the first source code.

[0053] Step 340: Based on the second source code, link at least each of the first machine instructions to generate an executable file corresponding to the neural network model.

[0054] Optionally, based on the second source code, a linker can be used to link at least the first machine instructions to generate an executable file corresponding to the neural network model. It is understood that the linker is a key component of the compilation toolchain, and its main function is to generate a complete executable file by performing symbol resolution, address space allocation, relocation, and merging on multiple independently compiled files. The format of the executable file corresponding to the neural network model can be, for example, Executable and Linkable Format (ELF). The executable file corresponding to the neural network model can be deployed on the heterogeneous computing platform 120.

[0055] In embodiments of this disclosure, electronic device 110 can determine multiple first source codes, each with a first intermediate representation under the same intermediate representation framework, and convert each first intermediate representation into first machine instructions suitable for execution on a first hardware unit matching the corresponding first source code. Based on second source code representing the dependencies between multiple first source codes, the first machine instructions are linked to generate an executable file corresponding to the neural network model. Therefore, in embodiments of this disclosure, when the first source code of the neural network model to be compiled includes multiple types, they can all be converted into intermediate representations under the same intermediate representation framework, the intermediate representations can be converted into machine instructions suitable for execution on the corresponding hardware unit, and the machine instructions can be linked based on the second source code to generate an executable file corresponding to the neural network model that can be deployed on the heterogeneous computing platform 120. Thus, electronic device 110 based on embodiments of this disclosure can further use the source code used in the neural network model training stage for the neural network model deployment stage, thereby achieving the training and deployment of the neural network model and its pre / post-processing based on a single development, thereby reducing the amount of code that needs to be developed and lowering development costs.

[0056] In some optional examples, Figure 3 Based on the illustrated embodiments, as Figure 4 As shown, step 340 includes steps 410, 420 and 430.

[0057] Step 410: Determine the second intermediate representation of the second source code under the intermediate representation frame (i.e., the preset intermediate representation frame mentioned above).

[0058] Optionally, the second source code can be converted to a preset intermediate representation framework in any feasible manner to obtain the second intermediate representation corresponding to the second source code.

[0059] Step 420: The second intermediate representation is converted into second machine instructions suitable for execution on a second hardware unit that matches the second source code.

[0060] Optionally, in addition to the computing units, the heterogeneous computing platform 120 also includes a control unit for directing and coordinating the computing units. The control unit may be, for example, but not limited to, a microcontroller unit (MCU) or a field-programmable gate array (FPGA).

[0061] Optionally, the control unit in the heterogeneous computing platform 120 can be identified as a second hardware unit that matches the second source code, and the second intermediate representation can be converted into binary machine instructions that can be efficiently executed by the second hardware unit that matches the second source code. The converted binary machine instructions can be used as second machine instructions suitable for execution on the second hardware unit that matches the second source code.

[0062] In some embodiments, the heterogeneous computing platform 120 includes a CPU. In this case, the heterogeneous computing platform 120 may not need to have an additional control unit, and the CPU may be used as both a computing unit and a control unit. In this case, the second hardware unit that matches the second source code may be the CPU.

[0063] Step 430: Link the first machine instructions and the second machine instructions to generate the executable file corresponding to the neural network model.

[0064] Optionally, each of the first and second machine instructions can be regarded as an independently compiled file. Using a linker, these independently compiled files can be processed by symbol resolution, address space allocation, relocation, merging, etc., so as to integrate these independently compiled files into a single file, which is the executable file corresponding to the neural network model.

[0065] In the embodiments of this disclosure, similar to the processing methods for multiple first source codes, the second source code can also be efficiently and quickly obtained by sequentially executing intermediate representation determination operations and intermediate representation to machine instruction conversion operations. These second machine instructions can then be linked with each of the first machine instructions, allowing them to be packaged in the executable file corresponding to the neural network model. Since the second source code represents the dependencies between multiple first source codes, and the second machine instructions are generated based on the second source code, while each first machine instruction is generated based on its corresponding first source code, the second machine instructions can represent the dependencies between the first machine instructions. Therefore, when the heterogeneous computing platform 120 executes the executable file corresponding to the neural network model, it can execute each first machine instruction in an orderly manner based on the dependencies between them. This is equivalent to effectively running the program of the neural network model corresponding to the heterogeneous source code, which helps improve computational efficiency.

[0066] In some optional examples, among multiple first and second source codes, the abstraction methods of any two source codes are different. The abstraction method of source code can be understood as: the transformation methods applied (such as generalization, encapsulation, etc.) to control complexity and hide unnecessary details during the process of mapping computational logic to source code. The abstraction method of source code includes, but is not limited to, abstraction level and abstraction dimension. The abstraction level of source code can be understood as: the degree to which underlying hardware details are hidden and the degree to which high-level semantic abstraction is provided when expressing computational logic through source code. Generally speaking, the more significant the degree of hiding underlying hardware details and providing high-level semantic abstraction, the higher the abstraction level of the source code; the less significant the degree of hiding underlying hardware details and providing high-level semantic abstraction, the lower the abstraction level of the source code.

[0067] In an optional example, the multiple first source codes include three types: Domain-Specific Language (DSL) source code, Triton source code, and Numba source code; the second source code is Python source code. In this example, any two of the three first source codes and the second source code have different abstraction methods; for example, the abstraction level of the Python source code is higher than that of the DSL source code. For ease of description, the abstraction method of the Python source code will be referred to as the first abstraction method, the abstraction method of the DSL source code as the second abstraction method, the abstraction method of the Numba source code as the third abstraction method, and the abstraction method of the Triton source code as the fourth abstraction method.

[0068] In some optional examples, the first hardware unit and the second hardware unit are determined in the following manner: Based on the abstraction method of each first source code, and according to the pre-set correspondence between the abstraction method and the hardware unit, the first hardware unit that matches each first source code is determined respectively; Based on the abstraction method of the second source code, and according to the pre-set correspondence between the abstraction method and the hardware unit, the second hardware unit that matches the second source code is determined.

[0069] Optionally, the correspondence between abstraction methods and hardware units can be pre-defined. As an example, in the pre-defined correspondence between abstraction methods and hardware units, the first abstraction method can correspond to the MCU, the second abstraction method can correspond to the TPU, the third abstraction method can correspond to the CPU, and the fourth abstraction method can correspond to the GPU or VPU.

[0070] Optionally, for each of the multiple first source codes, the hardware unit corresponding to the abstraction method of the first source code can be determined according to a pre-defined correspondence between abstraction methods and hardware units. The determined hardware unit can be used as the first hardware unit matching the first source code. Similarly, the hardware unit corresponding to the abstraction method of the second source code can be determined according to a pre-defined correspondence between abstraction methods and hardware units. The determined hardware unit can be used as the second hardware unit matching the second source code. Thus, if the first source code is DSL source code, the first hardware unit matching the first source code can be a TPU; if the first source code is Triton source code, the first hardware unit matching the first source code can be a GPU or VPU; if the first source code is Numba source code, the first hardware unit matching the first source code can be a CPU; if the second source code is Python source code, the second hardware unit matching the second source code can be an MCU.

[0071] In the embodiments of this disclosure, each first source code and second source code can be written according to its respective abstraction method, without necessarily using a unified abstraction method. It is sufficient to ensure that the programming environment is a Python environment or a Python-like environment, resulting in high programming flexibility. Based on the abstraction methods of each first source code and second source code, the hardware units matched to each first source code and second source code can be determined efficiently and reliably through a pre-set correspondence. Furthermore, each source code based on different abstraction methods, after being compiled to generate machine instructions, is linked to generate an executable file corresponding to the neural network model for deployment on the heterogeneous computing platform 120. During the model deployment phase, the neural network model and its pre / post-processing can be deployed on the heterogeneous computing platform 120 based on the executable file generated by this disclosure. This helps to reduce the amount of code that needs to be developed and lower development costs while completing the computing task.

[0072] In some optional examples, for any first source code, step 320 includes: In response to the existence of a first intermediate representation corresponding to the first source code in the cache, the first intermediate representation corresponding to the first source code is read from the cache; In response to the absence of a first intermediate representation corresponding to the first source code in the cache, the first source code is converted into the corresponding first intermediate representation based on the decorator used to identify the abstraction method in the first source code.

[0073] Alternatively, a cache is a space used to temporarily store data. As an example, the cache may store intermediate representations of several source codes, each derived from a different source code.

[0074] In the embodiments of this disclosure, a traversal search can be performed in the cache to determine whether a first intermediate representation corresponding to the first source code exists in the cache. If the first intermediate representation corresponding to the first source code exists in the cache, it can be obtained efficiently and reliably by reading the cache. If the first intermediate representation corresponding to the first source code does not exist in the cache, it can be obtained through a source code to intermediate representation conversion operation. For example, the first source code may have a decorator for identifying the abstraction method; based on the decorator for identifying the abstraction method in the first source code, the first source code can be converted into the corresponding first intermediate representation.

[0075] Generally, a decorator is a special syntactic construct used to add extra functionality or semantics to code without modifying its core logic. In the embodiments of this disclosure, the first source code may have a decorator to identify its abstraction method. For example, in a Python environment, if the first source code is DSL source code, the decorator might be `@leap_func` to identify it as a second abstraction method. As another example, if the first source code is Triton source code, the decorator might be `@hbdk_vfunc` to identify it as a fourth abstraction method. Yet another example, if the first source code is Numba source code, the decorator might be `@hbdk_func` to identify it as a third abstraction method.

[0076] In some optional embodiments of this disclosure, for any first source code, based on the decorator included in the first source code for identifying the abstraction method, the first source code is converted into a corresponding first intermediate representation, including: Determine the parser corresponding to the decorator used to identify the abstraction method in the first source code; The parser corresponding to the decorator is used to parse the first source code to obtain the parsing result; The parsing result is converted into the corresponding first intermediate representation.

[0077] Generally, a parser is a program component used to convert source code into a structured syntax tree representation, laying the foundation for subsequent semantic analysis, optimization, code generation, and other processes. Here, the correspondence between decorators and parsers can be pre-defined. As an example, in the pre-defined correspondence between decorators and parsers, `@leap_func` can correspond to the first parser, `@hbdk_vfunc` to the second parser, and `@hbdk_func` to the third parser. The first, second, and third parsers can all be parsers of any type.

[0078] In this implementation, the parser corresponding to the decorator used to identify abstraction methods in the first source code can be determined efficiently and reliably according to a pre-defined correspondence between decorators and parsers. Using the determined parser, the first source code can be parsed to determine its meaning, thereby generating a corresponding syntax tree, which serves as the parsing result. Referring to compilation techniques in related technologies, the parsing result is converted according to a standard conversion process from syntax tree to intermediate representation to obtain the corresponding intermediate representation, which is the first intermediate representation corresponding to the first source code. Thus, by sequentially executing the parser determination operation, the source code parsing operation, and the syntax tree-to-intermediate representation conversion operation, the conversion from the first source code to the first intermediate representation can be achieved efficiently and reliably.

[0079] Of course, the implementation method of converting the first source code into the corresponding first intermediate representation based on the decorator used to identify the abstraction method in the first source code is not limited to this. For example, a correspondence between decorators and conversion methods can be preset. According to the preset correspondence, the conversion method corresponding to the decorator used to identify the abstraction method in the first source code can be determined, and the first source code can be converted into the corresponding first intermediate representation according to the determined conversion method.

[0080] The above describes the conversion of the first source code into the corresponding first intermediate representation. The second source code may also need to be converted into the corresponding second intermediate representation. If the second source code is Python source code, it can be parsed using Python Abstract Syntax Tree (AST) or Python bytecode, and the parsed result can be further converted into the second intermediate representation.

[0081] In the embodiments of this disclosure, the first intermediate representation corresponding to the first source code can be determined according to whether a first intermediate representation corresponding to the first source code exists in the cache, using a corresponding determination method. For example, the first intermediate representation corresponding to the first source code can be read from the cache first. If the first intermediate representation corresponding to the first source code cannot be read from the cache, the first intermediate representation corresponding to the first source code can be obtained through a source code to intermediate representation conversion operation. In this way, the first intermediate representation corresponding to the first source code can be obtained while minimizing resource consumption and power consumption.

[0082] In some optional examples, processor 210 is also configured to execute for any first source code. Figure 5 The process is shown below. Figure 5 The process shown includes steps 510, 520 and 530.

[0083] Step 510: After converting the first source code into the corresponding first intermediate representation, determine the total number of first intermediate representations already existing in the cache.

[0084] Optionally, after converting the first source code into the corresponding first intermediate representation, a counter can be used to count the number of existing first intermediate representations in the cache, and obtain the total number of existing first intermediate representations in the cache.

[0085] Step 520: Determine the numerical relationship between the total quantity and the preset quantity threshold.

[0086] Optionally, the preset quantity threshold can be a pre-defined maximum number of first intermediate representations allowed to be stored in the cache. Here, the total quantity can be compared with the preset quantity threshold to obtain the size relationship between the total quantity and the preset quantity threshold, and this size relationship can be used as the numerical relationship in step 520.

[0087] Step 530: Update the cache according to the update method adapted to the numerical relationship, so that the updated cache contains the corresponding first intermediate representation converted from the first source code.

[0088] If the total number of numerical relationship representations equals a preset threshold, the update method adapted to the numerical relationships can be an overwrite update method. In this case, the first intermediate representation converted from the first source code can be used to overwrite the earliest first intermediate representation added to the cache, so that the updated cache contains the corresponding first intermediate representation converted from the first source code.

[0089] If the total number of numerical relationship representations is less than a preset threshold, the update method adapted to the numerical relationships can be a non-overwrite update method. In this case, the existing first intermediate representations in the cache can be retained, and the corresponding first intermediate representation converted from the first source code can be stored in the cache as a new first intermediate representation, so that the updated cache contains the corresponding first intermediate representation converted from the first source code.

[0090] In the embodiments of this disclosure, by combining the total number of existing first intermediate representations in the cache with a preset number threshold, the cache can be updated using a corresponding update method. On the one hand, the updated cache can be updated by adding the first source code converted into the corresponding first intermediate representation, so that the first intermediate representation can be obtained efficiently and reliably by reading the updated cache, thereby reducing resource consumption and power consumption. On the other hand, it can prevent the total number of first intermediate representations in the cache from exceeding the limit.

[0091] In some optional examples, such as Figure 6 As shown, step 340 includes steps 610 and 620.

[0092] Step 610: Based on the second source code, determine the execution order of each first machine instruction.

[0093] Optionally, the execution order of each first machine instruction can be determined based on the dependencies represented by the second source code. Assuming the first source code corresponding to the computational logic of the preprocessor is called source code D1, and the first source code corresponding to the computational logic of the neural network model is called source code D2, since source code D2 depends on source code D1, it can be determined that the first machine instructions corresponding to source code D1 are executed before the first machine instructions corresponding to source code D2. Similarly, assuming the first source code corresponding to the computational logic of the postprocessor is called source code D3, since source code D3 depends on source code D2, it can be determined that the first machine instructions corresponding to source code D2 are executed before the first machine instructions corresponding to source code D3. Furthermore, if there are no direct or indirect data dependencies between two first machine instructions, then these two first machine instructions can be executed concurrently.

[0094] Step 620: Based on the execution order, link the first machine instructions to generate the executable file corresponding to the neural network model.

[0095] Optionally, each first machine instruction can be regarded as an independently compiled file. Using the linker, symbol resolution, address space allocation, relocation, merging and other processes can be performed on these independently compiled files to integrate them into the executable file corresponding to the neural network model. In addition, during the integration process, these independently compiled files can be sorted according to the execution order determined in step 610.

[0096] In the embodiments of this disclosure, unlike the processing methods for multiple first source codes, for the second source code, it is not necessary to sequentially execute intermediate representation determination operations and intermediate representation to machine instruction conversion operations to obtain the second machine instructions. Instead, the execution order of each first machine instruction can be determined based on the second source code, and the determined execution order can be used as the linking basis for each first machine instruction. In this way, the executable file corresponding to the neural network model directly limits the execution order of each first machine instruction. Then, when the heterogeneous computing platform 120 executes the executable file corresponding to the neural network model, it can execute each first machine instruction in an orderly manner according to the execution order. This is equivalent to effectively running the program of the neural network model corresponding to the heterogeneous source code, which is beneficial to improving computing efficiency.

[0097] In some optional examples, such as Figure 7 As shown, step 310 includes steps 710, 720 and 730.

[0098] Step 710: Determine the code file corresponding to the neural network model.

[0099] Optionally, the electronic device 110 may have a file system, in which the code file corresponding to the neural network model can be determined. The code file corresponding to the neural network model may include at least part of the source code related to the neural network model's program.

[0100] Step 720: In response to the fact that the code file includes multiple source codes for characterizing computation functions and source codes for characterizing dependencies, the multiple source codes for characterizing computation functions in the code file are identified as multiple first source codes, and the source codes for characterizing dependencies in the code file are identified as second source codes.

[0101] Step 730: In response to the code file including multiple source codes used to characterize computation functions, the multiple source codes used to characterize computation functions in the code file are identified as multiple first source codes; the configuration file corresponding to the neural network model is determined, the configuration file including source codes used to characterize dependencies; the source codes used to characterize dependencies in the configuration file are identified as second source codes.

[0102] In some embodiments, the code file includes multiple source codes for characterizing computation functions and source codes for characterizing dependencies. In such cases, multiple source codes for characterizing computation functions and source codes for characterizing dependencies can be extracted from the code file. The extracted multiple source codes for characterizing computation functions can be used as multiple first source codes, and the extracted source codes for characterizing dependencies can be used as second source codes.

[0103] In other embodiments, the code file includes multiple source codes for representing computation functions, but excludes source codes for representing dependencies. In such cases, the multiple source codes for representing computation functions can be extracted from the code file as multiple first source codes. Additionally, a configuration file corresponding to the neural network model can be determined. The configuration file corresponding to the neural network model can be understood as a file storing program-related configuration information for the neural network model. For example, the configuration file may include source codes for representing dependencies. As another example, the configuration file may include model parameters of the neural network model. From the configuration file corresponding to the neural network model, source codes for representing dependencies can be extracted as second source codes.

[0104] In the embodiments of this disclosure, multiple first source codes and second source codes can be determined according to the composition information of the code file corresponding to the neural network model, using a corresponding determination method. For example, in some cases, multiple first source codes and second source codes can be determined solely based on the code file corresponding to the neural network model. In other cases, multiple first source codes and second source codes can be determined based on both the code file corresponding to the neural network model and the configuration file corresponding to the neural network model. Thus, the obtained multiple first source codes and second source codes can be compiled to generate an executable file corresponding to the neural network model.

[0105] In some optional examples, such as Figure 8 As shown, to generate the executable file corresponding to the neural network model, the following steps can be performed: (1) Determine multiple first source codes and second source codes that represent the dependencies between the multiple first source codes. The multiple first source codes can be represented as DSL source code, Triton source code, and Numba source code, respectively. The second source code can be represented as Python source code.

[0106] (2) Convert the DSL source code, Triton source code, and Numba source code to the MLIR intermediate representation framework to obtain the first intermediate representations corresponding to the DSL source code, Triton source code, and Numba source code, respectively. The first intermediate representation corresponding to the DSL source code can be... Figure 8 The TensorCore dialect in the Triton source code and the first intermediate representation corresponding to the Numba source code can be collectively referred to as... Figure 8 The LLVM dialect.

[0107] (3) Convert the first intermediate representation corresponding to the DSL source code to TensorCore backend. TensorCore backend can be used as the first machine instruction corresponding to the DSL source code. Convert the first intermediate representation corresponding to the Triton source code to LLVM IR (VPU) and VPU backend in sequence. VPU backend can be used as the first machine instruction corresponding to the Triton source code. LLVM IR (VPU) can be understood as an intermediate product of the conversion process from the first intermediate representation corresponding to the Triton source code to the first machine instruction corresponding to the Triton source code. Convert the first intermediate representation corresponding to the Numba source code to LLVM IR (CPU) and CPU backend in sequence. CPU backend can be used as the first machine instruction corresponding to the Numba source code. LLVM IR (CPU) can be understood as an intermediate product of the conversion process from the first intermediate representation corresponding to the Numba source code to the first machine instruction corresponding to the Numba source code.

[0108] (4) Based on the Python source code, determine the execution order of TensorCore backend, VPU backend and CPU backend. Based on the execution order, use the linker to link the three to generate an Object File. The Object File can be used as the executable file corresponding to the neural network model.

[0109] In summary, by employing the embodiments of this disclosure, all first source codes can be converted to the same intermediate representation framework and, after unified compilation and optimization, transformed into first machine instructions adapted to the corresponding first hardware unit. Based on the dependency relationships represented by the second source code, the first machine instructions are linked to generate the executable file corresponding to the neural network model, which can then be deployed on the heterogeneous computing platform 120, including TPUs, GPUs, and CPUs. This effectively integrates source codes with different abstraction methods, enabling the generation of deployment-side code (i.e., the executable file corresponding to the neural network model) based on the source code in a Python or Python-like environment, without secondary development (because there is no need to develop a separate set of code for the deployment of the neural network model and its pre / post-processing on the heterogeneous computing platform 120), further improving the binary performance of the deployment-side code.

[0110] Exemplary method for generating executable files for heterogeneous computing platforms Embodiments of this disclosure also provide a method for generating an executable file for a heterogeneous computing platform. The method for generating an executable file for a heterogeneous computing platform can be applied to the electronic device 110 described above. The method for generating an executable file for a heterogeneous computing platform includes: Determine multiple first source codes and second source codes corresponding to the neural network model, whereby the second source code represents the dependencies between the multiple first source codes; Determine the first intermediate representation of each first source code within the same intermediate representation framework; Each first intermediate representation is converted into a first machine instruction suitable for execution on a first hardware unit that matches the corresponding first source code; Based on the second source code, at least each of the first machine instructions is linked to generate an executable file corresponding to the neural network model.

[0111] In some optional examples, based on the second source code, at least each of the first machine instructions is linked to generate an executable file corresponding to the neural network model, including: Determine the second intermediate representation of the second source code within the intermediate representation framework; The second intermediate representation is converted into second machine instructions suitable for execution on a second hardware unit that matches the second source code; The first and second machine instructions are linked together to generate the executable file corresponding to the neural network model.

[0112] In some optional examples, in multiple first source code and second source code, the abstraction methods of any two source code are different; The first hardware unit and the second hardware unit are determined in the following manner: Based on the abstraction method of each first source code, and according to the pre-set correspondence between the abstraction method and the hardware unit, the first hardware unit that matches each first source code is determined respectively; Based on the abstraction method of the second source code, and according to the pre-set correspondence between the abstraction method and the hardware unit, the second hardware unit that matches the second source code is determined.

[0113] In some optional examples, for any first source code, a first intermediate representation under the same intermediate representation framework is determined, including: In response to the existence of a first intermediate representation corresponding to the first source code in the cache, the first intermediate representation corresponding to the first source code is read from the cache; In response to the absence of a first intermediate representation corresponding to the first source code in the cache, the first source code is converted into the corresponding first intermediate representation based on the decorator used to identify the abstraction method in the first source code.

[0114] In some optional examples, for any first source code, based on the decorator that identifies the abstraction method in the first source code, the first source code is converted into a corresponding first intermediate representation, including: Determine the parser corresponding to the decorator used to identify the abstraction method in the first source code; The parser corresponding to the decorator is used to parse the first source code to obtain the parsing result; The parsing result is converted into the corresponding first intermediate representation.

[0115] In some alternative examples, for any first source code, the methods provided by embodiments of this disclosure further include: After converting the first source code into the corresponding first intermediate representation, determine the total number of first intermediate representations already existing in the cache; Determine the numerical relationship between the total quantity and the preset quantity threshold; Update the cache according to the update method adapted to the numerical relationship, so that the updated cache contains the corresponding first intermediate representation converted from the first source code.

[0116] In some optional examples, based on the second source code, at least each of the first machine instructions is linked to generate an executable file corresponding to the neural network model, including: Based on the second source code, the execution order of each first machine instruction is determined; Based on the execution order, the first machine instructions are linked to generate the executable file corresponding to the neural network model.

[0117] In some optional examples, multiple first and second source codes corresponding to the neural network model are identified, including: Identify the code file corresponding to the neural network model; In response to the fact that the code file includes multiple source codes used to characterize computation functions and source codes used to characterize dependencies, the multiple source codes used to characterize computation functions in the code file are identified as multiple first source codes, and the source codes used to characterize dependencies in the code file are identified as second source codes. In response to the fact that the code file includes multiple source codes used to characterize computation functions, the multiple source codes used to characterize computation functions in the code file are identified as multiple first source codes; the configuration file corresponding to the neural network model is identified, and the configuration file includes source codes used to characterize dependencies; the source codes used to characterize dependencies in the configuration file are identified as second source codes.

[0118] In the methods disclosed herein, the various optional embodiments, optional implementation methods and optional examples disclosed in the exemplary electronic device section above can be flexibly selected and combined as needed to achieve the corresponding functions and effects, and this disclosure does not list them all.

[0119] The beneficial technical effects corresponding to the exemplary embodiments of this method can be found in the corresponding beneficial technical effects of the exemplary electronic device section described above, and will not be repeated here.

[0120] Exemplary device Figure 9 This is a schematic diagram of an apparatus for generating executable files for heterogeneous computing platforms, provided by some exemplary embodiments of this disclosure. The apparatus for generating executable files for heterogeneous computing platforms can be applied to the electronic device 110 described above. For example... Figure 9 As shown, the apparatus for generating executable files for heterogeneous computing platforms includes: The first determining module 910 is used to determine multiple first source codes and second source codes corresponding to the neural network model, wherein the second source code represents the dependency relationship between the multiple first source codes. The second determining module 920 is used to determine the first intermediate representation of each first source code under the same intermediate representation framework; The conversion module 930 is used to convert each first intermediate representation into a first machine instruction suitable for execution on a first hardware unit that matches the corresponding first source code. Linking module 940 is used to link at least each of the first machine instructions based on the second source code to generate an executable file corresponding to the neural network model.

[0121] In some optional examples, such as Figure 10 As shown, link module 940 includes: The first determining submodule 1010 is used to determine the second intermediate representation of the second source code within the intermediate representation framework; The first conversion submodule 1020 is used to convert the second intermediate representation into second machine instructions suitable for execution on a second hardware unit that matches the second source code; The first linking submodule 1030 is used to link the first machine instructions and the second machine instructions to generate an executable file corresponding to the neural network model.

[0122] In some optional examples, in multiple first source code and second source code, the abstraction methods of any two source code are different; The first hardware unit and the second hardware unit are determined in the following manner: Based on the abstraction method of each first source code, and according to the pre-set correspondence between the abstraction method and the hardware unit, the first hardware unit that matches each first source code is determined respectively; Based on the abstraction method of the second source code, and according to the pre-set correspondence between the abstraction method and the hardware unit, the second hardware unit that matches the second source code is determined.

[0123] In some optional examples, for any first source code, such as Figure 11 As shown, the second determining module 920 includes: The read submodule 1110 is used to read the first intermediate representation corresponding to the first source code from the cache in response to the existence of the first intermediate representation corresponding to the first source code in the cache; The second conversion submodule 1120 is used to convert the first source code into the corresponding first intermediate representation based on the decorator for identifying the abstraction method in the first source code in response to the absence of a first intermediate representation in the cache.

[0124] In some optional examples, for any first source code, the transformation submodule 1120 includes: The determining unit is used to determine the parser corresponding to the decorator used to identify the abstraction method in the first source code; The parsing unit is used to parse the first source code using the parser corresponding to the decorator and obtain the parsing result; The conversion unit is used to convert the parsed result into the corresponding first intermediate representation.

[0125] In some optional examples, for any first source code, such as Figure 12 As shown, the apparatus provided in the embodiments of this disclosure further includes: The third determining module 1210 is used to determine the total number of first intermediate representations already existing in the cache after converting the first source code into the corresponding first intermediate representation; The fourth determining module 1220 is used to determine the numerical relationship between the total quantity and the preset quantity threshold; The update module 1230 is used to update the cache according to the update method adapted to the numerical relationship, so that the updated cache contains the corresponding first intermediate representation converted from the first source code.

[0126] In some optional examples, such as Figure 13 As shown, link module 940 includes: The second determining submodule 1310 is used to determine the execution order of each first machine instruction based on the second source code; The second linking submodule 1320 is used to link the first machine instructions based on the execution order to generate an executable file corresponding to the neural network model.

[0127] In some optional examples, such as Figure 14 As shown, the first determining module 910 includes: The third determining submodule 1410 is used to determine the code file corresponding to the neural network model; The fourth determination submodule 1420 is used to determine, in response to the code file including multiple source codes used to characterize computation functions and source codes used to characterize dependencies, multiple source codes used to characterize computation functions in the code file as multiple first source codes and source codes used to characterize dependencies in the code file as second source codes. The fifth determination submodule 1430 is used to determine, in response to the code file including multiple source codes used to characterize computation functions, multiple source codes used to characterize computation functions in the code file as multiple first source codes; determine the configuration file corresponding to the neural network model, the neural network model including source codes used to characterize dependencies; and determine the source codes used to characterize dependencies in the configuration file as second source codes.

[0128] In the apparatus disclosed herein, the various optional embodiments, optional implementation methods and optional examples disclosed in the exemplary electronic device section above can be flexibly selected and combined as needed to achieve the corresponding functions and effects, and this disclosure does not list them all.

[0129] The beneficial technical effects corresponding to the exemplary embodiments of this device can be found in the corresponding beneficial technical effects of the exemplary electronic device section described above, and will not be repeated here.

[0130] Exemplary heterogeneous computing platform Figure 15 This is a schematic diagram of the structure of a heterogeneous computing platform 120 provided in some exemplary embodiments of this disclosure. For example... Figure 15 As shown, the heterogeneous computing platform 120 includes: Control unit 1510 is used to read executable file from memory 1520 and, based on the tensor to be calculated, control calculation unit 1530 to execute executable file to perform calculations on the tensor to be calculated; wherein, the executable file is generated by electronic device 110; The calculation unit 1530 is used to execute the executable file based on the control of the control unit 1510, calculate the tensor to be calculated, and obtain the calculation result.

[0131] The tensor to be computed can be a tensor used in the preprocessing program of the neural network model for computation, or it can be an input tensor to be computed by the neural network model. The types of tensors to be computed include, but are not limited to, images, speech, and video.

[0132] Optionally, the memory 1520 is hardware used to store data, instructions, etc. The memory 1520 can be located inside or outside the heterogeneous computing platform 120.

[0133] Optionally, the number of computing units 1530 can be various, and the type of computing units 1530 can be referred to the relevant introduction above, and will not be repeated here.

[0134] Optionally, the control unit 1510 is hardware used to perform read operations and to coordinate and control the operation of other components. The control unit 1510 can be electrically connected to the memory 1520 and the computing unit 1530 respectively, so that the control unit 1510 can read the required data, instructions, etc. from the memory 1520, and the control unit 1510 can coordinate and control the computing unit 1530.

[0135] In some optional embodiments, the heterogeneous computing platform 120 may be located in the intelligent driving chip of the intelligent driving vehicle, and the program of the neural network model may include a pre-processing program, an environmental perception model corresponding program, and a post-processing program. In this way, environmental images around the vehicle can be acquired by the onboard camera installed in the intelligent driving vehicle, the environmental images can be used as tensors to be calculated, and the executable file can be executed by the computing unit 1530 to perform calculations on the environmental images. This allows for pre-processing, environmental perception, and post-processing of the environmental images in sequence.

[0136] In the embodiments of this disclosure, the heterogeneous computing platform 120 executes an executable file, which can run the computational logic corresponding to the various first source codes in an orderly manner based on the dependencies between them. Thus, through the execution of the neural network model and its pre / post-processing on the heterogeneous computing platform 120, the computational task can be completed correctly and efficiently.

[0137] Exemplary tensor calculation method Figure 16 This is a flowchart illustrating a tensor computation method provided by some exemplary embodiments of this disclosure. The tensor computation method can be applied to a heterogeneous computing platform 120. For example... Figure 16 As shown, the methods for calculating tensors include: Step 1610: Read the executable file from memory; Step 1620: Based on the tensor to be calculated, execute the executable file to perform calculations on the tensor and obtain the calculation results; The executable file is generated using the method described above for generating executable files for heterogeneous computing platforms.

[0138] In the tensor calculation method disclosed herein, the various optional embodiments, optional implementation methods and optional examples disclosed in the above exemplary heterogeneous computing platform section can be flexibly selected and combined as needed to achieve the corresponding functions and effects. This disclosure does not list them all.

[0139] The beneficial technical effects corresponding to the exemplary embodiment of this tensor calculation method can be found in the corresponding beneficial technical effects of the exemplary heterogeneous computing platform section above, and will not be repeated here.

[0140] Exemplary computer program products and computer-readable storage media In addition to the methods and apparatus described above, embodiments of this disclosure may also be computer program products comprising computer program instructions that, when executed by a processor, cause the processor to perform the steps in the methods for generating executable files for heterogeneous computing platforms or tensor computation methods according to various embodiments of this disclosure as described in the "Exemplary Methods" section of this specification.

[0141] Computer program products can be written in any combination of one or more programming languages ​​to perform the operations of embodiments of this disclosure. These programming languages ​​include object-oriented programming languages ​​such as Java and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on a user's computing device, partially on a user's computing device, as a standalone software package, partially on a user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0142] Furthermore, embodiments of this disclosure may also be computer-readable storage media storing computer program instructions that, when executed by a processor, cause the processor to perform the steps in the methods for generating executable files for heterogeneous computing platforms or tensor computation methods according to various embodiments of this disclosure as described in the "Exemplary Methods" section of this specification.

[0143] The computer-readable storage medium may be any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may be, for example, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: an electrical connection having one or more wires, a portable disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof.

[0144] The basic principles of this disclosure have been described above with reference to specific embodiments. However, the advantages, benefits, and effects mentioned in this disclosure are merely examples and not limitations, and should not be considered as essential features of each embodiment of this disclosure. The specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the scope of this disclosure to the necessity of employing the specific details described above.

[0145] Various modifications and variations can be made to this disclosure without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include such modifications and variations.

Claims

1. An electronic device, comprising: processor; The processor is configured to: Determine multiple first source codes and second source codes corresponding to the neural network model, wherein the second source code represents the dependencies between the multiple first source codes; Determine the first intermediate representation of each of the first source codes within the same intermediate representation framework; Each of the first intermediate representations is converted into a first machine instruction suitable for execution on a first hardware unit that matches the corresponding first source code. Based on the second source code, at least each of the first machine instructions is linked to generate an executable file corresponding to the neural network model.

2. The electronic device according to claim 1, wherein, The step of linking at least each of the first machine instructions based on the second source code to generate an executable file corresponding to the neural network model includes: Determine the second intermediate representation of the second source code within the intermediate representation framework; The second intermediate representation is converted into second machine instructions suitable for execution on a second hardware unit that matches the second source code; The first machine instructions and the second machine instructions are linked together to generate an executable file corresponding to the neural network model.

3. The electronic device according to claim 2, wherein, In the multiple first source code and second source code, the abstraction methods of any two source code are different; The first hardware unit and the second hardware unit are determined in the following manner: Based on the abstraction method of each of the first source codes, and according to the pre-set correspondence between the abstraction method and the hardware unit, the first hardware unit that matches each of the first source codes is determined respectively; Based on the abstraction method of the second source code, and according to the pre-set correspondence between the abstraction method and the hardware unit, the second hardware unit that matches the second source code is determined.

4. The electronic device according to claim 3, wherein, For any of the first source codes, determining the first intermediate representation of each of the first source codes within the same intermediate representation framework includes: In response to the existence of the first intermediate representation corresponding to the first source code in the cache, the first intermediate representation corresponding to the first source code is read from the cache; In response to the absence of the first intermediate representation corresponding to the first source code in the cache, the first source code is converted into the corresponding first intermediate representation based on the decorator for identifying the abstraction method in the first source code.

5. The electronic device according to claim 4, wherein, For any of the first source code, the step of converting the first source code into a corresponding first intermediate representation based on the decorator used to identify the abstraction method in the first source code includes: Determine the parser corresponding to the decorator used to identify the abstraction method in the first source code; The first source code is parsed using the parser corresponding to the decorator to obtain the parsing result; The parsing result is converted into the corresponding first intermediate representation.

6. The electronic device according to claim 4, wherein, For any of the first source code, the executable instructions are further configured to implement: After converting the first source code into the corresponding first intermediate representation, determine the total number of the first intermediate representations already existing in the cache; Determine the numerical relationship between the total quantity and the preset quantity threshold; The cache is updated according to an update method adapted to the numerical relationship, so that the updated cache contains the corresponding first intermediate representation converted from the first source code.

7. The electronic device according to claim 1, wherein, The step of linking at least each of the first machine instructions based on the second source code to generate an executable file corresponding to the neural network model includes: Based on the second source code, the execution order of each of the first machine instructions is determined; Based on the execution order, the first machine instructions are linked to generate the executable file corresponding to the neural network model.

8. The electronic device according to any one of claims 1-7, wherein, The determination of multiple first and second source codes corresponding to the neural network model includes: Identify the code file corresponding to the neural network model; In response to the fact that the code file includes multiple source codes for characterizing computation functions and source codes for characterizing dependencies, the multiple source codes for characterizing computation functions in the code file are determined as multiple first source codes, and the source codes for characterizing dependencies in the code file are determined as second source codes; In response to the code file including multiple source codes for representing computation functions, the multiple source codes for representing computation functions in the code file are determined as multiple first source codes; a configuration file corresponding to the neural network model is determined, the configuration file including source codes for representing dependencies; the source codes for representing dependencies in the configuration file are determined as second source codes.

9. A method for generating an executable file for a heterogeneous computing platform, comprising: Determine multiple first source codes and second source codes corresponding to the neural network model, wherein the second source code represents the dependencies between the multiple first source codes; Determine the first intermediate representation of each of the first source codes within the same intermediate representation framework; Each of the first intermediate representations is converted into a first machine instruction suitable for execution on a first hardware unit that matches the corresponding first source code. Based on the second source code, at least each of the first machine instructions is linked to generate an executable file corresponding to the neural network model.

10. The method according to claim 9, wherein, The step of linking at least each of the first machine instructions based on the second source code to generate an executable file corresponding to the neural network model includes: Determine the second intermediate representation of the second source code within the intermediate representation framework; The second intermediate representation is converted into second machine instructions suitable for execution on a second hardware unit that matches the second source code; The first machine instructions and the second machine instructions are linked together to generate an executable file corresponding to the neural network model.

11. The method according to claim 9, wherein, The step of linking at least each of the first machine instructions based on the second source code to generate an executable file corresponding to the neural network model includes: Based on the second source code, the execution order of each of the first machine instructions is determined; Based on the execution order, the first machine instructions are linked to generate the executable file corresponding to the neural network model.

12. A computer-readable storage medium storing a computer program that is executed by a processor to implement the method for generating an executable file for a heterogeneous computing platform as described in any one of claims 9-11.

Images