Chip element region identification method, device, equipment and storage medium

Abstract

The application discloses a chip element region identification method and device, equipment and a storage medium, and relates to the chip preparation field. The method comprises the following steps: obtaining a chip layout and a chip acquisition image of a first chip; identifying first object positions corresponding to at least two boundary objects in the chip layout; mapping the first object positions to the chip acquisition image based on a size mapping relationship between the chip layout and the chip acquisition image, determining second object positions corresponding to the at least two boundary objects in the chip acquisition image; and regarding a region surrounded by the second object positions corresponding to the at least two boundary objects in the chip acquisition image as a chip element region. According to the affine transformation relationship between the chip layout and the chip acquisition image, the positions of the boundary objects in the chip layout are mapped to the chip acquisition image, so that the positions of the boundary objects in the chip acquisition image are determined, and the identification efficiency of the boundary objects is improved.

Description

Technical Field

[0001] This application relates to the field of chip fabrication, and in particular to a method, apparatus, device, and storage medium for identifying chip element regions. Background Technology

[0002] During chip manufacturing, it is often necessary to perform targeted processing on the chip component areas, such as defect detection.

[0003] In related technologies, the first step is to acquire images of the fabricated chip and then delineate the chip component regions from the acquired chip images. Since chip images are high-resolution, resulting in a large amount of image data, a manual selection method is used to determine the distribution areas of chip components from the chip images.

[0004] However, the above method of determining chip component areas is time-consuming and inefficient. Furthermore, the manually selected key areas may contain non-critical parts, such as other chip components, which may affect the subsequent application of the chip component areas. Summary of the Invention

[0005] This application provides a method, apparatus, device, and storage medium for identifying chip component regions. The technical solution is as follows:

[0006] According to one aspect of the embodiments of this application, a method for identifying chip element regions is provided, the method comprising:

[0007] The chip layout and chip acquisition image of the first chip are obtained. The chip layout refers to the arrangement of the chip components in the first chip, and the chip acquisition image is obtained by taking pictures of the first chip.

[0008] Identify the positions of the first objects corresponding to at least two boundary objects in the chip layout, wherein the at least two boundary objects are chip constituent elements of a pre-specified type in the first chip;

[0009] The chip layout is scaled based on the size mapping relationship between the chip layout and the chip acquisition image, and the positions of the second objects corresponding to the at least two boundary objects are mapped in the chip acquisition image based on the positions of the first objects in the scaled chip layout.

[0010] At least two second object positions are determined from the second object positions corresponding to the at least two boundary objects, and the region box is determined using the at least two second object positions as the chip element region.

[0011] According to another aspect of the embodiments of this application, a chip element region identification device is provided, the device comprising:

[0012] The acquisition module is used to acquire the chip layout and chip acquisition image of the first chip. The chip layout refers to the arrangement of the chip components in the first chip, and the chip acquisition image is acquired by taking pictures of the first chip.

[0013] The identification module is used to identify the positions of the first objects corresponding to at least two boundary objects in the chip layout, wherein the at least two boundary objects are chip constituent elements of a pre-specified type in the first chip.

[0014] The mapping module is used to scale the chip layout based on the size mapping relationship between the chip layout and the chip acquisition image, and to map the positions of the second objects corresponding to the at least two boundary objects in the chip acquisition image based on the positions of the first objects in the scaled chip layout.

[0015] The determination module is used to determine at least two second object positions from the second object positions corresponding to the at least two boundary objects respectively, and use the at least two second object positions to determine a region box as the chip element region.

[0016] According to one aspect of the embodiments of this application, a computer device is provided, the computer device including a processor and a memory, the memory storing a computer program, the computer program being loaded and executed by the processor to implement the above-described method.

[0017] According to one aspect of the embodiments of this application, a computer-readable storage medium is provided, wherein a computer program is stored in the storage medium, the computer program being loaded and executed by a processor to implement the above-described method.

[0018] According to one aspect of the embodiments of this application, a computer program product is provided, the computer program product including a computer program stored in a computer-readable storage medium. A processor of a computer device reads the computer program from the computer-readable storage medium, and the processor executes the computer program, causing the computer device to perform the method described above.

[0019] The technical solutions provided in this application embodiment may have the following beneficial effects:

[0020] Boundary objects in the chip acquisition image are identified, and chip element regions are delineated based on the identified boundary objects. Specifically, when identifying boundary objects, the chip layout of the first chip during the design process is obtained, and the boundary objects in the chip layout are identified to obtain the position of the boundary objects in the chip layout. Then, based on the affine transformation relationship between the chip layout and the chip acquisition image, the position of the boundary objects in the chip layout is mapped to the chip acquisition image, thereby determining the position of the boundary objects in the chip acquisition image. This improves the efficiency of boundary object identification and thus improves the efficiency of chip element region delineation. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of a superconducting quantum chip provided in one embodiment of this application;

[0022] Figure 2 This is a schematic diagram illustrating the identification process of a chip element region according to an illustrative embodiment of this application;

[0023] Figure 3 This is a schematic diagram of a chip element region identification system provided in one embodiment of this application;

[0024] Figure 4 This is a flowchart of a chip element region identification method provided in an exemplary embodiment of this application;

[0025] Figure 5 This is a schematic diagram of the structure of a boundary object provided in an exemplary embodiment of this application;

[0026] Figure 6 This is a flowchart of a chip element region identification method provided in another exemplary embodiment of this application;

[0027] Figure 7 Based on Figure 6 A schematic diagram of some elements of a chip layout provided in the illustrated embodiment;

[0028] Figure 8 This is a schematic diagram illustrating the configuration process of configuring the first line translation data according to an exemplary embodiment of this application;

[0029] Figure 9 Based on Figure 6 The illustrated embodiment provides a schematic diagram of the PAD and CPW structures after etching;

[0030] Figure 10 Based on Figure 6 A schematic diagram of vertex Boolean operations provided in the illustrated embodiment;

[0031] Figure 11 This is a flowchart of a chip element region identification method provided in another exemplary embodiment of this application;

[0032] Figure 12 Based on Figure 11 The illustrated embodiment provides a schematic diagram of the Boolean subtraction algorithm;

[0033] Figure 13 This is a schematic diagram illustrating the overall process of identifying boundary objects from a chip layout, provided in an exemplary embodiment of this application.

[0034] Figure 14 This is a flowchart of a chip element region identification method provided in another exemplary embodiment of this application;

[0035] Figure 15 Based on Figure 14 The illustrated embodiment provides a schematic diagram of the capture frame mapped to the chip-acquired image;

[0036] Figure 16 Based on Figure 14 A schematic diagram of the mapping frame provided in the illustrated embodiment;

[0037] Figure 17 Based on Figure 14 A schematic diagram of the image content within the mapping frame provided in the illustrated embodiment;

[0038] Figure 18 Based on Figure 14 The illustrated embodiment provides a schematic diagram of the template correction process;

[0039] Figure 19 Based on Figure 14 The illustrated embodiment provides a schematic diagram of a connected unit tree;

[0040] Figure 20 Based on Figure 14 A schematic diagram of the corrected mapping frame provided in the illustrated embodiment;

[0041] Figure 21 Based on Figure 14 The illustrated embodiment provides a schematic diagram of scalar image erosion results;

[0042] Figure 22 This is a flowchart of a chip element region identification method provided in another exemplary embodiment of this application;

[0043] Figure 23 This is a structural block diagram of a chip element region identification device provided in an exemplary embodiment of this application;

[0044] Figure 24 This is a structural block diagram of a chip element region identification device provided in another exemplary embodiment of this application;

[0045] Figure 25This is a structural block diagram of a computer device provided in an exemplary embodiment of this application. Detailed Implementation

[0046] Before introducing the technical solutions of this application, some terms involved in this application will be explained. The following related explanations are optional solutions and can be arbitrarily combined with the technical solutions of the embodiments of this application, all of which fall within the protection scope of the embodiments of this application. The embodiments of this application include at least some of the following contents.

[0047] Chip layout, also known as circuit layout, is a design diagram describing the arrangement and interconnections of chip components in a chip circuit. It is a planar geometric description of the physical state of the chip circuit. The chip layout design must comply with constraints such as chip fabrication process, timing, area, and power consumption. The chip layout design file contains the shape, area, and location information of each chip component on the chip. Illustratively, the chip layout design file defines in detail the physical layout of various chip components on the chip, including transistors, resistors, capacitors, and other components, as well as interconnects, metal layers, vias, and metal contacts. In some embodiments, the chip design process typically includes the following stages: 1. Front-end design: Involves the circuit design and verification of the chip, using a hardware description language to create the logic design of the circuit; 2. Synthesis design: Converts the logic design into a gate-level netlist, that is, converts the logic design into a text format describing the digital circuit, representing the logic structure of the circuit. The gate-level netlist details all logic gates in the chip circuit and their interconnections; 3. Back-end design: Involves physical design and layout. This stage includes Place and Route, used to generate the physical layout; 4. Verification stage: ensuring the layout conforms to the Design Rule Check (DRC), which typically checks width, spacing, area, etc.; and Layout-Versus-Schematic (LVS), which compares the netlist of the original circuit diagram with the netlist of the circuit diagram extracted from the layout to ensure consistency between the two.

[0048] Chip layout design files typically use standardized formats such as GDSII (Graphic Design System II) or OASIS (Open Artwork System Interchange Standard), which are industry standards used in chip manufacturing. They are used by chip manufacturers to generate photomasks to fabricate actual chips on wafers.

[0049] Component: In the field of circuit design, a component refers to an independent unit that constitutes a circuit system. For example, in integrated circuits, components include transistors, resistors, and capacitors. In superconducting quantum chips, components include resonant cavities, cross-shaped large capacitors, test junctions, and superconducting quantum bits.

[0050] Metal contacts (PADs): Also known as solder pads, these are the metal contact points used for electrical signal input and output on a chip. PADs are typically located at the edge of the chip and are used to connect external and internal circuits. (Illustrative example) Figure 1 This is a schematic diagram of a superconducting quantum chip provided in an exemplary embodiment of this application, as shown below. Figure 1 As shown, the superconducting quantum chip 100 includes multiple PADs 110, which are distributed in the edge region of the superconducting quantum chip 100 and are used to connect external circuits and internal circuits 120 of the superconducting quantum chip.

[0051] Chip constituent elements refer to various elements designed and fabricated on a chip, including the aforementioned components, metal contacts, and other elements. Other elements include interconnects for transmitting electrical signals, vias for connecting different chip layers, heat dissipation structures for chip thermal management, and identifiers for marking chip models, etc. This application embodiment does not limit these specific elements. The method provided in this application embodiment is used to identify a specified type of chip constituent element from the various chip constituent elements on a chip, such as identifying a metal contact point (PAD) from the various chip constituent elements on a chip. In this application embodiment, chip constituent elements are expressed as a broad concept encompassing components; that is, any element on a first chip used to construct or form the first chip can be called a chip constituent element. Chip constituent elements include components and non-component elements. Components include large cross-shaped capacitors, test junctions, etc., while non-component elements include vias, heat dissipation structures, PADs, etc. Optionally, chip components include logic gates, flip-flops, registers, adders, etc. on the circuit diagram. They generally refer to the devices that constitute the circuit part on the chip and realize the circuit operation function. In addition to chip components, chip components also include through holes, heat dissipation structures, solder pads, etc. that do not participate in the circuit operation function.

[0052] The chip component region identification method provided in this application can be used in defect detection scenarios. Defect detection refers to the use of detection technologies and tools during chip fabrication to identify components and defect types that may be defective within the chip, thereby ensuring the fabrication quality and performance of the chip and avoiding errors or ineffective chip operation due to defects. In some embodiments, planar defects are classified into short-circuit defects, open-circuit defects, and distortion defects based on the changes in the chip's electrical characteristics caused by the defects. The causes of defects include impurity particles, uneven photoresist spin coating, excessive or insufficient electron beam exposure, and uneven image development.

[0053] In chip fabrication, defect detection is a crucial step in ensuring chip quality and performance. Typically, during chip fabrication, chip images are acquired to inspect components within these images, determining whether the fabrication process or result meets requirements. However, chip images may contain irrelevant chip components such as internal die components, the imaging substrate, and calibration structures. Therefore, prior to inspection, it's necessary to extract and automatically calibrate chip component areas from the captured image based on the chip layout to eliminate the influence of these irrelevant elements and ensure the accuracy of subsequent component extraction and defect detection. Related technologies use manual selection of the four vertices of the chip component area for extraction and automatic calibration. However, this method requires high accuracy in manually selecting vertices and hinders the realization of a fully automated process, reducing defect detection efficiency.

[0054] To address this issue, this application proposes an automatic identification method for chip element regions. When identifying chip element regions where elements are distributed within the chip, the method first identifies boundary objects within the chip. These boundary objects refer to chip constituent elements of a specified type within the chip. Optionally, boundary objects refer to chip constituent elements distributed around the chip element regions. Illustratively, when the chip is implemented as a superconducting quantum chip, the boundary objects refer to the PADs within the superconducting quantum chip.

[0055] By acquiring the chip layout of the first chip during the design process and identifying boundary objects within the chip layout, the positions of these boundary objects are determined. Based on the dimensional mapping relationship between the chip layout and the acquired chip image, the positions of the boundary objects in the chip layout are mapped onto the acquired chip image, thus determining their positions within the acquired image. This improves the efficiency of boundary object identification, thereby increasing the efficiency of chip component area segmentation and downstream application efficiency. Based on the topological features of the image, chip component areas can be automatically identified and calibrated, enabling automatic defect detection and improving production efficiency and inspection accuracy.

[0056] The solution provided in this application includes at least the following features:

[0057] 1. Automatically identify PADs in the chip layout based on the topological characteristics of components;

[0058] 2. Based on the PADs in the chip layout, automatically match and obtain the PADs in the chip acquisition image;

[0059] 3. Using the PADs in the chip layout and the PADs in the chip acquisition image, extract the rotation angle and scaling ratio between the chip layout and the chip acquisition image, perform affine transformation, and realize the extraction and automatic calibration of chip component areas in the chip acquisition image.

[0060] Affine transformations are geometric transformations in linear algebra that preserve the "affine properties" between points, lines, and planes in two- or three-dimensional space. These properties include collinearity (points on a line remain on the line) and parallelism (parallel lines remain parallel). Affine transformations can be composed of linear transformations (such as rotation, scaling, and shearing) followed by translation, but do not include nonlinear transformations such as reflection or projection.

[0061] In some embodiments, the boundary object provided in this application may also be a component in the first chip, such as a cross-shaped large capacitor. By identifying at least two cross-shaped large capacitors in the chip's acquired image, the smallest bounding rectangle surrounding the at least two cross-shaped large capacitors is taken as the chip component region.

[0062] Indicative:

[0063] 1. Based on the topological features of components, automatically identify large cross-shaped capacitors in the chip layout. For example, a large cross-shaped capacitor is shaped like a cross with a rectangular outer frame. The upper left, lower left, upper right, and lower right corners of the outer frame are blank areas. Then, based on the area ratio between the blank areas and the non-blank areas, identify the large cross-shaped capacitors in the chip layout.

[0064] 2. Map the large cross-shaped capacitors identified in the chip layout onto the chip acquisition image, and automatically match the large cross-shaped capacitors in the chip acquisition image;

[0065] 3. Define the bounding box containing the large cross-shaped capacitor in the chip acquisition image as the chip element area of ​​the first chip, and perform downstream applications on the chip element area, such as defect detection.

[0066] In this embodiment, the boundary object can also be implemented as other chip components, such as vias for connecting different chip layers or heat dissipation structures for chip thermal management. In this embodiment, a PAD is used as an example to illustrate the boundary object implementation.

[0067] The chips involved in the embodiments of this application may include quantum chips, superconducting quantum chips, or any other type of chip. The embodiments of this application do not limit the chip type. In the embodiments, the first chip is used as an example for illustration.

[0068] Indicative, Figure 2 This is a schematic diagram illustrating the identification process of a chip element region according to an illustrative embodiment of this application, such as... Figure 2 As shown, the process includes at least the following stages.

[0069] Step 210: Input the chip layout and chip acquisition image.

[0070] In this context, "chip layout" refers to the arrangement of the chip's constituent elements within the first chip. The chip layout is the design document for the first chip; it is the circuit layout of the first chip, a design drawing describing the placement and connection relationships of the components within the first chip, and a planar geometric description of the physical circuitry of the first chip.

[0071] The first chip is fabricated using a chip layout as a guide, following the constraints of the fabrication process and component arrangement indicated by the chip layout.

[0072] Chip acquisition images are images captured by photographing the fabricated first chip. In some embodiments, chip acquisition images are images captured by photographing the first chip using a digital microscope. Schematic, the first chip is photographed using a Smartzoom intelligent digital microscope to obtain chip acquisition images of the first chip.

[0073] Step 220: PAD automatically recognized.

[0074] Identifying PADs in a chip layout, in some embodiments, is based on the topological features of PADs in the chip layout.

[0075] Figure 5 This is a schematic diagram of a PAD structure provided in an exemplary embodiment of this application, as shown below. Figure 5 Taking the PAD structure shown as an example, the structure of the PAD is an enclosed structure, which contains a pentagonal conductor region 510 inside, and an insulating region 520 surrounds the conductor region.

[0076] Based on the topological features of the PAD structure, PADs in the chip layout are identified, and the first object position of the PAD in the chip layout is determined.

[0077] Step 230, PAD image capture.

[0078] This refers to mapping the first object position of a PAD in the chip layout to the chip acquisition image based on the size mapping relationship between the chip layout and the chip acquisition image, thereby obtaining the second object position of the PAD in the chip acquisition image.

[0079] In some embodiments, the bounding boxes of the PADs identified in the chip layout are first obtained. These bounding boxes are used to encompass a single PAD. Optionally, the bounding box is implemented as the minimum bounding rectangle of a single PAD in the chip layout. Based on the size mapping relationship between the chip layout and the chip acquisition image, the bounding boxes of at least two PADs are mapped onto the chip acquisition image, resulting in mapped boxes of at least two PADs on the chip acquisition image. There is a one-to-one correspondence between the bounding boxes of the at least two PADs and the mapped boxes of the at least two PADs.

[0080] The image content in the mapping box on the chip-acquired image is identified, and the mapping box is corrected according to the PAD structure and the image content in the mapping box, thereby obtaining the second object position of the PAD in the chip-acquired image.

[0081] Step 240: Geometric center calculation and cluster analysis.

[0082] In some embodiments, the first object location indicates the geometric center of a first region in which the PAD is located in the chip layout, and the second object location indicates the geometric center of a second region in which the PAD is located in the chip-acquired image.

[0083] Because image acquisition by the chip may involve image distortion, jitter, etc., the image acquired after PAD image overlay may not necessarily reflect its original shape and original relative coordinates.

[0084] In this embodiment, cluster analysis is performed based on the difference between the distribution characteristics of the PAD on the chip layout and the distribution characteristics of the PAD on the chip acquisition image, thereby obtaining the affine transformation information between the chip layout and the chip acquisition image.

[0085] Step 250: Output the registered image.

[0086] Based on the aforementioned affine transformation information, the calibration chip acquires the position of the PAD in the image and outputs the registered image.

[0087] Based on the position of the PADs on the above-mentioned registration image, the area surrounded by the PADs on the chip acquisition image can be determined as the chip element area.

[0088] Figure 3 A schematic diagram of a chip component region identification system according to an embodiment of this application is shown. This identification system can implement a system architecture for a chip component region identification method. The identification system may include a terminal 300 and an image acquisition device 320.

[0089] Terminal 300 can be an electronic device such as a mobile phone, tablet computer, vehicle terminal (vehicle system), wearable device, or PC (Personal Computer). A client application for the target application can be installed and run on terminal 300. This target application can be a chip design application or other applications that provide chip defect detection functions; this application does not limit the specific application. Furthermore, this application does not limit the form of the target application, including but not limited to apps, mini-programs, etc., installed on terminal 300, and can also be in web page form.

[0090] The image acquisition device 320 can be a Smartzoom digital microscope or other types of microscopes. A wired connection can be established between the image acquisition device 320 and the terminal 300, or a connection can be established via a communication network; this application does not limit this. After the image acquisition device 320 acquires an image from the chip, it sends the chip-acquired image to the terminal.

[0091] The chip element region identification method provided in this application embodiment can be executed by a computer device, which refers to an electronic device with data computing, processing, and storage capabilities. Figure 3 Taking the identification system shown as an example, the identification method of the chip component area can be executed by the terminal 300 (such as the identification method of the chip component area executed by the client of the target application installed and running in the terminal 300), or by the server 340, or by the terminal 300 and the server 340 interacting and cooperating to execute it. This application does not limit this.

[0092] Schematic illustration: When the terminal 300 executes the chip component region identification method, the terminal 300 obtains the chip layout of the first chip, such as by obtaining a chip layout of the first chip already stored locally, or by obtaining the chip layout of the first chip from the server 340. Additionally, the terminal 300 obtains a chip acquisition image of the first chip from the image acquisition device 320. In the client of the target application, based on the chip layout of the first chip and the chip acquisition image of the first chip, the PAD in the chip acquisition image is identified.

[0093] When the server 340 executes the chip component region identification method, the server 340 obtains the chip layout of the first chip, such as: the server 340 obtains a stored chip layout of the first chip, or the server 340 receives the chip layout of the first chip uploaded by the terminal 300 or other terminals. Additionally, the server 340 obtains the chip acquisition image of the first chip acquired by the image acquisition device 320, such as: the server 340 directly receives the chip acquisition image uploaded by the image acquisition device 320, or the image acquisition device 320 acquires the chip acquisition image of the first chip and sends it to the terminal 300, and the server 340 receives the chip acquisition image uploaded by the terminal 300.

[0094] When the terminal 300 and server 340 interact and cooperate to execute the chip component region identification method, illustratively, the terminal 300 performs the above-mentioned PAD automatic identification stage and uploads the identification result to the server 340. The server 340 then performs the above-mentioned PAD image overlay stage based on the identification result. Alternatively, the terminal 300 and server 340 can interact and cooperate to execute the chip component region identification method in any form, and this application embodiment does not limit this.

[0095] It is worth noting that the aforementioned servers can be independent physical servers, server clusters or distributed systems composed of multiple physical servers, or cloud servers that provide basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, content delivery networks (CDN), and big data and artificial intelligence platforms.

[0096] Furthermore, the aforementioned server can also be implemented as a node in a blockchain system. The technical solution of this application can be combined with blockchain technology. For example, some data involved in the chip component area identification method disclosed in this application can be stored on a blockchain. The terminal 300 and the server 340 can communicate via a network, such as a wired or wireless network.

[0097] Based on the above explanation, Figure 4This is a flowchart illustrating a chip element region identification method provided in an exemplary embodiment of this application. The method is executed by a computer device, and can be executed by a terminal, a server, or a combination of both. Figure 4 As shown, the method includes at least the following steps.

[0098] Step 420: Obtain the chip layout and chip acquisition image of the first chip.

[0099] Chip layout refers to the arrangement of the chip's constituent elements within the first chip. Chip constituent elements include the elements that make up the first chip.

[0100] A chip layout is the circuit layout of a first chip. It is a design drawing that describes the layout and connection relationships of the chip components in the first chip. It is a planar geometric description of the physical circuit of the first chip.

[0101] The first chip is fabricated using a chip layout as a guide, following the constraints of the fabrication process and component arrangement indicated by the chip layout.

[0102] In some embodiments, the chip layout of the first chip is obtained in at least one of the following ways: 1. The chip layout of the first chip is a layout file designed in the current device; therefore, the chip layout stored locally in the current device is directly obtained. For example, an application for designing chips is installed in the current device. After designing the first chip in the application, the chip layout of the first chip is exported and obtained. 2. The chip layout of the first chip is a layout file downloaded by the current device from a server. The server stores chip layouts corresponding to various different chips. When defect detection of the first chip is required, the current device downloads the chip layout of the first chip from the server. 3. The chip layout of the first chip is a layout file designed in another device. The current device receives the chip layout of the first chip sent by the other device. The above methods for obtaining the chip layout of the first chip are merely illustrative examples, and the embodiments of this application do not limit this.

[0103] The chip acquisition image is obtained by photographing the first chip. Specifically, the chip acquisition image is an image captured by photographing the fabricated first chip, that is, an image captured by photographing the first chip in its physical form. In some embodiments, the chip acquisition image is an image captured by photographing the first chip using a digital microscope; schematically, a Smartzoom intelligent digital microscope is used to photograph the first chip to obtain the chip acquisition image.

[0104] In some embodiments, after the image acquisition device completes image acquisition of the first chip, it directly transmits the acquired chip image to the current device; or, after the image acquisition device completes image acquisition of the first chip, it uploads the chip image of the first chip to the server, and the current device downloads the chip image of the first chip from the server.

[0105] In some embodiments, the chip acquisition images include fabrication process images acquired during the fabrication of the first chip; or, the chip acquisition images include fabrication result images acquired after the fabrication of the first chip is completed.

[0106] When the chip acquisition image includes the fabrication process image acquired during the fabrication of the first chip, defect detection is performed on the chip element area in the fabrication process image. Defects existing in the chip element area are detected in time during the fabrication process, avoiding the continued fabrication of chips with defective semi-finished products, which would lead to the ineffective consumption of chip fabrication resources. Furthermore, defects generated during the chip fabrication process can be detected in time, thereby generating corresponding defect avoidance schemes. These defect avoidance schemes can be applied to subsequent chip fabrication processes and to the fabrication processes of other chips, reducing the probability of defect generation and improving chip fabrication efficiency and accuracy.

[0107] When the chip acquisition image includes the preparation result image acquired after the first chip is prepared, defect detection is performed on the chip element area in the preparation result image. After preparation, it is detected whether there are preparation defects in the first chip. This avoids the occurrence of calculation errors caused by using the first chip with defects in the computer device's operation process, thereby improving the reliability of the first chip.

[0108] In some embodiments, the first chip includes at least one of the following: a quantum chip, a digital chip, an analog chip, and a memory chip. In this application embodiment, the first chip is described as including a quantum chip. Specifically, when the first chip is a quantum chip, it can be implemented as at least one of a superconducting quantum chip, an ion trap chip, a semiconductor quantum dot chip, a topological quantum chip, and a photonic quantum chip.

[0109] The superconducting quantum chip serves as the central processing unit (CPU) of a superconducting quantum computer. A quantum computer is a machine that performs calculations using the principles of quantum mechanics. Based on the superposition principle and quantum entanglement in quantum mechanics, quantum computers possess strong parallel processing capabilities. Superconducting quantum chips utilize superconducting circuits to realize qubits; commonly used structures include Josephson junctions.

[0110] Ion trap chips use electromagnetic fields to capture and manipulate charged ions, and the internal energy levels of charged ions can be used as qubits.

[0111] Semiconductor quantum dot chips utilize quantum dots in semiconductor materials to realize qubits, which are typically achieved by controlling electrons or holes.

[0112] Topological quantum chips are based on the theory of topological quantum computing and use quasi-particles (such as anyons) to realize qubits.

[0113] Photonic quantum chips use photons (light particles) as qubits and manipulate and measure the quantum state of photons through optical elements.

[0114] In this embodiment, the first chip is implemented as a superconducting quantum chip as an example for illustration.

[0115] Step 440: Identify the positions of the first objects corresponding to at least two boundary objects in the chip layout.

[0116] Identify at least two boundary objects in the chip layout and determine the location of the first object corresponding to each of the at least two boundary objects.

[0117] Boundary objects are pre-specified chip components in the first chip, and at least two boundary objects are pre-specified chip components in the first chip. Optionally, boundary objects are metal contacts or interconnects in the first chip. In this embodiment, a metal contact in the first chip is used as an example for illustration.

[0118] In some embodiments, boundary objects are chip constituent elements distributed around the chip element region in the first chip. Optionally, multiple boundary objects are distributed around the chip element region in a surrounding manner, and the shape of the surrounding enclosure formed by at least two boundary objects matches the shape of the chip element region. Schematic, if the chip element region where the elements are distributed in the first chip is rectangular, then the surrounding enclosure formed by at least two boundary objects is rectangular and distributed around the chip element region.

[0119] In some embodiments, at least two boundary objects are distributed at the edge of the first chip, wherein the first chip includes an outer edge of the chip, and the at least two boundary objects are distributed on the first chip in a manner adjacent to the outer edge of the chip. Schematic, the distance between the at least two boundary objects and the outer edge of the chip is within a first distance threshold range.

[0120] In this embodiment, the first chip is implemented as a superconducting quantum chip, and the boundary object is implemented as a PAD on the superconducting quantum chip.

[0121] by Figure 1 Taking the superconducting quantum chip 100 shown as an example, the superconducting quantum chip 100 includes multiple PADs 110 as boundary objects, and the multiple PADs 110 are distributed in the edge region of the superconducting quantum chip 100.

[0122] It is worth noting that when the first chip is implemented as another type of chip, the boundary object can also be a chip component element distributed on the periphery of the chip element area on another type of chip, and the embodiments of this application do not limit this.

[0123] Identify boundary objects in the chip layout to determine the location of a first object on the chip layout where the boundary objects are laid out. In some embodiments, boundary objects are identified from the chip layout based on their geometric features.

[0124] In some embodiments, identifying boundary objects in a chip layout includes at least one of the following methods:

[0125] 1. Identify multiple chip components on the chip layout, obtain geometric information data of the chip components, and determine boundary objects from the multiple chip components based on the geometric information data. The geometric information data can be area data, geometric center data, etc., and this application embodiment does not limit this. Optionally, first obtain the geometric feature data of the boundary object. The geometric feature data is pre-set data used to constrain the geometric features of the boundary object. Illustratively, the geometric feature data includes the pre-obtained area data of the boundary object, used to express the area range corresponding to the boundary object, such as: the area data of the boundary object is 0.2 to 0.3 mm. 2 In other words, the area of ​​the boundary object is constrained to 0.2 mm. 2 up to 0.3mm 2 Within this range, if the area of ​​the chip's constituent elements is 0.25 mm², then... 2 If so, the chip's constituent elements are identified as boundary objects. It's worth noting that when identifying boundary objects, various geometric feature data are referenced, such as combining area data and geometric center data to determine whether a chip's constituent element belongs to a boundary object.

[0126] In some embodiments, the boundary object is implemented as an enclosing structure, divided into an inner conductor region and an outer insulating region. When identifying the boundary object, the convex hull enclosing region corresponding to the chip component in the chip layout is extracted. The intersection and non-intersection regions between the chip component and the convex hull enclosing region are determined. The intersection region can be understood as the outer insulating region of the chip component, and the non-intersection region can be understood as the inner conductor region of the chip component; alternatively, the intersection region can be understood as the inner conductor region of the chip component, and the non-intersection region as the outer insulating region of the chip component. If the geometric relationship between the non-intersection and intersection regions meets preset requirements, the chip component is determined as the boundary object in the chip layout, and the first object position of the boundary object in the chip layout is determined.

[0127] This is an illustrative example, using a boundary object implemented as a PAD. Figure 5 This is a schematic diagram of the structure of a boundary object provided in an exemplary embodiment of this application. For example... Figure 5 As shown, PAD500 includes an inner conductor region 510 and an outer insulating region 520. When identifying boundary objects, the convex hull surrounding regions of the chip components are extracted, and the intersection and non-intersection regions between the chip components and the convex hull surrounding regions are determined. Taking PAD500 as an example, the convex hull surrounding region 530 of the PAD is extracted. Using the outer insulating region 520 as the identification subject, the intersection region is the region corresponding to the outer insulating region 520, and the non-intersection region is the region corresponding to the inner conductor region 510. Based on the area ratio or geometric center relationship between the outer insulating region 520 and the inner conductor region 510, it is determined whether the chip component belongs to the boundary object. The area ratio or geometric center relationship between the outer insulating region 520 and the inner conductor region 510 needs to conform to the area ratio or geometric center characteristics exhibited by PAD500.

[0128] Optionally, a first geometric center of the non-intersecting region and a second geometric center of the intersecting region are obtained; if the positional difference between the first geometric center and the second geometric center meets the difference requirements, the chip constituent element is determined as a boundary object in the chip layout; or, a first geometric area of ​​the non-intersecting region and a second geometric area of ​​the intersecting region are obtained; if the ratio of the first geometric area to the second geometric area is within a preset ratio range, the chip constituent element is determined as a boundary object in the chip layout.

[0129] Boundary objects can be identified from the chip layout by acquiring geometric information data. Since the chip components in the chip layout are composed of lines built from pixels, the geometric information data of the chip components can be directly obtained by using the coordinates of the pixels on the chip layout, which improves the efficiency of identifying boundary objects and avoids introducing additional calculation processes.

[0130] 2. Using a pre-trained object recognition model, analyze each chip component in the chip layout and identify boundary objects from these components. The object recognition model is a pre-trained machine learning model. In some embodiments, given a sample chip layout labeled with boundary object tags, the machine learning model identifies the boundary objects in the sample chip layout, obtaining object recognition results. Based on the difference between the object recognition results and the boundary object tags, the machine learning model is trained to obtain the object recognition model. The boundary object tags can be boundary object regions defined on the chip layout or additionally acquired coordinate data used to label the position coordinates of the boundary objects on the chip layout.

[0131] By using a pre-trained object recognition model to identify each chip component in the chip layout, boundary objects can be determined. Since the object recognition model has stronger data processing and analysis capabilities, it can analyze chip components from dimensions such as shape and structure, thereby determining chip components belonging to boundary objects and improving the accuracy of chip component recognition.

[0132] It is worth noting that the above-described method for identifying boundary objects is merely an illustrative example. This method can also be applied in combination, such as first using a pre-trained object recognition model to identify candidate boundary objects in each chip component, and then determining the boundary object from the candidate boundary objects using geometric information data. This application does not limit this approach.

[0133] In some embodiments, the first object location can be understood as the concept of a location point or the concept of an image region. When the first object location is understood as the concept of a location point, the first object location can be the location of the geometric center of the boundary object in the chip layout or the location of a specified object portion of the boundary object in the chip layout. When the first object location is understood as the concept of an image region, the first object location can be the minimum bounding box of the boundary object in the chip layout.

[0134] In some embodiments, the position of the first object is expressed by constructing a coordinate system in units of pixels. In some embodiments, the coordinate system is constructed with the lower left corner vertex of the chip layout as the origin, the long side as the positive x-axis, and the wide side as the positive y-axis. The position of the pixel in the boundary object chip layout is determined, and the coordinates of the pixel in the coordinate system are used as the position of the first object.

[0135] Step 460: Scaling the chip layout based on the size mapping relationship between the chip layout and the chip acquisition image, and mapping the positions of at least two boundary objects in the chip acquisition image based on the positions of the first objects in the scaled chip layout.

[0136] There is a one-to-one correspondence between at least two first object positions and at least two second object positions.

[0137] The first chip is a chip fabricated under the guidance of a chip layout. The chip layout design file uses a standardized format, which serves as the industry standard for chip manufacturing. Chip manufacturers use the standardized chip layout to generate photomasks in order to manufacture the actual chip on the wafer.

[0138] In other words, the fabrication of the first chip is based on the design results of the chip layout, specifically fabricating the physical chip according to the design concept of the chip layout. Therefore, there is a matching relationship between the chip layout of the first chip and the chip acquisition image of the first chip. This matching relationship includes the chip components in the chip layout being fabricated in physical form on the first chip, so that the acquired chip image includes image regions corresponding to the chip components, and the chip structure, component connection methods, and other features shown in the chip layout match the chip structure, component connection methods, and other features shown in the chip acquisition image.

[0139] In some embodiments, since the chip layout is a design file of the first chip, and the chip acquisition image is an image acquired from the first chip that has been fabricated into a physical entity, there is a size difference between the chip layout and the chip acquisition image. For example, when designing the first chip, the chip layout is 8mm × 8mm (length × width), while the acquired chip acquisition image of the first chip is 8.1mm × 8.2mm (length × width). That is, there is a size deviation of 0.1mm in length and 0.2mm in width between the chip layout and the chip acquisition image. Based on the smaller deviation, the chip layout is stretched with a target of 0.1mm, so that the chip layout and the chip acquisition image maintain a basic size match.

[0140] In some embodiments, the stretching / compression ratio corresponding to the chip layout is determined based on the size of the chip acquisition image. If the side length of the chip acquisition image is greater than the side length of the chip layout, the stretching ratio of the chip layout is determined. If the side length of the chip acquisition image is less than the side length of the chip layout, the compression ratio of the chip layout is determined. After adjustment according to the stretching / compression ratio, the first object position of the boundary object on the chip layout is determined, and the first object position is mapped onto the chip acquisition image to obtain the second object position of the boundary object on the chip acquisition image.

[0141] When stretching / compressing the chip layout, the number of pixels in the stretching / compression direction remains constant, and the chip layout is scaled by the size of the stretched / compressed pixels. In some embodiments, when determining the size of the chip layout, the length of the chip layout in the length and width directions is obtained according to the number of pixels and the size of the pixels in the length and width directions, respectively. Similarly, when determining the size of the chip acquisition image, the length of the chip acquisition image in the length and width directions is obtained according to the number of pixels and the size of the pixels in the length and width directions, respectively. When determining the size mapping relationship between the chip layout and the chip acquisition image, the size mapping relationship between the chip layout and the chip acquisition image is determined according to the lengths in the length and width directions obtained by multiplying the number of pixels and the size of the pixels as described above. To illustrate, taking the long side as an example, the length of the chip layout is obtained by multiplying the pixel size in the chip layout by the number of pixels along the long side; the length of the chip acquisition image is obtained by multiplying the pixel size in the chip acquisition image by the number of pixels along the long side; and the size mapping relationship between the chip layout and the chip acquisition image along the long side is determined based on the length of the chip layout and the length of the chip acquisition image.

[0142] Optionally, the dimensions in the embodiments of this application are expressed in length units, such as nanometers, millimeters, etc.

[0143] In some embodiments, since the chip image acquisition may be subject to problems such as lens shake and distortion during acquisition, based on the size mapping relationship between the chip layout and the chip image acquisition, at least two boundary objects corresponding to the positions to be corrected are first determined from the chip image acquisition, and the positions to be corrected are corrected to obtain the positions of the second objects corresponding to the boundary objects.

[0144] In some embodiments, the second object location can be understood as a location point or an image region. When the first object location is understood as a location point, the second object location is also understood as a location point. When the first object location is understood as an image region in the chip layout, the second object location is also understood as an image region in the chip's image acquisition.

[0145] Step 480: Determine at least two second object positions from the second object positions corresponding to at least two boundary objects respectively, and use the at least two second object positions to determine a region box as the chip element region.

[0146] Optionally, at least two second object positions are determined from the second object positions corresponding to at least two boundary objects as the region vertices or points on the region boundary of the chip acquisition area, and the chip element area is selected.

[0147] The chip component area includes the components in the first chip.

[0148] The region enclosed by boundary objects refers to the smallest region formed by multiple boundary objects, where the shape of the smallest region is the same as the shape of the first chip. For example, if the first chip is implemented as a rectangle, then the chip element region is a rectangle formed by at least three boundary objects. Taking boundary objects A, B, and C as an example, the line connecting boundary objects A and B forms the long side of the rectangle, the line connecting boundary objects A and C forms the short side, and the line connecting boundary objects B and C forms the diagonal. Using boundary objects A, B, and C as vertices of the rectangle, the rectangular region formed by these boundary objects constitutes the region enclosed by the boundary objects. Optionally, the edges of the smallest region formed by multiple boundary objects have a one-to-one correspondence with and are parallel to the edges of the first chip.

[0149] In the field of circuit design, a component refers to an independent unit that makes up the overall system. For example, in integrated circuits, components can be transistors, resistors, capacitors, etc. In superconducting quantum chips, components can be resonant cavities, cross-shaped large capacitors, test junctions, superconducting qubits, etc.

[0150] In some embodiments, when dividing the chip element region after determining the location of the second object, at least one of the following methods is included:

[0151] 1. According to pre-defined object determination rules, at least two target objects are identified from the boundary objects. Region boxes are generated based on the second object positions of these at least two target objects, and the chip element regions within these region boxes are obtained. The object determination rules include: identifying p boundary objects from the at least two boundary objects that are closest to the center point of the first chip as target objects, where p is an integer greater than 1; or, identifying q boundary objects from the at least two boundary objects that are closest to the vertices of the first chip as target objects, where q is an integer greater than 1.

[0152] By using object-based identification rules to determine chip component regions from chip acquisition images, only the region bounding boxes constructed from at least two target objects need to be determined, which improves the efficiency of determining chip component regions and thus improves the efficiency of chip defect detection.

[0153] 2. After determining the location of the second object, display the location markers corresponding to each location on the chip acquisition image. For example, if the coordinates of the second object are (2, 3), then display the location marker at coordinates (2, 3) on the chip acquisition image. Receive selection operations for at least two location markers, generate a bounding box based on the second object location corresponding to the selected location marker, and obtain the chip component area within the bounding box. The coordinate unit is a preset unit, such as mm, or pixels. The coordinate system is a preset coordinate system, such as establishing a coordinate system with the lower left corner of the chip acquisition image as the origin, the longer side as the horizontal axis, and the wider side as the vertical axis.

[0154] By defining chip component regions through location markers, users can customize the determination of chip component regions from chip-acquired images based on their region division preferences, thereby improving the flexibility and accuracy of chip component region determination.

[0155] It is worth noting that the above-described method for determining the chip element region is merely an illustrative example, and the embodiments of this application do not limit it.

[0156] In summary, the solution provided in this application first identifies boundary objects in the chip acquisition image, thereby delineating chip component areas based on the identified boundary objects, and then performing defect detection on the chip component areas. Specifically, when identifying boundary objects, the chip layout of the first chip during the design process is obtained, and the boundary objects in the chip layout are identified to obtain the position of the boundary objects in the chip layout. Based on the affine transformation relationship between the chip layout and the chip acquisition image, the position of the boundary objects in the chip layout is mapped to the chip acquisition image, thereby determining the position of the boundary objects in the chip acquisition image. This improves the efficiency of boundary object identification, thereby improving the efficiency of delineating chip component areas and the efficiency of defect detection on the first chip.

[0157] Taking a superconducting quantum chip as an example, the superconducting quantum chip includes coplanar waveguide (CPW) transmission lines. CPW transmission lines are high-performance and easy-to-fabricate microwave planar transmission lines, which include readout lines or control lines. In the wired superconducting quantum chip, the PADs are usually connected to the CPW coplanar waveguide readout lines or control lines. Therefore, to achieve automatic PAD identification, the CPW double-line structure needs to be removed from the chip layout, thus separating the original PAD portion.

[0158] In some embodiments, the chip components in the chip layout are constructed from lines. When identifying boundary objects, it is necessary to first erode the lines in the chip layout to remove CPW coplanar waveguide transmission lines and other noise elements in the chip layout.

[0159] Figure 6 This is a flowchart of a chip element region identification method provided in another exemplary embodiment of this application. The method is executed by a computer device, and can be executed by a terminal, a server, or a combination of both. Figure 6 As shown, step 440 above can be implemented by including steps 620 to 680.

[0160] Step 620: Obtain data for at least one line in the chip layout.

[0161] At least one line data is used to indicate the lines in the chip layout used to build the chip's constituent elements.

[0162] A chip layout is a layout file obtained by designing a first chip using chip design software. In this layout file, the various chip components and their interconnections are drawn using lines. (For illustrative purposes, please refer to [reference needed]). Figure 7 It illustrates a schematic diagram of some elements of a chip layout provided in an exemplary embodiment of this application, such as... Figure 7 As shown, the chip layout includes a metal contact 710 and a coplanar waveguide transmission line 720 connected to the metal contact 710. The coplanar waveguide transmission line 720 is implemented as a two-line structure, with each line connected to an insulated endpoint of the metal contact 710. In the two-line structure of the coplanar waveguide transmission line 720, the two lines are parallel, and the spacing between the two lines corresponds to the distance between the two insulated endpoints of the metal contact 710. In some embodiments, such as... Figure 7 As shown, one end of the coplanar waveguide transmission line 720 is connected to the metal contact point 710, and the other end is connected to other components 730 in the first chip.

[0163] In the chip layout, the aforementioned metal contact point 710, coplanar waveguide transmission line 720, and other components 730 are all constructed using lines. Figure 7 Only a portion of the elements constructed from lines in the chip layout are shown. It is understood that other elements in the chip layout are also constructed from line data.

[0164] In some embodiments, line data is expressed as the coordinates of a starting point and an ending point in the chip layout. That is, a line segment is obtained by connecting the starting point (expressed by the starting point coordinates) and the ending point (expressed by the ending point coordinates), which serves as the line segment of the element constructed in the chip layout. Alternatively, line data is expressed as the coordinates of multiple sequentially arranged endpoints in the chip layout. The line segments between two adjacent endpoints are expressed by the coordinates of multiple sequentially arranged endpoints, resulting in multiple line segments that connect sequentially, constituting an element or part of an element in the chip layout. Alternatively, line data is expressed as the coordinates of multiple element points in the chip layout, wherein the multiple element points are arranged sequentially to generate lines and construct the element in the chip layout. It is worth noting that the above implementation methods of line data are merely illustrative examples, and the embodiments of this application do not limit this.

[0165] Step 640: Obtain the translation data of the first line.

[0166] The first line translation data is used to indicate the first direction and first distance of translation of at least one line, and the first line translation data is used to shrink the chip constituent elements by controlling the line translation.

[0167] The first line translation data is either pre-configured data or generated data based on configuration operations.

[0168] In some embodiments, the method for obtaining the first line translation data includes at least one of the following:

[0169] 1. Obtain the pre-configured configuration file, which includes the translation parameters of at least one line in the chip layout. The translation parameters of at least one line are the translation data of the first line mentioned above.

[0170] The configuration of at least one line includes at least one of the following methods:

[0171] 1.1 After obtaining the chip layout, at least one line in the chip layout is configured independently. For example, the selection operation of the first line in the chip layout is received, the configuration box of the first line is displayed, and the first direction and first distance of the first line translation are filled in the configuration box of the first line. After configuring the translation direction and distance of at least one line that needs to be translated in sequence, the configuration data is combined to obtain the configuration file.

[0172] In some embodiments, in response to receiving an object identification request for requesting identification of boundary objects in the chip layout, a pre-stored configuration file is read, and at least one line is translated based on the configuration data for at least one line in the configuration file.

[0173] After designing the chip layout, the lines in the chip layout are independently configured to obtain the first line translation data. The translation of the lines in the chip layout is pre-configured, which improves the process efficiency in the defect detection process and avoids the problem of long defect detection time caused by temporarily determining the line translation. In addition, the translation data of at least one line is independently configured, which improves the flexibility of translation data configuration.

[0174] 1.2 After obtaining the chip layout, the translation direction of at least one line in the chip layout is configured independently, and the translation distance of at least one line is set uniformly. For example, the system receives the selection operation of the second line in the chip layout, and based on the selection of the second line, receives the operation to configure the translation direction of the second line. For example, please refer to... Figure 8 This illustrates the configuration process of the configuration operation of the first line translation data provided in an exemplary embodiment of this application, such as... Figure 8 As shown, in the chip layout, a drag operation on the second line 810 is received, and the drag direction is used as the translation direction of the second line 810; translation directions are configured sequentially for at least one line that needs to be translated. A configuration operation on the translation distance is received, such as displaying a translation distance configuration box 820, receiving a distance fill operation in the translation distance configuration box 820, and determining a uniform translation distance for at least one line configured with a translation direction based on the distance fill operation. A configuration file is obtained by combining the configured translation direction data and the translation distance data.

[0175] By uniformly setting the translation distance of at least one line, the configuration efficiency of the first line translation data is improved. By controlling the translation of at least one line with uniform translation requirements, the controllability of the image erosion process is improved.

[0176] 2. Before etching the chip components in the chip layout, receive translation data configuration operations to obtain the first line translation data.

[0177] In some embodiments, after obtaining the chip layout, a translation data configuration operation is received, wherein the translation data configuration operation includes a translation line configuration operation, or the translation data configuration operation includes a translation distance configuration operation, or the translation data configuration operation includes both a translation line configuration operation and a translation distance configuration operation.

[0178] The translation line configuration operation refers to configuring the translation direction of at least one line to be translated from the chip layout. In some embodiments, the translation line configuration operation further includes configuring at least one line to be translated from the chip layout, or each line in the chip layout is used as the line to be translated. The translation distance configuration operation refers to configuring the translation distance of at least one line individually or uniformly.

[0179] Before image erosion, translation data for at least one line is configured. This configuration is based on the characteristics of the acquired chip layout itself, avoiding the use of uniform or pre-configured data that does not meet the requirements of current boundary object recognition. For example, boundary object recognition may require the erosion of CPW double-line structures, while the preset translation data aims to remove finer double-line structures and cannot remove CPW double-line structures. This improves the adaptability between translation data and chip layout erosion requirements.

[0180] Image erosion is a morphological operation in image processing and computer vision. Its purpose includes eliminating smaller image objects, reducing their size, separating adjacent objects, and smoothing boundaries. In this embodiment, the image erosion effect produced by the first line translation data primarily removes the CPW double-line structure in the chip layout, preventing it from affecting PAD recognition. Since the CPW double-line structure is usually connected to the PAD, it might be mistaken for part of the PAD during recognition, thus affecting the accuracy of PAD recognition.

[0181] The image erosion in this embodiment mainly removes the CPW double-line structure in the chip layout by translating lines in the chip layout. Each line in the CPW double-line structure is translated in the direction of the other line. For example, the first line is translated towards the second line, and the second line is translated towards the first line. The total translation distance of the two lines is greater than the preset distance between the two lines in the chip layout design. That is, after image erosion, the distance between the two lines after translation is less than 0, thereby removing the two lines from the chip layout and realizing the image erosion process of the chip layout.

[0182] 3. After obtaining the chip layout, the lines in the chip layout are automatically identified, and the first line translation data is obtained based on the automatically identified lines to be translated.

[0183] In some embodiments, lines in the chip layout are automatically identified, such as by setting line translation rules and automatically identifying at least one line to be translated and its translation direction from the chip layout based on the line translation rules, and determining the translation distance of at least one line according to a default translation distance or a custom translation distance. For example, the chip translation rule is to determine the polygonal element formed by each line, and take the geometric center of the polygonal element as the reference direction for line translation, that is, to translate the line in the direction of the geometric center, specifically the line normal direction. For example, if the line includes normals a and b with opposite directions, where normal a points in the direction of the geometric center, then normal a is taken as the translation direction; or, the chip translation rule is to determine the line closest to each line, take the two closest lines as a pair of lines to be translated, and if the distance between the closest line pairs is less than a preset distance threshold, then take the two lines in the line pair as the lines to be translated, and take the translation direction of one of the lines in the line pair as the translation direction of the other line, thus obtaining multiple lines to be translated. The configuration file is generated based on the default or custom translation distance and the lines to be translated.

[0184] The first line translation data is automatically generated by automatically identifying lines in the chip layout. The line translation rules are then matched with the lines in the chip layout to determine the translation method of at least one line, which improves the efficiency and accuracy of image erosion.

[0185] It is worth noting that the above-described method for obtaining the translation data of the first line is merely an illustrative example, and the embodiments of this application do not limit it.

[0186] Step 660: Based on the translation data of the first line, translate at least one line to obtain the shrunken chip constituent elements.

[0187] Elements with line spacing smaller than the translation distance are removed after shrinking.

[0188] The chip is shrunk by translating at least one line in the chip layout based on the first line translation data. The at least one line is a line in the first line translation data that is configured with a translation direction and a translation distance.

[0189] Image erosion is a morphological image processing operation used to reduce the edges of objects in an image. It is typically used to remove minor noise, break narrow connections, or thin objects in an image. In this embodiment, after translating the lines in the chip layout using the first line translation data, at least the CPW double-line structure connected to the PAD can be removed. That is, in an optional embodiment, the line spacing between the two lines of the CPW double-line structure is less than the translation distance of the two lines. The two lines of the CPW double-line structure are translated towards the opposite edge structure. After both lines are translated towards the opposite edge structure, the distance between the two lines shrinks by twice the translation distance of a single line. In this embodiment, the line spacing between the two lines in the chip layout is less than twice the translation distance of a single line. Therefore, after image erosion, the CPW double-line structure is eroded, that is, removed.

[0190] This is illustrative; please refer to it. Figure 7 It shows a schematic diagram of the PAD and CPW structure provided in an exemplary embodiment of this application during corrosion, as shown below. Figure 7 As shown, the chip layout includes PAD710 and CPW720. According to the indication of the first line translation data, the line translation directions of PAD710 and CPW720 are as follows: Figure 7 The direction indicated by the middle arrow indicates the line translation distance, which is either the default or a preset translation distance.

[0191] exist Figure 7 Please refer to the translation of the lines for PAD710 and CPW720. Figure 9 It shows a schematic diagram of the PAD and CPW structures after etching, provided by an exemplary embodiment, as shown below. Figure 9 As shown, after the lines are translated, Figure 7 The CPW720 shown is corroded, while Figure 9 The image shows a PAD710 after corrosion.

[0192] Step 680: Identify the shrunken chip components to obtain at least two boundary objects in the chip layout, and determine the position of the first object in the chip layout of the at least two boundary objects.

[0193] After the chip components in the chip layout are etched, the CPW double-line structure in the chip layout is etched to obtain the shrunken chip components. The shrunken chip components are identified to obtain the boundary objects in the chip layout, such as PAD objects, and to determine the first object position of the identified boundary objects in the chip layout.

[0194] In some embodiments, after line translation, the lines in the chip layout may intersect to form new vertices. For these newly formed vertices, a Boolean operation needs to be performed on the lines in the chip layout to determine the newly formed vertices resulting from the intersections of the lines in the eroded chip layout, thus ensuring that the eroded chip layout can form valid polygons. The chip components are then identified based on the chip layout after the Boolean operation to obtain the boundary objects in the chip layout. Boolean operations refer to logical operations performed on Boolean variables, including basic operations such as AND, OR, and NOT.

[0195] In some embodiments, a Boolean intersection operation is performed on the lines in the etched chip layout to determine the vertices formed between the lines in the etched chip layout. In some embodiments, the line segments connecting the original vertices and newly generated vertices in the etched chip layout are removed, thereby avoiding the presence of invalid lines in the etched chip layout.

[0196] Indicative, such as Figure 10 The diagram illustrates a vertex Boolean operation provided in an exemplary embodiment of this application. Figure 10 The chip layout shown includes rectangular and triangular elements. The triangular elements include top and bottom 1011, vertex 1012, and vertex 1013. Taking vertex 1011 as an example, after eroding the rectangular element, Boolean operations are used to determine that each line in the eroded chip layout forms new vertices 1021, 1022, 1023, 1024, 1025, and 1026. The line segments between vertices in the eroded graphic are removed, such as the line segment between vertex 1011 and vertex 1021.

[0197] When translating lines in a chip layout to achieve vector image erosion, at least the following steps are included:

[0198] 1) Determine the translation distance: The translation distance refers to the absolute distance the lines are translated during chip layout etching. The translation distance can be the default or a custom configuration, and this embodiment does not limit it.

[0199] 2) Line translation: This refers to translating at least one line in the chip layout inward by the determined distance. For each line to be translated, its normal vector is calculated, and the line is translated along the direction of the normal vector. Inward translation means translating the line inward according to the polygonal shape of the virtual element formed by the lines.

[0200] 3) Handling intersections: During the translation of lines, lines may intersect or form new vertices. Boolean operations are required to remove invalid line segments generated in the chip layout after erosion to ensure that the result is still a valid polygon.

[0201] 4) Generate new elements: After removing invalid line segments from the translated lines, new chip constituent elements are generated to obtain the etched chip layout.

[0202] In an optional embodiment, the chip layout includes at least two layout layers, each layout layer including one or a group of chip components. For example, a layout layer includes a PAD and a CPW double-line structure connected by a PAD. Image erosion is performed on each layout layer, and chip components are identified on the eroded image to obtain the boundary objects in each layout layer. The first object position of the boundary object in the chip layout is determined based on the positional relationship between the layout layer and the chip layout and the position of the boundary object on the layout layer.

[0203] In summary, the method provided in this application first identifies boundary objects in the chip acquisition image before performing defect detection on the chip acquisition image of the first chip. Before identifying the boundary objects, the chip layout is first eroded to remove small noise, disconnect narrow connections, or thin objects in the image. In this application embodiment, when the boundary object is implemented as a PAD, the CPW double-line structure connected to the PAD in the chip layout is removed by image erosion to avoid interference from the CPW double-line structure to the identification of the PAD, thereby improving the accuracy of boundary object identification and thus improving the accuracy of dividing the chip element area and the efficiency of defect detection on the first chip.

[0204] In an optional embodiment, the boundary object is implemented as a semi-enclosed structure, surrounded by an insulating frame that is also semi-enclosed, with an enclosed conductor region inside. The semi-enclosed structure indicates that the outer insulating frame has an opening and does not completely enclose the inner conductor region. The inner conductor region communicates with the conductor outside the insulating frame through the opening in the insulating frame. For illustration, please refer to [reference needed]. Figure 5 In this design, PAD500 is implemented as a semi-enclosed structure, with an outer insulating region 520 surrounding the inner conductor region 510. However, the outer insulating region 520 has an opening, through which the inner conductor region 510 connects to the external conductor. The chip's constituent elements are determined to conform to the geometric features corresponding to the boundary object by extracting the convex hull.

[0205] Figure 11This is a flowchart of a chip element region identification method provided in another exemplary embodiment of this application. The method is executed by a computer device, and can be executed by a terminal, a server, or a combination of both. Figure 11 As shown, step 440 above can be implemented by including steps 1120 to 1160.

[0206] Step 1120: Extract the convex hull regions corresponding to the chip components in the chip layout.

[0207] In some embodiments, the conductor region is the main area in the chip layout. Taking a PAD as an example, the overall structure of a PAD is typically represented by an etched semi-enclosed insulating frame on the chip layout. The structure of a PAD includes the semi-enclosed insulating frame and the conductor region retained inside. The convex hull is used to outline the complete PAD structure, including the semi-enclosed insulating frame and the internal conductor region. The convex hull is a minimal convex polygon containing a set of points, formed by connecting the outermost points of this set of points, and the interior angles of the polygon are all less than 180 degrees.

[0208] In the chip layout, lines are formed by points, and chip components are constructed from these lines. Points in the chip layout can be understood as pixels or preset points.

[0209] When extracting the region enclosed by the convex hull, at least one of the following algorithms can be used: Graham's Scan, Jarvis March, and Andrew's Monotone Chain Algorithm.

[0210] Optionally, in this embodiment, the convex hull extraction of chip components is performed based on the Andrew monotonic chain algorithm. The Andrew monotonic chain algorithm is an algorithm for calculating the convex hull of a point set; it generates the minimum convex hull by constructing monotonic chains. A coordinate system is constructed with the top-left vertex of the chip component as the origin. The algorithm first sorts the point set according to its x-coordinate, then constructs two monotonic chains for points above and below the x-axis respectively, and finally merges these two chains to form a complete convex hull. First, the point set is sorted according to its x-coordinate. Specifically, for points in the chip component, they are sorted in ascending order of x-coordinate; if the x-coordinates are the same, they are sorted in ascending order of y-coordinate.

[0211] When constructing the monotonic chain of the upper convex hull, the construction proceeds from right to left, ensuring that the y-coordinate of each point is no greater than the y-coordinate of its predecessor. That is, the sorted set of points is traversed sequentially, checking if the current point constitutes a "right turn". If it is not a "right turn", the previous point is removed, continuing until a "right turn" is formed. A "right turn" means that the current point is to the right of the previous point in the monotonic chain; alternatively, a "right turn" can be understood as the vector formed between the previous point and the current point pointing in the positive x-axis direction of the coordinate system.

[0212] When constructing a monotonic chain of the lower convex hull, traverse each point from left to right, ensuring that the y-coordinate of each point is not less than the y-coordinate of its predecessor. That is, traverse the sorted set of points in reverse order, checking if the current point constitutes a "right turn". If it is not a "right turn", remove the previous point, continuing until a "right turn" is formed.

[0213] Merge the lower and upper convex hulls to form a complete convex hull, thus constructing the region enclosed by the convex hull.

[0214] Andrew's monotonic chain algorithm is highly efficient for processing large datasets because it only requires sorting the point set once and then constructing monotonic chains for each set. The algorithm is easy to implement, with clear steps, and is suitable for implementation in various programming environments. It has a wide range of applications, particularly for point sets in a two-dimensional plane, and can efficiently generate convex hulls.

[0215] In some embodiments, the chip components in the chip layout are first defined as follows: Figure 6 The erosion method shown is used to perform image erosion, shrink the chip components, and then extract the convex hull of the shrunken chip components to obtain the convex hull-enclosed region.

[0216] Step 1140: Determine the intersection and non-intersection regions between the chip constituent elements and the convex hull-enclosed region.

[0217] In some embodiments, a Boolean subtraction operation is performed on the chip constituent elements and the convex hull enclosed region to obtain the non-intersecting region within the convex hull enclosed region, and the region within the convex hull enclosed region other than the non-intersecting region is obtained to obtain the intersecting region.

[0218] In some embodiments, taking the chip constituent elements implemented as boundary objects PAD as an example, optionally, if the semi-enclosed insulating frame of PAD is used as the identification subject in the chip layout, then a Boolean subtraction operation is performed on the chip constituent elements and the convex hull enclosed region to obtain the non-intersecting region corresponding to the conductor region inside PAD in the convex hull enclosed region, and to obtain the intersecting region corresponding to the semi-enclosed insulating frame other than the non-intersecting region in the convex hull enclosed region.

[0219] Indicative, Figure 12This illustration shows a schematic diagram of a Boolean subtraction algorithm provided in an illustrative embodiment of this application, such as... Figure 12 As shown, the convex hull-enclosed region 1210 of the chip constituent elements is extracted, and a Boolean subtraction operation is performed between the convex hull-enclosed region and the chip constituent element 1200 to obtain a non-intersecting region 1220 and an intersecting region 1230. Specifically, the Boolean subtraction operation refers to taking the non-intersecting region between the convex hull-enclosed region 1210 and the chip constituent element 1200, resulting in the non-intersecting region 1220.

[0220] Optionally, the internal conductor region of the PAD can also be used as the identification subject in the chip layout. Then, a Boolean subtraction operation is performed on the chip constituent elements and the convex hull-enclosed region to obtain the non-intersecting region corresponding to the PAD semi-enclosed insulating frame in the convex hull-enclosed region, and to obtain the intersecting region corresponding to the internal conductor region of the PAD other than the non-intersecting region in the convex hull-enclosed region.

[0221] In this embodiment of the application, the non-intersecting regions corresponding to the conductor regions inside the PAD and the intersecting regions corresponding to the semi-enclosed insulating frame, other than the non-intersecting regions, are used as examples for illustration.

[0222] In some embodiments, a Boolean subtraction operation is performed on the chip constituent elements and the convex hull-enclosed region to obtain a non-intersecting region within the convex hull-enclosed region, and image erosion is performed on the non-intersecting region. Specifically, line translation data of the non-intersecting region is acquired. This line translation data can be pre-configured data or automatically triggered translation operations on the lines after automatic identification of the non-intersecting region. This line translation operation is used to shrink the non-intersecting region and remove fragmented lines between the convex hull-enclosed region and the outer edge of the original chip constituent elements.

[0223] Step 1160: If the geometric relationship between the non-intersecting region and the intersecting region meets the preset requirements, the chip constituent elements are determined as boundary objects in the chip layout, and the first object position of the boundary object in the chip layout is determined.

[0224] Geometric relationships refer to the relationship between a first geometric feature of a non-intersecting region and a second geometric feature of an intersecting region. In some embodiments, whether a chip component belongs to a boundary object is determined based on the difference between the first and second geometric features; or, whether a chip component belongs to a boundary object is determined based on the proportional relationship between the first and second geometric features; or, whether a chip component belongs to a boundary object is determined based on the positional relationship between the first and second geometric features.

[0225] In some embodiments, a first geometric feature vector of non-intersecting regions and a second geometric feature vector of intersecting regions are extracted. The chip constituent elements are then determined to belong to boundary objects based on the first and second geometric feature vectors. The first geometric feature vector includes at least one of a geometric center vector and a geometric area vector of the non-intersecting regions, and the second geometric feature vector includes at least one of a geometric center vector and a geometric area vector of the intersecting regions.

[0226] In this embodiment of the application, the method for determining boundary objects based on geometric relationships includes at least one of the following:

[0227] First, obtain the first geometric center of the non-intersecting region, and obtain the second geometric center of the intersecting region; if the positional difference between the first geometric center and the second geometric center meets the difference requirements, determine the chip constituent elements as boundary objects in the chip layout.

[0228] The geometric center, also known as the geometric centroid, is the center point of a polygon. In essence, the geometric center is the center point of a shape or object, usually calculated by averaging the positions of all points on the shape. In image processing and computational geometry, the geometric center is used to describe and locate the center of an object. In objects with uniform mass distribution, the geometric center is located at the same point as the center of gravity.

[0229] Here, the first geometric center refers to the position coordinates of the geometric center of the non-intersecting region on the chip layout. Optionally, these position coordinates are determined using a preset coordinate system corresponding to the chip layout. The first geometric center is the geometric center of the non-intersecting region automatically identified by the terminal. In some embodiments, since the lines in the chip layout can be divided into pixels with finer granularity, the pixel corresponding to the geometric center of the non-intersecting region is automatically generated based on the distribution of pixels in the non-intersecting region on the chip layout, and the position coordinates of this pixel on the chip layout are determined as the position coordinates of the first geometric center.

[0230] By calculating the geometric centers of the intersection and non-intersection regions, and using these geometric centers to determine whether chip components belong to boundary objects, boundary objects are identified according to the geometric center positional relationship that the intersection and non-intersection regions should conform to. This avoids misidentification of other chip components due to their similar area to the boundary objects, thus improving the accuracy of boundary object identification.

[0231] In some embodiments, taking the PAD's internal conductor region corresponding to the non-intersecting region and the semi-enclosed insulating frame corresponding to the intersecting region as an example, since the PAD's internal conductor region is implemented as a convex polygon, when automatically generating the first geometric center, it can be done through at least one of the following methods:

[0232] 1. Calculate the average value of the vertex coordinates of the non-intersecting regions to obtain the first geometric center.

[0233] The process involves summing the coordinates of all vertices in the non-intersecting region and dividing by the number of vertices to obtain an average coordinate, which is then used as the coordinates of the first geometric center. The vertex coordinates of the non-intersecting region can include the coordinates of multiple pixels on the bounding box of the non-intersecting region.

[0234] For the second geometric center of the intersection region, since the intersection region is implemented as a semi-enclosed structure, it is divided into multiple convex polygons. The position coordinates of the center of each convex polygon are calculated, and the average value of the position coordinates of the center of each convex polygon is obtained to obtain the position coordinates of the second geometric center. The method of dividing the intersection region into multiple convex polygons is based on the pre-configured geometric characteristics of the intersection region, such as identifying multiple vertices of the intersection region and using preset vertices of the intersection region as dividing points to obtain multiple convex polygons.

[0235] 2. Obtain the minimum bounding rectangle of the non-intersecting regions and determine the center point of the minimum bounding rectangle as the first geometric center; and obtain the minimum bounding rectangle of the intersecting regions and determine the center point of the minimum bounding rectangle as the second geometric center.

[0236] It is worth noting that the above-described method for obtaining the geometric center is merely an illustrative example, and the embodiments of this application do not limit it.

[0237] After obtaining the first position coordinates of the first geometric center and the first position coordinates of the second geometric center, the chip constituent elements in the intersection region and the non-intersection region are determined to be boundary objects based on the distance between the first position coordinates and the second position coordinates.

[0238] In this design, the boundary object is a semi-enclosed structure, with an outer semi-enclosed insulating frame and an inner conductor region. Under this structure, the geometric centers of the semi-enclosed insulating frame and the conductor region conform to a preset distance characteristic. Illustratively, the distance between the first and second geometric centers is less than a preset distance threshold. After obtaining the first position coordinates of the first geometric center and the second position of the second geometric center, the distance between the first and second position coordinates is determined. If the distance between the first and second geometric centers is less than the preset distance threshold, the chip components containing the intersection and non-intersection regions are defined as boundary objects in the chip layout.

[0239] For illustration purposes, the preset distance threshold is 10 (e.g., 10 pixels long, or the length of 10 pixels). If the distance between the first geometric center and the second geometric center is 8, or 8 pixels long, then the chip constituent elements where the intersection region and the non-intersection region are located are determined as boundary objects in the chip layout.

[0240] Second, obtain the first geometric area of ​​the non-intersecting region and the second geometric area of ​​the intersecting region; if the ratio of the first geometric area to the second geometric area is within a preset ratio range, determine the chip constituent elements as boundary objects in the chip layout.

[0241] In some embodiments, the terminal automatically obtains the first geometric area of ​​the non-intersecting region and automatically obtains the second geometric area of ​​the intersecting region.

[0242] Specifically, the first geometric area of ​​the non-intersecting region is obtained based on the number of pixels in the non-intersecting region, or the first geometric area of ​​the non-intersecting region is represented by the number of pixels in the non-intersecting region. Similarly, the second geometric area of ​​the intersecting region is obtained based on the number of pixels in the intersecting region, or the second geometric area of ​​the intersecting region is represented by the number of pixels in the intersecting region.

[0243] There is an area ratio relationship between the semi-enclosed insulating frame and the inner conductor region of the boundary element. In some embodiments, the area ratio between the semi-enclosed insulating frame and the inner conductor region is within a preset ratio range. Therefore, after obtaining the first geometric area of ​​the non-intersecting region and the second geometric area of ​​the intersecting region, the ratio between the first geometric area and the second geometric area is determined. When the ratio between the first geometric area and the second geometric area is within the preset ratio range, the chip constituent element is determined as a boundary object in the chip layout.

[0244] For illustrative purposes, the preset ratio range is 1.2-1.4. If the ratio between the first geometric area and the second geometric area is 1.25, then the chip constituent elements containing the intersection region and the non-intersection region are determined as boundary objects in the chip layout.

[0245] By calculating the geometric areas of the intersection and non-intersection regions, and using these geometric areas to determine whether chip components belong to boundary objects, boundary objects are identified according to the geometric area ratio that the intersection and non-intersection regions should conform to. This avoids misidentification of other chip components due to their total area being similar to that of the boundary objects, thus improving the accuracy of boundary object identification.

[0246] In some embodiments, determining boundary elements requires combining the determination of geometric center and geometric area. That is, obtaining the first geometric center of the non-intersecting region and the second geometric center of the intersecting region; obtaining the first geometric area of ​​the non-intersecting region and the second geometric area of ​​the intersecting region; and determining the chip constituent element as a boundary object in the chip layout when the ratio of the first geometric area to the second geometric area is within a preset ratio range and the positional difference between the first geometric center and the second geometric center meets the difference requirements.

[0247] In an optional embodiment, before determining the boundary objects based on the non-intersecting and intersecting regions, second line translation data is obtained. This second line translation data indicates a second direction and a second distance for translating at least one border line of the intersecting and non-intersecting regions. The second line translation data is used to shrink the intersecting and non-intersecting regions by controlling the line translation. Based on the second line translation data, at least one border line is translated to obtain the shrunken intersecting and non-intersecting regions. At least one border line of the intersecting and non-intersecting regions refers to at least one line on the outer border of the intersecting region or at least one line on the outer border of the non-intersecting region. The outer border refers to a frame-like structure composed of at least three line segments around the outer edge of the region. Taking the intersecting region as an example, when the intersecting region is implemented as a rectangular region, the outer border is the four sides of the rectangular region; when the intersecting region is implemented as a triangular region, the outer border is the three sides of the triangular region; and when the intersecting region is implemented as an irregular shape region, the outer border is the multiple sides that frame the irregular shape region.

[0248] The second line translation data is either pre-configured data or generated data based on configuration operations.

[0249] In some embodiments, the second line translation data is obtained in at least one of the following ways:

[0250] 1. Obtain the pre-configured configuration files corresponding to the intersection and non-intersection regions. The configuration files include translation parameters of at least one border line corresponding to the intersection and non-intersection regions in the chip layout. The translation parameters of at least one border line are the translation data of the second line mentioned above.

[0251] 2. After determining the intersection and non-intersection regions, receive the translation data configuration operation to obtain the second line translation data.

[0252] In some embodiments, after obtaining the chip layout, a translation data configuration operation is received, wherein the translation data configuration operation includes a translation line configuration operation, or the translation data configuration operation includes a translation distance configuration operation, or the translation data configuration operation includes both a translation line configuration operation and a translation distance configuration operation.

[0253] 3. After determining the intersection and non-intersection regions, the lines in the intersection and non-intersection regions are automatically identified, and the second line translation data is obtained based on the automatically identified border lines to be translated.

[0254] It is worth noting that the above-described method for obtaining the translation data of the second line is merely an illustrative example, and the embodiments of this application do not limit it.

[0255] In summary, the method provided in this application first identifies boundary objects in the chip acquisition image before performing defect detection on the chip acquisition image of the first chip. During boundary object identification, the convex hull enclosed region is extracted from the chip components in the chip layout, and the intersection and non-intersection regions between the chip components and the convex hull enclosed region are collected based on the convex hull enclosed region. According to the geometric features exhibited by the boundary object, it is determined whether the chip component belongs to the boundary object. For example, the geometric center position and geometric area ratio of the intersection and non-intersection regions are used to determine whether the chip component belongs to the boundary object. This improves the accuracy of boundary object identification, thereby improving the accuracy of dividing the chip component region and the efficiency of defect detection on the first chip.

[0256] Figure 13 This is a schematic diagram illustrating the overall process of identifying boundary objects from a chip layout, provided in an exemplary embodiment of this application. Figure 13 As shown, the process mainly includes the following steps.

[0257] Step 1301: Input chip layout.

[0258] In some embodiments, chip defects of the first chip are detected by defect detection software. Therefore, a chip layout is input to the defect detection software, wherein the defect detection software determines the position of the boundary object on the chip layout by recognizing the chip layout.

[0259] In some embodiments, the defect detection software identifies the complete chip layout. Alternatively, the chip layout includes at least two layout layers, each used to lay out one or a group of chip components, such as a layout layer including a PAD and a CPW double-line structure connected to the PAD. The defect detection software obtains at least two layout layers from the chip layout and performs boundary object identification in parallel for at least two layout layers. Optionally, different chip elements (polygons) can be located on the same or different layout layers. When chip elements are located on different layout layers, boundary object identification is performed in parallel for the layout layers containing the different chip elements.

[0260] Step 1302, first corrosion.

[0261] Acquire first line translation data, which is used to indicate the first direction and first distance of translation of at least one line in the chip layout, and is used to shrink chip constituent elements by controlling line translation.

[0262] Based on the line translation direction and distance indicated by the first line translation data, an erosion is performed on the chip layout. This first erosion is an image erosion operation aimed at shrinking the chip components within the chip layout. In some embodiments, in the CPW double-line structure, the spacing between the two lines is less than the total translation distance of the two lines, and each line in the double line is translated in the direction of the other line, thereby removing the CPW double-line structure after image erosion.

[0263] Step 1303, convex hull extraction.

[0264] In some embodiments, the convex hull enclosed region corresponding to the chip constituent element in the chip layout after one etch is extracted. The convex hull enclosed region is the smallest convex polygon that encloses the chip constituent element.

[0265] Optionally, the convex hull of the chip components is extracted based on the Andrew monotonic chain algorithm. Each pixel on the chip components is traversed in units of pixels. The Andrew monotonic chain algorithm is used to determine the pixels that form the convex hull enclosing region from the chip components during the pixel traversal process, thereby constructing the smallest convex polygon enclosing the chip components.

[0266] Step 1304, Boolean subtraction.

[0267] A Boolean subtraction operation is performed on the convex hull-enclosed region and the chip constituent elements. The Boolean subtraction operation determines the non-intersecting regions that do not belong to the chip constituent elements from the convex hull-enclosed region. Based on the non-intersecting regions, the intersecting regions that belong to the chip constituent elements are determined from the convex hull-enclosed region. Specifically, the Boolean subtraction operation is performed on the convex hull-enclosed region and the non-intersecting regions to determine the intersecting regions.

[0268] Alternatively, in some embodiments, the region where the chip constituent elements are located can be directly used as the intersection region. Boolean subtraction operations are used to determine the non-intersection region that does not belong to the chip constituent elements from the convex hull-enclosed region, and the region where the chip constituent elements are located can be obtained as the intersection region.

[0269] In some embodiments, taking the chip constituent element as an example, after performing a Boolean subtraction operation on the convex hull surrounding region and the chip constituent element, the non-intersecting region in the PAD corresponding to the inner conductor region is determined, and the intersecting region in the PAD corresponding to the outer semi-enclosed insulating region is determined.

[0270] Step 1305, secondary corrosion.

[0271] After determining the intersection and non-intersection regions, a second erosion is performed on the corresponding frames of the intersection and non-intersection regions to remove the fragments between the convex hull-enclosed areas and the outer edges of the chip constituent elements.

[0272] Step 1306, Feature vector extraction.

[0273] The process involves extracting a first geometric feature vector from non-intersecting regions and a second geometric feature vector from intersecting regions. The chip's constituent elements are then determined to be boundary objects based on these first and second geometric feature vectors. The first geometric feature vector includes at least one of a geometric center vector and a geometric area vector from the non-intersecting regions, and the second geometric feature vector includes at least one of a geometric center vector and a geometric area vector from the intersecting regions.

[0274] Step 1307: Output the boundary object region.

[0275] Optionally, a first geometric center of the non-intersecting region is obtained, and a second geometric center of the intersecting region is obtained; if the positional difference between the first geometric center and the second geometric center meets the difference requirement, the chip constituent element is determined as a boundary object in the chip layout.

[0276] Optionally, a first geometric area of ​​the non-intersecting region is obtained, and a second geometric area of ​​the intersecting region is obtained; if the ratio of the first geometric area to the second geometric area is within a preset ratio range, the chip constituent elements are determined as boundary objects in the chip layout.

[0277] In summary, the solution provided in this application first identifies boundary objects in the chip acquisition image before performing defect detection on the chip acquisition image of the first chip. This allows for the delineation of chip component regions based on the identified boundary objects, followed by defect detection on the chip component regions. Specifically, when identifying boundary objects, the chip layout of the first chip during the design process is obtained, and the boundary objects in the chip layout are identified to determine their positions within the chip layout. Then, based on the affine transformation relationship between the chip layout and the chip acquisition image, the positions of the boundary objects in the chip layout are mapped to the chip acquisition image, thereby determining the positions of the boundary objects in the chip acquisition image. This improves the efficiency of boundary object identification, thereby increasing the efficiency of chip component region delineation and defect detection on the first chip.

[0278] In an optional embodiment, when determining the boundary object on the chip acquisition image, it is necessary to first map the first object position of the boundary object on the chip layout to the chip acquisition image, and the bounding box selection deviation of the boundary object at the mapped position also needs to be considered during the mapping.

[0279] Figure 14 This is a flowchart of a chip element region identification method provided in another exemplary embodiment of this application. The method is executed by a computer device, and can be executed by a terminal, a server, or a combination of both. Figure 14As shown, step 460 above can be implemented by including steps 1420 to 1480.

[0280] Step 1420: In the chip layout, obtain the bounding boxes that are respectively bounded to at least two boundary objects based on the positions of the first objects corresponding to at least two boundary objects.

[0281] In some embodiments, when the first object position is used to indicate the minimum bounding box of a boundary object in the chip layout, the first object position is obtained as the snapping box for the boundary object; when the first object position is used to indicate the coordinates of a specified point on the chip layout, the snapping box for the boundary object based on the first object position in the chip layout is obtained. For example, if the first object position includes the coordinates of the upper left corner and the lower right corner of the boundary object, the line segment between the upper left corner and the lower right corner is determined as the diagonal of the snapping box based on the first object position, and the snapping box for the boundary object is determined based on the diagonal; or, if the first object position includes the coordinates of the geometric center of the boundary object and the length and width dimensions of the boundary object, the snapping box corresponding to the boundary object is obtained based on the coordinates of the geometric center and the length and width dimensions.

[0282] In some embodiments, each boundary object corresponds to one or a group of first object positions. A bounding box is obtained for the i-th boundary object based on the i-th first object position, where i is a positive integer. That is, one boundary object corresponds to one bounding box.

[0283] Step 1440: Scaling the chip layout based on the size mapping relationship between the chip layout and the chip acquisition image; mapping at least two bounding boxes in the chip acquisition image based on the bounding boxes in the scaled chip layout.

[0284] In some embodiments, when the first object position is used to indicate the minimum bounding box of a boundary object in the chip layout, the minimum bounding box corresponding to the first object position is directly mapped to the chip acquisition image to determine the mapping box corresponding to the first object position in the chip acquisition image; when the first object position is used to indicate the coordinates of a specified point on the chip layout, the fitting boxes that are respectively fitted to the boundary objects in the chip layout based on the first object position are obtained, and based on the size mapping relationship between the chip layout and the chip acquisition image, the fitting boxes that are respectively fitted to at least two boundary objects are mapped to the chip acquisition image to determine at least two mapping boxes.

[0285] In this embodiment, there is a one-to-one correspondence between the bounding boxes that are respectively overlaid on at least two boundary objects in the chip layout and the mapping boxes on the chip acquisition image. It is worth noting that the size of the chip acquisition image involved in this application refers to the size of the first chip acquired by the chip acquisition image. That is, the chip acquisition image also includes other blank areas or invalid areas acquired at the boundary positions when the first chip is image acquired. When mapping the size of the chip layout and the chip acquisition image, the size of the first chip in the chip acquisition image is used as the reference.

[0286] Optionally, the image region where the first chip is located is first identified and segmented from the chip-acquired image, or an image segmentation operation is received, which is used to segment the image region where the first chip is located from the chip-acquired image.

[0287] The fabrication of the first chip is based on the design results of the chip layout, specifically fabricating the physical chip according to the design concept of the chip layout. Therefore, there is a matching relationship between the chip layout of the first chip and the chip acquisition image of the first chip. This matching relationship includes the chip components in the chip layout being fabricated in physical form on the first chip, so that the acquired chip image includes image regions corresponding to the chip components, and the chip structure, component connection methods, and other features shown in the chip layout match the chip structure and component connection methods shown in the chip acquisition image.

[0288] In some embodiments, since the chip layout belongs to the design file of the first chip, while the chip acquisition image is an image acquired after the first chip is fabricated into a physical chip, there is a size difference between the chip layout and the chip acquisition image.

[0289] In some embodiments, when mapping the bounding boxes corresponding to at least two boundary objects to the chip acquisition image based on the size mapping relationship between the chip layout and the chip acquisition image, the size of the chip layout is stretched or compressed based on the size of the chip acquisition image. The layout content in the chip layout is stretched or compressed synchronously with the stretching or compression of the chip layout. In addition, the bounding boxes of the boundary objects identified in the chip layout are stretched or compressed synchronously with the stretching or compression of the chip layout.

[0290] After stretching or compressing the chip layout based on the size of the chip acquisition image, the overlay box is mapped to the chip acquisition image according to the same coordinates based on the matching relationship between the stretched or compressed chip layout and the chip acquisition image, thus obtaining the mapping box on the chip acquisition image.

[0291] During the scaling of a chip layout, taking the lower left corner of the chip layout as the origin to construct a coordinate system as an example, while keeping the lower left corner of the chip layout stationary, the length or width of the chip layout is scaled. The coordinate system constructed with the lower left corner of the chip layout as the origin remains unchanged. After scaling, the pixels on the chip layout undergo a proportional coordinate transformation based on the scaling ratio. For example, if the long side is extended by 1.1 times, the value of the pixels on the chip layout on the x-axis will be 1.1 times the original value.

[0292] For example, if the size of the chip layout is 100×100 (length×width), the coordinates of the top left corner of the bounding box of one of the boundary objects in the chip layout are (20, 10), and the coordinates of the bottom right corner of the bounding box of the boundary objects in the chip layout are (30, 15). If the size of the first chip in the chip acquisition image is 110×100, then the chip layout is stretched by 1.1 times along the long side. The bounding box of the boundary object is stretched synchronously with the stretching of the chip layout. After stretching, the coordinates of the top left corner of the bounding box of the boundary object in the chip layout are (22, 10), and the coordinates of the bottom right corner of the bounding box of the boundary object in the chip layout are (33, 15).

[0293] In some embodiments, to ensure that the shapes of the chip components in the chip layout do not change, the length and width of the chip layout are scaled proportionally.

[0294] Optionally, a first scaling ratio is obtained between the side length of the chip image in the first direction and the side length of the chip acquisition image in the first direction; a second scaling ratio is obtained between the side length of the chip image in the second direction and the side length of the chip acquisition image in the second direction; the chip layout and the nesting boxes in the chip layout are scaled based on the scaling ratio that meets the preset conditions in the first scaling ratio and the second scaling ratio; the scaled nesting boxes are mapped to the chip acquisition image to determine at least two mapping boxes in the chip acquisition image.

[0295] In some embodiments, the scaling ratio of the long side and the scaling ratio of the wide side are determined, and a specified scaling ratio that meets preset requirements is selected from the scaling ratios of the long side and the wide side. The chip layout is then scaled according to the specified scaling ratio. For example, a smaller scaling ratio is selected from the scaling ratios of the long side and the wide side, and the chip layout is scaled according to the smaller scaling ratio.

[0296] For example, the size of the chip layout is 100×100 (length×width). The coordinates of the top left corner of the bounding box of one of the boundary objects in the chip layout are (20, 10), and the coordinates of the bottom right corner of the bounding box of the boundary objects in the chip layout are (30, 15). The size of the first chip in the chip acquisition image is 110×120, the scaling ratio of the long side is 1.1, and the scaling ratio of the wide side is 1.2. Then, if the chip layout is stretched by 1.1 times, the size of the stretched chip layout will be 110×110. The bounding box of the boundary object will be stretched synchronously with the stretching of the chip layout. After stretching, the coordinates of the top left corner of the bounding box of the boundary object in the chip layout are (22, 11), and the coordinates of the bottom right corner of the bounding box of the boundary object in the chip layout are (33, 16.5).

[0297] Indicative, Figure 15 This illustration shows a schematic diagram of a snap-in frame mapped to a chip-acquired image, provided in an exemplary embodiment of this application. Figure 15 As shown, the size of the first chip in the chip acquisition image 1510 is 110×120, the size of the chip layout 1520 is 100×100, the coordinates of the upper left corner of the boundary object's frame 1521 in the chip layout are (20, 10), and the coordinates of the lower right corner of the boundary object's frame 1521 in the chip layout are (30, 15). When mapping the snap frame onto the first chip in the chip acquisition image, the chip layout is first stretched based on the size of the first chip in the chip acquisition image to obtain the stretched chip layout 1520. The snap frame 1521 of the boundary object is stretched synchronously, and the coordinates of the upper left corner of the snap frame in the chip layout 1520 are (22, 11) and the coordinates of the lower right corner in the chip layout 1520 are (33, 16.5). The snap frame 1521 of the boundary object is mapped onto the chip acquisition image 1510 according to the stretched chip layout 1520 to obtain the mapping frame 1511 on the chip acquisition image. After mapping, the coordinates of the upper left corner of the mapping frame in the chip acquisition image 1510 are (22, 11) and the coordinates of the lower right corner in the chip acquisition image 1510 are (33, 16.5).

[0298] The scaling method described above can reduce the impact of scaling operations on image content and, to a certain extent, enable size registration between the chip layout and the chip acquisition object, thereby improving the mapping accuracy between the chip layout and the chip acquisition image.

[0299] In some embodiments, after acquiring the mapping frame on the chip acquisition image, since there is a stretching deviation when the chip layout is stretched, such as different scaling ratios for length and width, a smaller scaling ratio is used for scaling, and the edges with larger stretching deviations are supplemented with stretching. Optionally, when the scaling ratios for length and width of the chip layout and the chip acquisition image are different, the edges with larger scaling ratios are supplemented with stretching or compression for the image content in the mapping frame.

[0300] Specifically, when supplementing, stretching, or compressing the edges of the mapping frame with a large scaling ratio, the image content within the mapping frame is first acquired. The mapping frame and its image content are then supplemented, stretched, or compressed using the edges with the large scaling ratio. The supplemented, stretched, or compressed mapping frame and image content are then stitched together with the chip-acquired image. Optionally, when stitching the scaled mapping frame and image content with the chip-acquired image, the scaled mapping frame and image content are overlaid onto the chip-acquired image according to the coordinates of a specified point of the mapping frame (e.g., the center point or the top left corner) on the chip-acquired image.

[0301] That is, determine the remaining scaling ratio and the corresponding side direction of the remaining scaling ratio that were not used in the scaling process of the frame in the first scaling ratio and the second scaling ratio; based on the remaining scaling ratio, supplement the scaling of the mapping frame with the side direction corresponding to the remaining scaling ratio to obtain the image content in the supplemented scaling mapping frame; stitch the image content in the supplemented scaling mapping frame with the chip acquisition image to obtain the stitched chip acquisition image; then when the candidate recognizes the image content in the mapping frame, recognize the image content in the supplemented scaling mapping frame in the stitched chip acquisition image.

[0302] Optionally, based on the difference between the actual stretching or compression ratio of the chip layout and the remaining scaling ratio in the length and width sides, the mapping frame is further stretched or compressed. For example, the stretching ratio of the frame during mapping is 1.1, which is determined according to the scaling ratio of the chip layout and the chip acquisition image on the long side. Since the scaling ratio of the chip layout and the chip acquisition image on the wide side is 1.2, the image content within the mapping frame is stretched by a factor of 1.09 in the wide side direction. Here, 1.09 is the ratio of 1.2 to 1.1, rounded to two decimal places.

[0303] Taking a PAD as an example to illustrate the process, based on the automatic recognition results of PADs on the chip layout, the bounding box of the PAD is extracted and scaled horizontally and vertically, with the smaller scaling ratio used as the reference. The coordinates of the scaled bounding box are then transformed to the coordinate system of the chip acquisition image to obtain the mapped box. At this point, since the initial scaling only uses the ratio of a specific direction (the direction with the smaller scaling ratio) as the reference ratio, there may be a misalignment in the other direction. Therefore, after the initial scaling, the coordinate system needs to be adjusted based on the image center of the chip layout and the chip acquisition image. At the same time, the mapped box needs to be stretched in the unused direction to ensure that more PAD areas are captured. Based on the captured chip acquisition image within the mapped box, high-resolution small-view images are stitched together.

[0304] Figure 16 This is a schematic diagram of a mapping frame provided in an exemplary embodiment of this application, as shown below. Figure 16 As shown, the chip acquisition image (only a portion of the image area 1600 is shown) includes PAD1610. After obtaining the mapping frame based on the chip layout, the mapping frame and the image content within the mapping frame are supplemented and stretched, and the supplemented and stretched mapping frame 1620 is stitched with the chip acquisition image 1600.

[0305] In this embodiment, the capturing box and the mapping box are implemented as bounding boxes. A bounding box is the smallest rectangular box that encloses a target object in an image, and it is typically used for object detection and localization. It defines the position and size of the object in the image, usually represented by the coordinates of the top-left and bottom-right corners.

[0306] Step 1460: Identify the image content in the mapping frame, correct the selection range of the mapping frame in the chip-acquired image, and obtain the corrected mapping frame.

[0307] In some embodiments, when identifying the image content in the mapping frame, the image content of the chip-acquired image after being selected and stitched by the mapping frame before scaling is supplemented, and the image content is identified; or, the image content of the chip-acquired image after being selected and stitched by the mapping frame after scaling is supplemented, and the image content is identified. This application embodiment does not limit this.

[0308] In some embodiments, after stitching the chip acquisition images, the image within the mapping frame is retained, while the area outside the mapping frame is left blank. Due to a certain coordinate offset between the chip layout and the chip acquisition image, other devices, such as PADs other than the target PAD, may be overlaid within the mapping frame. However, based on the aforementioned mapping operations, the overlaid portion of the target PAD image within the mapping frame is larger than the overlaid portions of other PAD images. The aforementioned supplementary scaling operations are to ensure that the template matching can match the target PAD image portion, reducing the probability of mismatching other parts.

[0309] Indicative, such as Figure 17 The diagram illustrates an image content within a mapping frame provided in an exemplary embodiment of this application. The mapping frame is obtained through the aforementioned mapping operation and supplementary scaling operations. PAD1710 and PAD1720 are captured within the mapping frame, where PAD1710 is the target PAD, and the captured area of ​​PAD1710 is larger than the captured area of ​​PAD1720.

[0310] Optionally, when correcting the mapping box, at least one of the following methods may be included:

[0311] The first method involves acquiring an object template image of the boundary object. Using this template image, the image content within the mapping frame is identified, and the registration relationship between the image content within the mapping frame and the template is determined. This registration relationship indicates the region in the object template image that matches the image content within the mapping frame. Based on this registration relationship, the bounding box range of the mapping frame in the chip-acquired image is corrected, resulting in the corrected mapping frame.

[0312] A boundary template image is a template image used to characterize the structural features of a boundary object.

[0313] In some embodiments, the object template image is obtained in at least one of the following ways:

[0314] 1. Obtain a pre-configured template file, which includes object template images. In some embodiments, the template file includes template images corresponding to at least one type of chip component, including template images corresponding to boundary objects.

[0315] In some embodiments, during the process of identifying boundary objects, the object identifier is determined based on the chip component elements set in the identification task creation stage, and the object template image corresponding to the object identifier is automatically read from the template file, which is the object template image corresponding to the boundary object.

[0316] By pre-setting a template file, template images of at least one chip component are stored in advance. When there is a need to identify chip components, the template image is automatically retrieved from the template file, which improves the efficiency and accuracy of template image retrieval.

[0317] 2. Obtain the object image identified at the first object location in the chip layout as the object template image.

[0318] Since the fabrication of the first chip is completed under the design concept of chip layout, the boundary objects fabricated in the first chip are structurally matched with the boundary objects designed in the chip layout. The object image identified at the position of the first object in the chip layout is directly obtained as a template, which improves the template acquisition efficiency.

[0319] By directly obtaining the identified boundary objects from the chip layout as object template images, the flexibility of obtaining object template images is improved. Since the first chip itself is prepared based on the chip layout, the structure of the boundary objects on the first chip is more similar to the design result in the chip layout. This avoids deviations between the structure or size of the boundary objects in the pre-set template file and the design of the first chip, thus improving the registration accuracy of the boundary objects.

[0320] In some embodiments, when registering an object template image with the image content in a mapping frame, a specified pixel in the object template image is determined, such as the top-left pixel of the template display area in the object template image; the specified pixel is sequentially aligned with the pixels in the mapping frame, and the overlap between the image content in the mapping frame and the image content in the object template image after alignment is matched, such as the number of pixels with the same pixel value at the overlapping position. The pixels in the mapping frame are sequentially traversed, and the target pixel with the largest number of pixels with the same pixel value at the overlapping position when aligned with the specified pixel is found. The relative positional relationship between the target pixel and the specified pixel is the relative positional relationship between the image content in the mapping frame and the object template image during registration.

[0321] The second method involves inputting the image content within the mapping box into a pre-trained correction model. The correction model identifies the deviation between the image content and the standard image content of the boundary object, thereby correcting the bounding box's selection range in the chip-acquired image based on the deviation, resulting in a corrected mapping box.

[0322] The calibration model is a machine learning model pre-trained using sample images of the boundary objects. In some embodiments, the sample images of the boundary objects are labeled with offset labels, which represent the deviation between the sample images and the content of the standard image. The sample images of the boundary objects are input into the calibration model, which identifies the image content of the sample images and outputs the predicted deviation of the sample images. Based on the difference between the predicted deviation and the offset labels, the calibration model is trained to obtain the trained calibration model.

[0323] It is worth noting that the above-described correction method for the mapping frame is merely an illustrative example, and the embodiments of this application do not limit it.

[0324] Taking the correction of the image content in the mapping frame using the object template image as an example, after obtaining the object template image as the template, the image content in the mapping frame is matched with the object template image to determine the position of the image content in the object template image, and the correction direction of the mapping frame is determined based on the part of the object template image that does not match the image content.

[0325] This is illustrative; please refer to it. Figure 18 It illustrates a schematic diagram of a template correction process provided in an exemplary embodiment of this application, such as... Figure 18 As shown, the image content in the mapping box includes PAD1810. The mapping box only outlines a portion of the area of ​​PAD1810. By matching template 1820 with the image content, the registration relationship between PAD1810 and template 1820 is determined. It can be seen that the lower right part of PAD1810 is not within the selection range of the mapping box, which means that the mapping box needs to be shifted to the lower right for correction, resulting in the corrected offset box.

[0326] In some embodiments, the target PAD image selected by the mapping box is only a partial sub-region of the actual image, requiring separation of the complete target PAD image from the chip mapping image. Optionally, in this embodiment, a connected unit algorithm based on mask construction is used to separate the complete target PAD image. This includes at least the following steps:

[0327] 1) For the spliced ​​chip acquisition image, extract the connected components.

[0328] In binary images, a connected unit refers to a group of pixels where all pixel values ​​are non-zero and all pixels are interconnected. Connected unit algorithms are commonly used in image processing to detect and analyze independent objects in an image. Pixel connection methods can be divided into two types: four-connection (connecting to one of the four adjacent pixels in the top, bottom, left, and right directions) and eight-connection (connecting to one of the eight adjacent pixels within a one-pixel straight-line distance). This embodiment uses an eight-connection connected unit as an example for illustration.

[0329] For the image content within the chip-acquired image, at least one connected unit is determined using the 8-connected unit algorithm.

[0330] 2) Construct a connected unit tree based on all connected units.

[0331] In some embodiments, when constructing the connected unit tree, the chip acquisition image is used as the root node, and the chip acquisition image is divided into multiple image regions according to a preset partitioning method. For example, the layout layer where each chip element polygon is located is considered as one image region, and the multiple image regions are the first-level child nodes of the root node. The connected units in the image regions are the second-level child nodes under the root node, that is, the connected units located in the m-th image region are the child nodes under the node corresponding to the m-th image region.

[0332] Indicative, Figure 19 This is a schematic diagram of a connected unit tree provided in an exemplary embodiment of this application, as shown below. Figure 19 As shown, the root node 1900 represents the chip-acquired image, the first-level child node 1910 represents multiple image regions divided in the chip-acquired image, and the second-level child node 1920 represents the connected units in the image regions.

[0333] It is worth noting that the above-described construction of the connected unit tree is merely an illustrative example, and the connected unit tree may include more or fewer levels, which is not limited in this application embodiment.

[0334] 3) For the region after template matching, perform collision detection between the mapping box and the connected units in the connected unit tree to find the overlapping connected units between the mapping boxes.

[0335] After identifying the connected units in the image acquired by the chip, collision detection is performed between the connected units and the mapping box. This identifies the connected units that collide with the mapping range of the mapping box, i.e., the connected units within the mapping range of the mapping box.

[0336] 4) Perform intersection detection on the mapped frame and connected units, and return the connected units that intersect with it.

[0337] In some embodiments, after matching the object template image with the image content in the mapping frame and determining the position of the image content in the object template image, if there are parts in the object template image that do not match the image content, optionally, after determining the connected units that intersect with the mapping frame from the connected unit tree, the connected units that match the parts in the object template image that do not match the image content are determined, and the position of the mapping frame where the connected unit is located in the chip-acquired image is used as the offset direction of the current mapping frame. In some embodiments, the offset distance is determined based on the size of the missing boundary object part in the mapping frame. For example, if the actual boundary object in the mapping frame includes a 10×10 region, the mapping frame is offset by 1.2 times the offset.

[0338] In some embodiments, intersection detection is performed on the mapping frame and the connected unit to determine the intersection area between the connected unit and the mapping frame. The connected unit with the largest intersection area with the mapping frame is identified and used as the target connected unit of the mapping frame. The mapping area of ​​the mapping frame is then corrected based on the target connected unit.

[0339] Step 1480: Determine the positions of the second objects corresponding to at least two boundary objects based on the corrected mapping frame.

[0340] In some embodiments, after obtaining the corrected bounding box, the image content within the corrected bounding box is obtained. (Illustrative example, such as...) Figure 20 As shown, after obtaining the corrected mapping frame, the image content 2000 in the corrected mapping frame is obtained, which includes the PAD image 2010 and the CPW double-line structure 2020.

[0341] Optionally, the image content within the corrected mapping frame is eroded to obtain the image region corresponding to PAD. The algorithm for eroding scalar images differs from that for vector images. The basic concept of scalar image erosion is to scan and traverse every pixel in the image using a template called a structuring element (or kernel), thereby reducing the edges of objects in the image. In this embodiment, the scalar image erosion algorithm includes at least the following steps:

[0342] 1) Definition of basic corrosion structural elements: Define the size and shape of the basic structural elements, which are usually squares or circles.

[0343] 2) Scan the image: Align the center of the structuring element with each pixel in the image, traverse each pixel in turn, and check all pixel values ​​of the pixels in the neighborhood of the pixel that correspond to the shape of the structuring element.

[0344] 3) Erosion operation: If all pixel values ​​within the structuring element's coverage area are 1 (foreground), then the value of the central pixel is retained as 1; otherwise, the value of the central pixel is set to 0. This is equivalent to using the structuring element to erode the edges of objects in the image. In a binary image, the foreground pixel value is considered to be 255.

[0345] Indicative, Figure 21 This is a schematic diagram of a scalar image erosion result provided in an exemplary embodiment of this application, such as... Figure 21 As shown, after the image content in the above-corrected mapping frame is eroded, an eroded image 2100 is obtained. The eroded image 2100 includes PAD 2110, which removes the CPW double-line structure through erosion.

[0346] Optionally, the positions of the second objects corresponding to at least two boundary objects are determined based on the content of the eroded image.

[0347] In summary, the method provided in this application first identifies boundary objects in the chip acquisition image before performing defect detection on the chip acquisition image of the first chip. When mapping the boundary objects identified in the chip layout to the chip acquisition image, a size mapping is first performed between the chip layout and the chip acquisition image. Based on the size mapping, the bounding box of the boundary object is mapped to the chip acquisition image to obtain a mapping box. The position of the second object on the chip acquisition image is determined based on the mapping box, which improves the accuracy of boundary object recognition, thereby improving the accuracy of dividing the chip component area and the efficiency of defect detection on the first chip.

[0348] In an optional embodiment, when determining the boundary object on the chip acquisition image, it is necessary to first map the first object position of the boundary object on the chip layout to the chip acquisition image, and then perform overlay on the boundary object according to the mapping result on the chip acquisition image to obtain the second object position of the boundary object on the chip acquisition image.

[0349] Figure 22 This is a flowchart of a chip element region identification method provided in another exemplary embodiment of this application. The method is executed by a computer device, and can be executed by a terminal, a server, or a combination of both. Figure 22 As shown, step 460 above can be implemented by including steps 2220 to 2240.

[0350] Step 2220: Scaling the chip layout based on the size mapping relationship between the chip layout and the chip acquisition image; and mapping the positions of at least two boundary objects to be corrected in the chip acquisition image based on the position of the first object in the scaled chip layout.

[0351] In some embodiments, since the chip layout belongs to the design file of the first chip, while the chip acquisition image is an image acquired after the first chip is fabricated into a physical chip, there is a size difference between the chip layout and the chip acquisition image.

[0352] In some embodiments, when mapping the bounding boxes corresponding to at least two boundary objects to the chip acquisition image based on the size mapping relationship between the chip layout and the chip acquisition image, the size of the chip layout is stretched or compressed based on the size of the chip acquisition image. The layout content in the chip layout is stretched or compressed synchronously with the stretching or compression of the chip layout. In addition, the bounding boxes of the boundary objects identified in the chip layout are stretched or compressed synchronously with the stretching or compression of the chip layout.

[0353] After stretching or compressing the chip layout based on the size of the chip acquisition image, the overlay box is mapped to the chip acquisition image according to the same coordinates based on the matching relationship between the stretched or compressed chip layout and the chip acquisition image, thus obtaining the mapping box on the chip acquisition image.

[0354] In some embodiments, based on the above Figure 14 The illustrated embodiment provides a method for obtaining the location of the second object, thereby obtaining the location to be corrected.

[0355] Step 2240: Based on the first positional relationship between n first object positions in the chip layout and the second positional relationship between n positions to be corrected in the chip acquisition image, correct the positions to be corrected to obtain the second object positions corresponding to at least two boundary objects in the chip acquisition image.

[0356] There is a one-to-one correspondence between the n first object positions and the n positions to be corrected.

[0357] n is an integer greater than 1. In some embodiments, a first connection line is obtained between the positions of the first objects corresponding to at least two boundary objects in the chip layout, and a second connection line is obtained between the positions to be corrected corresponding to at least two second boundary objects in the chip acquisition image, wherein the positional relationship between the at least two first boundary objects and the at least two second boundary objects is matched; based on the difference between the first connection line and the second connection line, the positions to be corrected corresponding to the at least two boundary objects in the chip acquisition image are calibrated to obtain the positions of the second objects corresponding to the at least two boundary objects in the chip acquisition image.

[0358] Optionally, two boundary objects are selected in the chip layout to form a first boundary object pair, and the line connecting the geometric centers of the two boundary objects in the chip layout is obtained as the first connecting line. Similarly, two boundary objects are selected in the chip acquisition image to form a second boundary object pair, and the line connecting the geometric centers of the two boundary objects in the chip layout is obtained as the second connecting line. The first and second boundary object pairs are a set of matched boundary objects, and the difference between the coordinates of the first boundary object pair in the chip layout and the coordinates of the second boundary object pair in the chip acquisition image is less than a difference threshold.

[0359] The first and second lines contain the geometric information required for the affine transformation of the image. By using the ratio of the length of the first line to the length of the second line as the reference ratio for the secondary scaling of the image acquired by the chip, and the angle difference between the first and second lines as the reference angle for the rotation of the image acquired by the chip, automatic image calibration can be achieved.

[0360] However, due to potential image distortion and jitter during image capture, the stitched PAD image in step 1440 may not accurately reflect its original shape and relative coordinates. Therefore, calculating the geometric centers of a random pair of PADs may introduce unnecessary errors into the affine transformation. In this embodiment, cluster analysis is introduced to process the data and reduce the impact of shooting errors on automatic calibration.

[0361] Optionally, the reference scale and angle difference of the image secondary scaling are transformed to the Cartesian coordinate system, k-means clustering analysis is performed, and the average value of the largest cluster is used as the reference for affine transformation to obtain the final scaling scale and angle difference results.

[0362] That is, based on the difference between the first and second connections, the affine transformation information between the chip layout and the chip acquisition image is determined; the affine transformation information between m groups of first boundary objects and m groups of second boundary objects is obtained, wherein there is a one-to-one correspondence between the m groups of first boundary objects and the m groups of second boundary objects, and m is an integer greater than 1; based on the clustering results of the m affine transformation information, the positions to be corrected corresponding to at least two boundary objects in the chip acquisition image are calibrated, and the positions of the second objects corresponding to at least two boundary objects in the chip acquisition image are obtained.

[0363] In some embodiments, the clustering results of multiple affine transformation information may correspond to a cluster. For example, when the difference between multiple affine transformation information is less than the clustering difference threshold, it corresponds to a cluster. Then, based on the cluster center of the cluster, multiple boundary objects are subjected to affine transformation. The affine transformation center includes the scaling ratio and rotation angle of the affine transformation. That is, based on the affine transformation center, the positions of the objects to be determined corresponding to the multiple boundary objects in the chip-acquired image are calibrated to obtain the second object positions corresponding to the multiple boundary objects in the chip-acquired image.

[0364] Optionally, multiple clusters may exist in the clustering results of multiple affine transformation information. At least two clustering degrees are obtained from the clustering results of m affine transformation information, where the i-th cluster includes the affine transformation center of the affine transformation information of the i-th group of boundary objects, where i is a positive integer. The affine transformation center includes the scaling ratio and rotation angle of the affine transformation. Based on the affine transformation center of the i-th group of boundary objects, the position to be corrected of the i-th group of boundary objects is calibrated to obtain the position of the second object corresponding to the i-th group of boundary objects in the chip-acquired image.

[0365] In some embodiments, calibrating the position to be corrected includes at least one of the following methods:

[0366] 1. Keeping the position to be corrected unchanged, scale and rotate the chip acquisition image according to the affine transformation center to obtain the chip acquisition image after affine transformation, and obtain the coordinates of the position to be corrected on the chip acquisition image after affine transformation, and obtain the position of the second object.

[0367] 2. Using a specified point on the chip-acquired image as a reference point, perform an affine transformation on the position to be corrected on the chip-acquired image according to the affine transformation center to obtain the coordinates of the position to be corrected on the chip-acquired image after the affine transformation, which is used as the second object position.

[0368] In summary, the method provided in this application first identifies boundary objects in the chip acquisition image before performing defect detection on the chip acquisition image of the first chip. After obtaining the position to be corrected of the boundary objects in the chip acquisition image, in order to reduce the influence of factors such as shaking and exposure during image capture, the position to be corrected of the boundary objects in the chip acquisition image is corrected based on the first connection between at least two boundary objects in the chip layout and the second connection between at least two boundary objects in the chip acquisition image, thereby improving the accuracy of determining the position of boundary objects in the chip acquisition pattern.

[0369] To illustrate, for a 40Gmon quantum chip layout, the angle difference of the vertex coordinates of the chip element region is manually specified as 0.012. The angle difference calculated by the method provided in this application embodiment is 0.0116813, with an error of 2.66%. For a 60Gmon quantum chip layout, the angle difference of the vertex coordinates of the chip element region is manually specified as -0.039. The angle difference calculated by the method provided in this application embodiment is -0.039897, with an error of 2.3%, which is within the ideal error range.

[0370] Figure 23 This is a structural block diagram of a chip element region identification device provided in an exemplary embodiment of this application, such as... Figure 23 As shown, the device includes:

[0371] The acquisition module 2310 is used to acquire the chip layout and chip acquisition image of the first chip. The chip layout refers to the arrangement of the chip components in the first chip, and the chip acquisition image is acquired by taking pictures of the first chip.

[0372] The identification module 2320 is used to identify the positions of the first objects corresponding to at least two boundary objects in the chip layout, wherein the at least two boundary objects are chip constituent elements of a pre-specified type in the first chip;

[0373] The mapping module 2330 is used to scale the chip layout based on the size mapping relationship between the chip layout and the chip acquisition image, and to map the positions of the second objects corresponding to the at least two boundary objects in the chip acquisition image based on the positions of the first objects in the scaled chip layout.

[0374] The determining module 2340 is used to determine at least two second object positions from the second object positions corresponding to the at least two boundary objects respectively, and use the at least two second object positions to determine a region box as the chip element region.

[0375] In an optional embodiment, the acquisition module 2310 is further configured to acquire at least one line data in the chip layout, the at least one line data being used to indicate the lines in the chip layout used to construct the chip constituent elements;

[0376] The acquisition module 2310 is further configured to acquire first line translation data, the first line translation data being used to indicate the first direction and first distance of the translation of the at least one line, and the first line translation data being used to shrink the chip constituent elements by controlling the line translation;

[0377] The identification module 2320 is further configured to translate the at least one line based on the first line translation data to obtain the shrunken chip constituent elements, wherein elements with line spacing less than the translation distance are removed after shrinkage; and to identify the shrunken chip constituent elements to obtain the positions of the first objects corresponding to the at least two boundary objects in the chip layout.

[0378] In an optional embodiment, such as Figure 24 As shown, the identification module 2320 includes:

[0379] Extraction unit 2321 is used to extract the convex hull enclosed region corresponding to the chip constituent elements in the chip layout;

[0380] The determining unit 2322 is used to determine the intersection region and non-intersection region between the chip constituent element and the convex hull enclosed region; when the geometric relationship between the non-intersection region and the intersection region meets the preset requirements, the chip constituent element is determined as the boundary object in the chip layout, and the position of the boundary object as the first object in the chip layout is determined.

[0381] In an optional embodiment, the determining unit 2322 is further configured to obtain a first geometric center of the non-intersecting region and a second geometric center of the intersecting region; if the positional difference between the first geometric center and the second geometric center meets the difference requirement, the chip constituent element is determined as the boundary object in the chip layout; or,

[0382] The determining unit 2322 is further configured to obtain a first geometric area of ​​the non-intersecting region and a second geometric area of ​​the intersecting region; and, if the ratio of the first geometric area to the second geometric area is within a preset ratio range, to determine the chip constituent element as the boundary object in the chip layout.

[0383] In an optional embodiment, the determining unit 2322 is further configured to perform a Boolean subtraction operation on the chip constituent elements and the convex hull enclosed region to obtain the non-intersecting region in the convex hull enclosed region; obtain the region in the convex hull enclosed region other than the non-intersecting region to obtain the intersecting region; or, obtain the region where the chip constituent elements are located as the intersecting region.

[0384] In an optional embodiment, the determining unit 2322 is further configured to acquire second line translation data, the second line translation data being used to indicate a second direction and a second distance of translation of at least one border line of the intersection region and the non-intersection region, the second line translation data being used to shrink the intersection region and the non-intersection region by controlling the line translation;

[0385] The determining unit 2322 is further configured to translate the at least one border line based on the second line translation data to obtain the shrunken intersection region and the non-intersection region.

[0386] In an optional embodiment, the acquisition module 2310 is further configured to acquire, in the chip layout, a bounding box that is respectively fitted to the at least two boundary objects based on the positions of the first objects corresponding to the at least two boundary objects;

[0387] The mapping module 2330 is further configured to scale the chip layout based on the size mapping relationship between the chip layout and the chip acquisition image, and to map at least two mapping frames in the chip acquisition image based on the overlay frame in the scaled chip layout.

[0388] The recognition module 2320 is also used to recognize the image content in the mapping frame, correct the selection range of the mapping frame in the image acquired by the chip, and obtain the corrected mapping frame;

[0389] The determining module 2340 is further configured to determine the positions of the second objects corresponding to the at least two boundary objects based on the corrected mapping frame.

[0390] In an optional embodiment, the acquisition module 2310 is further configured to acquire a first scaling ratio between the side length of the chip image in the first direction and the side length of the chip acquisition image in the first direction; and acquire a second scaling ratio between the side length of the chip image in the second direction and the side length of the chip acquisition image in the second direction.

[0391] The acquisition module 2310 is further configured to scale the chip layout and the nesting frame in the chip layout based on the scaling ratio that meets the preset conditions in the first scaling ratio and the second scaling ratio.

[0392] The mapping module 2330 is further configured to map the scaled frame to the image acquired by the chip, thereby determining the at least two mapping frames.

[0393] In an optional embodiment, the determining module 2340 is further configured to determine the remaining scaling ratios that were not used in the scaling process of the snap frame in the first scaling ratio and the second scaling ratio, and the side direction corresponding to the remaining scaling ratios.

[0394] The determining module 2340 is further configured to use the remaining scaling ratio as a reference to supplement the scaling of the mapping frame in the side direction corresponding to the remaining scaling ratio, so as to obtain the image content in the supplemented scaling mapping frame; and to stitch the image content in the supplemented scaling mapping frame with the chip acquisition image to obtain the stitched chip acquisition image.

[0395] The recognition module 2320 is also used to recognize the image content in the supplemented and scaled mapping frame in the stitched chip acquisition image.

[0396] In an optional embodiment, the acquisition module 2310 is further configured to acquire an object template image of the boundary object, wherein the boundary template image is a template image used to characterize the structural features of the boundary object;

[0397] The recognition module 2320 is further configured to use the object template image as a template to recognize the image content in the mapping frame, determine the registration relationship between the image content in the mapping frame and the template, the registration relationship being used to indicate the area in the object template image that matches the image content in the mapping frame; and correct the bounding box range of the mapping frame in the chip-acquired image based on the registration relationship to obtain the corrected mapping frame.

[0398] In an optional embodiment, the acquisition module 2310 is further configured to acquire an image of the boundary object identified at the first object location in the chip layout as the object template image.

[0399] In an optional embodiment, the mapping module 2330 is further configured to scale the chip layout based on the size mapping relationship between the chip layout and the chip acquisition image, and map the positions to be corrected corresponding to the at least two boundary objects in the chip acquisition image based on the position of the first object in the scaled chip layout.

[0400] The mapping module 2330 is further configured to correct the position to be corrected based on the first positional relationship between n first object positions in the chip layout and the second positional relationship between n positions to be corrected in the chip acquisition image, so as to obtain the second object positions corresponding to the at least two boundary objects in the chip acquisition image, where n is an integer greater than 1.

[0401] In an optional embodiment, the mapping module 2330 is further configured to: obtain a first connection between the positions of the first objects corresponding to at least two first boundary objects in the chip layout; obtain a second connection between the positions to be corrected corresponding to at least two second boundary objects in the chip acquisition image, wherein the positional relationship between the at least two first boundary objects and the at least two second boundary objects is matched; and calibrate the positions to be corrected corresponding to the at least two boundary objects in the chip acquisition image based on the difference between the first connection and the second connection, thereby obtaining the positions of the second objects corresponding to the at least two boundary objects in the chip acquisition image.

[0402] In an optional embodiment, the mapping module 2330 is further configured to: determine affine transformation information between the chip layout and the chip acquisition image based on the difference between the first connection and the second connection; acquire the affine transformation information between m groups of first boundary objects and m groups of second boundary objects, wherein there is a one-to-one correspondence between the m groups of first boundary objects and the m groups of second boundary objects, and m is an integer greater than 1; calibrate the positions to be corrected corresponding to the at least two boundary objects in the chip acquisition image based on the clustering results of the m affine transformation information, and obtain the positions of the second objects corresponding to the at least two boundary objects in the chip acquisition image.

[0403] In an optional embodiment, the mapping module 2330 is further configured to obtain at least two clusters from the clustering results of the m affine transformation information, wherein the i-th cluster includes the affine transformation center of the affine transformation information of the i-th group of boundary objects, and i is a positive integer; calibrate the position to be corrected of the i-th group of boundary objects based on the affine transformation center of the i-th group of boundary objects to obtain the position of the second object corresponding to the i-th group of boundary objects in the chip-acquired image.

[0404] In summary, the chip component region identification device provided in this application first identifies boundary objects in the chip acquisition image before performing defect detection on the chip acquisition image of the first chip, thereby delineating the chip component region based on the identified boundary objects. Specifically, when identifying boundary objects, the chip layout of the first chip during the design process is obtained, and the boundary objects in the chip layout are identified to obtain the position of the boundary objects in the chip layout. Based on the affine transformation relationship between the chip layout and the chip acquisition image, the position of the boundary objects in the chip layout is mapped to the chip acquisition image, thereby determining the position of the boundary objects in the chip acquisition image. This improves the efficiency of boundary object identification and thus improves the efficiency of chip component region delineation.

[0405] It should be noted that the apparatus provided in the above embodiments is only illustrated by the division of the above functional modules when implementing its functions. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. In addition, the apparatus and method embodiments provided in the above embodiments belong to the same concept, and the specific implementation process can be found in the method embodiments, which will not be repeated here.

[0406] Please refer to Figure 25 This diagram illustrates a structural block diagram of a computer device according to an embodiment of this application. This computer device can be used to implement the chip element region identification method provided in the above embodiments, and may specifically include the following:

[0407] The computer device 2500 includes a central processing unit (such as a CPU, GPU, or FPGA) 2501, a system memory 2504 including RAM (Random-Access Memory) 2502 and ROM (Read-Only Memory) 2503, and a system bus 2505 connecting the system memory 2504 and the central processing unit 2501. The computer device 2500 also includes a basic input / output system 2506 to facilitate information transfer between various devices within the server, and a large-capacity storage device 2507 for storing the operating system 2513, application programs 2514, and other program modules 2515.

[0408] The basic input / output system 2506 includes a display 2508 for displaying information and an input device 2509 for user input, such as a mouse or keyboard. Both the display 2508 and the input device 2509 are connected to the central processing unit 2501 via an input / output controller 2510 connected to the system bus 2505. The basic input / output system 2506 may also include the input / output controller 2510 for receiving and processing input from multiple other devices such as a keyboard, mouse, or electronic stylus. Similarly, the input / output controller 2510 also provides output to a display screen, printer, or other types of output devices.

[0409] The mass storage device 2507 is connected to the central processing unit 2501 via a mass storage controller (not shown) connected to the system bus 2505. The mass storage device 2507 and its associated computer-readable media provide non-volatile storage for the computer device 2500. That is, the mass storage device 2507 may include computer-readable media (not shown) such as a hard disk or a CD-ROM (Compact Disc Read-Only Memory) drive.

[0410] Without loss of generality, the computer-readable medium may include computer storage media and communication media. Computer storage media include volatile and non-volatile, removable and non-removable media implemented using any method or technology for storing information such as computer-readable instructions, data structures, program modules, or other data. Computer storage media include RAM, ROM, EPROM (Erasable Programmable Read-Only Memory), EEPROM (Electrically Erasable Programmable Read-Only Memory), flash memory or other solid-state storage technologies, CD-ROM, DVD (Digital Video Disc) or other optical storage, magnetic tape cassettes, magnetic tape, disk storage, or other magnetic storage devices. Of course, those skilled in the art will recognize that the computer storage medium is not limited to the above-mentioned types. The system memory 2504 and mass storage device 2507 described above can be collectively referred to as memory.

[0411] According to an embodiment of this application, the computer device 2500 can also be connected to a remote computer on a network, such as the Internet. That is, the computer device 2500 can be connected to a network 2512 via a network interface unit 2511 connected to the system bus 2505, or the network interface unit 2511 can be used to connect to other types of networks or remote computer systems (not shown).

[0412] The memory also includes a computer program stored in the memory and configured to be executed by one or more processors to implement the above-described method for identifying chip element regions.

[0413] In some embodiments, a computer-readable storage medium is also provided, wherein a computer program is stored therein, which, when executed by a processor, implements the above-described method for identifying chip element regions.

[0414] Optionally, the computer-readable storage medium may include: ROM (Read-Only Memory), RAM (Random Access Memory), SSD (Solid State Drives), or optical disc, etc. The random access memory may include ReRAM (Resistance Random Access Memory) and DRAM (Dynamic Random Access Memory).

[0415] In some embodiments, a computer program product is also provided, the computer program product including a computer program stored in a computer-readable storage medium. A processor of a computer device reads the computer program from the computer-readable storage medium, and the processor executes the computer program, causing the computer device to perform the above-described chip element region identification method.

[0416] It should be noted that, in this application embodiment, before and during the collection of user data, a prompt interface, pop-up window, or voice prompt message can be displayed. This prompt interface, pop-up window, or voice prompt message is used to inform the user that their data is currently being collected. This ensures that the application only begins executing the steps related to acquiring user data after receiving confirmation from the user regarding the prompt interface or pop-up window; otherwise (i.e., without receiving confirmation from the user), the steps to acquire user data end, meaning no user data is acquired. In other words, all user data collected in this application is processed strictly in accordance with the requirements of relevant national laws and regulations. The acquisition of informed consent or separate consent from the personal information subject is done with the user's consent and authorization. Subsequent data use and processing are conducted within the scope of laws, regulations, and the personal information subject's authorization. Furthermore, the collection, use, and processing of relevant user data must comply with the relevant laws, regulations, and standards of the relevant countries and regions. For example, the parameters, quantum circuits, and energy involved in this application are all obtained with full authorization.

[0417] It should be understood that "multiple" as used herein refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. Furthermore, the step numbers described herein are merely illustrative of one possible execution order. In some other embodiments, the steps may not be executed in numerical order, such as two steps with different numbers being executed simultaneously, or two steps with different numbers being executed in the reverse order of the illustration. This application does not limit this.

[0418] The above description is merely an exemplary embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A method for identifying chip component regions, characterized in that, The method includes: The chip layout and chip acquisition image of the first chip are obtained. The chip layout refers to the arrangement of the chip components in the first chip, and the chip acquisition image is obtained by taking pictures of the first chip. Identify the positions of the first objects corresponding to at least two boundary objects in the chip layout, wherein the at least two boundary objects are chip constituent elements of a pre-specified type in the first chip; The chip layout is scaled based on the size mapping relationship between the chip layout and the chip acquisition image, and the positions of the second objects corresponding to the at least two boundary objects are mapped in the chip acquisition image based on the position of the first object in the scaled chip layout. At least two second object positions are determined from the second object positions corresponding to the at least two boundary objects, and the region box is determined using the at least two second object positions as the chip element region.

2. The method according to claim 1, characterized in that, The step of identifying the positions of the first objects corresponding to at least two boundary objects in the chip layout includes: Obtain at least one line data in the chip layout, wherein the at least one line data is used to indicate the line in the chip layout used to construct the chip components; Acquire first line translation data, the first line translation data being used to indicate a first direction and a first distance of translation of the at least one line, the first line translation data being used to shrink the chip constituent elements by controlling the line translation; Based on the first line translation data, at least one line is translated to obtain the shrunken chip constituent elements, wherein elements whose line spacing is smaller than the translation distance are removed after shrinkage. Identify the constituent elements of the shrunken chip to obtain the positions of the first object corresponding to the at least two boundary objects in the chip layout.

3. The method according to claim 1, characterized in that, The step of identifying the positions of the first objects corresponding to at least two boundary objects in the chip layout includes: Extract the convex hull-enclosed regions corresponding to the chip components in the chip layout; Determine the intersection and non-intersection regions between the chip constituent elements and the convex hull enclosed region; When the geometric relationship between the non-intersecting region and the intersecting region meets the preset requirements, the chip constituent element is determined as the boundary object in the chip layout, and the position of the boundary object as the first object in the chip layout is determined.

4. The method according to claim 3, characterized in that, When the geometric relationship between the non-intersecting region and the intersecting region meets preset requirements, the chip constituent element is determined as the boundary object in the chip layout, including: Obtain the first geometric center of the non-intersecting region, and obtain the second geometric center of the intersecting region; if the positional difference between the first geometric center and the second geometric center meets the difference requirement, determine the chip component as the boundary object in the chip layout; or, Obtain the first geometric area of ​​the non-intersecting region, and obtain the second geometric area of ​​the intersecting region; if the ratio of the first geometric area to the second geometric area is within a preset ratio range, determine the chip constituent element as the boundary object in the chip layout.

5. The method according to claim 3, characterized in that, Determining the intersection and non-intersection regions between the chip constituent elements and the convex hull enclosed region includes: Perform a Boolean subtraction operation on the chip constituent elements and the convex hull enclosed region to obtain the non-intersecting region within the convex hull enclosed region; The intersection region is obtained by acquiring the region outside the non-intersection region within the convex hull-enclosed region; or, the region where the chip constituent elements are located is acquired as the intersection region.

6. The method according to claim 3, characterized in that, Before determining the chip component as the boundary object in the chip layout when the geometric relationship between the non-intersecting region and the intersecting region meets the preset requirements, the method further includes: Acquire second line translation data, which is used to indicate a second direction and a second distance of translation of at least one border line of the intersection region and the non-intersection region, and is used to shrink the intersection region and the non-intersection region by controlling the line translation; Based on the second line translation data, translate at least one border line to obtain the shrunken intersection region and the non-intersection region.

7. The method according to any one of claims 1 to 6, characterized in that, The scaling of the chip layout based on the size mapping relationship between the chip layout and the chip acquisition image, and the mapping of the second object positions corresponding to the at least two boundary objects in the chip acquisition image based on the first object position in the scaled chip layout, include: In the chip layout, obtain the bounding boxes that are respectively fitted to the at least two boundary objects based on the positions of the first objects corresponding to the at least two boundary objects; Based on the size mapping relationship between the chip layout and the chip acquisition image, the chip layout is scaled, and based on the overlay box in the scaled chip layout, at least two mapping boxes are mapped in the chip acquisition image. The image content in the mapping frame is identified, and the selection range of the mapping frame in the image acquired by the chip is corrected to obtain the corrected mapping frame. The positions of the second objects corresponding to the at least two boundary objects are determined based on the corrected mapping frame.

8. The method according to claim 7, characterized in that, The chip layout is scaled based on the size mapping relationship between the chip layout and the chip acquisition image. Based on the overlay boxes in the scaled chip layout, at least two mapping boxes are obtained in the chip acquisition image, including: Obtain a first scaling ratio between the side length of the chip image in the first direction and the side length of the chip acquisition image in the first direction; Obtain a second scaling ratio between the side length of the chip image in the second direction and the side length of the chip acquisition image in the second direction; Based on the scaling ratio that meets the preset conditions between the first scaling ratio and the second scaling ratio, the chip layout and the nesting frame in the chip layout are scaled. The scaled frame is mapped onto the image acquired by the chip to determine at least two mapping frames.

9. The method according to claim 8, characterized in that, After mapping the scaled frame to the image acquired by the chip and determining the at least two mapping frames, the process further includes: Determine the remaining scaling ratios that were not used in the scaling process of the frame between the first scaling ratio and the second scaling ratio, and the side direction corresponding to the remaining scaling ratios; Based on the remaining scaling ratio, the mapping frame is further scaled in the side direction corresponding to the remaining scaling ratio to obtain the image content in the mapping frame after further scaling. The image content in the supplemented and scaled mapping frame is stitched together with the chip acquisition image to obtain the stitched chip acquisition image; The process of recognizing the image content within the mapping frame includes: Identify the image content within the supplemented and scaled mapping frame in the stitched chip-acquired image.

10. The method according to claim 7, characterized in that, The process of identifying the image content within the mapping frame, correcting the bounding area of ​​the mapping frame in the image acquired by the chip, and obtaining the corrected mapping frame includes: Obtain the object template image of the boundary object, wherein the boundary template image is a template image used to characterize the structural features of the boundary object; Using the object template image as a template, the image content in the mapping frame is identified, and the registration relationship between the image content in the mapping frame and the template is determined. The registration relationship is used to indicate the area in the object template image that matches the image content in the mapping frame. Based on the registration relationship, the selection range of the mapping frame in the chip-acquired image is corrected to obtain the corrected mapping frame.

11. The method according to claim 10, characterized in that, The step of obtaining the object template image of the boundary object includes: The image of the boundary object identified at the first object location in the chip layout is used as the object template image.

12. The method according to any one of claims 1 to 6, characterized in that, The scaling of the chip layout based on the size mapping relationship between the chip layout and the chip acquisition image, and the mapping of the second object positions corresponding to the at least two boundary objects in the chip acquisition image based on the first object position in the scaled chip layout, include: Based on the size mapping relationship between the chip layout and the chip acquisition image, the chip layout is scaled and processed. Based on the position of the first object in the scaled chip layout, the positions to be corrected corresponding to the at least two boundary objects are mapped in the chip acquisition image. Based on the first positional relationship between n first object positions in the chip layout and the second positional relationship between n positions to be corrected in the chip acquired image, the positions to be corrected are corrected to obtain the second object positions corresponding to the at least two boundary objects in the chip acquired image, where n is an integer greater than 1.

13. The method according to claim 12, characterized in that, The step of correcting the positions to be corrected based on the first positional relationship between n first object positions in the chip layout and the second positional relationship between n positions to be corrected in the chip acquired image, to obtain the second object positions corresponding to at least two boundary objects in the chip acquired image, includes: Obtain the first connection line between the positions of at least two first boundary objects in the chip layout; Obtain a second line connecting the positions to be corrected corresponding to at least two second boundary objects in the chip-acquired image, wherein the positional relationship between the at least two first boundary objects and the at least two second boundary objects is matched; Based on the difference between the first connection and the second connection, the positions to be corrected corresponding to the at least two boundary objects in the chip-acquired image are calibrated to obtain the positions of the second objects corresponding to the at least two boundary objects in the chip-acquired image.

14. The method according to claim 13, characterized in that, The step of calibrating the positions to be corrected corresponding to the at least two boundary objects in the chip-acquired image based on the difference between the first connection and the second connection, to obtain the positions of the second objects corresponding to the at least two boundary objects in the chip-acquired image, includes: Based on the difference between the first connection and the second connection, the affine transformation information between the chip layout and the chip acquired image is determined; Obtain the affine transformation information between m groups of first boundary objects and m groups of second boundary objects, wherein there is a one-to-one correspondence between the m groups of first boundary objects and the m groups of second boundary objects, and m is an integer greater than 1; Based on the clustering results of the m affine transformation information, the positions to be corrected corresponding to the at least two boundary objects in the chip-acquired image are calibrated to obtain the positions of the second objects corresponding to the at least two boundary objects in the chip-acquired image.

15. The method according to claim 14, characterized in that, The clustering results based on m affine transformation information are used to calibrate the positions to be corrected corresponding to the at least two boundary objects in the chip-acquired image, respectively, to obtain the positions of the second objects corresponding to the at least two boundary objects in the chip-acquired image, including: Obtain at least two clusters from the clustering results of m affine transformation information, wherein the i-th cluster includes the affine transformation center of the affine transformation information of the i-th group of boundary objects, and i is a positive integer; Based on the affine transformation center of the i-th group of boundary objects, the position to be corrected of the i-th group of boundary objects is calibrated to obtain the position of the second object corresponding to the i-th group of boundary objects in the chip-acquired image.

16. A device for identifying chip element regions, characterized in that, The device includes: The acquisition module is used to acquire the chip layout and chip acquisition image of the first chip. The chip layout refers to the arrangement of the chip components in the first chip, and the chip acquisition image is acquired by taking pictures of the first chip. The identification module is used to identify the positions of the first objects corresponding to at least two boundary objects in the chip layout, wherein the at least two boundary objects are chip constituent elements of a pre-specified type in the first chip. The mapping module is used to scale the chip layout based on the size mapping relationship between the chip layout and the chip acquisition image, and to map the positions of the second objects corresponding to the at least two boundary objects in the chip acquisition image based on the positions of the first objects in the scaled chip layout. The determination module is used to determine at least two second object positions from the second object positions corresponding to the at least two boundary objects respectively, and use the at least two second object positions to determine a region box as the chip element region.

17. A computer device, characterized in that, The computer device includes a processor and a memory, the memory storing a computer program that is loaded and executed by the processor to implement the method as described in any one of claims 1 to 15.

18. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that is loaded and executed by a processor to implement the method as described in any one of claims 1 to 15.

19. A computer program product, characterized in that, The computer program product includes a computer program stored in a computer-readable storage medium, which a processor reads from and executes to implement the method as described in any one of claims 1 to 15.

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