Display module and display device

Abstract

A display module and a display device are provided. The display module includes: a substrate, the substrate including a display area and a peripheral area surrounding the display area, the peripheral area including a first sub-peripheral area located at least one side of the display area; a plurality of sub-pixels located in the display area; a plurality of data lines located in the display area and respectively electrically connected with the plurality of sub-pixels; a plurality of data transmission lines located in the first sub-peripheral area, the plurality of data transmission lines respectively electrically connected with the plurality of data lines; a plurality of first pads for connecting output pins of a first chip, the plurality of first pads respectively electrically connected with the plurality of data transmission lines; a plurality of second pads for connecting input pins of the first chip, the second pads located at a side of the first pads away from the display area; and a plurality of third pads respectively electrically connected with the plurality of data transmission lines, the first pads and the second pads located at a same side of the third pads.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a display module and a display device. Background Technology

[0002] During the fabrication of display substrates, array test (AT) units are typically used to charge and discharge the pixel circuits during the backplane process, and to perform charge detection and processing, thereby identifying display problems such as short circuits, image abnormalities, and driving abnormalities in advance. To match the test fixtures, there are certain size requirements for the test pins of the AT units.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] In one aspect, a display module is provided, comprising: a substrate, the substrate including a display area and a peripheral area surrounding the display area, the peripheral area including a first sub-peripheral area located on at least one side of the display area;

[0005] Multiple sub-pixels are located in the display area;

[0006] Multiple data lines are located in the display area and are electrically connected to the multiple sub-pixels respectively;

[0007] Multiple data transmission lines are located in the first sub-peripheral area, and the multiple data transmission lines are electrically connected to the multiple data lines respectively;

[0008] Multiple first pads are provided, each first pad being used to connect to the output pins of a first chip, and the multiple first pads are respectively electrically connected to the multiple data transmission lines.

[0009] Multiple second pads are provided for connecting the input pins of the first chip, and the second pads are located on the side of the first pads away from the display area; and

[0010] Multiple third pads are provided, each of which is electrically connected to multiple data transmission lines, and the first pad and the second pad are located on the same side of the third pads.

[0011] According to some exemplary embodiments, the plurality of third pads are located on the side of the plurality of first pads closer to the display area.

[0012] According to some exemplary embodiments, the plurality of third pads includes M rows of third pads spaced apart along a first direction, where M is a positive integer greater than or equal to 1, and the first direction is substantially parallel to the extension direction of the data transmission line.

[0013] According to some exemplary embodiments, the plurality of data transmission lines are spaced apart along a second direction, which intersects with the first direction;

[0014] The plurality of third pads include N columns of third pads spaced apart, and the extension direction of the entire column of the plurality of third pads located in the same column intersects both the first direction and the second direction, wherein N is a positive integer greater than or equal to 1.

[0015] According to some exemplary embodiments, the ratio of the number of the plurality of third pads to the number of the plurality of data transmission lines is in the range of 1 / 4 to 1.

[0016] According to some exemplary embodiments, the third pad has a first width in the second direction, the data transmission line has a second width in the second direction, and the ratio of the first width to the second width is greater than or equal to 7.

[0017] According to some exemplary embodiments, two adjacent third pads in the same row are spaced apart by a first spacing distance in the second direction, and two adjacent data transmission lines are spaced apart by a second spacing distance in the second direction, wherein the ratio of the first spacing distance to the second spacing distance is greater than or equal to 1.5.

[0018] According to some exemplary embodiments, the first width is greater than the first interval distance; and / or,

[0019] The second width is less than the second interval distance.

[0020] According to some exemplary embodiments, the plurality of third pads are located on the side of the plurality of second pads away from the display area.

[0021] According to some exemplary embodiments, at least a portion of the data transmission line includes a main body and an extension, the main body being electrically connected to the first pad and the extension being electrically connected to the third pad, wherein the extension extends from one end of the main body away from the display area along a fourth direction to a first region, the fourth direction being substantially parallel to the first direction, and the first region being located on the side of the module cut track away from the display area.

[0022] According to some exemplary embodiments, the plurality of third pads are located in the first region and are spaced apart along a second direction.

[0023] According to some exemplary embodiments, the orthographic projection of the extension on the substrate at least partially overlaps with the orthographic projection of the second pad on the substrate.

[0024] According to some exemplary embodiments, the display module further includes multiple lead-out traces located on the side of the first pad away from the display area.

[0025] Wherein, at least a portion of the orthographic projection of the second pad on the substrate falls within the orthographic projection of at least a portion of the lead-out trace on the substrate; and

[0026] The orthographic projection of the extension on the substrate at least partially overlaps with the orthographic projection of the lead-out trace on the substrate.

[0027] According to some exemplary embodiments, the first width is approximately 30 micrometers; and / or,

[0028] The first interval is approximately 10 micrometers; and / or,

[0029] The second width is approximately 3 micrometers; and / or,

[0030] The second interval is approximately 5 micrometers.

[0031] According to some exemplary embodiments, the display module further includes: a first conductive layer located on one side of the substrate; a first insulating layer located on the side of the first conductive layer away from the substrate; and a second conductive layer located on the side of the first insulating layer away from the substrate.

[0032] The data line and the data transmission line are located in the first conductive layer;

[0033] The first pad is located in at least one of the first conductive layer and the second conductive layer;

[0034] The second pad is located in at least one of the first conductive layer and the second conductive layer; and

[0035] The third pad is located on the second conductive layer.

[0036] In another aspect, a display device is provided, wherein the display device includes a display module as described in any of the preceding claims. Attached Figure Description

[0037] The foregoing contents, as well as other objects, features, and advantages of this disclosure, will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0038] Figure 1This is a plan view of a display module according to an embodiment of the present disclosure;

[0039] Figure 2 yes Figure 1 A magnified view of a portion of region S1 in the diagram;

[0040] Figure 3 yes Figure 2 A magnified view of a portion of region S2 in the diagram;

[0041] Figure 4 This is a partial plan view of the peripheral area of ​​a display module according to an embodiment of the present disclosure;

[0042] Figure 5 yes Figure 4 A magnified view of a portion of region S3 in the diagram;

[0043] Figure 6 It is along Figure 5 A schematic diagram of the cross-section taken by the centerline AA';

[0044] Figure 7 This is a partial plan view of the peripheral area of ​​a display module according to an embodiment of the present disclosure;

[0045] Figure 8 It is along Figure 7 A schematic diagram of the cross-section taken by the midline BB';

[0046] Figure 9 This is a partial plan view of the peripheral area of ​​a display module according to an embodiment of the present disclosure; and

[0047] Figure 10 This is a structural block diagram of a display device according to an embodiment of the present disclosure.

[0048] It should be noted that, for clarity, the dimensions of layers, structures, or regions in the accompanying drawings used to describe embodiments of the present invention may be enlarged or reduced; that is, these drawings are not drawn to actual scale. Detailed Implementation

[0049] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0050] It should be noted that, for clarity and / or descriptive purposes, the dimensions and relative dimensions of components may be enlarged in the accompanying drawings. Therefore, the dimensions and relative dimensions of the individual components are not necessarily limited to those shown in the drawings. In the specification and accompanying drawings, the same or similar reference numerals indicate the same or similar parts.

[0051] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects.

[0052] In this document, unless otherwise specified, directional terms such as "up," "down," "left," "right," "inner," and "outer" are used to indicate orientation or positional relationships based on the accompanying drawings, and are used only for the convenience of describing this disclosure, and are not intended to indicate or imply that the device, element, or component referred to must have a specific orientation, or be constructed or operated in a specific orientation. It should be understood that when the absolute position of the described object changes, the relative positional relationships they represent may also change accordingly. Therefore, these directional terms should not be construed as limitations on this disclosure.

[0053] In this document, the terms “approximately,” “about,” “approximately,” and other similar terms are used as terms of approximation rather than as terms of degree, and they are intended to account for inherent deviations in measured or calculated values ​​that would be recognized by one of ordinary skill in the art. Taking into account factors such as process variations, measurement problems, and errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), “about” or “approximately” as used herein includes stated values ​​and indicates that a particular value is within an acceptable range of deviation for one of ordinary skill in the art. For example, “about” may mean within one or more standard deviations, or within ±10% or ±5% of the stated value.

[0054] In this document, directional terms such as "first direction," "second direction," "third direction," and "fourth direction" are used to describe different directions of the display module, such as the row and column directions of subpixels or pads. It should be understood that such representations are merely exemplary descriptions and not limitations of this disclosure.

[0055] In this document, unless otherwise stated, the term "electrical connection" can mean that two components or elements are directly electrically connected, for example, component or element A is in direct contact with component or element B, and an electrical signal can be transmitted between them; it can also mean that two components or elements are electrically connected through a conductive medium, such as a conductive wire, for example, component or element A is electrically connected to component or element B through a conductive wire to transmit an electrical signal between the two components or elements; it can also mean that two components or elements are electrically connected through at least one electronic component, for example, component or element A is electrically connected to component or element B through at least one thin-film transistor to transmit an electrical signal between the two components or elements.

[0056] In this article, "parallel" or "nearly parallel" refers to the state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore also includes the state where the angle is greater than -5° and less than 5°. In addition, "perpendicular" refers to the state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore also includes the state where the angle is greater than 85° and less than 95°.

[0057] During the fabrication of the display substrate, by designing AT units, the pixel circuits can be charged and discharged during the backplane process, and charge detection and processing can be performed. This allows for the early identification of display problems such as short circuits, image abnormalities, and driving abnormalities, which helps to improve the yield of the display substrate and reduce costs.

[0058] To facilitate understanding by relevant personnel, some technical terms in this disclosure are explained briefly.

[0059] AT unit test pins: When performing array testing on the display module, it is necessary to electrically connect the data lines in the display module to the external test fixture. The test pins of the AT unit are conductive components (also called pins, terminals, or pads) that connect signal lines such as data lines to the external test fixture.

[0060] Backplane process: The manufacturing process of display panels is mainly divided into the backplane segment, the front panel segment, and the module segment. The backplane process mainly includes multiple process steps of the backplane segment. The backplane can be prepared through processes such as film deposition, photoresist coating, exposure, development, etching, and lift-off. The backplane segment is usually located before the slicing process (cutting and separating multiple display substrates on a large substrate).

[0061] Before slicing large display substrates, AT inspection is usually required to identify or repair abnormal display areas, thereby improving the yield of display substrates and reducing costs.

[0062] In some embodiments, the test pins of the AT unit of an IC product are located between the IC input pins and output pins. During IC product iterations, new IC products gradually face limited internal space, leading to a reduction in the number of pins that can be placed in the AT unit, or even a complete lack of space. This makes it impossible to effectively perform electrical signal testing during backplane fabrication, identify risks in advance, mitigate risks, and reduce cost losses.

[0063] This disclosure provides a display module. Specifically, the display module includes: a substrate, the substrate including a display area and a peripheral area surrounding the display area; a plurality of sub-pixels located in the display area; a plurality of data lines located in the display area and electrically connected to the plurality of sub-pixels respectively; a plurality of data transmission lines located in the peripheral area on at least one side of the display area, the plurality of data transmission lines being electrically connected to the plurality of data lines respectively; a plurality of first pads, the first pads being used to connect to the output pins of a first chip, and the plurality of first pads being electrically connected to the plurality of data transmission lines respectively; a plurality of second pads, the second pads being used to connect to the input pins of the first chip, and the second pads being located on the side of the first pads away from the display area; and a plurality of third pads, the plurality of third pads being electrically connected to the plurality of data transmission lines respectively, and the first pads and the second pads being located on the same side of the third pads.

[0064] This design allows the test pins of the AT unit to be placed in the external area of ​​the chip, solving the spatial constraints of the chip space on the test pins of the AT unit, which is beneficial to improving the pixel detection ratio and enhancing the reliability of detection.

[0065] Figure 1 This is a plan view of a display module according to an embodiment of the present disclosure.

[0066] Exemplarily, in an embodiment of this disclosure, a display module 100 is provided. (Refer to...) Figure 1 The display module 100 may include a substrate 1, which includes a display area AA and a peripheral area NA surrounding the display area AA.

[0067] The display area AA can have various shapes. For example, the display area AA can be set in various shapes such as a polygon (e.g., a rectangle) with a closed shape including straight sides, a circle or ellipse with curved sides, and a semicircle or semi-ellipse with both straight and curved sides. In embodiments of this disclosure, the display area AA is set as a region having a quadrilateral shape including straight sides. It should be understood that this is only an exemplary embodiment of this disclosure and not a limitation thereof. A peripheral area NA can be set on at least one side of the display area AA. In embodiments of this disclosure, the peripheral area NA can surround the outer periphery of the display area AA.

[0068] For example, the display module 100 may also include a plurality of subpixels PX. The plurality of subpixels are located in the display area AA. A pixel unit PX is the smallest unit for displaying an image and may be configured to have a plurality of them. For example, a pixel unit PX may include a light-emitting device that emits white light and / or colored light.

[0069] Pixel units PX can be configured in multiples, arranged in a matrix along columns extending in the first direction X and rows extending in the second direction Y. However, embodiments of this disclosure do not specifically limit the arrangement of pixel units PX, and pixel units PX can be arranged in various forms. For example, pixel units PX can be arranged such that the direction inclined relative to the first direction X and the second direction Y is the column direction, and the direction intersecting the column direction is the row direction.

[0070] For example, continue to refer to Figure 1 The display module may also include multiple data lines DL1. These multiple data lines DL1 are located in the display area AA and are electrically connected to multiple sub-pixels PX. For example, one data line DL1 can be electrically connected to multiple sub-pixels PX located in the same column, thereby providing data signals to a column of sub-pixels.

[0071] For example, after the data line DL1 is connected to the sub-pixel PX, it can extend along the first direction X to the boundary of the display area AA. It should be noted that the embodiments of this disclosure do not specifically limit the arrangement of the data line DL1 within the display area. For example, the data line DL1 can extend along the first direction X to the boundary of the display area, or it can extend along a direction intersecting the first direction X to the boundary of the display area.

[0072] For example, the display module 100 may further include multiple data transmission lines DL2. The multiple data transmission lines DL2 may be located in the peripheral area NA on at least one side of the display area. The multiple data transmission lines DL2 are electrically connected to multiple data lines DL1 respectively.

[0073] For example, the number of data lines DL1 and the number of data transmission lines DL2 can be the same. For instance, multiple data lines DL1 and multiple data transmission lines DL2 are connected in a one-to-one correspondence.

[0074] For example, the display module 100 may further include a driving unit 50. The peripheral area NA may include a first sub-peripheral area NA1, which is located on one side of the display area AA, for example, below the display area AA. The driving unit 50 may be located in the first sub-peripheral area NA1. The driving unit 50 may be electrically connected to the data transmission line DL2. The driving unit 50 can provide data signals, which are sequentially written to the sub-pixel PX via the data transmission line DL2 and the data line DL1, thereby controlling the sub-pixel to display different images.

[0075] For example, the driving unit 50 may include a first chip. For instance, the first chip may be a driving chip capable of providing data signals or other driving signals to the display module, controlling the sub-pixels to display different images.

[0076] For example, the driving unit 50 may include an AT unit (array test unit). The AT unit can charge and discharge the pixel circuits of the sub-pixels and perform charge detection and processing, thereby identifying display problems such as short circuits, image abnormalities, and driving abnormalities in advance.

[0077] The AT unit connects to an external test fixture and can temporarily replace the function of the driver chip, driving and illuminating sub-pixels to detect display abnormalities in the display area. AT testing allows for early identification of abnormal areas, enabling repairs and improving yield. Unrepairable areas can be marked and treated as defective products in subsequent processes, avoiding further processing such as chip bonding and polarizer application. This reduces unnecessary process steps, material waste, and ultimately lowers production costs.

[0078] For example, the drive unit 50 may include an FPC connector. The FPC connector can be connected to an external drive power supply or driver to provide drive power to the display module.

[0079] In some embodiments, in order to house multiple electronic components such as a first chip, an AT unit, and an FPC connector in the drive unit 50, multiple pads (or terminals, pins) need to be designed in the area where the drive unit 50 is located. For example, the multiple pads can be used to solder the chip or to solder the FPC connector.

[0080] For example, at least a portion of the multiple pads may also include test pins of the AT unit for connection to an AT test fixture, thereby enabling array testing of the display module.

[0081] Figure 2 yes Figure 1 A magnified view of a portion of region S1 in the diagram. Figure 3 yes Figure 2 A magnified view of the S2 region in the diagram.

[0082] For example, in conjunction with reference Figure 2 and Figure 3 The display module 100 may include multiple first pads P1. The first pads P1 can be used to connect to the output pins (IC Output Pins) of a first chip, and the multiple first pads P1 are electrically connected to multiple data transmission lines DL2 respectively. The multiple first pads P1 may be located in the chip output pad area S11.

[0083] The display module 100 may also include multiple second pads P2. The second pads P2 can be used to connect to the input pins (IC Input Pins) of the first chip. The multiple second pads P2 can be located in the chip input pad area S12. The chip input pad area S12 is located on the side of the chip output pad area S11 furthest from the display area AA.

[0084] For example, the first chip can be fixed in the display module by connecting the output pin (IC Output Pin) of the first chip to a plurality of first pads P1 and the input pin (IC Input Pin) of the first chip to a plurality of second pads P2 through soldering technology.

[0085] For example, the display module 100 may also include multiple third pads P3. The third pads P3 can serve as test pins for the AT unit. By connecting the third pads P3 to the array test fixture, testing of the display module can be performed, thereby identifying display problems such as short circuits, screen anomalies, and drive anomalies in advance, which helps improve yield and reduce costs. For example, AT unit testing can be performed before bonding the first chip.

[0086] In some embodiments, in conjunction with reference Figure 2 and Figure 3 The third pad, P3, is typically located within the AT pad area S13. The AT pad area S13 is situated between the chip output pad area S11 and the chip input pad area S12; that is, it lies within the space between the chip's input and output pins. With the trend towards narrower bezels in display substrates, chip sizes are decreasing, and the space between the chip's input and output pins is also shrinking, thus compressing the layout space for the test pins of the AT unit. For example, Figure 3 If the distance H1 between the first pad P1 and the second pad P2 in the first direction X is reduced, or if the width H2 of the area where the first pad P1 and the second pad P2 are located in the second direction Y is reduced, the layout space of the third pad P3 will be reduced, which will result in a reduction in the number of test pins of the AT unit. This is not conducive to the effect of AT testing of the display module, and may cause some problematic sub-pixels to be missed.

[0087] However, to match the AT test fixture, the test pins of the AT unit have certain size requirements. For example, the width D1 of the AT unit's test pins in the second direction Y is approximately 30 micrometers, and the width D3 in the first direction X is approximately 80 micrometers. This may result in a reduction, or even an inability, of the number of AT unit test pins that can be set in the space between the chip's input and output pins (e.g., the AT pad area S13). This makes it impossible to effectively perform electrical signal testing, identify risks in advance, mitigate risks, and reduce cost losses during the backplane process.

[0088] In some embodiments, the detection ratio of the AT unit is approximately 1 / 4, meaning that only one of the four data lines can be connected to the test pin of the AT unit to obtain detection.

[0089] To address the space constraints on the test pin layout of the AT unit, embodiments of this disclosure optimize the design of the AT unit's test pins by placing them in the external area of ​​the chip. This design completely resolves the space constraints on the AT unit's test pins, thereby improving pixel detection ratio, increasing yield, and reducing costs.

[0090] Figure 4 This is a partial planar schematic diagram of the peripheral area of ​​a display module according to an embodiment of the present disclosure.

[0091] As an example, in an embodiment of this disclosure, a display module is provided. The test pins of the AT unit in the display module can be designed in the area between the chip and the display area.

[0092] For example, refer to Figure 4 The display module 100 may include multiple first pads P1. The first pads P1 can be used to connect to the output pins (IC Output Pins) of a first chip, and the multiple first pads P1 are electrically connected to multiple data transmission lines DL2 respectively. The multiple first pads P1 may be located in the chip output pad area S11.

[0093] The display module 100 may also include multiple second pads P2. The second pads P2 can be used to connect to the input pins (IC Input Pins) of the first chip. The multiple second pads P2 can be located in the chip input pad area S12. The chip input pad area S12 is located on the side of the chip output pad area S11 furthest from the display area AA.

[0094] By using soldering technology, the output pins (IC Output Pins) of the first chip can be connected to multiple first pads P1, and the input pins (IC Input Pins) of the first chip can be connected to multiple second pads P2, thereby fixing the first chip in the display module. In other words, the first chip can at least partially cover the chip output pad area S11 and the chip input pad area S12. The first chip can also cover the gap area between the chip output pad area S11 and the chip input pad area S12.

[0095] For example, continue to refer to Figure 4 The display module 100 may also include multiple third pads P3. Each of the multiple third pads P3 is electrically connected to multiple data transmission lines DL2. The third pads P3 can be used as test pins for the AT unit. The test fixture can write test signals to the data transmission lines DL2 via the third pads P3, and then transmit them to the pixel circuit of the sub-pixel for testing.

[0096] For example, the first pad P1 and the second pad P2 are located on the same side of the third pad P3. For example, multiple third pads P3 are located on the side of multiple first pads P1 near the display area AA. For example, refer to... Figure 4 Multiple third pads P3 are located in the AT pad area S13. The chip output pad area S11 and the chip input pad area S12 are both located on the side of the AT pad area S13 away from the display area AA. That is to say, the test pins of the AT unit can be located in the area between the chip pins and the display area.

[0097] The space between the chip pins and the display area is larger than the space inside the chip. Therefore, this design solves the space constraint on the test pins of the AT unit within the chip, allowing for better spatial layout of the AT unit's test pins, increasing the pixel detection ratio, thereby improving yield and reducing costs.

[0098] For example, continue to refer to Figure 4 At least a portion of the plurality of third pads P3 can be arranged in a matrix form with columns extending along the third direction X1 and rows extending along the second direction Y. The angle θ between the third direction X1 and the first direction X can be an acute angle. For example, the angle θ between the third direction X1 and the first direction X can be less than 15°.

[0099] In some embodiments, at least a portion of the plurality of third pads may be arranged in a matrix form with columns extending along the fifth direction X1' and rows extending along the second direction Y. The angle between the fifth direction X1' and the first direction X may be an acute angle. For example, the angle between the fifth direction X1' and the first direction X may be less than 15°. Exemplarily, the third direction X1 and the fifth direction X1' may be symmetrical about the first direction X.

[0100] This design allows for the symmetrical distribution of multiple third pads, which helps to make full use of wiring space and facilitates the narrowing of the bezel of the display substrate.

[0101] For example, multiple data transmission lines DL2 are spaced apart along a second direction Y, which intersects with a first direction X. Multiple third pads P3 may include N columns of third pads spaced apart, and the extension direction of the entire column of multiple third pads located in the same column intersects both the first direction X and the second direction Y, where N is a positive integer greater than or equal to 1. The number of columns of the third pads P3 can be designed accordingly based on the number of columns of the data transmission lines DL2. For example, the number of columns of the third pads P3 can be equal to the number of columns of the data transmission lines DL2. As another example, the number of columns of the third pads P3 can be approximately 1 / 2, 1 / 3, or 1 / 4 of the number of columns of the data transmission lines DL2.

[0102] For example, the extension direction of the entire column of multiple third pads located in the same column can be parallel to the third direction X1. Through such offset (or partial misalignment) design, adjacent data transmission lines DL2 can alternately connect third pads P3 located in different rows. This can reduce mutual interference between third pads P3 in adjacent rows while ensuring that the third pads P3 have sufficient size, which is beneficial to improving the reliability of the connection between the third pads P3 and the data transmission lines DL2.

[0103] For example, continue to refer to Figure 4 The plurality of third pads P3 may include M rows of third pads P3 spaced apart along the first direction X, where M is a positive integer greater than or equal to 1. The first direction X is substantially parallel to the extension direction of the data transmission line DL2.

[0104] It should be noted that, although Figure 4 In some embodiments, the number of rows of the plurality of third pads P3 is 2, but the embodiments of this disclosure are not limited to this. In some embodiments of this disclosure, the plurality of third pads P3 may also include one row, or the plurality of third pads P3 may also include 3, 4 or more rows spaced apart along the first direction X.

[0105] This design allows for full utilization of the space in the first direction X, enabling the placement of more third pads P3. This allows more data transmission lines DL2 to be connected to the test fixture, improving the pixel detection ratio.

[0106] In some embodiments, the third pad P3 is arranged in a multi-row, multi-column array, which is beneficial for increasing the number of third pads P3. For example, the ratio of the number of multiple third pads to the number of multiple data transmission lines is in the range of 1 / 4 to 1.

[0107] This design can increase the detection ratio of AT units, for example, it can achieve full-ratio detection, that is, every data line can be detected, which helps to improve the yield of display substrates and reduce costs.

[0108] For example, the display module may further include multiple fourth pads P4. The multiple fourth pads P4 may be located in the FPC pad area S14. The multiple fourth pads P4 may be used to connect to the FPC circuit board. The FPC pad area S14 may be located on the side of the chip input pad area S12 away from the display area AA.

[0109] Figure 5 yes Figure 4 A magnified view of the S3 region in the diagram.

[0110] In some embodiments of this disclosure, reference is made to Figure 5 The third pad P3 has a first width D1 in the second direction Y, and the data transmission line DL2 has a second width D2 in the second direction Y. For example, the ratio of the first width D1 to the second width D2 is greater than or equal to 7.

[0111] For example, two adjacent third pads P3 located in the same row are spaced apart by a first spacing distance DS1 in the second direction Y, and two adjacent data transmission lines DL2 are spaced apart by a second spacing distance DS2 in the second direction Y. The ratio of the first spacing distance DS1 to the second spacing distance DS2 is greater than or equal to 1.5.

[0112] For example, the first width D1 is greater than the first interval distance DS1.

[0113] For example, the second width D2 is smaller than the second spacing distance DS2.

[0114] In some embodiments of this disclosure, the first width D1 is approximately 30 micrometers; and / or, the first spacing distance DS1 is approximately 10 micrometers; and / or, the second width D2 is approximately 3 micrometers; and / or, the second spacing distance DS2 is approximately 5 micrometers.

[0115] For example, continue to refer to Figure 5The third pad P3 has a third width D3 in the first direction X. The third width D3 is greater than the first width D1. For example, the ratio of the third width D3 to the first width D1 is between 2 and 3. For example, the third width D3 is approximately 80 micrometers and the first width D1 is approximately 30 micrometers.

[0116] For example, two adjacent rows of third pads P3 may be spaced apart by a third spacing distance DS3 in the first direction X. The third spacing distance DS3 may be substantially equal to the first spacing distance DS1. For example, the third spacing distance DS3 is approximately 10 micrometers, and the first spacing distance DS1 is approximately 10 micrometers.

[0117] This design ensures that multiple third pads are connected to multiple data transmission lines while maintaining sufficient size and adequate spacing between adjacent rows or columns of third pads. This facilitates the connection of test fixtures to the third pads for pixel detection, thereby improving the detection results.

[0118] Figure 6 It is along Figure 5 A schematic diagram of the cross-section taken by the midline AA'.

[0119] By way of example, in some embodiments of this disclosure, the display module may further include: a first conductive layer 101 located on one side of the substrate 1; a first insulating layer 102 located on the side of the first conductive layer 101 away from the substrate 1; and a second conductive layer 103 located on the side of the first insulating layer 102 away from the substrate 1.

[0120] For example, in conjunction with reference Figure 1 , Figures 4-6 Data line DL1 and data transmission line DL2 can be located on the first conductive layer 101. The third pad P3 can be located on the second conductive layer 103.

[0121] The third pad P3 can be electrically connected to the data transmission line DL2 through the via VH1 that penetrates the first insulating layer 102.

[0122] For example, the first pad P1 may be located in at least one of the first conductive layer 101 and the second conductive layer 103. For instance, both the first pad P1 and the data transmission line DL2 are located in the first conductive layer 101, and the first pad P1 and the data transmission line DL2 can be connected via traces inside the first conductive layer 101. As another example, the first pad P1 may be located in the second conductive layer 103, and the first pad P1 can be electrically connected to the data transmission line DL2 via a third via VH3.

[0123] For example, the second pad P2 may be located in at least one of the first conductive layer 101 and the second conductive layer 103.

[0124] This design allows for full utilization of the vertical space of the display module, which helps to increase the wiring density of the display module, reduce the planar size of the display module, and facilitates the miniaturization of the display module.

[0125] In some embodiments of this disclosure, the test pins of the AT unit can also be located on the side of the chip pins away from the display area, thereby solving the space limitation of the internal space of the chip on the test pins of the AT unit, which is beneficial to increase the AT detection ratio, improve the yield, and reduce costs.

[0126] Figure 7 This is a partial planar schematic diagram of the peripheral area of ​​a display module according to an embodiment of the present disclosure.

[0127] Exemplary, in some embodiments of this disclosure, reference is made to Figure 7 The data transmission line DL2 can extend along the fourth direction X2 after passing through the chip output pad area S11, through the chip input pad area S12 and the FPC pad area S14 to the first region S10. The third pad P3 can be connected to the extended portion of the data transmission line DL2 in the first region S10. That is, the AT pad area S13 can be located in the first region S10, or the AT pad area S13 can be in the same region as the first region S10.

[0128] For example, multiple third pads P3 are located on the side of multiple second pads P2 away from the display area AA.

[0129] This design solves the space constraints on the test pins of the AT unit within the chip's internal space, which helps to increase the AT inspection ratio, improve yield, and reduce costs.

[0130] For example, continue to refer to Figure 7 At least part of the data transmission line DL2 includes a main body DL21 and an extension DL22. The main body DL21 is located on the side of the extension DL22 closer to the display area AA.

[0131] The main body DL21 is electrically connected to the first pad P1, and the extension DL2 is electrically connected to the third pad P3. Exemplarily, at least a portion of the extension DL22 of the data transmission line DL2 extends from the end O1 of the main body DL21 away from the display area along a fourth direction X2 to the first region S10. The fourth direction X2 may be substantially parallel to the first direction X, or the fourth direction X2 may intersect the first direction X.

[0132] In some embodiments, at least a portion of the extension DL22 of the data transmission line DL2 extends from the end O1 of the main body portion DL21 away from the display area along the sixth direction X2' to the first region S10. The sixth direction X2' may be substantially parallel to the first direction X, or the sixth direction X2' may intersect the first direction X.

[0133] For example, the fourth direction X2 and the sixth direction X2' can be symmetrical about the first direction X.

[0134] For example, the extension portion DL22 of the data transmission line can adopt a polygonal design, that is, the extension portion DL22 of the data transmission line can be divided into multiple sub-segments, and the extension directions of the multiple sub-segments can be the same or different, so that the extension portion DL22 of the data transmission line extends along the fourth direction X2 as a whole.

[0135] This design allows for flexible adjustment of the routing and spacing of the data transmission line extension DL22, which is beneficial for the subsequent connection design between the third pad P3 and the data transmission line extension DL22.

[0136] For example, continue to refer to Figure 7 The first region S10 is located on the side of the module cutting channel L1 away from the display area AA. The module cutting channel L1 can be used as a cutting area when slicing modules to separate multiple display modules located on a large substrate and form multiple independent display modules.

[0137] For example, a plurality of third pads P3 are located in the first region S10, and the plurality of third pads P3 are spaced apart along the second direction Y. The plurality of third pads P3 can serve as test pins of the AT unit.

[0138] Since the area of ​​the first region S10 is larger than that of the internal space of the chip, more third pads P3 can be set in the first region S10, which is beneficial to improving the detection rate of AT test.

[0139] For example, at least one of two adjacent data transmission lines DL2 extends into the first region S10. The third pad P3 is electrically connected to the data transmission line DL2 extending into the first region S10. The ratio of the number of third pads P3 to the number of data transmission lines DL2 is approximately 1 / 2, that is, the ratio of the detection data lines using the AT unit can be approximately 1 / 2.

[0140] In some embodiments, after completing the AT unit test, the substrate can be sliced ​​in the area where the module cutting channel L1 is located, removing a portion of the substrate located on the side of the module cutting channel L1 away from the display area AA, to obtain the sliced ​​display substrate. This design can reduce the bezel size of the display substrate.

[0141] For example, continue to refer to Figure 7 The orthographic projection of the extension DL22 on the substrate overlaps at least partially with the orthographic projection of the second pad P2 on the substrate.

[0142] For example, the display module also includes multiple lead-out traces 20 located on the side of the first pad P1 away from the display area AA. For instance, the multiple lead-out traces 20 can be used as FPC connection traces for connection to the FPC circuit board.

[0143] For example, at least a portion of the orthographic projection of the second pad P2 on the substrate falls into at least a portion of the orthographic projection of the lead-out trace 20 on the substrate.

[0144] For example, the orthographic projection of the extension DL22 on the substrate at least partially overlaps with the orthographic projection of the lead-out trace 20 on the substrate.

[0145] This design allows for full utilization of the vertical space of the display module, which is beneficial for increasing the wiring density of the display module, reducing the planar size of the display module, and enabling the display module to have a narrow bezel.

[0146] For example, at least a portion of the lead-out traces 20 can be divided into a first sub-lead-out trace 201 and a second sub-lead-out trace 202 on the side away from the display area. The first sub-lead-out trace 201 and the second sub-lead-out trace 202 can serve as connection traces for bonding the FPC circuit board.

[0147] This design ensures that the width of the FPC connection traces is as consistent as possible in the second direction Y, which helps to improve the connection stability between the FPC connection traces and the FPC circuit board, thereby improving the stability and reliability of the display substrate.

[0148] Figure 8 It is along Figure 7 A schematic diagram of the cross-section taken from the centerline BB'.

[0149] Exemplarily, in embodiments of this disclosure, reference is made to Figure 7 and Figure 8 The display module may include: a first conductive layer 101 located on one side of the substrate 1; a first insulating layer 102 located on the side of the first conductive layer 101 away from the substrate 1; a second conductive layer 103 located on the side of the first insulating layer 102 away from the substrate 1; a second insulating layer 104 located on the side of the second conductive layer 103 away from the substrate 1; and a third conductive layer 105 located on the side of the second insulating layer 104 away from the substrate 1.

[0150] For example, the lead trace 20 can be located on the third conductive layer 105, and the second pad P2 can be located on the second conductive layer 103. The lead trace 20 can be electrically connected to the second pad P2 through a via VH2 that penetrates the second insulating layer 104.

[0151] For example, the extension DL22 of the data transmission line located in the first conductive layer 101 can be isolated from the second conductive layer 103 and the third conductive layer 105 by the first insulating layer 102.

[0152] Figure 9 This is a partial planar schematic diagram of the peripheral area of ​​a display module according to an embodiment of the present disclosure.

[0153] Exemplarily, in embodiments of this disclosure, reference is made to Figure 9 Multiple data transmission lines DL2 can all be extended into the first region S10.

[0154] Multiple third pads P3 can be arranged in a multi-row, multi-column array in the first region S10, thereby increasing the number of third pads P3 while ensuring the size requirements of the third pads P3.

[0155] This design allows for AT testing of each data line, improving testing efficiency, increasing the yield of display modules, and reducing costs.

[0156] Figure 10 This is a structural block diagram of a display device according to an embodiment of the present disclosure.

[0157] Optionally, embodiments of this disclosure also provide a display device, referring to... Figure 10 The display device 200 may include the aforementioned display module 100. The display device may include, but is not limited to, any product or component with display functionality, such as electronic paper, mobile phones, tablet computers, monitors, laptops, digital photo frames, and navigators. It should be understood that this display device has the same beneficial effects as the display module provided in the foregoing embodiments.

[0158] While some embodiments of the general concept of this disclosure have been shown and described, those skilled in the art will understand that changes may be made to these embodiments without departing from the principles and spirit of the general concept of this disclosure, the scope of which is defined by the claims and their equivalents.

Claims

1. A display module, characterized in that, include: A substrate, the substrate including a display area and a peripheral area surrounding the display area, the peripheral area including a first sub-peripheral area located on at least one side of the display area; Multiple sub-pixels are located in the display area; Multiple data lines are located in the display area and are electrically connected to the multiple sub-pixels respectively; Multiple data transmission lines are located in the first sub-peripheral area, and the multiple data transmission lines are electrically connected to the multiple data lines respectively; Multiple first pads are provided, each first pad being used to connect to the output pin of a first chip, and the multiple first pads are respectively electrically connected to the multiple data transmission lines. Multiple second pads are provided for connecting the input pins of the first chip, and the second pads are located on the side of the first pads away from the display area. and Multiple third pads are electrically connected to multiple data transmission lines, and the first pad and the second pad are located on the same side of the third pads.

2. The display module according to claim 1, wherein, The plurality of third pads are located on the side of the plurality of first pads that are closer to the display area.

3. The display module according to claim 2, wherein, The plurality of third pads include M rows of third pads spaced apart along a first direction, where M is a positive integer greater than or equal to 1, and the first direction is substantially parallel to the extension direction of the data transmission line.

4. The display module according to claim 3, wherein, The plurality of data transmission lines are spaced apart along a second direction, which intersects with the first direction; The plurality of third pads include N columns of third pads spaced apart, and the extension direction of the entire column of the plurality of third pads located in the same column intersects both the first direction and the second direction, wherein N is a positive integer greater than or equal to 1.

5. The display module according to any one of claims 1-4, wherein, The ratio of the number of the plurality of third pads to the number of the plurality of data transmission lines is in the range of 1 / 4 to 1.

6. The display module according to claim 4, wherein, The third pad has a first width in the second direction, and the data transmission line has a second width in the second direction, wherein the ratio of the first width to the second width is greater than or equal to 7.

7. The display module according to claim 6, wherein, Two adjacent third pads in the same row are spaced apart by a first spacing distance in the second direction, and two adjacent data transmission lines are spaced apart by a second spacing distance in the second direction, wherein the ratio of the first spacing distance to the second spacing distance is greater than or equal to 1.

5.

8. The display module according to claim 7, wherein, The first width is greater than the first interval distance; and / or, The second width is less than the second interval distance.

9. The display module according to claim 1, wherein, The plurality of third pads are located on the side of the plurality of second pads away from the display area.

10. The display module according to claim 9, wherein, At least a portion of the data transmission line includes a main body and an extension, the main body being electrically connected to the first pad and the extension being electrically connected to the third pad, wherein the extension extends from one end of the main body away from the display area along a fourth direction to a first region, the fourth direction being substantially parallel to the first direction, and the first region being located on the side of the module cutting track away from the display area.

11. The display module according to claim 10, wherein, The plurality of third pads are located in the first region and are spaced apart along the second direction.

12. The display module according to claim 11, wherein, The orthographic projection of the extension on the substrate at least partially overlaps with the orthographic projection of the second pad on the substrate.

13. The display module according to any one of claims 10-12, wherein, The display module also includes multiple lead-out traces, which are located on the side of the first pad away from the display area. Wherein, at least a portion of the orthographic projection of the second pad on the substrate falls within the orthographic projection of at least a portion of the lead-out trace on the substrate; and The orthographic projection of the extension on the substrate at least partially overlaps with the orthographic projection of the lead-out trace on the substrate.

14. The display module according to claim 7, wherein, The first width is approximately 30 micrometers; and / or, The first interval is approximately 10 micrometers; and / or, The second width is approximately 3 micrometers; and / or, The second interval is approximately 5 micrometers.

15. The display module according to any one of claims 1-14, wherein, The display module further includes: a first conductive layer located on one side of the substrate; a first insulating layer located on the side of the first conductive layer away from the substrate; and a second conductive layer located on the side of the first insulating layer away from the substrate. The data line and the data transmission line are located in the first conductive layer; The first pad is located in at least one of the first conductive layer and the second conductive layer; The second pad is located in at least one of the first conductive layer and the second conductive layer; and The third pad is located on the second conductive layer.

16. A display device, characterized in that, Includes the display module as described in any one of claims 1-15.

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