A method for detecting the brightness of a silicon-based OLED display module

Abstract

The application relates to the technical field of display control, and discloses a detection method for the brightness of a silicon-based OLED display module. The method acquires a frame scanning timing signal of a complementary metal oxide semiconductor driving circuit integrated on a silicon substrate, and divides a single display frame into a light-emitting data writing stage, a light-emitting maintaining stage and a non-light-emitting resetting stage according to the timing signal. In the light-emitting maintaining stage, a first integrated electric signal output by a photodetector integrated on the silicon substrate is extracted; in the non-light-emitting resetting stage and when a driving transistor is in a conducting state, a second integrated electric signal output by the photodetector is extracted. The first integrated electric signal and the second integrated electric signal are subjected to differential operation, and the differential operation result is taken as an effective brightness detection value of a corresponding pixel. Through frame timing segmentation and differential operation, the application strips parasitic photoelectric current mixed in the light-emitting signal, and improves the accuracy of the brightness detection result.

Description

Technical Field

[0001] This invention relates to the field of display control technology and discloses a method for detecting the brightness of a silicon-based OLED display module. Background Technology

[0002] In existing technologies, the conventional approach for brightness detection of silicon-based organic electroluminescent display modules involves integrating a photodetector on the silicon substrate. This photodetector receives the light signals emitted by the organic electroluminescent pixels and converts them into electrical signals. During detection, the photodetector remains in an integrated state throughout a single display frame cycle, accumulating the photocurrent generated over the entire frame cycle. After the single display frame cycle ends, the total integrated voltage accumulated by the photodetector is read and input into a pre-calibrated voltage-brightness lookup table to calculate the brightness value of the corresponding pixel. In this conventional approach, a high-density complementary metal-oxide-semiconductor (CMOS) driving circuit is integrated on the silicon substrate. The transistors in these driving circuits switch on and off according to predetermined logic during frame scanning.

[0003] The core problem with the aforementioned existing technical solutions lies in the fact that the continuous full-frame integration method leads to deviations in brightness detection results due to parasitic photocurrent interference. In the actual operation of silicon-based organic electroluminescent display modules, the complementary metal-oxide-semiconductor (CMOS) driving circuit is not completely de-energized during the non-light-emitting reset phase. Its internal transistors generate photogenerated carriers under ambient light, and the transistors themselves have leakage current. Since the photodetector in conventional solutions continuously integrates throughout the entire frame period, the parasitic photocurrent and leakage current generated during the non-light-emitting reset phase are also collected by the photodetector and superimposed on the effective photocurrent during the light-emitting maintenance phase. This aliasing of the effective optical signal and the parasitic electrical signal in the integration time dimension results in the total integrated voltage containing a noise baseline not generated by the emission of this pixel. Directly calculating the brightness value based on this total integrated voltage will deviate from the true luminous brightness of the organic electroluminescent pixel. Summary of the Invention

[0004] The purpose of this invention is to provide a method for detecting the brightness of a silicon-based OLED display module, which can effectively solve the problems mentioned in the background art.

[0005] To achieve the above objectives, the technical solution adopted by the present invention is as follows: A method for detecting the brightness of a silicon-based OLED display module includes: acquiring the frame scan timing signal of a CMOS driving circuit integrated on a silicon substrate in the silicon-based OLED display module under test; Based on the frame scanning timing signal, a single display frame is divided into an OLED light-emitting data writing stage, a light-emitting maintenance stage, and a non-light-emitting reset stage, which are performed sequentially. During the light emission maintenance phase, the photodetector integrated on the silicon substrate is controlled to perform photoelectric conversion, and the first integrated electrical signal output by the photodetector is extracted. During the non-light-emitting reset phase and when the driving transistor in the CMOS driving circuit is in the on state, the photodetector is controlled to perform photoelectric conversion, and the second integrated electrical signal output by the photodetector is extracted, wherein the second integrated electrical signal characterizes the parasitic photoresponse baseline of the silicon substrate under the influence of ambient light and the leakage current of the driving transistor. The first integrated electrical signal and the second integrated electrical signal are subjected to a differential operation, and the result of the differential operation is used as the effective brightness detection value of the corresponding pixel.

[0006] Preferably, the process of dividing a single display frame into an OLED light-emitting data writing stage, a light-emitting maintenance stage, and a non-light-emitting reset stage according to the frame scanning timing signal includes: synchronously acquiring the horizontal scanning driving signal and the data latching signal in the CMOS driving circuit; Edge detection is performed on the row scan drive signal to determine the start and end timestamps of the row scan, and level state parsing is performed on the data latch signal to determine the establishment timestamp of the data voltage; When the data voltage establishment timestamp is detected to be within the interval corresponding to the row scan start and end timestamps, the current time period is defined as the OLED light emission data writing stage; When a transition is detected at the edge of the row scan drive signal and the data latch signal remains locked, the current time period is defined as the light emission maintenance phase. When the row scan drive signal is detected to be reset to the initial level and the data latch signal is unlocked, the current time period is defined as the non-light emission reset phase.

[0007] Preferably, during the light emission sustaining phase, controlling the photodetector integrated on the silicon substrate to perform photoelectric conversion and extracting the first integrated electrical signal output by the photodetector includes: when the light emission sustaining phase is started, controlling the integrating operational amplifier connected to the photodetector to perform a dual-slope integration operation. During the positive integration period, the photocurrent generated by the photodetector during the light emission maintenance phase is positively charged and integrated for a fixed duration. After the positive integration period ends, the system switches to the reverse integration period and inputs a constant reference current to the integrating operational amplifier for reverse discharge until the output voltage of the integrating operational amplifier returns to the initial reference voltage. Record the duration of the reverse integration period, and convert the duration of the reverse integration period into a digital quantity as the first integration electrical signal.

[0008] Preferably, during the non-light-emitting reset phase and when the driving transistor in the CMOS driving circuit is in the on state, controlling the photodetector to perform photoelectric conversion and extracting the second integrated electrical signal output by the photodetector includes: during the non-light-emitting reset phase, cutting off the data voltage input path to the driving transistor, and simultaneously applying a conduction bias voltage with the same amplitude as the light-emitting maintenance phase to the gate of the driving transistor, so that the driving transistor is maintained in the linear region or saturation region on state; During the duration of the applied conduction bias voltage, the photodetector is controlled to synchronously integrate and acquire the leakage current inside the silicon substrate and the ambient light penetrating into the silicon substrate. The integrated voltage value acquired by the synchronous integration is obtained, and the integrated voltage value is quantized into a digital signal as the second integrated electrical signal.

[0009] Preferably, the first integrated electrical signal and the second integrated electrical signal are subjected to a differential operation, and the result of the differential operation is used as the effective brightness detection value of the corresponding pixel, including: calculating the difference between the first integrated electrical signal and the second integrated electrical signal in the current frame, and generating the initial differential value of the current frame; The initial difference values ​​corresponding to multiple consecutive historical frames are extracted to form a time series; The time series is input into a pre-built autoregressive moving average model to calculate the predicted value of the parasitic noise trend for the current frame. Subtract the parasitic noise trend prediction value from the initial difference value of the current frame to generate a corrected difference value after filtering out non-stationary random fluctuation residuals; The corrected difference value is mapped to a predetermined brightness calibration curve, and the effective brightness detection value is output.

[0010] Preferably, the physical structure relationship between the photodetector integrated on the silicon substrate and the CMOS driving circuit satisfies the following: the photodetector is formed inside the P-type well of the silicon substrate, and the driving transistor in the CMOS driving circuit is disposed adjacent to the photodetector. A ring-shaped deep N-well isolation structure is provided between the edge of the photosensitive surface of the photodetector and the active region of the drain of the driving transistor. The bottom of the deep N-well isolation structure extends into the N-type substrate below the P-type well, and the top of the deep N-well isolation structure is connected to a bias voltage lead with a fixed potential. The deep N-well isolation structure surrounds the photosensitive surface of the photodetector, blocking the lateral diffusion of charge carriers from the drain active region of the driving transistor to the photosensitive surface of the photodetector.

[0011] Preferably, edge detection of the row scan drive signal to determine the start and end timestamps of the row scan includes: performing multi-phase clock sampling processing on the row scan drive signal using a delay-locked loop; The delay-locked loop generates multiple sampling clocks with a fixed phase difference based on the delay order of the internal voltage-controlled delay line; The row scan drive signal is triggered in parallel using the multiple sampling clocks to generate a trigger state vector of the row scan drive signal under different phase clocks; The trigger state vector is decoded to determine the target delay level corresponding to the rising and falling edges of the row scan drive signal; Based on the target delay level and the unit delay time of the pressure-controlled delay line, the precise time coordinates of the start and end timestamps of the row scan are calculated.

[0012] Preferably, before controlling the integrating operational amplifier connected to the photodetector to perform dual-slope integration operation when the light emission maintenance phase is started, the method further includes: controlling the integrating operational amplifier to enter an automatic zeroing calibration cycle during the OLED light emission data writing phase. During the automatic zeroing calibration cycle, the calibration switch connected between the inverting input terminal and the output terminal of the integrating operational amplifier is closed, and the non-inverting input terminal of the integrating operational amplifier is grounded. The input offset voltage of the integrating operational amplifier in closed-loop state is stored in an external calibration capacitor; When entering the dual-slope integration operation, the calibration switch is disconnected, and the calibration capacitor is connected in series in the inverting input circuit of the integrating operational amplifier to cancel the input offset voltage of the integrating operational amplifier.

[0013] Preferably, applying a conduction bias voltage to the gate of the driving transistor with the same amplitude as the light emission sustaining phase includes: acquiring the real-time ambient temperature value of the silicon substrate at the current detection time and the maximum driving current value of the current pixel column in the previous frame display cycle; In a pre-stored bias voltage compensation lookup table, the target bias voltage compensation amount is obtained by querying the real-time ambient temperature value and the maximum drive current value as index variables. The initial bias voltage applied to the gate of the driving transistor during the light-emitting maintenance phase is superimposed with the target bias voltage compensation amount to generate a dynamic on-bias voltage. During the non-light-emitting reset phase, the dynamic on-bias voltage is applied to the gate of the driving transistor.

[0014] Preferably, the top of the deep N-well isolation structure is connected to a bias voltage lead with a fixed potential, including: the bias voltage lead is connected to an external regulated power supply through a passive low-pass filter network, and the cutoff frequency of the passive low-pass filter network is set according to the substrate coupling noise frequency band of the silicon substrate; At the junction of the bottom and side surfaces of the deep N-well isolation structure, a P-type protective injection band is provided around the deep N-well isolation structure; The P-type protection implantation band is doped on the surface of the P-type well, and the P-type protection implantation band is directly connected to the substrate ground potential of the silicon substrate. The deep N-well isolation structure and the P-type protection injection band constitute a three-dimensional shielding structure with longitudinal PN junction isolation and lateral electric field shielding.

[0015] Compared with the prior art, the beneficial effects of the present invention are as follows: 1. This invention divides a single display frame into a writing phase, a light-emitting sustaining phase, and a non-light-emitting reset phase based on the frame scanning timing signal of the complementary metal-oxide-semiconductor (CMOS) driving circuit. A first integrated electrical signal is extracted during the light-emitting sustaining phase, and a second integrated electrical signal is extracted during the non-light-emitting reset phase when the driving transistor is in the on state. The two signals are then differentially analyzed to obtain the effective brightness detection value. This scheme utilizes frame timing segmentation to limit the integration acquisition process of the photodetector within a specific time window, ensuring that the second integrated electrical signal accurately reflects the parasitic light response baseline of the silicon substrate in the non-light-emitting state, generated by ambient light and leakage current. The differential operation removes the parasitic photocurrent aliased in the light-emitting signal, solving the problem of aliasing between the effective light signal and the parasitic electrical signal in the integration time dimension, ensuring that the converted brightness value conforms to the true light-emitting state of organic electroluminescent pixels.

[0016] 2. By performing edge detection and potential analysis on the line scan drive signal and data latch signal, the frame timing interval is delineated, clarifying the boundaries of each stage and avoiding cross-stage signal crosstalk caused by timing ambiguity. A dual-slope integration operation is used to extract the first integral electrical signal, combined with an automatic zero-adjustment calibration cycle to eliminate the input offset voltage of the operational amplifier, reducing the hardware error of the integration circuit itself. During the non-light-emitting reset phase, the driving transistor is maintained in the on-state, and the on-bias voltage is dynamically adjusted based on ambient temperature and historical drive current, making the extraction environment of the second integral electrical signal approach that of the light-emitting maintenance phase, improving the consistency of parasitic baseline extraction. A three-dimensional shielding structure is constructed inside the silicon substrate, with a deep well isolation structure connected to a fixed potential and a hole-type protective injection band, blocking the lateral diffusion of charge carriers from the drain of adjacent driving transistors to the photodetector's photosensitive surface, suppressing physical crosstalk in the internal spatial dimensions of the silicon substrate. Attached Figure Description

[0017] Figure 1This is the main flowchart of the brightness detection method for silicon-based organic electroluminescent display modules of the present invention; Figure 2 This is a flowchart illustrating the frame scanning timing signal stage division of the present invention. Figure 3 This is a flowchart of the first integral electrical signal extraction process during the luminescence maintenance stage of the present invention. Figure 4 This is a flowchart of the second integral electrical signal extraction process during the non-light-emitting reset stage of the present invention; Figure 5 This is a flowchart of the differential operation and brightness mapping process of the present invention; Figure 6 This is a flowchart illustrating the operational control of the deep well isolation structure of the present invention. Detailed Implementation

[0018] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0019] Please refer to Figure 1 and Figure 2 This embodiment provides a method for detecting the brightness of a silicon-based OLED display module. The silicon-based OLED display module under test includes a silicon substrate, a CMOS driving circuit integrated inside the silicon substrate, an OLED light-emitting pixel array formed on the surface of the silicon substrate, and a photodetector integrated inside the silicon substrate and corresponding to the OLED light-emitting pixel array. The silicon substrate is an N-type heavily doped substrate with a P-type epitaxial layer formed on top. Multiple independent P-type well regions are formed within the P-type epitaxial layer. The driving transistors of the CMOS driving circuit and the photodetectors are formed within their respective P-type well regions. Each pixel unit in the OLED light-emitting pixel array includes an anode, an organic light-emitting layer, and a cathode. The anode is an ITO transparent conductive layer formed on the surface of the silicon substrate and electrically connected to the drain of the corresponding driving transistor via a metal interconnect. The organic light-emitting layer is formed on the anode surface using a vapor deposition process. The cathode is a metal cathode layer covering the organic light-emitting layer and connected to the common cathode potential of the module. The source of the driving transistor is connected to the power supply voltage terminal of the module, and the gate of the driving transistor is connected to the row scan driving line of the CMOS driving circuit and the output terminal of the data latch unit. The photosensitive surface of the photodetector is aligned vertically with the anode of the OLED light-emitting pixel, and the light-receiving area of ​​the photosensitive surface is matched with the light-emitting area of ​​the pixel unit.

[0020] Specifically, when acquiring the frame scan timing signal of the CMOS driving circuit integrated on the silicon substrate in the silicon-based OLED display module under test, a microprobe array set on the probe stage forms an ohmic contact with the timing test pads reserved at the edge of the silicon substrate. The timing test pads are directly electrically connected to the output terminal of the timing control unit inside the CMOS driving circuit through the top-layer metal interconnect. The impedance of the metal interconnect is less than 50Ω to ensure the complete transmission of the timing signal without distortion. The microprobe array synchronously acquires the frame synchronization signal, the row scan drive signal, and the data latch signal output by the timing control unit. The acquired signals together constitute the frame scan timing signal. Among them, the rising edge of the frame synchronization signal pulse corresponds to the start time of a single display frame, and the pulse period of the frame synchronization signal is equal to the complete duration of a single display frame. The row scan drive signal is a rectangular pulse signal that shifts row by row. The effective pulse of each row scan drive signal corresponds to the driving timing window of a row of pixel units. The data latch signal is a level signal synchronized with the row scan drive signal, and the effective level of the data latch signal corresponds to the latching period of the column data voltage. The frame scanning timing signal acquired by the micro probe array is processed by a passive low-pass filter network with a bandwidth of 100MHz and then input to the timing analysis unit. The filter network is used to filter out high-frequency electromagnetic interference signals coupled during the acquisition process to ensure the edge integrity of the timing signal.

[0021] Furthermore, based on the frame scan timing signal, a single display frame is divided into three sequentially occurring stages: OLED luminous data writing, luminous sustaining, and non-luminous reset. In this embodiment, the rising edge of the frame synchronization signal is taken as the zero point of a single display frame, and the synchronization timing of the line scan drive signal and the data latch signal is analyzed. Specifically, edge detection is performed on the line scan drive signal to identify the rising and falling edges. The rising edge is recorded as the line scan start timestamp, and the falling edge is recorded as the line scan end timestamp. The interval between the line scan start timestamp and the line scan end timestamp is the effective line scan interval. The level state of the data latch signal is analyzed to identify the moment when the data latch signal transitions from low to high level, which is recorded as the data voltage establishment timestamp. The moment when the data latch signal transitions from high to low level is recorded as the data voltage latch completion timestamp. When both the data voltage establishment timestamp and the data voltage latch completion timestamp are within the effective line scan interval, this period is defined as the OLED luminous data writing stage. During the OLED light-emitting data writing phase, the CMOS driving circuit latches the grayscale data voltage on the column data lines to the gate of the driving transistor of the corresponding pixel unit, completing the pixel light-emitting data writing operation. When the falling edge transition of the row scan driving signal is detected and the data latch signal remains in a high-level locked state, the current period is defined as the light-emitting sustain phase. During the light-emitting sustain phase, the gate potential of the driving transistor maintains the latched grayscale data voltage, the driving transistor is in the on state, and a constant driving current flows through the OLED light-emitting pixel, keeping the OLED light-emitting pixel in a stable light-emitting state. When the next rising edge of the frame synchronization signal is detected, the row scan driving signal is reset to the initial low level, and the data latch signal transitions from high level to low level and is unlocked, the current period is defined as the non-light-emitting reset phase. During the non-light-emitting reset phase, the driving current of the OLED light-emitting pixel is cut off, the pixel unit stops emitting light, and the driving transistor and data latch unit of the CMOS driving circuit enter the reset state, preparing for the writing operation of the next display frame.

[0022] In this embodiment, the timing parameters for each stage of a single display frame are shown in Table 1. Table 1 clearly defines the triggering conditions, duration, and working states of the corresponding circuits and pixels for each stage, providing a clear timing reference for the division of frame timing and the control of the integral acquisition window.

[0023] Table 1 Timing definition parameters for each stage of a single display frame In Table 1, the duration setting range is based on the conventional refresh rate setting of silicon-based OLED display modules, with a refresh rate range of 60Hz. 120Hz, the total duration of a single display frame is 8.33ms. 16.67ms. The duration of the OLED light-emitting data writing phase is related to the resolution of the display module. The higher the resolution, the longer the time required to write a single line of data. The duration of the light-emitting sustain phase is the main light-emitting period of the pixel, accounting for more than 90% of the total duration of a single display frame. The duration of the non-light-emitting reset phase needs to meet the dual requirements of driving transistor reset and parasitic baseline integration acquisition, ensuring that the acquisition duration of the second integral electrical signal is consistent with the integration duration of the light-emitting sustain phase, so as to improve the cancellation effect of differential operation.

[0024] Furthermore, during the light-emitting sustaining stage, the photodetector integrated on the silicon substrate is controlled to perform photoelectric conversion, and the first integrated electrical signal output by the photodetector is extracted. In this embodiment, the photodetector adopts a PN junction photodiode structure. The P-type active region of the photodiode is formed inside the P-type well, and the N-type active region is formed on the surface of the P-type active region. The photosensitive surface of the PN junction faces the light-emitting direction of the OLED light-emitting pixel array, and can receive the light signal emitted by the corresponding pixel unit and convert it into photocurrent. The output terminal of the photodetector is connected to an integration operation circuit, which includes an integration operation amplifier, an integration capacitor, and a reset switch. The inverting input terminal of the integration operation amplifier is electrically connected to the output terminal of the photodetector, and the non-inverting input terminal is connected to a reference voltage source. The integration capacitor and the reset switch are connected in parallel between the inverting input terminal and the output terminal of the integration operation amplifier. The integration operation amplifier adopts a rail-to-rail input / output structure, with an open-loop gain greater than 100dB and a unity-gain bandwidth greater than 10MHz. The integration capacitor adopts a metal-insulator-metal capacitor structure with a capacitance range of 1pF. The capacitor has a capacitance of 10pF and a capacitance deviation of less than ±5%. The reset switch uses a CMOS transmission gate structure with an on-resistance of less than 100Ω and a turn-off leakage current of less than 1pA. At the beginning of the light-up sustaining phase, the reset switch is opened, and the integrating circuit enters the integrating state. The photocurrent generated by the photodetector during the light-up sustaining phase flows into the inverting input of the integrating operational amplifier, charging the integrating capacitor. The output voltage of the integrating operational amplifier changes linearly with the increase of the charging charge. At the end of the light-up sustaining phase, the reset switch remains open, and the output voltage value of the integrating operational amplifier is read. This output voltage value is converted into a digital quantity by an analog-to-digital converter (ADC), which is the first integrated electrical signal. The ADC uses a successive approximation structure with a conversion bit depth of 12-16 bits and a conversion rate of 1MSPS-10MSPS, which can meet the synchronous conversion requirements of multi-pixel integrated electrical signals within a single frame. The amplitude of the first integrated electrical signal is positively correlated with the total luminous flux received by the photodetector during the light emission maintenance phase. The total luminous flux includes the effective light signal emitted by the corresponding OLED light-emitting pixel, the light signal generated by ambient light penetrating the silicon substrate, and the luminous flux corresponding to the parasitic light signal generated by the leakage current of the driving transistor.

[0025] Furthermore, during the non-light-emitting reset phase and when the driving transistor in the CMOS driving circuit is in the on state, the photodetector is controlled to perform photoelectric conversion, and the second integrated electrical signal output by the photodetector is extracted. This second integrated electrical signal characterizes the parasitic photoresponse baseline of the silicon substrate under the influence of ambient light and the leakage current of the driving transistor. In this embodiment, after entering the non-light-emitting reset phase, the power supply voltage path input to the source of the driving transistor is cut off. Simultaneously, a DC bias voltage with the same amplitude as the grayscale data voltage latched during the light-emitting sustain phase is applied to the gate of the driving transistor, causing the driving transistor to maintain the same on state as during the light-emitting sustain phase. During the duration of the driving transistor maintaining the on state, the reset switch of the integration operation circuit is kept off, and the integration operation circuit enters an integration working state with the same duration as the light-emitting sustain phase. At this time, the OLED light-emitting pixels have no driving current input and are in a completely non-light-emitting state. The light signal received by the photodetector only includes the light signal generated by ambient light penetrating the silicon substrate and the parasitic light signal generated inside the silicon substrate by the leakage current of the driving transistor. The photocurrent generated by the photodetector is entirely parasitic photocurrent, which flows into the integration operation circuit to charge the integration capacitor. After the integration time is completed, the output voltage value of the integrating operational amplifier is read, and the output voltage value is converted into a digital quantity through an analog-to-digital converter. This digital quantity is the second integrating electrical signal.

[0026] Furthermore, a differential operation is performed between the first integrated electrical signal and the second integrated electrical signal, and the result of the differential operation is used as the effective brightness detection value of the corresponding pixel. In this embodiment, the differential operation is implemented by a digital signal processing unit, which adopts a field-programmable gate array or an application-specific integrated circuit (ASIC) structure. Its input terminal is electrically connected to the output terminal of the analog-to-digital converter (ADC), and it receives the digital quantities corresponding to the first and second integrated electrical signals. Specifically, the digital quantity of the first integrated electrical signal is denoted as... The digital quantity of the second integral electrical signal is denoted as The effective brightness detection value S is calculated through differential operation, and the corresponding calculation formula is: Where S is the effective brightness detection value of the corresponding pixel. This is the digital quantity corresponding to the first integral electrical signal. This is the digital quantity corresponding to the second integral electrical signal. During this differential operation, the parasitic signal components generated by ambient light and leakage current of the driving transistor in the first integral electrical signal have the same amplitude as the parasitic signal components in the second integral electrical signal. They can be completely canceled out through differential operation. The final effective brightness detection value is only related to the photocurrent corresponding to the effective light signal emitted by the OLED light-emitting pixel during the light-emitting maintenance phase.

[0027] In this embodiment, by acquiring and parsing the frame scanning timing signal, a single display frame is divided into three sequential stages. In each corresponding stage, an integrated electrical signal containing the effective light emission signal and the parasitic baseline signal is acquired. The parasitic signal component is stripped off by differential operation to obtain the detection value of the effective light emission brightness of the corresponding pixel. This eliminates the aliasing of the effective light signal and the parasitic electrical signal in the integration time dimension, so that the brightness detection result matches the actual light emission state of the pixel.

[0028] In an alternative embodiment, refer to Figure 6 The physical structure of the photodetector and CMOS driving circuit integrated on the silicon substrate employs an isolation and shielding design to block the lateral diffusion of charge carriers within the silicon substrate and suppress physical crosstalk in the spatial dimension. Specifically, the silicon substrate is an N-type heavily doped substrate, on which a 2μm thick layer is grown. A 5μm P-type epitaxial layer is formed, within which multiple isolated P-type well regions are created using ion implantation. The photodetector is formed within a separate first P-type well. The driving transistor in the CMOS driving circuit is formed within a second P-type well adjacent to the first P-type well. The driving transistor is positioned close to the photodetector, and the horizontal distance between the drain active region of the driving transistor and the edge of the photosensitive surface of the photodetector is 0.5μm. 2μm.

[0029] Furthermore, a ring-shaped deep N-well isolation structure is disposed between the edge of the photosensitive surface of the photodetector and the active region of the drain of the driving transistor. The deep N-well isolation structure is formed using a high-energy ion implantation process with an implantation energy range of 1.5 MeV. 3MeV, injection dose range of 1E12cm -2 1E14cm -2 The deep N-well isolation structure has a depth greater than that of the first and second P-type wells. The bottom of the deep N-well isolation structure extends into the N-type substrate below the P-type wells, forming an ohmic contact with the N-type substrate. The deep N-well isolation structure is a closed rectangular ring structure, with the dimensions of the rectangle matching the dimensions of the photosensitive surface of the photodetector. The distance between the inner edge of the rectangular ring and the edge of the photosensitive surface of the photodetector is 0.2 μm. The outer edge of the rectangular ring is 0.5 μm, and the distance between it and the active region of the drain of the driving transistor is 0.3 μm. The 1μm diameter completely surrounds the sidewalls and bottom edge of the first P-type well where the photodetector is located, blocking the path of lateral carrier diffusion from the drain active region of the driving transistor to the photosensitive surface of the photodetector.

[0030] Furthermore, a fixed-potential bias voltage lead is connected to the top of the deep N-well isolation structure. This bias voltage lead is connected to an external regulated power supply via a top-layer metal interconnect. The bias voltage amplitude output by the external regulated power supply is the same as the potential of the N-type substrate. A passive low-pass filter network is connected between the bias voltage lead and the external regulated power supply. This passive low-pass filter network uses an RC filter structure, including a series filter resistor and a parallel filter capacitor. One end of the filter resistor is connected to the output terminal of the external regulated power supply, and the other end is connected to the bias voltage lead. One end of the filter capacitor is connected to the junction of the filter resistor and the bias voltage lead, and the other end is connected to the substrate ground potential of the silicon substrate. The resistance value of the filter resistor is in the range of 1kΩ. 10kΩ, the capacitance range of the filter capacitor is 10pF. The cutoff frequency of the 100pF passive low-pass filter network is set based on the substrate coupling noise bandwidth of the silicon substrate, and is set to 10kHz. 100kHz is used to filter out high-frequency noise signals coupled to the substrate, so as to keep the potential of the deep N-well isolation structure stable.

[0031] Furthermore, a P-type protective implantation band is formed at the junction of the bottom and side surfaces of the deep N-well isolation structure, surrounding the structure. This P-type protective implantation band is formed using a boron ion implantation process, doped into the surface layer of the first P-type well, with an implantation depth of 0.1 μm. The doping concentration of the 0.3 μm P-type protection implantation band is higher than that of the first P-type well, with a doping concentration range of 1E17 cm⁻¹. -3 1E19cm -3 The P-type protection injection band is directly connected to the substrate ground potential of the silicon substrate through metal contact holes, maintaining a constant ground potential. The number of metal contact holes is uniformly distributed along the perimeter of the deep N-well isolation structure, with the spacing between adjacent contact holes less than 5 μm, ensuring a consistent potential throughout the entire P-type protection injection band. The deep N-well isolation structure and the P-type protection injection band form a three-dimensional shielding structure with longitudinal PN junction isolation and lateral electric field shielding. A reverse-biased PN junction is formed between the deep N-well isolation structure and the P-type protection injection band. The depletion layer covers the sidewall region of the deep N-well isolation structure, preventing carriers injected from the drain active region from diffusing into the active region of the photodetector. The deep N-well isolation structure forms an equipotential structure with the underlying N-type substrate, shielding the longitudinal electric field interference inside the substrate and preventing carriers in the substrate from being collected by the PN junction of the photodetector.

[0032] In this embodiment, the process parameters of the deep N-well isolation structure and the three-dimensional shielding structure are shown in Table 2. Table 2 clarifies the setting range and core function of each process parameter, providing a clear design benchmark for the process implementation of the isolation and shielding structure.

[0033] Table 2. Process parameters for deep N-well isolation structure and three-dimensional shielding structure. In Table 2, the setting range of each process parameter is determined based on the standard CMOS process node of silicon-based OLED display modules, and is compatible with 0.18μm. A 0.35μm CMOS process platform. Matching settings for deep N-well implantation energy and dose ensure the formation of continuous longitudinal isolation walls in the deep N-well isolation structure, preventing isolation failure due to insufficient implantation depth. The cutoff frequency of the passive low-pass filter network is set to match the main frequency band of substrate noise generated by the switching action of the CMOS driver circuit, effectively filtering out substrate coupling noise. The parameter settings for the P-type protection implantation band ensure that the depletion layer of the reverse-biased PN junction formed between it and the deep N-well isolation structure completely covers the sidewall region of the deep N-well, achieving complete blocking of lateral carrier diffusion.

[0034] Furthermore, when a single display frame is divided into the OLED light-emitting data writing stage, the light-emitting maintenance stage, and the non-light-emitting reset stage according to the frame scanning timing signal, the horizontal scanning drive signal and the data latch signal in the CMOS driving circuit are simultaneously acquired. The edge detection of the horizontal scanning drive signal is performed to determine the start and end timestamps of the horizontal scanning, and the level state analysis of the data latch signal is performed to determine the establishment timestamp of the data voltage.

[0035] Specifically, when performing edge detection on the horizontal scan drive signal, a delay-locked loop (LDL) is used to perform multi-phase clock sampling processing on the horizontal scan drive signal. The LLL includes a reference clock input, a voltage-controlled delay line, a phase detector, and a loop filter. The reference clock input is connected to the module's system clock, and the system clock frequency range is 100MHz. The frequency is 500MHz with a 50% duty cycle and a frequency stability of less than ±100ppm. The voltage-controlled delay line (VCD) consists of multiple series-connected delay units. The output of each delay unit corresponds to a sampling clock of one phase. The phase difference between adjacent sampling clocks is fixed. The delay units adopt a differential delay structure with a power supply rejection ratio (PSRR) greater than 60dB, which can suppress the influence of power supply voltage fluctuations on the delay time. The delay-locked loop (LLL) generates multiple sampling clocks with fixed phase differences based on the delay stages of the internal VCD. The number of sampling clocks is equal to the number of delay units in the VCD, ranging from 8 to 32. The unit delay time between adjacent sampling clocks is 1 / N of the system clock cycle, where N is the number of sampling clocks. The locking process of the LLL is as follows: the phase detector compares the phase difference between the reference clock and the last sampling clock output by the VCD, outputting a phase error signal. After being filtered by the loop filter, the phase error signal is input to the control terminal of the VCD, adjusting the unit delay time of the VCD so that the total delay time of the VCD is equal to one cycle of the reference clock, thus achieving the locking of the LLL. Once locked, the phase difference between adjacent sampling clocks is fixed at 360° / N, ensuring the accuracy of multi-phase sampling.

[0036] Furthermore, multiple sampling clocks are used to trigger the row scan drive signal in parallel. The rising edge of each sampling clock sample the level of the row scan drive signal, generating sampling results for the row scan drive signal under different phase clocks. All sampling results are arranged in phase order to form a trigger state vector. The trigger state vector is a binary vector, with each bit corresponding to the sampling result of one sampling clock. A high level corresponds to a 1 bit, and a low level corresponds to a 0 bit. The holding time of the sampling result is one system clock cycle to ensure stable reading by the subsequent decoding circuit.

[0037] Furthermore, the trigger state vector is decoded to determine the target delay levels corresponding to the rising and falling edges of the row scan drive signal. Specifically, when a series of transitions from 0 to 1 occur in the trigger state vector, the rising edge of the row scan drive signal corresponding to this transition is identified, and the delay unit number corresponding to the transition position is the target delay level corresponding to the rising edge; when a series of transitions from 1 to 0 occur in the trigger state vector, the falling edge of the row scan drive signal corresponding to this transition is identified, and the delay unit number corresponding to the transition position is the target delay level corresponding to the falling edge. The decoding operation is implemented through combinational logic circuits, with a decoding delay of less than one system clock cycle, enabling real-time output of the target delay level.

[0038] Furthermore, based on the target delay level and the unit delay time of the pressure-controlled delay line, the precise time coordinates of the start and end timestamps of the row scan are calculated. The corresponding calculation formula is: in, This is the start timestamp of the row scan. For the end timestamp of the row scan, The starting time of the reference clock cycle corresponding to the trigger state vector, where n is the target delay level corresponding to the rising edge and m is the target delay level corresponding to the falling edge. This represents the unit delay time of the voltage-controlled delay line.

[0039] Furthermore, when analyzing the level state of the data latch signal, the same multi-phase clock sampling processing method as the row scan drive signal is used to determine the data voltage establishment timestamp and latch completion timestamp. When the data voltage establishment timestamp is detected to be within the interval corresponding to the row scan start and end timestamps, the current period is defined as the OLED light-emitting data writing stage; when the edge of the row scan drive signal is detected to transition and the data latch signal remains locked, the current period is defined as the light-emitting sustaining stage; when the row scan drive signal is detected to reset to the initial level and the data latch signal is unlocked, the current period is defined as the non-light-emitting reset stage. During the determination of the data voltage establishment timestamp, when the data latch signal level transitions from low to high and remains high for a period exceeding the preset establishment and sustaining time, this transition moment is determined as the data voltage establishment timestamp. The preset establishment and sustaining time is 10ns. 50ns, to ensure that the voltage on the column data lines has been stably established.

[0040] In this embodiment, a three-dimensional shielding structure composed of a deep N-well isolation structure and a P-type protection injection band is used to block the lateral diffusion of charge carriers from the active region of the driving transistor drain to the photodetector, thereby suppressing physical crosstalk in the internal spatial dimension of the silicon substrate. Through multi-phase clock sampling processing of the delay-locked loop, high-precision detection of the edge of the row scanning driving signal is achieved, improving the accuracy of frame timing stage division and avoiding cross-stage signal crosstalk caused by timing ambiguity.

[0041] In another alternative embodiment, refer to Figures 3 to 5During the light-emitting sustaining phase, a photodetector integrated on a silicon substrate is controlled to perform photoelectric conversion. When extracting the first integrated electrical signal output by the photodetector, a dual-slope integration operation is employed to achieve high-precision integration and acquisition of the photogenerated current. Specifically, the integration circuit connected to the output of the photodetector adopts a dual-slope integration structure, including an integrating operational amplifier, an integrating capacitor, a reset switch, a reference current source, a switching switch, and an automatic zero-adjustment calibration unit. The inverting input of the integrating operational amplifier can be selectively connected to either the output of the photodetector or the output of the reference current source via the switching switch. The non-inverting input is connected to the initial reference voltage, which is the common-mode input voltage of the analog-to-digital converter with an amplitude range of 0.5V. 1.5V, with a temperature drift coefficient less than 10ppm / ℃. The integrating capacitor is connected between the inverting input and output of the integrating operational amplifier. The reset switch is connected in parallel with the integrating capacitor. The reference current source is a constant current source using a bandgap reference structure. The output current's temperature drift coefficient is less than 50ppm / ℃, and the output current amplitude can be configured via a register. The direction of the output current is opposite to the photocurrent of the photodetector. The switching switch uses a single-pole double-throw CMOS transmission gate structure. The on-resistance matching degree of the two input channels is less than ±5%, and the switching time is less than 10ns, ensuring seamless switching between forward and reverse integration.

[0042] Furthermore, during the luminescence sustaining phase, the integrating operational amplifier connected to the photodetector is controlled to perform a dual-slope integration operation. Before performing the dual-slope integration operation, during the OLED luminescence data writing phase, the integrating operational amplifier is controlled to enter an automatic zero-calibration cycle. During the automatic zero-calibration cycle, the calibration switch connected between the inverting input and output of the integrating operational amplifier is closed. The calibration switch is the core switching element of the automatic zero-calibration unit. After the calibration switch is closed, the inverting input and output of the integrating operational amplifier are shorted, forming a unity-gain negative feedback closed-loop structure. Simultaneously, the non-inverting input of the integrating operational amplifier is grounded. At this time, the input offset voltage of the integrating operational amplifier in the closed-loop state is stored in an external calibration capacitor with a capacitance range of 1pF. The 10pF calibration capacitor, employing a metal-insulator-metal capacitor structure, is formed on the top metal layer of a silicon substrate. It features low parasitic capacitance and high capacitance accuracy. One end of the calibration capacitor is connected to the inverting input of the integrating operational amplifier, and the other end is connected to the common terminal of the switching switch. The duration of the automatic zero-adjustment calibration cycle is equal to the duration of the OLED light-emitting data writing phase, ensuring that the offset calibration of the integrating operational amplifier is completed simultaneously with pixel data writing, without occupying additional frame timing time or affecting the normal refresh of the display module. When entering dual-slope integration operation, the calibration switch is disconnected, and the calibration capacitor is connected in series in the inverting input circuit of the integrating operational amplifier. The offset voltage stored on the calibration capacitor has the same amplitude and opposite direction to the input offset voltage of the integrating operational amplifier, completely canceling the input offset voltage of the integrating operational amplifier and eliminating the influence of the offset voltage on the integration result.

[0043] Furthermore, the dual-slope integration operation is divided into a forward integration period and a reverse integration period. During the forward integration period, the control switch connects the inverting input of the integrating operational amplifier to the output of the photodetector, while the reset switch remains open. The photocurrent generated by the photodetector during the light-up sustaining phase is then integrated with a fixed-duration forward charge. The duration of the forward integration period is equal to the duration of the light-up sustaining phase. During this period, the photocurrent generated by the photodetector continuously flows into the integrating capacitor, and the output voltage of the integrating operational amplifier changes linearly with the increase of the integrated charge. At the end of the forward integration period, the output voltage of the integrating operational amplifier reaches its peak voltage. The formula corresponding to the voltage change during the forward integration process is: in, This represents the peak output voltage of the integrating operational amplifier at the end of the positive integration period. The initial reference voltage, This is the capacitance value of the integrating capacitor. The fixed duration of the positive integration period, This refers to the photocurrent generated by the photodetector.

[0044] Furthermore, after the forward integration period ends, the system switches to the reverse integration period. A control switch connects the inverting input of the integrating operational amplifier to the output of the reference current source, inputting a constant reference current to the integrating operational amplifier for reverse discharge until the output voltage of the integrating operational amplifier returns to the initial reference voltage. During the reverse integration period, the constant reference current output by the reference current source discharges the integrating capacitor in reverse, causing the output voltage of the integrating operational amplifier to linearly return from the peak voltage to the initial reference voltage. When the output voltage of the integrating operational amplifier equals the initial reference voltage, a stop signal is triggered by a voltage comparator, terminating the reverse integration process. The voltage comparator employs a high-speed comparator structure with a propagation delay of less than 10ns and an input offset voltage of less than 1mV, enabling precise detection of the moment when the output voltage equals the initial reference voltage. The duration of the reverse integration period is recorded and converted into a digital value by a high-speed counter; this digital value is the first integration electrical signal. The high-speed counter's clock frequency is 100MHz. At 1 GHz, with a counting bit depth of 16 to 24 bits, it can convert the duration of the reverse integration period into a high-precision digital value. The resolution of the counting result is positively correlated with the frequency of the counting clock. The formula for calculating the duration of the reverse integration process is as follows: in, The duration of the reverse integration period. The amplitude of the constant reference current output by the reference current source is given, and the meanings of the other parameters are consistent with the aforementioned formula. It can be seen from the formula that the duration of the reverse integration period is positively correlated with the total photogenerated charge generated by the photodetector during the forward integration period, and is independent of the capacitance value of the integrating capacitor. This eliminates the influence of the capacitance deviation on the integration result and improves the acquisition accuracy of the first integrated electrical signal.

[0045] Furthermore, during the non-light-emitting reset phase and when the driving transistor in the CMOS driving circuit is in the on state, the photodetector is controlled to perform photoelectric conversion, and the second integrated electrical signal output by the photodetector is extracted. Specifically, during the non-light-emitting reset phase, the data voltage input path to the driving transistor is cut off, and simultaneously, a conduction bias voltage with the same amplitude as that in the light-emitting sustain phase is applied to the gate of the driving transistor, so that the driving transistor is maintained in the linear region or saturation region conduction state. During the duration of the applied conduction bias voltage, the photodetector is controlled to synchronously integrate and acquire the leakage current inside the silicon substrate and the ambient light penetrating into the silicon substrate. The integration time of the synchronous integration acquisition is equal to the forward integration time of the light-emitting sustain phase, and the integrated voltage value of the synchronous integration acquisition is obtained. The integrated voltage value is quantized into a digital signal as the second integrated electrical signal.

[0046] Furthermore, when a conduction bias voltage with the same amplitude as the light-emitting sustaining phase is applied to the gate of the driving transistor, the amplitude of the conduction bias voltage is adjusted using dynamic compensation. Specifically, a temperature sensor integrated inside the silicon substrate is used to acquire the real-time ambient temperature value of the silicon substrate at the current detection moment. The temperature sensor employs a bandgap temperature sensor structure with a temperature measurement range of -40℃. With a temperature measurement accuracy of ±1℃ and a sampling rate of 1kSPS, it can track the temperature change of the silicon substrate in real time. Simultaneously, it reads the maximum drive current value of the current pixel column in the previous frame display cycle. The maximum drive current value is obtained by decoding the grayscale data voltage on the column data line. The correspondence between the grayscale data voltage and the drive current value is pre-stored in a register, and the storage depth of the register matches the number of grayscale levels.

[0047] Furthermore, in a pre-stored bias voltage compensation lookup table, the target bias voltage compensation amount is retrieved using the real-time ambient temperature and maximum drive current as index variables. The bias voltage compensation lookup table is pre-generated through calibration experiments. During these experiments, the changes in the on-resistance and leakage current of the driving transistor are measured under different ambient temperatures and drive currents. Based on these changes, the corresponding bias voltage compensation amount is calculated, ensuring that the driving transistor maintains the same conduction state as during the light-emitting sustaining phase under different ambient temperatures and historical drive currents. The initial bias voltage applied to the gate of the driving transistor during the light-emitting sustaining phase is superimposed with the target bias voltage compensation amount to generate a dynamic conduction bias voltage. During the non-light-emitting reset phase, this dynamic conduction bias voltage is applied to the gate of the driving transistor. The corresponding calculation formula is: in, This is the dynamic on-bias voltage. The initial bias voltage applied during the light emission maintenance phase. This is the target bias voltage compensation amount. This is the real-time ambient temperature value. This is the maximum drive current value of the current pixel column in the previous frame display cycle.

[0048] In this embodiment, the correspondence between the index of the bias voltage compensation lookup table and the compensation amount is shown in Table 3. Table 3 clarifies the target bias voltage compensation amount under different ambient temperatures and historical drive current conditions, providing a clear numerical benchmark for the dynamic adjustment of the conduction bias voltage.

[0049] Table 3. Correspondence between the index and compensation amount of the bias voltage compensation lookup table. Table 3 uses a 25°C ambient temperature and a 10μA driving current as the baseline conditions, with a target bias voltage compensation of 0mV. When the ambient temperature is below room temperature, the carrier mobility of the driving transistor increases and the on-resistance decreases, requiring a positive bias voltage compensation to maintain the driving transistor's conduction state consistent with the light emission sustaining phase. When the ambient temperature is above room temperature, the carrier mobility of the driving transistor decreases and the on-resistance increases, requiring a negative bias voltage compensation. Simultaneously, the larger the maximum driving current of the previous frame, the more pronounced the self-heating effect of the driving transistor, necessitating corresponding compensation adjustments to ensure that the leakage current level of the driving transistor in the non-light emission reset phase is consistent with the leakage current level in the light emission sustaining phase, enabling the second integrated electrical signal to accurately characterize the parasitic light response baseline.

[0050] Furthermore, a differential operation is performed between the first and second integrated electrical signals, and the result is used as the effective brightness detection value for the corresponding pixel. Specifically, the difference between the first and second integrated electrical signals of the current frame is calculated to generate the initial differential value for the current frame. The initial differential values ​​corresponding to multiple consecutive historical frames are extracted to form a time series. The number of historical frames ranges from 5 to 20 frames. The time series is arranged chronologically and stored in the internal memory of the digital signal processing unit. The memory uses a first-in-first-out (FIFO) structure to update the time series data in real time. The time series is then input into a pre-constructed autoregressive moving average model to calculate the predicted parasitic noise trend value for the current frame.

[0051] Specifically, the autoregressive moving average model adopts The model is defined as follows: p is the autoregressive order, q is the moving average order, and p ranges from 2. 5. The range of values ​​for q is 1. 3. The expression for the autoregressive moving average model is: in, Here is the predicted parasitic noise trend value for the current frame, where c is a constant term. These are the autoregressive coefficients. For the first The initial difference value of the frame, The moving average coefficient, For the first The residual term of the frame, This represents the residual term for the current frame. The autoregressive coefficients and moving average coefficients are pre-trained using historically acquired parasitic noise time series. During training, the initial difference values ​​of the display module in a fully black display state for more than 1000 consecutive frames are collected to form the training dataset. In the fully black display state, the OLED emitting pixels have no driving current input, and the initial difference values ​​only contain parasitic noise components. Based on the training dataset, the least squares method is used to fit and obtain the autoregressive coefficients and moving average coefficients. After fitting, the coefficients are stored in the internal register of the digital signal processing unit for use during real-time detection.

[0052] Furthermore, the predicted parasitic noise trend is subtracted from the initial difference value of the current frame to generate a corrected difference value after filtering out non-stationary random fluctuation residuals. This corrected difference value is then mapped to a predetermined brightness calibration curve to output the effective brightness detection value. The brightness calibration curve is pre-calibrated using a standard brightness source. The calibration process is performed in a dark room to avoid interference from ambient light. A standard luminance meter is placed on the light-emitting side of the silicon-based OLED display module under test. The standard luminance meter has a measurement accuracy higher than 0.1 cd / m². 2 The control module outputs images at different grayscale levels, with a grayscale range of 0. 255. For each gray level, the standard brightness value of the pixel is measured by a standard luminance meter, and the corresponding correction difference value is collected at the same time. Multiple sets of standard brightness values ​​and correction difference values ​​are linearly fitted to obtain the slope and intercept of the brightness calibration curve. The slope and intercept are stored in a register for mapping calculation during real-time detection.

[0053] In this embodiment, a dual-slope integration operation combined with an automatic zero-adjustment calibration cycle is used to eliminate the influence of the input offset voltage of the integrating operational amplifier and the capacitance deviation of the integrating capacitor on the integration result, thereby improving the acquisition accuracy of the first integrated electrical signal. By dynamically adjusting the on-bias voltage of the driving transistor based on ambient temperature and historical driving current, the extraction environment of the second integrated electrical signal is made closer to the light-emitting maintenance stage, improving the consistency of parasitic baseline extraction. The initial difference value is filtered by an autoregressive moving average model to remove residual noise from non-stationary random fluctuations, further improving the stability and accuracy of the brightness detection results.

Claims

1. A method for detecting the brightness of a silicon-based OLED display module, characterized in that, include: Acquire the frame scan timing signal of the CMOS driving circuit integrated on the silicon substrate in the silicon-based OLED display module under test; Based on the frame scanning timing signal, a single display frame is divided into an OLED light-emitting data writing stage, a light-emitting maintenance stage, and a non-light-emitting reset stage, which are performed sequentially. During the light emission maintenance phase, the photodetector integrated on the silicon substrate is controlled to perform photoelectric conversion, and the first integrated electrical signal output by the photodetector is extracted. During the non-light-emitting reset phase and when the driving transistor in the CMOS driving circuit is in the on state, the photodetector is controlled to perform photoelectric conversion, and the second integrated electrical signal output by the photodetector is extracted, wherein the second integrated electrical signal characterizes the parasitic photoresponse baseline of the silicon substrate under the influence of ambient light and the leakage current of the driving transistor. The first integrated electrical signal and the second integrated electrical signal are subjected to a differential operation, and the result of the differential operation is used as the effective brightness detection value of the corresponding pixel.

2. The method for detecting the brightness of a silicon-based OLED display module according to claim 1, characterized in that, Based on the frame scanning timing signal, a single display frame is divided into an OLED light-emitting data writing stage, a light-emitting maintenance stage, and a non-light-emitting reset stage, which are performed sequentially, including: synchronously acquiring the horizontal scanning drive signal and the data latch signal in the CMOS driving circuit; Edge detection is performed on the row scan drive signal to determine the start and end timestamps of the row scan, and level state parsing is performed on the data latch signal to determine the establishment timestamp of the data voltage; When the data voltage establishment timestamp is detected to be within the interval corresponding to the row scan start and end timestamps, the current time period is defined as the OLED light emission data writing stage; When a transition is detected at the edge of the row scan drive signal and the data latch signal remains locked, the current time period is defined as the light emission maintenance phase. When the row scan drive signal is detected to be reset to the initial level and the data latch signal is unlocked, the current time period is defined as the non-light emission reset phase.

3. The method for detecting the brightness of a silicon-based OLED display module according to claim 1, characterized in that, During the light emission sustaining phase, the photodetector integrated on the silicon substrate is controlled to perform photoelectric conversion, and the first integrated electrical signal output by the photodetector is extracted, including: when the light emission sustaining phase is started, the integrating operational amplifier connected to the photodetector is controlled to perform dual-slope integration operation. During the positive integration period, the photocurrent generated by the photodetector during the light emission maintenance phase is positively charged and integrated for a fixed duration. After the positive integration period ends, the system switches to the reverse integration period and inputs a constant reference current to the integrating operational amplifier for reverse discharge until the output voltage of the integrating operational amplifier returns to the initial reference voltage. Record the duration of the reverse integration period, and convert the duration of the reverse integration period into a digital quantity as the first integration electrical signal.

4. The method for detecting the brightness of a silicon-based OLED display module according to claim 1, characterized in that, During the non-light-emitting reset phase and when the driving transistor in the CMOS driving circuit is in the on state, the photodetector is controlled to perform photoelectric conversion and the second integrated electrical signal output by the photodetector is extracted. This includes: during the non-light-emitting reset phase, cutting off the data voltage input path to the driving transistor, and simultaneously applying a conduction bias voltage with the same amplitude as the light-emitting maintenance phase to the gate of the driving transistor, so that the driving transistor is maintained in the linear region or saturation region on state. During the duration of the applied conduction bias voltage, the photodetector is controlled to synchronously integrate and acquire the leakage current inside the silicon substrate and the ambient light penetrating into the silicon substrate. The integrated voltage value acquired by the synchronous integration is obtained, and the integrated voltage value is quantized into a digital signal as the second integrated electrical signal.

5. The method for detecting the brightness of a silicon-based OLED display module according to claim 1, characterized in that, Perform a differential operation between the first integrated electrical signal and the second integrated electrical signal, and use the result of the differential operation as the effective brightness detection value of the corresponding pixel, including: calculating the difference between the first integrated electrical signal and the second integrated electrical signal in the current frame, and generating the initial differential value of the current frame; The initial difference values ​​corresponding to multiple consecutive historical frames are extracted to form a time series; The time series is input into a pre-built autoregressive moving average model to calculate the predicted value of the parasitic noise trend for the current frame. Subtract the parasitic noise trend prediction value from the initial difference value of the current frame to generate a corrected difference value after filtering out non-stationary random fluctuation residuals; The corrected difference value is mapped to a predetermined brightness calibration curve, and the effective brightness detection value is output.

6. The method for detecting the brightness of a silicon-based OLED display module according to claim 1, characterized in that, The physical structure relationship between the photodetector integrated on the silicon substrate and the CMOS driving circuit satisfies the following: the photodetector is formed inside the P-type well of the silicon substrate, and the driving transistor in the CMOS driving circuit is disposed adjacent to the photodetector. A ring-shaped deep N-well isolation structure is provided between the edge of the photosensitive surface of the photodetector and the active region of the drain of the driving transistor. The bottom of the deep N-well isolation structure extends into the N-type substrate below the P-type well, and the top of the deep N-well isolation structure is connected to a bias voltage lead with a fixed potential. The deep N-well isolation structure surrounds the photosensitive surface of the photodetector, blocking the lateral diffusion of charge carriers from the drain active region of the driving transistor to the photosensitive surface of the photodetector.

7. The method for detecting the brightness of a silicon-based OLED display module according to claim 2, characterized in that, To determine the start and end timestamps of the row scan drive signal by edge detection, the method includes: performing multi-phase clock sampling processing on the row scan drive signal using a delay-locked loop; The delay-locked loop generates multiple sampling clocks with a fixed phase difference based on the delay order of the internal voltage-controlled delay line; The row scan drive signal is triggered in parallel using the multiple sampling clocks to generate a trigger state vector of the row scan drive signal under different phase clocks; The trigger state vector is decoded to determine the target delay level corresponding to the rising and falling edges of the row scan drive signal; Based on the target delay level and the unit delay time of the pressure-controlled delay line, the precise time coordinates of the start and end timestamps of the row scan are calculated.

8. The method for detecting the brightness of a silicon-based OLED display module according to claim 3, characterized in that, Before the photoluminescence sustaining phase is initiated and before the integrating operational amplifier connected to the photodetector performs a dual-slope integration operation, the method further includes: during the OLED photoluminescence data writing phase, controlling the integrating operational amplifier to enter an automatic zeroing calibration cycle. During the automatic zeroing calibration cycle, the calibration switch connected between the inverting input terminal and the output terminal of the integrating operational amplifier is closed, and the non-inverting input terminal of the integrating operational amplifier is grounded. The input offset voltage of the integrating operational amplifier in closed-loop state is stored in an external calibration capacitor; When entering the dual-slope integration operation, the calibration switch is disconnected, and the calibration capacitor is connected in series in the inverting input circuit of the integrating operational amplifier.

9. The method for detecting the brightness of a silicon-based OLED display module according to claim 4, characterized in that, Applying a bias voltage to the gate of the driving transistor with the same amplitude as the light emission sustaining phase includes: acquiring the real-time ambient temperature value of the silicon substrate at the current detection time and the maximum driving current value of the current pixel column in the previous frame display cycle; In a pre-stored bias voltage compensation lookup table, the target bias voltage compensation amount is obtained by querying the real-time ambient temperature value and the maximum drive current value as index variables. The initial bias voltage applied to the gate of the driving transistor during the light-emitting maintenance phase is superimposed with the target bias voltage compensation amount to generate a dynamic on-bias voltage. During the non-light-emitting reset phase, the dynamic on-bias voltage is applied to the gate of the driving transistor.

10. The method for detecting the brightness of a silicon-based OLED display module according to claim 6, characterized in that, The top of the deep N-well isolation structure is connected to a bias voltage lead with a fixed potential, including: the bias voltage lead is connected to an external regulated power supply through a passive low-pass filter network, and the cutoff frequency of the passive low-pass filter network is set according to the substrate coupling noise frequency band of the silicon substrate. At the junction of the bottom and side surfaces of the deep N-well isolation structure, a P-type protective injection band is provided around the deep N-well isolation structure; The P-type protection implantation band is doped on the surface of the P-type well, and the P-type protection implantation band is directly connected to the substrate ground potential of the silicon substrate. The deep N-well isolation structure and the P-type protection injection band constitute a three-dimensional shielding structure with longitudinal PN junction isolation and lateral electric field shielding.

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