Display device

Abstract

A display device includes a plurality of pixel circuits, N data lines, a data driving circuit, a scan driving circuit and a control circuit. The N data lines are divided into a first data line group, a second data line group and a third data line group. The data driving circuit is configured to generate data signals to the pixel circuits via the N data lines. The scan driving circuit is configured to generate scan signals to the pixel circuits. The control circuit is configured to selectively control the order of providing the data signals from the first data line group, the second data line group and the third data line group according to a duty cycle of a light emitting control signal corresponding to a frame of image data or a pixel on ratio corresponding to the frame of image data in one of a normal mode and an adjustment mode.

Description

Technical Field

[0001] This disclosure relates to a display device, and more particularly to a miniature light-emitting diode display device. Background Technology

[0002] Light-emitting diodes (LEDs) differ from traditional light sources in their light-emitting principle and structure, offering advantages such as low power consumption, long lifespan, no warm-up time, and fast response. Furthermore, LEDs are small, vibration-resistant, and suitable for mass production, easily manufactured into miniature or array-type components to meet specific application needs, resulting in their widespread market applications. For example, LEDs can be used in various fields, including lighting devices, displays, traffic signals, indicators, communication devices, lighting fixtures, and medical devices. Summary of the Invention

[0003] One aspect of this disclosure is to provide a display device comprising multiple pixel circuits, N data lines, a data driving circuit, a scan driving circuit, and a control circuit. The pixel circuits are arranged in an M-row, N-column matrix, where M and N are positive integers greater than 1. The N data lines are electrically connected to all pixel circuits in the N columns. The N data lines are divided into a first data line group, a second data line group, and a third data line group. The first data line group includes the (3i-2)th data line of the N data lines in sequence, the second data line group includes the (3i-1)th data line of the N data lines in sequence, and the third data line group includes the (3i)th data line of the N data lines in sequence, where i is an integer and 1 ≤ i ≤ (N / 3). The data driving circuit is electrically connected to the N data lines and configured to generate multiple data signals to the pixel circuits via the N data lines. The scan driving circuit is electrically connected to the pixel circuits and configured to generate multiple scan signals to the pixel circuits. The scanning time of each scan signal is divided into a first time segment, a second time segment, and a third time segment. The first data line group, the second data line group, and the third data line group respectively provide these data signals to the corresponding pixel circuits in the first time segment, the second time segment, and the third time segment. The control circuit is electrically connected to the scan drive circuit and the data drive circuit, and is configured to selectively control the order in which the first data line group, the second data line group, and the third data line group provide the corresponding data signals, based on the duty cycle of the light emission control signal corresponding to the first frame image data or the pixel activation ratio corresponding to the first frame image data, in either a normal mode or an adjustment mode.

[0004] According to some embodiments of this disclosure, in response to a duty cycle of the emission control signal corresponding to the first frame image data being greater than a first threshold and a pixel activation ratio corresponding to the first frame image data being less than a second threshold, the control circuit controls the delivery sequence in normal mode. In normal mode, for all pixel circuits in each row, the delivery sequence is a first data line group, a second data line group, and a third data line group.

[0005] According to some embodiments of this disclosure, when the duty cycle of the light emission control signal corresponding to the first frame image data is less than or equal to a first threshold or the pixel on-state ratio corresponding to the first frame image data is greater than or equal to a second threshold, the control circuit provides the sequence in an adjustment mode control.

[0006] According to some embodiments of this disclosure, in adjustment mode, for all pixel circuits in the (3k-2)th row of M rows, the order is provided as first data line group, second data line group and third data line group; for all pixel circuits in the (3k-1)th row of M rows, the order is provided as second data line group, third data line group and first data line group; for all pixel circuits in the (3k)th row of M rows, the order is provided as third data line group, first data line group and second data line group, where k is an integer and 1≤k≤(M / 3).

[0007] According to some embodiments of this disclosure, in adjustment mode, for all pixel circuits in the (3k-2)th row of M rows, the order is provided as the second data line group, the third data line group, and the first data line group; for all pixel circuits in the (3k-1)th row of M rows, the order is provided as the third data line group, the first data line group, and the second data line group; and for all pixel circuits in the (3k)th row of M rows, the order is provided as the first data line group, the second data line group, and the third data line group, where k is an integer and 1≤k≤(M / 3).

[0008] According to some embodiments of this disclosure, in adjustment mode, for all pixel circuits in the (3k-2)th row of M rows, the order is provided as the third data line group, the first data line group, and the second data line group; for all pixel circuits in the (3k-1)th row of M rows, the order is provided as the first data line group, the second data line group, and the third data line group; and for all pixel circuits in the (3k)th row of M rows, the order is provided as the second data line group, the third data line group, and the first data line group, where k is an integer and 1≤k≤(M / 3).

[0009] According to some embodiments of this disclosure, in adjustment mode, during the display of the first frame of image data, for each row of pixel circuits, the first data line group, the second data line group, and the third data line group sequentially provide data signals corresponding to the first frame of image data to the corresponding pixel circuits. During the display of the second frame of image data, for each row of pixel circuits, the second data line group, the third data line group, and the first data line group sequentially provide data signals corresponding to the second frame of image data to the corresponding pixel circuits. During the display of the third frame of image data, for each row of pixel circuits, the third data line group, the first data line group, and the second data line group sequentially provide data signals corresponding to the third frame of image data to the corresponding pixel circuits. The first frame of image data, the second frame of image data, and the third frame of image data are three sequential frames of image data.

[0010] According to some embodiments of this disclosure, in adjustment mode, during the display of the first frame of image data, for each row of pixel circuits, the first data line group, the second data line group, and the third data line group sequentially provide data signals corresponding to the first frame of image data to the corresponding pixel circuits. During the display of the second frame of image data, for each row of pixel circuits, the third data line group, the second data line group, and the first data line group sequentially provide data signals corresponding to the second frame of image data to the corresponding pixel circuits. The first frame of image data and the second frame of image data are two sequential frames of image data.

[0011] According to some embodiments of this disclosure, each pixel circuit includes a light-emitting element, and the light-emitting element is configured to emit light according to a drive current generated by a received data signal. The driving time of the drive current is controlled by the duty cycle of a light-emitting control signal.

[0012] According to some embodiments of this disclosure, the pixel opening ratio is the proportion of the number of pixels in the first frame image data whose pixel value is greater than a preset pixel value to the total number of pixels in the first frame image data.

[0013] In summary, this disclosure utilizes a control circuit to selectively control the sequence of data signal delivery in either normal or adjustment mode based on the duty cycle of the image data's emission control signal and / or the pixel activation ratio. This causes the timing of data signal reception by the pixel circuit to vary regularly across different lines or frames, preventing uneven brightness and the formation of bright and dark fringes caused by the accumulation of systemic driving conditions. Through this design, the uniformity and viewing quality of the displayed image can be effectively improved without significantly increasing hardware complexity, and it possesses good flexibility to adapt to different display scenarios and image characteristics. Attached Figure Description

[0014] The nature of this disclosure can be understood from the following detailed description and accompanying diagrams. It should be noted that many features are not drawn to industry-standard scale. In fact, the dimensions of various features may be increased or decreased arbitrarily for clarity of discussion.

[0015] Figure 1 This is a schematic diagram of a display device illustrated according to one embodiment of the present disclosure.

[0016] Figure 2 This is a timing diagram illustrating the delivery sequence in an adjustment mode according to one embodiment of the present disclosure.

[0017] Figure 3 This is a timing diagram illustrating the delivery sequence in an adjustment mode according to another embodiment of the present disclosure.

[0018] Figure 4 This is a timing diagram illustrating the delivery sequence in an adjustment mode according to another embodiment of the present disclosure.

[0019] Figure 5 This is a timing diagram illustrating the delivery sequence in an adjustment mode according to another embodiment of the present disclosure.

[0020] Figure 6 This is a timing diagram illustrating the delivery sequence in an adjustment mode according to another embodiment of the present disclosure.

[0021] In the attached figures, the following labels are used:

[0022] 100: Display device

[0023] 110: Data drive circuit

[0024] 130: Scan drive circuit

[0025] 150: Control Circuit

[0026] DL_1, DL_2, DL_3, DL_N: Data cables

[0027] EM_1, EM_2, EM_3, EM_M: Light emission control lines

[0028] GL_1, GL_2, GL_3, GL_M: Scan lines

[0029] GP1: First Data Cable Group

[0030] GP2: Second Data Cable Group

[0031] GP3: Third Data Cable Group

[0032] PX_11,PX_12,PX_13,PX_1N,PX_21,PX_22,

[0033] PX_23,PX_2N,PX_31,PX_32,PX_33,PX_3N,

[0034] PX_M1, PX_M2, PX_M3, PX_MN: Pixel circuits

[0035] SN: Scan signal

[0036] T1: First Time Segment

[0037] T2: Second Time Segment

[0038] T3: Third Time Segment Detailed Implementation

[0039] This disclosure will be described in detail with reference to the following embodiments. It should be noted that the following description of the embodiments of this disclosure is for illustrative purposes only and is not intended to disclose all embodiments in detail or to limit the specific embodiments of this disclosure.

[0040] It is understood that while terms such as "first" and "second" may be used in this document to describe various features, these terms should not limit these features. These terms are only used to distinguish one feature from another.

[0041] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of the claims. Unless otherwise limited, the singular forms of "a" or "the" may also be used to denote the plural forms.

[0042] The different embodiments disclosed below may reuse the same reference numerals and / or designations. These repetitions are for simplification and clarity and are not intended to limit any specific relationship between the different embodiments and / or structures discussed.

[0043] Please refer to Figure 1 , Figure 1This is a schematic diagram of a display device 100 illustrated according to one embodiment of the present disclosure. The display device 100 may include pixel circuits PX_11 to PX_MN, scan lines GL_1 to GL_M, data lines DL_1 to DL_N, light emission control lines EM_1 to EM_M, a data driving circuit 110, a scan driving circuit 130, and a control circuit 150. The pixel circuits PX_11 to PX_MN are arranged in an M-row, N-column matrix, where M and N are positive integers greater than 1. The data lines DL_1 to DL_N are electrically connected between the pixel circuits PX_11 to PX_MN and the data driving circuit 110. The data driving circuit 110 is configured to generate multiple data signals and provide them to the corresponding pixel circuits PX_11 to PX_MN via the data lines DL_1 to DL_N. The scan lines GL_1 to GL_M are electrically connected between the pixel circuits PX_11 to PX_MN and the scan driving circuit 130. The light emission control lines EM_1 to EM_M are electrically connected between the pixel circuits PX_11 to PX_MN and the scan drive circuit 130. The scan drive circuit 130 is configured to generate multiple scan signals and provide them to the corresponding pixel circuits PX_11 to PX_MN via the scan lines GL_1 to GL_M, and to generate multiple light emission control signals and provide them to the corresponding pixel circuits PX_11 to PX_MN via the light emission control lines EM_1 to EM_M.

[0044] In this embodiment, each pixel circuit may include multiple light-emitting elements and their respective driving circuits (not shown). The light-emitting elements are, for example, miniature light-emitting diodes (LEDs). For instance, each pixel circuit may include a red miniature LED, a green miniature LED, and a blue LED to form a pixel unit. Therefore, the display device 100 may be a miniature LED display device. For each pixel circuit, when a scan signal is received via a scan line, a switching transistor in its driving circuit can be turned on to allow the driving circuit to receive a data signal via a data line. The driving circuit can generate a driving current of a corresponding magnitude according to the received data signal, and during the enable period of the light-emitting control signal received via the light-emitting control line, it provides the driving current to the light-emitting elements to make them emit light. The brightness of the light-emitting elements may correspond to the pixel value (i.e., grayscale value) of the image data, which may be determined by the magnitude of the driving current (determined by the data signal) and the driving time (determined by the duty cycle of the light-emitting control signal).

[0045] In one embodiment, the data driving circuit 110 may be, for example, a data driving element, a digital-to-analog converter, or a driver amplifier, used to generate and output data signals corresponding to pixels. The scan driving circuit 130 may be, for example, a scan driving element, a shift register, or a level shifter, used to generate scan signals and light emission control signals. The control circuit 150 may be, for example, a timing controller (TCON), used to generate control signals, manage the operating timing of the data driving circuit 110 and the scan driving circuit 130, and adjust the scan order, the duty cycle of the light emission control signal, and the synchronization signal according to the input image data received via an image source (not shown), to ensure correct display of the displayed image and brightness control.

[0046] It should be noted that, in this embodiment, the circuit for generating the light emission control signal and the circuit for generating the scan signal are shown integrated into the same circuit element, such as a gate driver on array (GOA). This integrates the scan driving circuit onto the substrate of the display panel to directly generate the scan signal and the light emission control signal, reducing the need for external driving components and wiring. However, in other embodiments, the circuit for generating the light emission control signal and the circuit for generating the scan signal can also be integrated into different circuit elements or chips, and can be configured on both sides of the pixel circuit. This disclosure is not limited to this.

[0047] like Figure 1 As shown, because the light-emitting control lines EM_1~EM_M and the data lines DL_1~DL_N are interleaved, the time during which the light-emitting control signal is provided to the pixel circuit of a certain row may overlap with the time during which the pixel circuits of other rows receive data signals, causing electromagnetic coupling or capacitive coupling effects. These coupling effects may interfere with the data signal, leading to a deviation of the pixel current from the expected value, causing localized changes in the brightness of the light-emitting element, forming a mura phenomenon, thereby affecting the uniformity and viewing quality of the displayed image.

[0048] Accordingly, this disclosure provides a means of controlling the provision of data signals to solve the aforementioned problem of forming mura.

[0049] In this embodiment, the N data lines DL_1 to DL_N are further divided into a first data line group GP1, a second data line group GP2, and a third data line group GP3. For example, the first data line group GP1 may include the (3i-2)th data line among the N data lines in sequence, the second data line group GP2 may include the (3i-1)th data line among the N data lines in sequence, and the third data line group GP3 may include the (3i)th data line among the N data lines in sequence, where i is an integer and 1≤i≤(N / 3). For example, the first data line group GP1 may include the first data line, the fourth data line, ..., the (N-2)th data line among the N data lines DL_1 to DL_N in sequence. The second data line group GP2 may include the second data line, the fifth data line, ..., the (N-1)th data line among the N data lines DL_1 to DL_N in sequence. The third data line group GP3 may include the third data line, the sixth data line, ..., the Nth data line from DL_1 to DL_N in sequence.

[0050] Furthermore, for all pixel circuits in each row (i.e., N pixel circuits), when the corresponding scan signal is received, the switching transistors in their driving circuits are all turned on during the scan time (i.e., the enable time) of the scan signal. At this time, the driving circuits of these pixel circuits can receive the corresponding data signals via the first data line group GP1, the second data line group GP2, and the third data line group GP3 to generate the required driving current. In this embodiment, the scan time of each scan signal may include staggered (i.e., non-overlapping) first time segment, second time segment, and third time segment, and the first data line group GP1, the second data line group GP2, and the third data line group GP3 provide data signals to the corresponding pixel circuits in the first time segment, the second time segment, and the third time segment, respectively. In other words, for pixel circuits in the same row, the pixel circuit connected to the first data line group GP1 can only receive data signals in the first time segment, the pixel circuit connected to the second data line group GP2 can only receive data signals in the second time segment, and the pixel circuit connected to the third data line group GP3 can only receive data signals in the third time segment. The above-mentioned method of providing data signals can be called Time-Division Multiplexing (TDM).

[0051] Furthermore, the control circuit 150 is also configured to selectively control the order in which data signals are provided by the first data line group GP1, the second data line group GP2, and the third data line group GP3 are provided, either in a normal mode or an adjustment mode. In one embodiment, in normal mode, for all pixel circuits in each row, the order in which data signals are provided may be one of the following: the order of the first data line group GP1, the second data line group GP2, and the third data line group GP3; the order of the second data line group GP2, the third data line group GP3, and the first data line group GP1; and the order of the third data line group GP3, the first data line group GP1, and the second data line group GP2. Generally, without specific design, the display device 100 provides data signals in normal mode. However, as previously mentioned, under regular driving conditions, the mura phenomenon may be more pronounced. To mitigate this issue, the display device 100 disclosed herein can selectively employ an adjustment mode based on different conditions, altering the order in which data signals are provided. This changes the combination and order in which pixel circuits in different rows of the same frame, or in the same row of different frames, receive data signals at different times. By altering the temporal regularity of the data signals, mura can be reduced, improving the uniformity of the displayed image and viewing quality.

[0052] Specifically, the higher the duty cycle of the emission control signal corresponding to a frame of image data, the brighter the overall image appears, and the less noticeable the mura becomes. Conversely, when the image brightness is low (i.e., the duty cycle is low), the bright lines will be more noticeable against a dark background. Accordingly, in one embodiment, the control circuit 150 can determine whether to use an adjustment mode to regulate the order of data signal delivery based on whether the duty cycle of the emission control signal of the current frame's image data is less than or equal to a first threshold (e.g., 30%).

[0053] On the other hand, for a frame of image data, the pixel-on ratio (POR) is the proportion of the number of pixels in the first frame of image data whose pixel value (i.e., grayscale value) is greater than a preset pixel value. A higher pixel-on ratio results in a stronger perception of line mura by the human eye. Conversely, a lower pixel-on ratio allows for a greater increase in brightness, but reduces the importance of brightness uniformity. Accordingly, in one embodiment, the control circuit 150 can determine whether to use an adjustment mode to regulate the order of data signal delivery based on whether the pixel-on ratio of the current frame's image data is greater than or equal to a second threshold (e.g., 50%).

[0054] It should be noted that, in one embodiment, the preset pixel value for the pixel activation ratio can be zero. In other words, only pixels that are not completely black (i.e., not turned off) are included in the calculation. However, in other embodiments, the preset pixel value can also be set according to different display scenarios or image characteristics. For example, if the grayscale value range is 0 to 255, a certain proportion (e.g., 1 / 3) of the highest grayscale value can be set as the preset pixel value (i.e., 85), and only pixels with a grayscale value greater than 85 are included in the pixel activation ratio calculation. By setting a preset pixel value, the influence of low-brightness pixels on the statistical results can be eliminated, the accuracy of pixel activation ratio analysis can be improved, and it can be flexibly adjusted according to image characteristics or display requirements.

[0055] According to the above design, in one embodiment, when the duty cycle of the emission control signal corresponding to the current frame image data is greater than a first threshold and the pixel activation ratio corresponding to the current frame image data is less than a second threshold, the control circuit 150 controls the data signal provision order in normal mode. In normal mode, for all pixel circuits in each row (i.e., the first row to the Mth row), the provision order is the same, for example, the first data line group GP1, the second data line group GP2, and the third data line group GP3. In this example, for N pixel circuits in each row, during scanning, the control circuit 150 controls the first data line group GP1 to first provide the data signal corresponding to the current frame image data in the row to the corresponding pixel circuit, then the second data line group GP2 provides the data signal corresponding to the current frame image data in the row to the corresponding pixel circuit, and then the third data line group GP3 provides the data signal corresponding to the current frame image data in the row to the corresponding pixel circuit, thereby completing the data signal provision for this row. Then, the pixel circuits in the next row provide data signals in the same order until all pixel circuits have received data signals.

[0056] It should be noted that the aforementioned means of controlling different data lines to provide data signals at different times can be implemented, for example, by using switches and corresponding multiplexers connected between each data line and the data driving circuit 110. For example, the control circuit 150 can control the multiplexer connected to the (3i-2)th data line to turn on all switches connected to the (3i-2)th data line, so that the first data line group GP1 transmits data signals from the data driving circuit 110 to the corresponding pixel circuit. During this period, all switches connected to the (3i-1)th data line and the (3i)th data line are turned off, and so on, to achieve multiplexing.

[0057] In one embodiment, in response to a duty cycle of the illumination control signal corresponding to the current frame image data being less than or equal to a first threshold and a pixel on / off ratio corresponding to the current frame image data being greater than or equal to a second threshold, the control circuit 150 controls the data signal provision order in an adjustment mode. Examples of the provision order in various adjustment modes will be described below. It should be noted that in... Figures 2 to 6 In this context, all signals are in an enabled period when they are at a low logic level and in a disabled period when they are at a high logic level. This is related to the type of transistor used, and this disclosure is not limited to this. Furthermore, the signals corresponding to the first data line group GP1, the second data line group GP2, and the third data line group GP3 can refer to, for example, signals provided to the switch connected between the first data line group GP1 and the data drive circuit 110, the switch connected between the second data line group GP2 and the data drive circuit 110, and the switch connected between the third data line group GP3 and the data drive circuit 110. When the signal is in the enabled period, the switch is on, and the corresponding data line group can provide data signals to the pixel circuit. When the signal is in the disabled period, the switch is off, and the corresponding data line group does not provide data signals to the pixel circuit.

[0058] Please refer to Figure 2 . Figure 2 This is a timing diagram illustrating the provision order in an adjustment mode according to one embodiment of the present disclosure. In this embodiment, in the adjustment mode, for all pixel circuits in the (3k-2)th row (i.e., the first row, the fourth row, ..., the (M-2)th row) of M rows, the order is provided as first data line group GP1, second data line group GP2, and third data line group GP3; for all pixel circuits in the (3k-1)th row (i.e., the second row, the fifth row, ..., the (M-1)th row) of M rows, the order is provided as second data line group GP2, third data line group GP3, and first data line group GP1; for all pixel circuits in the (3k)th row (i.e., the third row, the sixth row, ..., the Mth row) of M rows, the order is provided as third data line group GP3, first data line group GP1, and second data line group GP2, where k is an integer and 1≤k≤(M / 3).

[0059] Specifically, for the N pixel circuits in the (3k-2)th row, during the scanning period of the scan signal SN (i.e., the enable period), the control circuit 150 controls the first data line group GP1 to provide the corresponding data signal for the current frame image data in the row to the corresponding pixel circuit in the first time segment T1. Then, the second data line group GP2 provides the corresponding data signal for the current frame image data in the row to the corresponding pixel circuit in the second time segment T2. Finally, the third data line group GP3 provides the corresponding data signal for the current frame image data in the row to the corresponding pixel circuit in the third time segment T3, thus completing the provision of data signals for these rows. In other words, for the N pixel circuits in the (3k-2)th row, the timing sequence for providing data signals is the first time segment T1, the second time segment T2, and the third time segment T3. Similarly, for the N pixel circuits in the (3k-1)th row, the timing sequence for providing data signals is the second time segment T2, the third time segment T3, and the first time segment T1. For the N pixel circuits in the (3k)th row, the timing sequence for providing the data signal is the third time segment T3, the first time segment T1, and the second time segment T2.

[0060] Please refer to Figure 3 . Figure 3 This is a timing diagram illustrating the provision order in an adjustment mode according to another embodiment of the present disclosure. In this embodiment, in the adjustment mode, for all pixel circuits in the (3k-2)th row sequentially in M ​​rows, the order provided during the scanning of the scan signal SN is second data line group GP2, third data line group GP3, and first data line group GP1. For all pixel circuits in the (3k-1)th row sequentially in M ​​rows, the order provided is third data line group GP3, first data line group GP1, and second data line group GP2. For all pixel circuits in the (3k)th row sequentially in M ​​rows, the order provided is first data line group GP1, second data line group GP2, and third data line group GP3.

[0061] In other words, for the N pixel circuits in row (3k-2), the timing sequence for providing the data signal is the second time segment T2, the third time segment T3, and the first time segment T1. For the N pixel circuits in row (3k-1), the timing sequence for providing the data signal is the third time segment T3, the first time segment T1, and the second time segment T2. For the N pixel circuits in row (3k), the timing sequence for providing the data signal is the first time segment T1, the second time segment T2, and the third time segment T3.

[0062] Please refer to Figure 4 . Figure 4This is a timing diagram illustrating the provision order in an adjustment mode according to another embodiment of the present disclosure. In this embodiment, in the adjustment mode, for all pixel circuits in the (3k-2)th row sequentially in M ​​rows, during the scanning of the scan signal SN, the order provided is third data line group GP3, first data line group GP1, and second data line group GP2. For all pixel circuits in the (3k-1)th row sequentially in M ​​rows, the order provided is first data line group GP1, second data line group GP2, and third data line group GP3. For all pixel circuits in the (3k)th row sequentially in M ​​rows, the order provided is second data line group GP2, third data line group GP3, and first data line group GP1.

[0063] In other words, for the N pixel circuits in row (3k-2), the timing sequence for providing the data signal is the third time segment T3, the first time segment T1, and the second time segment T2. For the N pixel circuits in row (3k-1), the timing sequence for providing the data signal is the first time segment T1, the second time segment T2, and the third time segment T3. For the N pixel circuits in row (3k), the timing sequence for providing the data signal is the second time segment T2, the third time segment T3, and the first time segment T1.

[0064] The above are merely examples of the order in which several different row pixel circuits receive data signals in different time segments. Without departing from the spirit and scope of the embodiments disclosed herein, some modifications and refinements can be made to obtain other different sequences.

[0065] exist Figures 2 to 4 The example given is an embodiment of adjusting the order in which pixel circuits of different rows receive data signals for image data of the same frame in the adjustment mode. The following will describe an embodiment of adjusting the order in which data signals are provided for image data of different frames in the adjustment mode.

[0066] Please refer to Figure 5 . Figure 5This is a timing diagram illustrating the delivery sequence in an adjustment mode according to another embodiment of the present disclosure. In this embodiment, in the adjustment mode, during the display of the j-th frame of image data, for all pixel circuits in each row, during the scanning of the scan signal SN, the first data line group GP1, the second data line group GP2, and the third data line group GP3 sequentially provide data signals corresponding to the j-th frame of image data to the corresponding pixel circuits. During the display of the (j+1)-th frame of image data, for all pixel circuits in each row, during the scanning of the scan signal SN, the second data line group GP2, the third data line group GP3, and the first data line group GP1 sequentially provide data signals corresponding to the (j+1)-th frame of image data to the corresponding pixel circuits. During the display of the (j+2)-th frame of image data, for all pixel circuits in each row, during the scanning of the scan signal SN, the third data line group GP3, the first data line group GP1, and the second data line group GP2 sequentially provide data signals corresponding to the (j+2)-th frame of image data to the corresponding pixel circuits, where j is a positive integer.

[0067] Specifically, the adjustment mode disclosed herein can adjust not only the order in which pixel circuits of different rows receive data signals during the display of the same frame of image, but also the order in which pixel circuits receive data signals during the display of different frames of image. When the control circuit 150 receives the j-th frame of image data, it can determine whether to control the data signal delivery order in normal mode or adjustment mode based on the duty cycle and / or pixel on-state of the corresponding light emission control signal for the j-th frame of image data. When it is determined that the control is to be performed in adjustment mode, the control circuit 150 can control all pixel circuits that are to display the j-th frame of image data to receive data signals in the same delivery order. For example, during the scanning period of the scan signal SN for each row, the timing of the data signal delivery can be in the order of the first time segment T1, the second time segment T2, and the third time segment T3. Next, during the display of the next frame of image data (i.e., the (j+1)th frame of image data), the control circuit 150 can control all pixel circuits that are to display the (j+1)th frame of image data to receive data signals in the same alternative delivery sequence. For example, during the scanning period of each row of scan signals SN, the timing of the data signal delivery can be in the order of the second time segment T2, the third time segment T3, and the first time segment T1. Then, during the display of the next frame of image data (i.e., the (j+2)th frame of image data), the control circuit 150 can control all pixel circuits that are to display the (j+2)th frame of image data to receive data signals in the same alternative delivery sequence. For example, during the scanning period of each row of scan signals SN, the timing of the data signal delivery can be in the order of the third time segment T3, the first time segment T1, and the second time segment T2. After displaying a set of image data (e.g., three consecutive frames), the control circuit 150 can re-determine whether to maintain the adjustment mode or switch to the normal mode to control the data signal delivery sequence based on the duty cycle and / or pixel on / off ratio of the illumination control signal for the current frame's image data (i.e., the (j+3)th frame's image data). If maintaining the adjustment mode, the control sequence described above is repeated. Similarly, Figure 5 This example only illustrates the order in which a single pixel circuit receives data signals in different time segments within a single frame. Without departing from the spirit and scope of the embodiments disclosed herein, some modifications and refinements may be made to obtain different delivery orders for other frame images.

[0068] Please refer to Figure 6 . Figure 6This is a timing diagram illustrating the delivery sequence in adjustment mode according to another embodiment of the present disclosure. In this embodiment, in adjustment mode, during the display of the j-th frame of image data, for all pixel circuits in each row, during the scanning of the scan signal SN, the first data line group GP1, the second data line group GP2, and the third data line group GP3 sequentially provide data signals corresponding to the j-th frame of image data to the corresponding pixel circuits. During the display of the (j+1)-th frame of image data, for all pixel circuits in each row, during the scanning of the scan signal SN, the third data line group GP3, the second data line group GP2, and the first data line group GP1 sequentially provide data signals corresponding to the (j+1)-th frame of image data to the corresponding pixel circuits. After the display of a set of image data (e.g., two consecutive frames) is completed, the control circuit 150 can re-determine whether to maintain the adjustment mode or switch to the normal mode to control the data signal delivery sequence based on the duty cycle and / or pixel on-state of the light emission control signal of the current frame of image data (i.e., the (j+2)-th frame of image data). If the adjustment mode is maintained, the control sequence described above is repeated.

[0069] Figure 6 and Figure 5 The difference lies in Figure 6 The adjustment mode can adjust the order in which some pixel circuits receive data signals. This reduces the complexity of the control logic, thereby reducing the computational and switching burden on the control circuit 150 and decreasing the risk of timing errors or unstable switching, thus improving overall drive stability. Furthermore, reducing the number of switches connected to the data lines not only improves the brightness and darkness of the patterns but also helps reduce power consumption.

[0070] In summary, this disclosure provides a display device and its data signal supply control method. By grouping multiple data lines and employing time-division multiplexing to supply data signals at different times, the number of required data driving circuits is reduced. Furthermore, this disclosure further utilizes a control circuit to selectively control the data signal supply sequence in normal or adjustment modes based on the duty cycle of the image data's emission control signal and / or the pixel on-state ratio. This causes the timing of data signal reception by the pixel circuits to vary regularly across different lines or frames, preventing uneven brightness and mura caused by the accumulation of systemic driving conditions. Through this design, the uniformity and viewing quality of the displayed image can be effectively improved without significantly increasing hardware complexity, and it possesses good flexibility to adapt to different display scenarios and image characteristics.

[0071] Although the embodiments of this disclosure have been disclosed above, they are not intended to limit the embodiments of this disclosure. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the embodiments of this disclosure. Therefore, the protection scope of the embodiments of this disclosure shall be determined by the appended claims.

Claims

1. A display device, characterized in that, include: Multiple pixel circuits are configured in a matrix of M rows and N columns, where M and N are positive integers greater than 1; N data lines are electrically connected to all pixel circuits in the N columns. The N data lines are divided into a first data line group, a second data line group, and a third data line group. The first data line group includes the (3i-2)th data line in sequence among the N data lines. The second data line group includes the (3i-1)th data line in sequence among the N data lines. The third data line group includes the (3i)th data line in sequence among the N data lines. Where i is an integer and 1≤i≤(N / 3). A data driving circuit is electrically connected to the N data lines and configured to generate multiple data signals to the pixel circuits via the N data lines. A scan driving circuit is electrically connected to the pixel circuits and configured to generate a plurality of scan signals to the pixel circuits, wherein a scan time of each of the scan signals includes a first time segment, a second time segment and a third time segment, and the first data line group, the second data line group and the third data line group respectively provide the data signals to the corresponding pixel circuits in the first time segment, the second time segment and the third time segment; as well as A control circuit, electrically connected to the scan drive circuit and the data drive circuit, is configured to selectively control the order in which the first data line group, the second data line group and the third data line group provide the corresponding data signals in one of a normal mode and an adjustment mode, according to a duty cycle of a light emission control signal corresponding to a first frame image data or a pixel on-statement corresponding to the first frame image data.

2. The display device as claimed in claim 1, characterized in that, When the duty cycle of the emission control signal corresponding to the first frame image data is greater than a first threshold and the pixel activation ratio corresponding to the first frame image data is less than a second threshold, the control circuit controls the supply order in the normal mode. In the normal mode, for all pixel circuits in each of the M rows, the supply order is the first data line group, the second data line group, and the third data line group.

3. The display device as claimed in claim 2, characterized in that, When the duty cycle of the light emission control signal corresponding to the first frame image data is less than or equal to the first threshold, or the pixel on-state ratio corresponding to the first frame image data is greater than or equal to the second threshold, the control circuit controls the supply sequence in the adjustment mode.

4. The display device as claimed in claim 3, characterized in that, In this adjustment mode, for all pixel circuits in the (3k-2)th row of the M rows, the provision order is the first data line group, the second data line group, and the third data line group; for all pixel circuits in the (3k-1)th row of the M rows, the provision order is the second data line group, the third data line group, and the first data line group; and for all pixel circuits in the (3k)th row of the M rows, the provision order is the third data line group, the first data line group, and the second data line group, where k is an integer and 1≤k≤(M / 3).

5. The display device as claimed in claim 3, characterized in that, In this adjustment mode, for all pixel circuits in the (3k-2)th row of the M rows, the provision order is the second data line group, the third data line group, and the first data line group; for all pixel circuits in the (3k-1)th row of the M rows, the provision order is the third data line group, the first data line group, and the second data line group; and for all pixel circuits in the (3k)th row of the M rows, the provision order is the first data line group, the second data line group, and the third data line group, where k is an integer and 1≤k≤(M / 3).

6. The display device as claimed in claim 3, characterized in that, In this adjustment mode, for all pixel circuits in the (3k-2)th row of the M rows, the provision order is the third data line group, the first data line group, and the second data line group; for all pixel circuits in the (3k-1)th row of the M rows, the provision order is the first data line group, the second data line group, and the third data line group; and for all pixel circuits in the (3k)th row of the M rows, the provision order is the second data line group, the third data line group, and the first data line group, where k is an integer and 1≤k≤(M / 3).

7. The display device as claimed in claim 3, characterized in that, In this adjustment mode, during the display of the first frame of image data, for all pixel circuits in each of the M rows, the first data line group, the second data line group, and the third data line group sequentially provide data signals corresponding to the first frame of image data to the corresponding pixel circuits. During the display of the second frame of image data, for all pixel circuits in each of the M rows, the second data line group, the third data line group, and the first data line group sequentially provide data signals corresponding to the second frame of image data to the corresponding pixel circuits. During the display of the third frame of image data, for all pixel circuits in each of the M rows, the third data line group, the first data line group, and the second data line group sequentially provide data signals corresponding to the third frame of image data to the corresponding pixel circuits. The first frame of image data, the second frame of image data, and the third frame of image data are three sequential frames of image data.

8. The display device as claimed in claim 3, characterized in that, In this adjustment mode, during the display of the first frame of image data, for all pixel circuits in each of the M rows, the first data line group, the second data line group, and the third data line group sequentially provide data signals corresponding to the first frame of image data to the corresponding pixel circuits. During the display of the second frame of image data, for all pixel circuits in each of the M rows, the third data line group, the second data line group, and the first data line group sequentially provide data signals corresponding to the second frame of image data to the corresponding pixel circuits. The first frame of image data and the second frame of image data are two sequential frames of image data.

9. The display device as claimed in claim 1, characterized in that, Each of the pixel circuits includes a light-emitting element, and the light-emitting element is configured to emit light according to a drive current generated by the received data signal, wherein the drive time of the drive current is controlled by the duty cycle of the light-emitting control signal.

10. The display device as claimed in claim 1, characterized in that, The pixel enable ratio is the proportion of the number of pixels in the first frame of image data whose pixel value is greater than a preset pixel value to the total number of pixels in the first frame of image data.

Images