Managing programming operations in storage devices

Abstract

Example memory devices, systems, and methods for improving retention of memory cells during verify operations of a memory device. An example method includes a method of operating a memory device. The method includes programming a memory cell coupled to a first word line and verifying whether the memory cell is programmed to a program level of a plurality of program levels, including applying a verify voltage to the first word line and applying a first pass voltage to one or more second word lines adjacent to the first word line. The first pass voltage has a value lower than a value of a second pass voltage applied to the one or more second word lines when performing a read operation on the memory cell coupled to the first word line.

Description

Technical Field

[0001] This disclosure relates to storage devices, systems, and methods for erasure operations in storage devices. Background Technology

[0002] Flash memory is a low-cost, high-density, non-volatile solid-state storage medium that can be electrically erased and reprogrammed. Flash memory includes NOR flash memory and NAND flash memory. Various operations (e.g., programming and verification operations) can be performed on flash memory to change the threshold voltage of each memory cell to a corresponding level. For NAND flash memory, a verification operation is performed at the target word line after the programming operation. Summary of the Invention

[0003] This disclosure relates to storage devices, systems, and methods for erasure operations in storage devices.

[0004] One aspect of this disclosure is a method of operating a storage device. The method includes programming a memory cell coupled to a first word line. The method further includes verifying whether the memory cell is programmed to a programming level among a plurality of programming levels, which includes applying a verification voltage to the first word line; and applying a first pass voltage to one or more second word lines adjacent to the first word line, wherein the value of the first pass voltage is lower than the value of a second pass voltage applied to the one or more second word lines when a read operation is performed on the memory cell coupled to the first word line.

[0005] In some implementations, the programming level of the storage cell used to verify whether the storage cell is programmed to the programming level is equal to the programming level of the storage cell during the read operation of the storage cell.

[0006] In some implementations, verifying whether the memory cell is programmed to a programming level among multiple programming levels further includes applying a third pass voltage to the remaining word lines in the memory device, excluding the first word line and the one or more second word lines, wherein the value of the third pass voltage is equal to the value of a fourth pass voltage applied to the remaining word lines when the read operation is performed on the memory cell.

[0007] In some implementations, the first pass voltage is determined based on the verification voltage of the first word line, and the value of the first pass voltage decreases as the value of the verification voltage increases.

[0008] In some implementations, the plurality of programming levels are divided into a plurality of groups arranged in ascending order, wherein when verifying programming levels in the same group, the same value of the first through voltage is applied, and when verifying programming levels in a higher-order group, a lower value of the first through voltage is applied.

[0009] In some embodiments, the method further includes: determining the operating temperature of the storage device; and adjusting the value of the first through voltage corresponding to the operating temperature.

[0010] In some implementations, the value of the first through voltage decreases as the operating temperature increases.

[0011] In some implementations, the operating temperatures are divided into multiple groups arranged in ascending order, wherein when verifying whether the memory cell is programmed to the same programming level among the multiple programming levels, the same value of the first through voltage is applied when the operating temperature values ​​are in the same group, and the lower value of the first through voltage is applied when the operating temperature values ​​are in the group with a higher order.

[0012] In some implementations, the value of the first through voltage is further determined based on the number of programming cycles of the memory cell, wherein the value of the first through voltage increases as the number of programming cycles increases.

[0013] In some implementations, the minimum value of the first through voltage is greater than 5V.

[0014] Another aspect of this disclosure is a storage device. The storage device includes a memory cell array; and peripheral circuitry coupled to the memory cell array and configured to perform programming operations on the memory cell array. The programming operations include: programming memory cells in the memory cell array coupled to a first word line; verifying whether the memory cells are programmed to a programming level among a plurality of programming levels, including: applying a verification voltage to the first word line; and applying a first pass voltage to one or more second word lines adjacent to the first word line, wherein the value of the first pass voltage is lower than the value of a second pass voltage applied to the one or more second word lines when a read operation is performed on the memory cells coupled to the first word line.

[0015] In some implementations, the programming level of the storage cell used to verify whether the storage cell is programmed to the programming level is equal to the programming level of the storage cell during the read operation of the storage cell.

[0016] In some implementations, verifying whether the memory cell is programmed to a programming level among multiple programming levels further includes applying a third pass voltage to the remaining word lines in the memory device, excluding the first word line and the one or more second word lines, wherein the value of the third pass voltage is equal to the value of a fourth pass voltage applied to the remaining word lines when the read operation is performed on the memory cell.

[0017] In some implementations, the first pass voltage is determined based on the verification voltage of the first word line, wherein the value of the first pass voltage decreases as the value of the verification voltage increases.

[0018] In some implementations, the plurality of programming levels are divided into a plurality of groups arranged in ascending order, wherein when verifying programming levels in the same group, the same value of the first through voltage is applied, and when verifying programming levels in a higher-order group, a lower value of the first through voltage is applied.

[0019] In some embodiments, the storage device is further configured to: determine the operating temperature of the storage device; and adjust the value of the first through voltage corresponding to the operating temperature.

[0020] In some implementations, the value of the first through voltage decreases as the operating temperature increases.

[0021] In some implementations, the operating temperatures are divided into multiple groups arranged in ascending order, wherein when verifying whether the memory cell is programmed to the same programming level among multiple programming levels, the same value of the first through voltage is applied when the values ​​of the operating temperatures are in the same group, and the lower value of the first through voltage is applied when the values ​​of the operating temperatures are in the group with higher order.

[0022] In some implementations, the value of the first through voltage is further determined based on the number of programming cycles of the memory cell, wherein the value of the first through voltage increases as the number of programming cycles increases.

[0023] Another aspect of this disclosure features a storage system. The storage system includes a storage device and a memory controller coupled to and configured to control the storage device. The storage device includes a memory cell array; and peripheral circuitry coupled to and configured to perform programming operations on the memory cell array. The programming operations include: programming a memory cell coupled to a first word line; verifying whether the memory cell is programmed to a programming level among a plurality of programming levels, including: applying a verification voltage to the first word line; and applying a first pass voltage to one or more second word lines adjacent to the first word line, wherein the value of the first pass voltage is lower than the value of a second pass voltage applied to the one or more second word lines when a read operation is performed on the memory cell coupled to the first word line.

[0024] These and other aspects and details of the implementation of this disclosure are set forth in the accompanying drawings and the following description. Other features, objects, and advantages of this disclosure will be apparent from the specification, drawings, and claims. Attached Figure Description

[0025] Figure 1 Examples of schematic circuit diagrams of a storage device including peripheral circuitry, according to some aspects of this disclosure, are shown.

[0026] Figure 2 An example of a side view of a cross-section of a memory cell array including NAND memory strings, according to some aspects of this disclosure, is shown.

[0027] Figure 3 Examples of transactions between a host and a device are shown in accordance with some aspects of this disclosure.

[0028] Figure 4A An example threshold voltage distribution of a memory cell is shown in accordance with some aspects of this disclosure.

[0029] Figure 4B An example of a side view of a cross-section of a memory cell array according to some aspects of this disclosure is shown.

[0030] Figure 4C A 3D schematic diagram of a storage cell array 400c according to some aspects of this disclosure is shown.

[0031] Figure 4D Examples of charge retention with different spacing sizes of memory cell arrays are shown, according to some aspects of this disclosure.

[0032] Figure 4EExamples of charge retention with different programming levels of storage cells are shown, according to some aspects of this disclosure.

[0033] Figure 4F Examples of charge retention with different pass voltages applied to adjacent word lines during verification operations are shown, according to some aspects of this disclosure.

[0034] Figures 5A to 5B A graph illustrating an example effect of operating temperature on a first through voltage is shown, according to some aspects of this disclosure.

[0035] Figures 6A to 6B A graph illustrating the example effect of the operating cycle on the first through voltage is shown, according to some aspects of this disclosure.

[0036] Figure 7 An example flowchart of a method for verifying whether a memory cell has been programmed to a programming level among multiple programming levels, according to some aspects of this disclosure, is shown.

[0037] Figure 8 A block diagram of an example system with a storage device is shown, according to some aspects of this disclosure.

[0038] Figure 9A A diagram of a memory card with a storage device is shown, according to some aspects of this disclosure.

[0039] Figure 9B A diagram of a solid-state drive (SSD) with a storage device is shown, according to some aspects of this disclosure.

[0040] The same reference numerals and symbols in the various figures indicate the same elements. Detailed Implementation

[0041] Due to the demand for cheaper storage devices with higher density, storage devices (e.g., 3D NAND flash memory) can be formed with a large number of layers and a high aspect ratio. The large number of layers and high aspect ratio of such storage devices can pose challenges to device retention during programming operations. For example, during the verification operation of the storage device, a pass voltage is applied to a word line adjacent to a selected word line. A high pass voltage can affect the retention of the memory cells coupled to the selected word line. In other words, a high pass voltage can affect the programming level of the memory cells coupled to the selected word line during verification operations.

[0042] Embodiments of this disclosure can provide one or more of the following technical effects. For example, the pass voltage applied to a word line adjacent to a selected word line is based on the programming level of the memory cell coupled to the selected word line. The pass voltage can be further adjusted based on the operating temperature and number of operating cycles of the memory cell. Therefore, changing the pass voltage on adjacent word lines during the verification process of the memory device can improve the retention of the memory cell in the selected word line by mitigating the charge loss effect during the verification process.

[0043] Figure 1 An example of a schematic circuit diagram of a storage device 100 including peripheral circuitry according to some aspects of this disclosure is shown. The storage device 100 may include a storage cell array 101 and peripheral circuitry 102 coupled to the storage cell array 101. The storage cell array 101 may be a NAND flash memory storage cell array, wherein storage cells 106 are provided in the form of an array of NAND storage strings 108, each extending vertically above a substrate (not shown). In some embodiments, each NAND storage string 108 includes a plurality of storage cells 106 coupled in series and stacked vertically. Each storage cell 106 may hold a continuous analog value (such as voltage or charge) depending on the number of electrons trapped in the region of the storage cell 106. Each storage cell 106 may be a floating-gate type storage cell including a floating-gate transistor, or a charge-trapping type storage cell including a charge-trapping transistor.

[0044] In some implementations, each memory cell 106 is a single-level cell (SLC) having two possible storage states and thus capable of storing one bit of data. For example, a first storage state "0" may correspond to a first voltage range, and a second storage state "1" may correspond to a second voltage range. In some implementations, each memory cell 106 is a multi-level cell (MLC) capable of storing more than one bit of data in more than four storage states. For example, an MLC may store two bits per cell, three bits per cell (also known as a three-level cell (TLC)), or four bits per cell (also known as a four-level cell (QLC)). Each MLC can be programmed to take a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed from an erase state to take one of three possible programming levels by writing one of the three possible nominal storage values ​​to the cell. A fourth nominal storage value can be used for the erase state.

[0045] like Figure 1As shown, each NAND flash memory string 108 may include a source select gate (SSG) 110 at its source end and a drain select gate (DSG) 112 at its drain end. SSG 110 and DSG 112 can be configured to activate the selection of the NAND flash memory string 108 (column of the array) during read and program operations. In some embodiments, the sources of the NAND flash memory strings 108 in the same block 104 are coupled via the same source line (SL) 114 (e.g., a common SL). In other words, according to some embodiments, all NAND flash memory strings 108 in the same block 104 have an array common source (ACS). According to some embodiments, the DSG 112 of each NAND flash memory string 108 is coupled to a corresponding bit line 116 from which data can be read or written via an output bus (not shown). In some implementations, each NAND storage string 108 is configured to be selected or deselected by applying a selection voltage or deselection voltage (e.g., 0V) to the corresponding DSG 112 via one or more DSG lines 113 and / or by applying a selection voltage or deselection voltage (e.g., 0V) to the corresponding SSG 110 via one or more SSG lines 115.

[0046] like Figure 1 As shown, NAND memory strings 108 can be organized into multiple blocks 104, each block 104 may have a common source line 114, for example, coupled to the ACS. In some implementations, each block 104 is the basic data unit for an erase operation, i.e., all memory cells 106 on the same block 104 are erased simultaneously. To erase memory cells 106 in a selected block 104, the source line 114 coupled to the selected block 104 and unselected blocks 104 located in the same plane as the selected block 104 can be biased with an erase voltage (Vers) (such as a high positive voltage (e.g., 20V or higher)). In some examples, the erase operation can be performed at the half-block level, quarter-block level, or at the level of any suitable number of blocks or any suitable fraction of blocks. Memory cells 106 of adjacent NAND memory strings can be coupled via word lines 118, which select which row of memory cells 106 is affected by read and program operations. Each word line 118 may include multiple control gates (gate electrodes) at each memory cell 106 and gate lines coupled to the control gates. Figure 1 The example word lines (WL) shown include dummy WL, WL1, WL2, WL3, WL4 and WL5 between one or more DSG lines 113 and one or more SSG lines 115.

[0047] Figure 2 An example of a cross-sectional side view of a memory cell array 101 including NAND memory strings 108 is shown, according to some aspects of this disclosure. (See example...) Figure 2 As shown, the NAND memory string 108 may extend vertically through the memory stack 204 above the substrate 202. The substrate 202 may include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0048] The memory stack 204 may include interleaved gate conductive layers 206 and gate-gate dielectric layers 208. The number of pairs of gate conductive layers 206 and gate-gate dielectric layers 208 in the memory stack 204 determines the number of memory cells 106 in the memory cell array 101. The gate conductive layers 206 may include conductive materials, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, or silicides or any combination thereof. In some embodiments, each gate conductive layer 206 includes a metal layer, such as a tungsten layer. In some embodiments, each gate conductive layer 206 includes a doped polysilicon layer. Each gate conductive layer 206 may include a control gate surrounding the memory cell 106, DSG 112, or SSG 110, and may extend laterally as a DSG line 113 at the top of the memory stack 204, an SSG line 115 at the bottom of the memory stack 204, or a word line 118 between DSG line 113 and SSG line 115.

[0049] Peripheral circuitry 102 can be coupled to memory cell array 101 via bit line 116, word line 118, source line 114, SSG line 115, and DSG line 113. Peripheral circuitry 102 may include any suitable analog, digital, and mixed-signal circuitry for facilitating operation of memory cell array 101 by applying voltage and / or current signals to each target memory cell in memory cell 106 via bit line 116, word line 118, source line 114, SSG line 115, and DSG line 113, and sensing voltage and / or current signals from each target memory cell. Peripheral circuitry 102 may include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 3 Some example peripheral circuitry according to certain aspects of this disclosure is shown. The example peripheral circuitry includes a page buffer / sensor amplifier 304, a column decoder / bit line driver 306, a row decoder / word line driver 308, a voltage generator 310, control logic 312, a register 314, an interface 316, and a data bus. In some examples, it may also include... Figure 3 Additional peripheral circuitry not shown.

[0050] Page buffer / sensor amplifier 304 can be configured to read data from memory cell array 101 and program (write) data to memory cell array 101 according to control signals from control logic 312. In one example, page buffer / sensor amplifier 304 can store one page of programming data (write data) to be programmed into memory cell array 101. In another example, page buffer / sensor amplifier 304 can perform a programming verification operation to ensure that data has been correctly programmed into memory cell 106 coupled to selected word line 118. In yet another example, page buffer / sensor amplifier 304 can also sense a low-power signal from bit line 116 representing data bits stored in memory cell 106 and amplify small voltage swings to a recognizable logic level during read operations. Column decoder / bit line driver 306 can be configured to be controlled by control logic 312 and select one or more NAND memory strings 108 by applying a bit line voltage generated from voltage generator 310.

[0051] The row decoder / word line driver 308 can be configured to be controlled by control logic 312 and to select / deselect block 104 of memory cell array 101 and select / deselect word line 118 of block 104. The row decoder / word line driver 308 can also be configured to drive word line 118 using word line voltage generated from voltage generator 310. In some embodiments, the row decoder / word line driver 308 can also select / deselect and drive SSG line 115 and DSG line 113. The row decoder / word line driver 308 can be configured to apply a read voltage to the selected word line 118 during read operations on memory cells 106 coupled to the selected word line 118.

[0052] Voltage generator 310 can be configured to be controlled by control logic 312 and generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to memory cell array 101.

[0053] Control logic 312 can be coupled to each of the aforementioned peripheral circuits and configured to control the operation of each peripheral circuit. Register 314 can be coupled to control logic 312 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. The status register of register 314 may include one or more registers configured to store open block information (e.g., a list with Automatic Dynamic Start Voltage (ADSV)) indicating open blocks in all blocks 104 of the memory cell array 101. In some embodiments, the open block information also indicates the last programmed page of each open block.

[0054] Interface 316 can be coupled to control logic 312 and act as a control buffer to buffer and relay control commands received from the host (not shown) to control logic 312, and to buffer and relay status information received from control logic 312 to the host. Interface 316 can also be coupled to column decoder / bit line driver 306 via a data bus and act as a data input / output (I / O) interface and data buffer to buffer and relay data to and from memory cell array 101.

[0055] Figure 4A An example threshold voltage distribution of a memory cell according to some aspects of this disclosure is shown. In some embodiments, memory cell 106 may be a TLC 402. TLC 402 may include eight levels, and memory cell 106 may be programmed to one of eight levels (including one level of erase state and seven levels of programmable states). Each level may correspond to a corresponding threshold voltage range of the memory cell. For example, the lowest threshold voltage range of TLC 402 (… Figure 4A The level corresponding to the leftmost threshold voltage distribution in the diagram can be considered as level 0.406, and the second lowest threshold voltage range ( Figure 4A The level corresponding to the second-to-last threshold voltage distribution in the range can be considered as level 1,408, and so on, until the highest threshold voltage range ( Figure 4A The rightmost threshold voltage distribution in the table corresponds to level 7410. In some embodiments, memory cell 106 may be a QLC 404. QLC 404 may include 16 levels, and memory cell 106 may be programmed to one of 16 levels (including one level of erase state and 15 levels of programmable state). Each level may correspond to a corresponding threshold voltage range of the memory cell. For example, the lowest threshold voltage range of QLC 404 ( Figure 4A The level corresponding to the leftmost threshold voltage distribution in the diagram can be considered as level 0.412, and the second lowest threshold voltage range ( Figure 4A The level corresponding to the second-to-last threshold voltage distribution in the range can be considered as level 1, 414, and so on, until the highest threshold voltage range ( Figure 4A The rightmost threshold voltage distribution in the diagram corresponds to level 15, 416. In some implementations (not shown in Figure 4), the memory cell can be a single-level cell (SLC), a multi-level cell (MLC) with four levels, or a five-level cell (PLC) with 32 levels.

[0056] Figure 4BAn example of a side view of a cross-section of a memory cell array 400b according to some aspects of this disclosure is shown. The memory cell array 400b and... Figure 2 The memory cell array 101 is similar to or identical to the memory cell array 106. The memory cell array may include word lines 418, 420, and 422 coupled to the memory cells 106. In some embodiments, word lines 418, 410, and 422 may be similar to or identical to the memory cell array 106. Figure 2 The gate conductive layer 206 of the memory cell array 101 is similar or identical. In some embodiments, the peripheral circuitry 102 coupled to the memory cell array 101 is configured to perform a programming operation on a selected memory cell 106 coupled to a first word line 418. The programming operation includes programming the selected memory cell 106 to a programming level and verifying whether the memory cell 106 is programmed to a programming level among a plurality of programming levels. In some embodiments, verifying whether the memory cell 106 is programmed to a programming level among a plurality of programming levels includes applying a verification voltage to the first word line 418 and applying a first pass voltage to one or more second word lines 420 adjacent to the first word line 418. In some embodiments, the value of the first pass voltage is lower than the value of a second pass voltage applied to one or more second word lines 420. When a read operation is performed on the memory cell 106 coupled to the first word line 418, a second pass voltage is applied to one or more second word lines 420. In some implementations, the programming level of the memory cell 106 coupled to the first word line 418 is equal to the programming level of the memory cell 106 coupled to the first word line 418 during a read operation, used to verify whether the memory cell 106 is programmed to a programming level among a plurality of programming levels. For example, as Figure 4A As shown, memory cell 106 is a QLC 404 and is programmed to level 15416. When verifying whether memory cell 106 of the first word line 418 is programmed to level 15416, a first pass voltage is applied to one or more second word lines 420. When a read operation is performed on memory cell 106, a second pass voltage is applied to one or more second word lines 420. The read operation is performed to determine whether memory cell 106 of the first word line 418 is programmed to level 15. The first pass voltage is less than the second pass voltage. In some embodiments, such as Figure 4B As shown, the first letter 418 is located between one or more second letter 420 along a vertical direction (e.g., the Z direction).

[0057] In some embodiments, verifying whether memory cell 106 is programmed to a programming level among multiple programming levels includes applying a third pass voltage to one or more remaining word lines 422 of memory cell array 101. In some embodiments, the one or more remaining word lines 422 may be one or more word lines that are not adjacent to the first word line 418. For example, as Figure 4BAs shown, one of the second character lines 420 can be between the first character line 418 and the remaining character lines 422. Figure 4B As shown, the remaining word line 422 is the word line in the memory cell array 101 excluding the first word line 418 and one or more second word lines 420. In some embodiments, the value of the third pass voltage is equal to the value of the fourth pass voltage applied to the remaining word line 422 when a read operation is performed on the memory cell 106 coupled to the first word line 418. In some embodiments, the first pass voltage is determined based on the verification voltage of the first word line 418. In some embodiments, the value of the first pass voltage decreases as the value of the verification voltage increases. In some other embodiments, multiple programming levels are divided into multiple groups arranged in ascending order, wherein the same value of the first pass voltage is applied when verifying programming levels in the same group, and a lower value of the first pass voltage is applied when verifying programming levels in a higher-order group. In some embodiments, the value of the first pass voltage is greater than the highest threshold voltage of the corresponding programming level of the memory cell. In some embodiments, the first pass voltage is applied to memory cells coupled to one or more second word lines 420 to ensure accurate verification operation of memory cells coupled to the first word line 418. In some implementations, as the programming level of the memory cell coupled to the first word line 418 increases, the first through voltage decreases. This decrease in the first through voltage can reduce the impact of retention degradation on the memory cell coupled to the first word line 418, such as... Figure 4F As shown.

[0058] Figure 4C A 3D schematic diagram of a memory cell array 400c according to some aspects of this disclosure is shown. The memory cell array 400c and... Figure 2 Storage cell array 101 or Figure 4BThe memory cell array 400b is similar to or identical to the memory cell array 400c. The memory cell array 400c may include word lines 424 and 426 connected to the channel structure 428. In some embodiments, word line 424 is coupled to a memory cell 106 selected for programming, and word line 426 is adjacent to word line 424 in the memory cell array 400c. In some examples, the channel structure 428 may be cylindrical or pillar-shaped and may include a core-filling layer 429a surrounded by a tunneling layer 429b, a charge-trapping layer 429c, and a barrier layer 429d. In some embodiments, the core-filling layer 429a may include silicon, such as amorphous silicon, polycrystalline silicon, or monocrystalline silicon; the tunneling layer 429b may include silicon oxide, silicon nitride, or any combination thereof; the barrier layer 429d may include silicon oxide, silicon nitride, a high-k dielectric, or any combination thereof; and the charge-trapping layer 429c may include silicon nitride, silicon oxynitride, silicon, or any combination thereof. In some embodiments, the tunneling layer 429b, charge trapping layer 429c, and barrier layer 429d (collectively referred to as the memory film) may include an ONO dielectric (silicon oxide-silicon nitride-silicon oxide). In some embodiments, such as Figure 4C As shown, two adjacent word lines 424 and 426 are separated by a dielectric layer 430. In some embodiments, the dielectric layer 430 is filled with a dielectric material. In some embodiments, the dielectric layer 430 may be... Figure 2 The gate-to-gate dielectric layer 208 is similar to or identical to the gate-to-gate dielectric layer 208. In some embodiments, the spacing of the memory cell array 400c is defined by the ratio between the thickness of the word line 424 along the Z direction and the thickness of the dielectric layer 430. In some embodiments, the charge trapping layer 429c stores multiple programming levels of the memory cell 106 (similar to...). Figure 4A The charge corresponding to the programming level, and the retention of the charge in the charge trapping layer 429c of the memory cell 106 coupled to the word line 424 corresponds to the spacing size of the memory cell array 400c, such as Figure 4D As shown. In some implementations, such as Figure 4C As shown, the spacing dimension of the memory cell array 400c refers to the ratio between the thickness of the word line 424 along the Z direction and the thickness of the dielectric layer 430. A decrease in the spacing dimension may lead to an increase in retention degradation due to charge tunneling through the dielectric layer 430.

[0059] Figure 4D Examples of charge retention with different spacing sizes of a memory cell array 400c according to some aspects of this disclosure are shown. For example... Figure 4D As shown, as the spacing of the memory cell array 400c decreases, the degradation of charge retention increases. In some embodiments, the degradation of charge retention may lead to an increase in the failure bit count during read operations of the memory cell 106 coupled to the word line 424.

[0060] Figure 4E Examples of charge retention with different programming levels of memory cells according to some aspects of this disclosure are shown. In some embodiments, such as Figure 4E As shown, the charge retention of memory cells coupled to selected word line 424 is strongly correlated with the programming level of memory cells coupled to adjacent word line 426.

[0061] For example, such as Figure 4E As shown, memory cells coupled to a selected word line 424 and two adjacent word lines 426 are programmed to a programmable-programmable-programmable (PPP) mode 432, wherein the programming level of the memory cells coupled to the adjacent word lines 426 is higher than the programming level of the memory cells coupled to the selected word line 424. For example, if the memory cells coupled to the selected word line 424 are a TLC 402 that may include eight levels. The memory cells coupled to the selected word line 424 are programmed to programming level P2, and the memory cells coupled to the adjacent word lines 426 are programmed to programming level P5, wherein the threshold voltage value corresponding to the programming level P2 of the memory cells coupled to the selected word line 424 is lower than the threshold voltage value corresponding to the programming level P5 of the memory cells coupled to the adjacent word lines 426. After charge retention in PPP mode 432, the threshold voltage of the memory cells coupled to the selected word line 424 decreases from a first threshold voltage 436 to a second threshold voltage 440.

[0062] In some implementations, such as Figure 4E As shown, memory cells coupled to a selected word line 424 and two adjacent word lines 426 are programmed in an erase-program-erase (EPE) mode 434, wherein the programming level of the memory cells coupled to the adjacent word lines 426 is lower than the programming level of the memory cells coupled to the selected word line 424. For example, if the memory cells coupled to the selected word line 424 are a TLC 402 that may include eight levels. The memory cells coupled to the selected word line 424 are programmed to programming level P2, and the memory cells coupled to the adjacent word lines 426 are programmed to erase level P0, wherein the threshold voltage value corresponding to the programming level P2 of the memory cells coupled to the selected word line 424 is greater than the threshold voltage value corresponding to the erase level P0 of the memory cells coupled to the adjacent word lines 426. After charge retention in EPE mode 434, the threshold voltage of the memory cells coupled to the selected word line 424 decreases from a third threshold voltage 438 to a fourth threshold voltage 442. The difference between the third threshold voltage 438 and the fourth threshold voltage 442 is greater than the difference between the first threshold voltage 436 and the second threshold voltage 440.

[0063] In some implementations, when a memory cell of an adjacent word line 426 is programmed to a lower programming level (compared to the programming level of a memory cell coupled to a selected word line 424), the larger downshift effect of the memory cell coupled to the selected word line 424 causes a larger difference between the third threshold voltage 438 and the fourth threshold voltage 442 of the EPE mode 434.

[0064] Figure 4F Examples of charge retention with different pass voltages applied to adjacent word lines during a verification operation are shown according to some aspects of this disclosure. In some embodiments, a verification operation is performed on a memory cell coupled to a selected word line 424 to verify whether the memory cell has been programmed to a selected programming level among a plurality of programming levels after a programming operation. The programming operation of the memory cell coupled to the selected word line 424 programs the memory cell to the selected programming level among a plurality of programming levels. During the verification operation, a verification pass voltage is applied to adjacent word lines 426.

[0065] For example, in case 444, such as Figure 4F As shown, a first verification pass voltage is applied to the adjacent word line 426, wherein the first verification voltage is equal to the first read pass voltage applied to the adjacent word line 426 during a read operation of the memory cell. After charge retention, the first threshold voltage 436 of the first case 444 corresponding to PPP mode 432 decreases to the second threshold voltage 440, and the third threshold voltage 438 of the first case 444 corresponding to EPE mode 434 decreases to the fourth threshold voltage 442.

[0066] In another example, under case 446, such as Figure 4F As shown, a second verification pass voltage is applied to adjacent word line 426, wherein the second verification pass voltage is lower than the first read pass voltage applied to adjacent word line 426 during a read operation of a memory cell. After charge retention, the first threshold voltage 436b of the second case 446 corresponding to PPP mode 432 decreases to a second threshold voltage 440b, and the third threshold voltage 438b of the second case 446 corresponding to EPE mode 434 decreases to a fourth threshold voltage 442b. The difference between the third threshold voltage 438b and the fourth threshold voltage 442b of the second case 446 is lower than the difference between the third threshold voltage 438 and the fourth threshold voltage 442 of the first case 444. In some embodiments, the lower second verification pass voltage allows programming of the higher third threshold voltage 438b of the EPE mode 434 of the second case 446 during a programming operation of a memory cell coupled to the selected word line 424. In some implementations, in the second case 446, the value of the third threshold voltage 438b of the EPE mode 434 is slightly higher than the value of the first threshold voltage 436b of the PPP mode 432, which helps to reduce, for example, Figure 4B The downgrade is maintained as shown.

[0067] In some implementations, the smaller difference between the threshold voltages of the two modes 432 and 434 represents an improvement in charge retention of the memory cell coupled to the selected word line 424, where the verification pass voltage is lower than the read pass voltage applied to the adjacent word line 426 during verification or read operations. This improvement in charge retention results in a lower failure bit count during operation of the memory cell.

[0068] Figures 5A to 5B Figure 500 illustrates an example effect of operating temperature on a first pass voltage according to some aspects of this disclosure. In some embodiments, peripheral circuitry 102 may include a temperature sensor configured to determine the operating temperature of memory cell 106 coupled to first word line 418, and control logic 312 of peripheral circuitry 102 is configured to adjust the first pass voltage corresponding to the operating temperature. In some embodiments, the value of the first pass voltage decreases as the operating temperature increases. In some embodiments, the operating temperatures are divided into multiple groups arranged in ascending order, wherein when verifying whether a memory cell is programmed to the same programming level among multiple programming levels, the same value of the first pass voltage is applied to second word line 420 when the operating temperature values ​​are in the same group, and a lower value of the first pass voltage is applied to second word line 420 when the operating temperature values ​​are in a higher-order group. In some embodiments, the operating temperature range is -40°C to 100°C. In some embodiments, such as Figure 5A As shown, the value of the first through voltage is further determined based on the verification voltage of the first word line 418 at the same operating temperature, wherein the value of the first through voltage decreases as the programming level increases. For example, as Figure 5A As shown, the temperature of the first operating temperature 502 is lower than the temperature of the second operating temperature 504. The temperature of the second operating temperature 504 is lower than the temperature of the third operating temperature 506. At the same programming level, the value of the first pass voltage applied to the second word line 420 for the third operating temperature 506 is lower than the value of the first pass voltage applied to the second word line 420 for the second operating temperature 504 and the first operating temperature 502. In some embodiments, such as Figure 5B As shown, multiple programming levels are divided into multiple groups 508 arranged in ascending order. When verifying programming levels in the same group 508a, the same first through voltage is applied to the second word line 420. When verifying programming levels in a higher-order group 508b at the same operating temperature, a lower first through voltage is applied to the second word line 420. For example, as Figure 5BAs shown, the memory cell 106 coupled to the first word line 418 can be a QLC 404, and the multiple programming levels of the QLC 404 are divided into three groups 508a, 508b, and 508c in ascending order. At the same group 508a, 508b, and 508c of the multiple programming levels, the value of the first pass voltage applied to the second word line 420 for the third operating temperature 506 is lower than the value of the first pass voltage applied to the second word line 420 for the second operating temperature 504 and the first operating temperature 502.

[0069] Figures 6A to 6B A graph illustrating the example effect of operating cycles on a first through voltage according to some aspects of this disclosure is shown. In some embodiments, control logic 312 of peripheral circuitry 102 is configured to determine the number of programming cycles of memory cell 106 coupled to first word line 418. In some embodiments, the value of the first through voltage is further determined based on the number of programming cycles of memory cell 106 coupled to first word line 418, wherein the value of the first through voltage increases as the number of programming cycles increases. In some embodiments, such as Figure 6A As shown, the value of the first through voltage is further determined based on the verification voltage of the first word line 418 under the same number of programming cycles, wherein the value of the first through voltage decreases as the programming level increases. For example, as Figure 6A As shown, the number of first programming cycles 602 is less than the number of second programming cycles 604. The number of programming cycles 604 is less than the number of third programming cycles 606. At the same programming level, the value of the first pass voltage applied to the second word line 420 for the third programming cycle 606 is higher than the value of the first pass voltage for the second programming cycle 604 and the first programming cycle 602. In some embodiments, such as Figure 6B As shown, multiple programming levels are divided into multiple groups 608 arranged in ascending order. When verifying programming levels in the same group 608a, the same first pass voltage is applied to the second word line 420. When verifying programming levels in a higher-order group 608b at the same number of programming cycles, a lower first pass voltage is applied to the second word line 420. For example, as Figure 6B As shown, the memory cell 106 coupled to the first word line 418 can be a QLC 404, and the multiple programming levels of the QLC 404 are divided into three groups 608a, 608b, and 608c in ascending order. At the same groups 608a, 608b, and 608c of the multiple programming levels, the value of the first pass voltage applied to the second word line 420 for the third programming cycle 606 is higher than the value of the first pass voltage applied to the second word line 420 for the second programming cycle 604 and the first programming cycle 602.

[0070] Figure 7An example process 700 for operating a storage device according to some aspects of this disclosure is shown.

[0071] At operation 702, the memory device is coupled to the first word line (e.g., ...). Figure 4B The storage unit of the first word line 418 (e.g., Figure 1 The storage unit 106 is programmed.

[0072] At operation 704, the storage device verifies whether the storage cell has been programmed to a programming level among multiple programming levels, wherein operations include operations 706 and 708.

[0073] At operation 706, the memory device applies a verification voltage to the first word line.

[0074] At operation 708, the storage device directs data to one or more second word lines adjacent to the first word line (e.g., ...). Figure 4B A first pass voltage is applied to the second word line 420, wherein the value of the first pass voltage is lower than the value of the second pass voltage applied to one or more second word lines when a read operation is performed on a memory cell coupled to the first word line.

[0075] In some implementations, the programming level of the storage cell used to verify whether the storage cell is programmed to the programming level is equal to the programming level of the storage cell during a read operation of the storage cell.

[0076] In some implementations, verifying whether a memory cell has been programmed to a programming level among multiple programming levels further includes: programming the remaining word lines in the memory device (e.g., besides the first word line and one or more second word lines) to the programming level. Figure 4B A third pass voltage is applied to the remaining word line 422, wherein the value of the third pass voltage is equal to the value of the fourth pass voltage applied to the remaining word line when a read operation is performed on the memory cell.

[0077] In some implementations, the first pass voltage is determined based on the verification voltage of the first word line, wherein the value of the first pass voltage decreases as the value of the verification voltage increases.

[0078] In some implementations, multiple programming levels are divided into multiple groups arranged in ascending order, wherein when verifying programming levels in the same group, the same value of the first through voltage is applied, and when verifying programming levels in a higher-order group, a lower value of the first through voltage is applied.

[0079] In some embodiments, the operation further includes: determining the operating temperature of the storage device; and adjusting the value of a first through voltage corresponding to the operating temperature.

[0080] In some implementations, the value of the first through voltage decreases as the operating temperature increases.

[0081] In some implementations, the operating temperatures are divided into multiple groups arranged in ascending order, wherein when verifying whether the memory cell is programmed to the same programming level among multiple programming levels, the same value of the first through voltage is applied when the operating temperature values ​​are in the same group, and the lower value of the first through voltage is applied when the operating temperature values ​​are in the group with a higher order.

[0082] In some implementations, the value of the first through voltage is further determined based on the number of programming cycles of the memory cell, wherein the value of the first through voltage increases as the number of programming cycles increases.

[0083] In some implementations, the minimum value of the first through voltage is greater than 5V.

[0084] Figure 8 A block diagram of an example system 800 with storage devices according to some aspects of this disclosure is shown. System 800 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage devices therein. Figure 8 As shown, system 800 may include a host 808 and a memory system 802 having one or more storage devices 804 and a memory controller 806. The host 808 may be a processor (such as a central processing unit (CPU)) or a system-on-a-chip (SoC) (such as an application processor (AP)). The host 808 may be configured to send data to or receive data from storage device 804.

[0085] Storage device 804 can be any storage device disclosed herein. According to some embodiments, memory controller 806 is coupled to storage device 804 and host 808 and configured to control storage device 804. Memory controller 806 can manage data stored in storage device 804 and communicate with host 808. In some embodiments, memory controller 806 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, Compact Flash (CF) card, Universal Serial Bus (USB) flash drive, or other media for electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, memory controller 806 is designed to operate in a high duty cycle environment, in an SSD or embedded multimedia card (eMMC), for data storage in mobile devices such as smartphones, tablets, laptops, etc., and enterprise storage arrays. Memory controller 806 can be configured to control the operation of storage device 804, such as read, erase, and program operations. The memory controller 806 can also be configured to manage various functions relating to data stored or to be stored in the storage device 804, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 806 is also configured to handle error correction codes (ECC) relating to data read from or written to the storage device 804. Any other suitable functions may also be performed by the memory controller 806, such as formatting the storage device 804.

[0086] The memory controller 806 can communicate with an external device (e.g., the host 808) according to a specific communication protocol. For example, the memory controller 806 can communicate with the external device through at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-E, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, etc.

[0087] The memory controller 806 and one or more storage devices 804 can be integrated into various types of storage devices, for example, included in the same package, such as a Universal Flash Memory (UFS) package or an eMMC package. That is, the storage system 802 can be implemented and packaged into different types of end electronic products. Figure 9AIn one example shown, the memory controller 806 and a single storage device 804 can be integrated into a memory card 902. The memory card 902 can include PC cards (PCMCIA, Personal Computer Memory Card International Association), CF cards, Smart Media (SM) cards, Memory Sticks, Multimedia Cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 902 may further include a connection between the memory card 902 and a host (e.g., Figure 8 The memory card connector 904 is coupled to the host 808. In such a... Figure 9B In another example shown, the memory controller 806 and multiple storage devices 804 may be integrated into the SSD 906. The SSD 906 may also include an SSD connector 908 that couples the SSD 906 to a host (e.g., host 808 in FIG. 6). In some embodiments, the storage capacity and / or operating speed of the SSD 906 is greater than the storage capacity and / or operating speed of the memory card 902.

[0088] While this specification contains numerous details of specific embodiments, these should not be construed as limiting the scope of the claims, but rather as descriptions of features specific to particular embodiments. Certain features described herein in the context of individual embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. Furthermore, although previously described features may be described as functioning in certain combinations and even initially claimed, in some cases, one or more features from the claimed combination may be removed from the combination, and the claimed combination may be for sub-combinations or variations thereof.

[0089] As used in this disclosure, unless the context clearly indicates otherwise, the terms “a,” “an,” or “the” are used to include one or more. Unless otherwise indicated, the term “or” is used to mean a non-exclusive “or.” The phrase “at least one of A and B” has the same meaning as “A, B, or A and B.” Furthermore, all wording and terms used in this disclosure unless otherwise defined are for descriptive purposes only and not for limitation. Any use of section headings is intended to aid in reading the document and is not to be construed as restrictive; information relating to a section heading may appear within or outside that particular section.

[0090] As used in this disclosure, the terms “about” or “approximately” may allow for a degree of variability in a value or range, for example, within 10% of a specified value, within 1% of a specified value, or within a specified limit of a range.

[0091] As used in this disclosure, the term “substantially” means the majority or most, at least about 50%, 60%, 70%, 80%, 90%, 95%, 96%, 97%, 98%, 99%, 99.5%, 99.9%, 99.99%, or at least about 99.999% or higher.

[0092] Values ​​expressed in range format should be interpreted flexibly to include not only the numerical values ​​explicitly stated as the limits of the range, but also all individual numerical values ​​or subranges contained within that range, as if each numerical value and subrange were explicitly stated. For example, the range “0.1% to about 5%” or “0.1% to 5%” should be interpreted to include about 0.1% to about 5%, as well as the individual values ​​(e.g., 1%, 2%, 3%, and 4%) and subranges (e.g., 0.1% to 0.5%, 1.1% to 2.2%, 3.3% to 4.4%) within the indicated range. Unless otherwise stated, the statement “X to Y” has the same meaning as “about X to about Y”. Similarly, unless otherwise stated, the statement “X, Y, or Z” has the same meaning as “about X, about Y, or about Z”.

[0093] Specific embodiments of the subject matter have been described. Other embodiments, variations, and arrangements of the described embodiments are within the scope of the appended claims and will be apparent to those skilled in the art. Although operations are depicted in a specific order in the drawings or claims, such operations need not be performed in the specific order shown or in a sequential order, or all shown operations need to be performed (some operations may be considered optional) to achieve the desired result. In some cases, multitasking or parallel processing (or a combination of multitasking and parallel processing) may be advantageous and considered appropriate.

[0094] Furthermore, not all implementations require the separation or integration of the various system modules and components described in the previously described implementations, and the described components and systems can generally be integrated together or packaged into multiple products.

[0095] Therefore, the exemplary embodiments described above do not limit or restrict the scope of this disclosure. Other changes, substitutions, and modifications are possible without departing from the spirit and scope of this disclosure.

Claims

1. A method of operating a storage device, comprising: Program the memory cells coupled to the first word line; Verifying whether the memory cell has been programmed to a programming level among multiple programming levels includes: Apply a verification voltage to the first word line; and A first pass voltage is applied to one or more second word lines adjacent to the first word line, wherein the value of the first pass voltage is lower than the value of a second pass voltage applied to the one or more second word lines when a read operation is performed on the memory cell coupled to the first word line.

2. The method according to claim 1, wherein, The programming level of the storage cell used to verify whether the storage cell has been programmed to the programming level is equal to the programming level of the storage cell during the read operation of the storage cell.

3. The method according to claim 1 or 2, wherein, Verifying whether the storage unit has been programmed to a programming level among multiple programming levels further includes: A third pass voltage is applied to the remaining word lines in the storage device, excluding the first word line and the one or more second word lines, wherein the value of the third pass voltage is equal to the value of the fourth pass voltage applied to the remaining word lines when the read operation is performed on the storage cell.

4. The method according to any one of claims 1 to 3, wherein, The first pass voltage is determined based on the verification voltage of the first word line. When the value of the verification voltage increases, the value of the first pass voltage decreases.

5. The method according to any one of claims 1 to 4, wherein, The multiple programming levels are divided into multiple groups arranged in ascending order, wherein when verifying programming levels in the same group, the same value of the first through voltage is applied, and when verifying programming levels in a higher-order group, a lower value of the first through voltage is applied.

6. The method according to any one of claims 1 to 5, further comprising: Determine the operating temperature of the storage device; as well as Adjust the value of the first through voltage corresponding to the operating temperature.

7. The method according to any one of claims 1 to 6, wherein, As the operating temperature increases, the value of the first through voltage decreases.

8. The method according to any one of claims 1 to 7, wherein, The operating temperatures are divided into multiple groups arranged in ascending order. When verifying whether the memory cell is programmed to the same programming level among the multiple programming levels, if the operating temperature values ​​are in the same group, the same value of the first through voltage is applied, and if the operating temperature values ​​are in a group with a higher order, a lower value of the first through voltage is applied.

9. The method according to any one of claims 1 to 8, wherein, The value of the first through voltage is further determined based on the number of programming cycles of the memory cell, wherein the value of the first through voltage increases as the number of programming cycles increases.

10. The method according to any one of claims 1 to 9, wherein, The minimum value of the first voltage is greater than 5V.

11. A storage device, comprising: Storage cell array; as well as Peripheral circuitry, coupled to the memory cell array and configured to perform programming operations on the memory cell array, the programming operations including: Programming the memory cells in the memory cell array that are coupled to the first word line; Verifying whether the memory cell has been programmed to a programming level among multiple programming levels includes: Apply a verification voltage to the first word line; and A first pass voltage is applied to one or more second word lines adjacent to the first word line, wherein the value of the first pass voltage is lower than the value of a second pass voltage applied to the one or more second word lines when a read operation is performed on the memory cell coupled to the first word line.

12. The storage device according to claim 11, wherein, The programming level of the storage cell used to verify whether the storage cell has been programmed to the programming level is equal to the programming level of the storage cell during the read operation of the storage cell.

13. The storage device according to claim 11 or 12, wherein, Verifying whether the storage unit has been programmed to a programming level among multiple programming levels further includes: A third pass voltage is applied to the remaining word lines in the storage device, excluding the first word line and the one or more second word lines, wherein the value of the third pass voltage is equal to the value of the fourth pass voltage applied to the remaining word lines when the read operation is performed on the storage cell.

14. The storage device according to any one of claims 11 to 13, wherein, The first pass voltage is determined based on the verification voltage of the first word line, wherein the value of the first pass voltage decreases as the value of the verification voltage increases.

15. The storage device according to any one of claims 11 to 14, wherein, The multiple programming levels are divided into multiple groups arranged in ascending order, wherein when verifying programming levels in the same group, the same value of the first through voltage is applied, and when verifying programming levels in a higher-order group, a lower value of the first through voltage is applied.

16. The storage device according to any one of claims 11 to 15, wherein, The storage device is also configured to: Determine the operating temperature of the storage device; and Adjust the value of the first through voltage corresponding to the operating temperature.

17. The storage device according to any one of claims 11 to 16, wherein, As the operating temperature increases, the value of the first through voltage decreases.

18. The storage device according to any one of claims 11 to 17, wherein, The operating temperatures are divided into multiple groups arranged in ascending order. When verifying whether the memory cell is programmed to the same programming level among multiple programming levels, the same value of the first through voltage is applied when the operating temperature values ​​are in the same group, and the lower value of the first through voltage is applied when the operating temperature values ​​are in a group with a higher order.

19. The storage device according to any one of claims 11 to 18, wherein, The value of the first through voltage is further determined based on the number of programming cycles of the memory cell, wherein the value of the first through voltage increases as the number of programming cycles increases.

20. A storage system, comprising: Storage device; And A memory controller, coupled to and configured to control the memory device. The storage device includes: Storage cell array; and Peripheral circuitry, coupled to the memory cell array and configured to perform programming operations on the memory cell array, the programming operations including: Program the memory cells coupled to the first word line; Verifying whether the memory cell has been programmed to a programming level among multiple programming levels includes: Apply a verification voltage to the first word line; and A first pass voltage is applied to one or more second word lines adjacent to the first word line, wherein the value of the first pass voltage is lower than the value of a second pass voltage applied to the one or more second word lines when a read operation is performed on the memory cell coupled to the first word line.

Images