Systems, methods, apparatus, and storage media of signal duty cycle calibration

Abstract

The application relates to the technical field of semiconductor memories, and discloses a signal duty cycle calibration system, method, device and storage medium. The system comprises: a power-on control module for monitoring an input signal, outputting a duty cycle calibration enabling signal when it is determined that the system meets the conditions of electrical stability and configuration completion; a duty cycle calibration configuration logic module for responding to the enabling signal and dispatching an output control signal according to preset parameter configuration calibration parameters; a delay chain circuit for selecting a corresponding delay tap, generating a delay signal and transmitting the delay signal to a DCA positive / negative circuit; and measuring the high and low level time lengths of an adjusted clock signal in real time through a built-in measurement circuit, and calculating a time length difference; and the DCA positive / negative circuit is used for completing duty cycle adjustment according to the delay signal; the delay chain circuit feeds back a calibration state to the power-on control module, and updates a module state output signal.

Description

Technical Field

[0001] This application relates to the field of semiconductor memory technology, specifically to a system, method, apparatus, and storage medium for calibrating signal duty cycle. Background Technology

[0002] High-speed memory has become a core hardware component supporting high-performance computing. In such high-speed memory systems, the duty cycle accuracy of clock signals, such as the write strobe signal, directly determines the effective sampling window size of the data eye diagram, and is a key factor in ensuring signal integrity, system stability, and transmission reliability. Ideally, the signal duty cycle should be maintained at around 50% to maximize timing margin and avoid read / write errors. However, in practical applications, the signal duty cycle of high-speed memory is easily distorted by multiple factors. Summary of the Invention

[0003] In view of this, embodiments of this application provide a signal duty cycle calibration system, method, device, and storage medium to solve the problem that the signal duty cycle of a memory is easily distorted by multiple factors.

[0004] In a first aspect, embodiments of this application provide a signal duty cycle calibration system, the system including a power-on control module, a duty cycle calibration configuration logic module, a delay chain circuit, and a DCA positive / negative circuit; The power-on control module is used to monitor the input signal, determine whether the system meets the electrical stability and configuration completion conditions based on the input signal, and output the duty cycle calibration enable signal when the electrical stability and configuration completion conditions are met, and transmit the duty cycle calibration enable signal to the duty cycle calibration configuration logic module. The duty cycle calibration configuration logic module is used to receive the duty cycle calibration enable signal, configure calibration parameters according to preset parameters to respond to and schedule the duty cycle calibration enable signal, output a control signal, and transmit the control signal to the delay chain circuit. The delay chain circuit is used to select the corresponding delay tap according to the step mode set by the control signal to generate a delay signal and transmit it to the DCA positive / negative circuit; and to measure the high and low level durations of the adjusted clock signal in real time through the built-in measurement circuit, calculate the duration difference and feed it back to the duty cycle calibration configuration logic module. The DCA positive / negative circuit is used to select the delayed clock edge according to the delayed signal to complete the duty cycle adjustment. The delay chain circuit feeds back the calibration status to the power-on control module and updates the module status output signal.

[0005] This embodiment systematically solves the problem of duty cycle distortion in high-speed memory signals by constructing a closed-loop calibration architecture consisting of a power-on control module, a duty cycle calibration configuration logic module, a delay chain circuit, and a DCA positive / negative circuit. From a technical logic perspective, the power-on control module, as the trigger core, ensures that calibration only starts after the system is electrically stable (e.g., core voltage stable, reset released) and configuration is complete, avoiding conflicts between the calibration process and system initialization. The duty cycle calibration configuration logic module achieves precise scheduling through preset parameters, providing a clear execution standard for calibration. The delay chain circuit achieves flexible delay adjustment through configurable delay taps, while its built-in measurement circuit provides real-time feedback of the high and low level duration differences, forming a dynamic adjustment basis. The DCA positive / negative circuit directly corrects the duty cycle and provides status feedback by selecting the delayed clock edge. This architecture achieves full-process automation from triggering, scheduling, adjustment to feedback, significantly improving the coordination and reliability of calibration compared to the decentralized adjustment mechanisms in related technologies. In practical applications, it can effectively offset the duty cycle distortion caused by process deviations, PVT variations and channel losses, stabilize the signal duty cycle in the ideal range of about 50%, significantly expand the effective sampling window of the data eye diagram, reduce the read and write error rate under high-speed transmission, and provide key signal integrity guarantees for high-speed memories with speeds exceeding 6Gbps such as HBM3 and DDR, supporting the stringent requirements of high-bandwidth storage in scenarios such as high-performance computing and artificial intelligence.

[0006] In conjunction with the first aspect, in one implementation, the power-on control module is specifically used to receive input signals, perform real-time status monitoring based on the input signals, and obtain real-time status data of the system; based on the status data, determine whether the core voltage is stable, whether the reset is released, and whether the initialization is completed, and obtain a judgment result on whether the system meets the electrical stability and configuration completion requirements; if the judgment result is that the conditions are met, the duty cycle calibration start logic is triggered to generate an enable signal, and a high-level valid duty cycle calibration enable signal is obtained.

[0007] This embodiment, through meticulous design of the power-on control module, clarifies the criteria for determining whether the system meets electrical stability and configuration completion requirements, as well as the logic for generating the enable signal, providing a reliable starting premise for the calibration process. From a technical perspective, this module does not simply trigger calibration; instead, it acquires system status data by monitoring input signals in real time, focusing on verifying core voltage stability, reset release status, and initialization completion. These three key indicators directly determine the effectiveness of the calibration environment. Unstable core voltage leads to fluctuations in circuit delay characteristics, and failure to release the reset or complete initialization will cause calibration parameter configuration to fail. Only when all three are met can the accuracy of the calibration results be ensured. When the criteria are met, a high-level valid duty cycle calibration enable signal is generated. This signal serves as the starting key for the calibration process, achieving timing coordination between calibration and system initialization. Compared to related technologies that lack clearly defined starting conditions, this embodiment avoids calibration failures or system anomalies caused by improper startup timing, ensuring that the calibration process is carried out in a stable and controllable environment. This lays the foundation for the accurate execution of subsequent calibration steps and further enhances the robustness of the entire calibration system, especially adapting to the complex electrical environment changes during the power-on initialization phase of high-speed memory.

[0008] In conjunction with the first aspect, in one implementation, the duty cycle calibration configuration logic module includes: a main control finite state machine and a memory-mapped register; The main control finite state machine is used to receive the duty cycle calibration enable signal, perform calibration process start judgment, and obtain calibration process start command. The memory-mapped register is used to read preset calibration parameters, parse and store the parameters to obtain calibration configuration parameters including step mode and termination condition; and generate and encode control signals according to the calibration configuration parameters and start command to obtain the tap selection and working mode control signals of the delay chain circuit. The main control finite state machine is used to output the encoded control signal, schedule the calibration process, and obtain a control signal that can drive the delay chain circuit to perform duty cycle adjustment.

[0009] This embodiment achieves flexible scheduling and precise control of the calibration process by separating the duty cycle calibration configuration logic module into a dual-core structure of a main control finite state machine and a memory-mapped register. Technically, the main control finite state machine focuses on the initiation judgment and scheduling of the calibration process, quickly responding to the enable signal of the power-on control module to ensure the calibration process proceeds sequentially. The memory-mapped register, on the other hand, handles parameter management, reading preset calibration parameters and parsing key configuration information such as step mode and termination conditions. These parameters directly determine the accuracy and efficiency of the calibration; a reasonable step mode balances calibration speed and accuracy, and clear termination conditions prevent over-calibration or under-calibration. Working together, the register first parses parameters to generate coded control signals, which are then scheduled and output by the state machine, achieving standardized execution of parameter configuration, signal generation, and process scheduling. Compared to related technologies where configuration and scheduling are integrated, this separated structure reduces module coupling and supports adaptation to different speeds and types of memory by modifying preset parameters, significantly improving the system's versatility. Meanwhile, the encoded control signal can accurately drive the delay chain circuit, ensuring that the calibration action is executed according to the preset logic, reducing interference and false triggering during the transmission of control signals, further guaranteeing calibration accuracy, and enabling the system to meet the duty cycle calibration requirements in different scenarios.

[0010] In conjunction with the first aspect, in one embodiment, the delay chain circuit is specifically used to receive the control signal output by the duty cycle calibration configuration logic module, perform step mode parsing on the control signal to obtain a tap selection instruction; select and combine delay units according to the tap selection instruction to obtain a target delay path; transmit the original clock signal through the target delay path to obtain a clock signal with a fixed delay; output the delayed clock signal, perform signal distribution, and obtain a delayed signal to be transmitted to the DCA positive / negative circuit.

[0011] This embodiment optimizes the signal processing flow of the delay chain circuit, achieving accurate generation and efficient distribution of the delayed signal, providing a customizable delay basis for duty cycle adjustment. In the technical derivation process, the circuit first performs step mode analysis on the control signal to clarify the tap selection instruction. This step is the core of achieving flexible delay; different step modes correspond to different delay accuracies, and coarse or fine adjustment modes can be selected according to calibration requirements. Subsequently, the target delay path is constructed through the selection and combination of delay units, ensuring that the original clock signal obtains a fixed and accurate delay amount, avoiding calibration errors caused by delay fluctuations. Finally, the delayed clock signal is distributed to the DCA positive / negative circuit, completing the effective transmission of the delayed signal. Compared to the fixed delay path design in related technologies, this configurable delay path scheme supports dynamic adjustment of the delay amount according to the control signal, adapting to different degrees of duty cycle distortion scenarios. For slight distortion, small-step fine adjustment can be selected; for severe distortion, large-step coarse adjustment can be selected, significantly improving the flexibility and adaptability of calibration. Meanwhile, the generation of a fixed delay ensures the stability of the delay signal, provides a reliable input for the precise adjustment of the DCA positive / negative circuit, reduces the adjustment deviation caused by delay signal fluctuations, further improves the overall accuracy of duty cycle calibration, and meets the stringent requirements of high-speed memory for signal delay control.

[0012] In conjunction with the first aspect or its corresponding implementation, in one implementation, the delay chain circuit is used to acquire the rising edge and falling edge of the clock signal to obtain the start time and end time of the high and low levels; calculate the duration of the high and low levels based on the start time and the end time to obtain their respective durations; perform a difference operation on the durations of the high and low levels to obtain duration difference data and complete the verification, and feed back the verified duration difference data to the duty cycle calibration configuration logic module.

[0013] This embodiment constructs a key feedback closed loop in the calibration process by providing real-time measurement and feedback capabilities to the delay chain circuit, providing data support for precise adjustments. Technically, the circuit first captures the rising and falling edges of the clock signal to accurately pinpoint the start and end times of high and low levels. This is fundamental for duration measurement; the accuracy of edge positioning directly determines the accuracy of duration calculation. The built-in measurement circuit avoids delays and interference from external measurements. Subsequently, the duration of the high and low levels is calculated and the difference is calculated to quantify the duty cycle distortion, while data verification ensures the reliability of the feedback data. Finally, the verified duration difference is fed back to the duty cycle calibration configuration logic module, providing a clear basis for subsequent adjustments. Compared to related technologies that lack real-time measurement feedback, this embodiment achieves closed-loop control of adjustment, measurement, feedback, and readjustment. The configuration logic module can dynamically optimize the control signal based on the feedback duration difference, avoiding inefficient or failed calibration caused by blind adjustments. For example, when the feedback indicates that the high-level duration is significantly longer than the low-level duration, the configuration logic can immediately adjust the control signal to drive the DCA negative circuit to delay the rising edge and shorten the high-level duration. This dynamic feedback mechanism significantly improves the convergence speed and accuracy of calibration, ensuring that the duty cycle can quickly approach the ideal value of 50%, effectively addressing the problem of dynamic duty cycle drift caused by factors such as PVT changes in high-speed memory.

[0014] In conjunction with the first aspect or its corresponding implementation, in one implementation, the DCA positive / negative circuit is used to receive the delay signal output by the delay chain circuit, determine the clock edge delay direction, and obtain a delay execution instruction for the rising edge or falling edge; select the falling edge of the original clock signal or select the rising edge of the original clock signal to delay according to the delay execution instruction, and obtain a target clock signal with adjusted duty cycle; collect the duty cycle data of the target clock signal to determine the calibration result, and obtain status information of calibration completion or needing further adjustment; and feed back the status information to the power-on control module.

[0015] This embodiment achieves precise duty cycle correction and real-time feedback of calibration status by designing a selection delay mechanism for the positive / negative DCA circuit, completing the final execution and closed-loop termination of the calibration process. In the technical derivation process, the circuit first determines the clock edge delay direction based on the delay signal, clarifying whether it is a delay of the rising or falling edge. This determination directly corresponds to the duty cycle adjustment direction; delaying the falling edge extends the high-level duration (positive adjustment), and delaying the rising edge extends the low-level duration (negative adjustment), achieving precise bidirectional control of the duty cycle. Subsequently, the original clock signal is specifically adjusted according to the delay execution command to generate a target clock signal, ensuring the accuracy of the adjustment action. Simultaneously, the duty cycle data of the target clock signal is collected for result determination, clarifying whether the calibration is complete and avoiding over-adjustment or under-adjustment. Finally, the status information is fed back to the power-on control module to update the module status, realizing a complete closed loop of the calibration process. Compared to the unidirectional adjustment schemes in related technologies, this bidirectional adjustment mechanism can adapt to different types of duty cycle distortion, such as excessively long high-level and low-level cycles, significantly improving the system's adaptability. Real-time feedback of the calibration status ensures that the power-on control module can promptly grasp the calibration progress, avoiding repeated calibration or calibration interruptions, thus enhancing system controllability. In practical applications, this circuit can quickly respond to control signals, correcting the distorted duty cycle to the ideal range. Simultaneously, status feedback ensures the integrity of the calibration process, providing a stable, high-quality clock signal for the high-speed memory, significantly reducing timing margin issues caused by duty cycle distortion, and ensuring the reliability of high-speed data transmission.

[0016] Secondly, embodiments of this application provide a method for calibrating the signal duty cycle. The method is applied to a signal duty cycle calibration system according to the first aspect described above or any corresponding embodiment. The method includes: Monitor the input signal, determine whether the system meets the electrical stability and configuration completion conditions based on the input signal, and output the duty cycle calibration enable signal when the electrical stability and configuration completion conditions are met; The calibration parameters are configured according to preset parameters to respond to and schedule the duty cycle calibration enable signal, and output a control signal. The delay signal is generated by selecting a delay tap based on the control signal, the duration of the high and low levels of the clock is measured and the result is fed back, and the duty cycle is adjusted by selecting a delay clock edge based on the delay signal. The delay chain circuit feeds back the calibration status.

[0017] In conjunction with the second aspect, in one embodiment, the method further includes: Energy consumption is calculated based on real-time data during the calibration process to obtain the real-time power consumption value of the calibration process. The power consumption threshold is determined using the real-time power consumption value to obtain a result indicating whether the system is currently in a low-power mode. Based on the judgment results, the calibration process parameters are adjusted to obtain the power consumption calibration strategy; Based on the power consumption calibration strategy, the state machine timing is optimized and the number of idle state clock toggles is reduced to obtain a target execution scheme that balances calibration accuracy and power consumption.

[0018] Thirdly, embodiments of this application provide a computer device, including: a memory and a processor, which are communicatively connected to each other. The memory stores computer instructions, and the processor executes the computer instructions to perform the signal duty cycle calibration method described in the second aspect or any corresponding embodiment.

[0019] Fourthly, embodiments of this application provide a computer-readable storage medium storing computer instructions for causing a computer to perform a signal duty cycle calibration method described in the second aspect or any corresponding embodiment. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the specific embodiments or related technologies of this application, the drawings used in the description of the specific embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0021] Figure 1 This is a structural block diagram of a signal duty cycle calibration system according to some embodiments of this application; Figure 2 This is a schematic flowchart of a signal duty cycle calibration method according to some embodiments of this application; Figure 3 This is a schematic diagram of the hardware structure of a computer device according to an embodiment of this application. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0023] This application provides a signal duty cycle calibration system. Figure 1 This is a structural block diagram of a signal duty cycle calibration system according to some embodiments of this application, such as... Figure 1As shown, the signal duty cycle calibration system includes a power-on control module 11, a duty cycle calibration configuration logic module 12, a delay chain circuit 13, and a DCA positive / negative circuit 14.

[0024] The power-on control module 11 is used to monitor the input signal, determine whether the system meets the electrical stability and configuration completion conditions based on the input signal, and output the duty cycle calibration enable signal when the electrical stability and configuration completion conditions are met, and transmit the duty cycle calibration enable signal to the duty cycle calibration configuration logic module 12.

[0025] In this embodiment, the input signals may include a power stabilization signal (power_good), a global reset signal (reset_b), an initialization status code (init_state[3:0]), a mode register write completion signal (mr_wr_done), a software-configurable clock cycle completion signal (soft_config_cycles_done), and a system reference clock (clk_sys). The electrical stability and configuration completion conditions specifically refer to the core voltage stabilizing within the rated tolerance range, the reset signal being released to a high level, the basic initialization steps being completed, the mode register being configured, and the software-configurable clock cycle counting ending. The power-on control module implements logic control through a hardware state machine, sequentially experiencing six states: power-on reset wait, basic initialization wait, mode register configuration wait, software configuration cycle wait, calibration trigger, and calibration completion, ensuring that calibration only starts after the system environment has stabilized.

[0026] This application embodiment avoids conflicts between the calibration process and system initialization through precise status monitoring and timing control, ensuring that calibration is performed in a stable environment, improving the reliability of calibration results from the source, and laying the foundation for subsequent calibration steps.

[0027] The duty cycle calibration configuration logic module 12 is used to receive the duty cycle calibration enable signal, configure calibration parameters according to preset parameters, respond to and schedule the duty cycle calibration enable signal, output control signals, and transmit the control signals to the delay chain circuit 13.

[0028] In this embodiment, preset parameters can be stored in a memory-mapped register, including a global enable switch, mode selection (automatic / manual), step mode level, calibration tolerance threshold, etc. After receiving the enable signal from the power-on control module, the module first parses the preset parameters through the memory-mapped register to determine the calibration execution standard. Then, the main control finite state machine schedules the calibration process according to the parameters, generating control signals including tap selection instructions and working mode instructions to ensure that the delay chain circuit performs the calibration operation according to the preset logic.

[0029] The embodiments of this application enable flexible configuration of calibration parameters and orderly scheduling of calibration processes, supporting both automatic closed-loop calibration and manual fine-tuning modes to adapt to different scenario requirements and improve the versatility and operability of the system.

[0030] The delay chain circuit 13 is used to select the corresponding delay tap according to the step mode set by the control signal to generate a delayed signal and transmit it to the DCA positive / negative circuit 14. It also uses a built-in measurement circuit to measure the high and low level durations of the adjusted clock signal in real time, calculate the duration difference, and feed it back to the duty cycle calibration configuration logic module 12.

[0031] In this embodiment, the stepping mode supports multiple levels, including ±1, ±2, ±4 up to ±128, corresponding to different calibration accuracies (2-5 ps / step). The delay chain consists of 65536 delay units based on SVT buffers. A multiplexer selects the target delay path according to the tap selection instruction, generating a delay signal with a fixed delay amount. The built-in measurement circuit uses Time to Digital Converter (TDC) technology. By capturing the propagation positions of the rising and falling edges of the clock signal on the delay chain, it calculates the duration of high and low levels, performs difference calculations and verification, and feeds back to the configuration logic module to form a dynamic adjustment basis.

[0032] This application embodiment achieves picosecond-level precision delay adjustment through a configurable delay chain, while integrating real-time measurement functions to form a closed-loop mechanism of adjustment, measurement, and feedback. This not only ensures high calibration accuracy but also dynamically responds to changes in duty cycle, improving the flexibility and accuracy of calibration.

[0033] DCA positive / negative circuit 14 is used to select the delayed clock edge according to the delayed signal to complete the duty cycle adjustment. Delay chain circuit 13 feeds back the calibration status to the power-on control module 11 and updates the module status output signal.

[0034] In this embodiment, as an example, the DCA positive / negative circuit is the final signal shaping execution unit of the duty cycle calibration system, including a DCA positive adjustment circuit and a DCA negative adjustment circuit. Both are implemented based on pure digital logic and operate mutually exclusively under the control of the enable signal output by the duty cycle calibration configuration logic module. Specifically, selecting a delayed clock edge refers to applying a delay to only a single specific edge (rising edge or falling edge) of the clock signal according to calibration requirements, while keeping the other edge synchronized, thereby precisely adjusting the duty cycle.

[0035] The core structure of the DCA forward adjustment circuit is an SR latch or a combination of an OR gate and an inverter. The input signals include the original clock signal (clk_in) and a delayed signal (clk_delayed) from the delay chain circuit, controlled by the forward adjustment enable signal (pos_adj_en). During operation, the original clock signal is directly input to the latch's set terminal (OR gate input), ensuring an immediate response on the rising edge. The delayed signal, after being inverted, is input to the latch's reset terminal (the other input of the OR gate), causing the falling edge to be delayed by T_delay time before output. This design achieves a positive increase in duty cycle by widening the high-level duration and shortening the low-level duration.

[0036] The DCA negative adjustment circuit is also based on the SR latch, with input logic reversed compared to the positive circuit. It is enabled by the negative adjustment enable signal (neg_adj_en). The original clock signal is input to the latch's reset terminal via an inverter, ensuring immediate response on the falling edge. The delay signal is directly input to the latch's set terminal, causing the rising edge to be delayed by T_delay time before output. This design achieves a negative reduction in the duty cycle by shortening the high-level duration and widening the low-level duration.

[0037] The calibration status feedback is completed by the delay chain circuit by measuring the duty cycle data of the adjusted target clock signal. The determination result (calibration completed or further adjustment required) is fed back to the power-on control module in the form of status information. The power-on control module updates the module status output signal (module_status[1:0]) according to this information. For example, when calibration is completed, the status is set to 2'b11.

[0038] This application embodiment achieves bidirectional precise adjustment of the duty cycle through a pure digital logic design that selects a delayed clock edge, avoiding changes in the signal period; a mutual exclusion enable mechanism prevents circuit conflicts and ensures the safety of the adjustment process; real-time status feedback ensures that the system can keep track of the calibration progress in a timely manner, and finally stabilizes the clock signal duty cycle within the ideal range of 50%±2%, effectively offsetting the distortion effects caused by process deviations, PVT changes, etc., and providing stable signal integrity protection for high-speed memory.

[0039] This embodiment systematically solves the problem of duty cycle distortion in high-speed memory signals by constructing a closed-loop calibration architecture consisting of a power-on control module 11, a duty cycle calibration configuration logic module 12, a delay chain circuit 13, and a DCA positive / negative circuit 14. From a technical logic perspective, the power-on control module 11 acts as the trigger core, ensuring that calibration only starts after the system is electrically stable (e.g., core voltage stable, reset released) and configuration is complete, avoiding conflicts between the calibration process and system initialization. The duty cycle calibration configuration logic module 12 achieves precise scheduling through preset parameters, providing a clear execution standard for calibration. The delay chain circuit 13 achieves flexible delay adjustment through configurable delay taps, while its built-in measurement circuit provides real-time feedback of the high and low level duration differences, forming a basis for dynamic adjustment. The DCA positive / negative circuit 14 directly corrects the duty cycle and provides feedback on the status by selecting the delayed clock edge. This architecture achieves full-process automation from triggering, scheduling, adjustment to feedback, significantly improving the coordination and reliability of calibration compared to the decentralized adjustment mechanisms in related technologies. In practical applications, it can effectively offset duty cycle distortion caused by process variations, PVT changes, and channel losses, stabilizing the signal duty cycle within the ideal range of approximately 50%. This significantly expands the effective sampling window of the data eye diagram, reduces read / write error rates under high-speed transmission, and provides crucial signal integrity guarantees for high-speed memories with data rates exceeding 6Gbps, such as HBM3 and DDR. This supports the stringent high-bandwidth storage requirements of high-performance computing, artificial intelligence, and other scenarios. This application is particularly suitable for high-speed interfaces with data rates exceeding 6Gbps, such as HBM3, HBM3E, HBM4, LPDDR, GDDR, and DDR storage devices.

[0040] In one implementation, the power-on control module 11 is specifically used to receive input signals, perform real-time status monitoring based on the input signals, and obtain real-time status data of the system. Based on the status data, it determines whether the core voltage is stable, whether the reset is released, and whether the initialization is completed, to obtain a judgment result on whether the system meets the requirements of electrical stability and configuration completion. If the judgment result is that the conditions are met, the duty cycle calibration start logic is triggered to generate an enable signal, resulting in a high-level valid duty cycle calibration enable signal.

[0041] In this embodiment, real-time status monitoring is achieved by continuously acquiring the level status and timing information of the input signal. Core voltage stability is determined by the power_good signal output by the power management chip. Reset release is based on the reset_b signal changing from low to high. Initialization completion is confirmed by the init_state[3:0] status codes. When all three conditions are met, the internal calibration start logic is triggered, generating a high-level valid duty cycle calibration enable signal (dca_calib_en signal). This signal serves as the start signal for the calibration process, directly activating the subsequent configuration logic and delay chain measurement circuit.

[0042] The embodiments of this application clearly define the rigid conditions for calibration initiation, avoiding calibration failure due to voltage fluctuations, failure to release reset, etc., ensuring that calibration is initiated after the system is completely stable, and further improving the consistency and reliability of calibration results.

[0043] This embodiment, through the refined design of the power-on control module 11, clarifies the criteria for determining whether the system meets electrical stability and configuration completion requirements, as well as the logic for generating the enable signal, providing a reliable starting premise for the calibration process. From a technical perspective, this module does not simply trigger calibration; instead, it acquires system status data by monitoring input signals in real time, focusing on verifying core voltage stability, reset release status, and initialization completion. These three key indicators directly determine the effectiveness of the calibration environment. Unstable core voltage leads to fluctuations in circuit delay characteristics, and failure to release the reset or complete initialization will cause calibration parameter configuration to fail. Only when all three are met can the accuracy of the calibration results be ensured. When the criteria are met, a high-level valid duty cycle calibration enable signal is generated. This signal serves as the starting key for the calibration process, achieving timing coordination between calibration and system initialization. Compared to related technologies that lack clearly defined starting conditions, this embodiment avoids calibration failures or system anomalies caused by improper starting timing, ensuring that the calibration process is carried out in a stable and controllable environment. This lays the foundation for the accurate execution of subsequent calibration steps and further enhances the robustness of the entire calibration system, especially adapting to the complex electrical environment changes during the power-on initialization phase of high-speed memory.

[0044] In one implementation, the duty cycle calibration configuration logic module 12 includes a main control finite state machine and a memory-mapped register.

[0045] The main control finite state machine is used to receive the duty cycle calibration enable signal, determine the start of the calibration process, and obtain the calibration process start command.

[0046] In this embodiment, the calibration process initiation requires two conditions to be met simultaneously: first, a high-level duty cycle calibration enable signal is received from the power-on control module; second, the global enable bit (dca_enable) in the memory-mapped register is enabled. After the start command is generated, the main control finite state machine will schedule measurement, decision-making, and adjustment operations according to a preset process, realizing closed-loop iteration of calibration in automatic mode and responding to user configuration commands in manual mode.

[0047] This application embodiment serves as the "scheduling hub" of the calibration process, realizing the condition verification and process control for calibration initiation, ensuring the orderly execution of calibration operations, and connecting automatic and manual modes to improve the operational flexibility of the system.

[0048] The memory-mapped register is used to read preset calibration parameters, parse and store the parameters to obtain calibration configuration parameters including step mode and termination condition. Based on the calibration configuration parameters and start command, control signals are generated and encoded to obtain the tap selection and operating mode control signals for delay chain circuit 13.

[0049] In this embodiment, preset calibration parameters are written to the memory-mapped register via the system bus (such as APB or AXI-Lite), including DCA_CTRL_REG (global enable, mode selection, calibration start), DCA_STEP_REG (step mode configuration), and DCA_TOLERANCE_REG (calibration tolerance threshold). After parameter parsing, key information such as the step mode (e.g., 8-step coarse adjustment, 1-step fine adjustment) and termination condition (e.g., the difference between high and low level durations is less than one step precision) is extracted and combined with the start command encoding to generate control signals, ensuring that the delay chain circuit performs calibration according to the specified precision and standard.

[0050] The embodiments of this application realize flexible configuration and storage of calibration parameters through registers, support calibration requirements with different rates and different distortion levels, and at the same time standardize the control signal generation process, reduce the coupling between modules, and improve the scalability of the system.

[0051] The main control finite state machine is used to output the encoded control signal, schedule the calibration process, and obtain the control signal that can drive the delay chain circuit 13 to perform duty cycle adjustment.

[0052] In this embodiment, the encoded control signal may include information such as step mode encoding, tap selection address, measurement start command, and adjustment direction enable. The main control finite state machine implements scheduling logic through state transitions. In automatic mode, measurement, decision-making, and adjustment operations are triggered sequentially until the calibration termination condition is met. In manual mode, the user-configured control code is directly output to the delay chain circuit, while also supporting measurement result feedback and query.

[0053] The embodiments of this application can realize automated scheduling and closed-loop control of the calibration process. In automatic mode, calibration can be completed without manual intervention, while in manual mode, it meets the requirements for precise debugging, taking into account both mass production efficiency and R&D flexibility.

[0054] This embodiment achieves flexible scheduling and precise control of the calibration process by splitting the duty cycle calibration configuration logic module 12 into a dual-core structure of a main control finite state machine and a memory-mapped register. Technically, the main control finite state machine focuses on the initiation judgment and scheduling of the calibration process, quickly responding to the enable signal of the power-on control module 11 to ensure the calibration process proceeds sequentially. The memory-mapped register handles parameter management, reading preset calibration parameters and parsing key configuration information such as step mode and termination conditions. These parameters directly determine the accuracy and efficiency of the calibration; a reasonable step mode balances calibration speed and accuracy, and clear termination conditions prevent over-calibration or under-calibration. Working together, the register first parses parameters to generate coded control signals, which are then scheduled and output by the state machine, achieving standardized execution of parameter configuration, signal generation, and process scheduling. Compared to related technologies where configuration and scheduling are integrated, this split structure reduces module coupling and supports adaptation to different speeds and types of memory by modifying preset parameters, significantly improving the system's versatility. Meanwhile, the encoded control signal can accurately drive the delay chain circuit 13, ensuring that the calibration action is executed according to the preset logic, reducing interference and false triggering during the transmission of control signals, further ensuring calibration accuracy, and enabling the system to meet the duty cycle calibration requirements in different scenarios.

[0055] In one implementation, the delay chain circuit 13 is specifically used to receive the control signal output by the duty cycle calibration configuration logic module 12, perform step mode parsing on the control signal to obtain a tap selection instruction. Based on the tap selection instruction, delay units are selected and combined to obtain a target delay path. The original clock signal is transmitted through the target delay path to obtain a clock signal with a fixed delay. The delayed clock signal is output and distributed to obtain a delayed signal transmitted to the DCA positive / negative circuit 14.

[0056] In this embodiment, the control signal parsing is implemented through combinational logic circuits, and the tap selection instruction corresponds to a fixed tap point on the delay chain (after units 1, 2, 4, 8...32768). The selection and combination of delay units are implemented using a switch matrix. The coarse adjustment delay path is determined according to the tap selection instruction, and then the subsequent delay units are controlled by the control code (ctrl_code[15:0]) to achieve fine adjustment, finally forming a clock signal with a fixed delay amount, which is distributed to the DCA positive / negative circuit.

[0057] This application embodiment employs a two-stage delay mechanism combining coarse and fine adjustments to balance calibration range and accuracy, addressing different scenarios such as slight and severe distortion. Simultaneously, a fixed delay path ensures the stability of the delayed signal, providing a reliable input for duty cycle adjustment.

[0058] This embodiment optimizes the signal processing flow of the delay chain circuit 13, achieving accurate generation and efficient distribution of the delayed signal, providing a customizable delay basis for duty cycle adjustment. In the technical derivation process, the circuit first performs step mode analysis on the control signal to clarify the tap selection instruction. This step is the core of achieving flexible delay; different step modes correspond to different delay accuracies, and coarse or fine adjustment modes can be selected according to calibration requirements. Subsequently, the target delay path is constructed through the selection and combination of delay units, ensuring that the original clock signal obtains a fixed and accurate delay amount, avoiding calibration errors caused by delay fluctuations. Finally, the delayed clock signal is distributed to the DCA positive / negative circuit 14, completing the effective transmission of the delayed signal. Compared to the fixed delay path design in related technologies, this configurable delay path scheme supports dynamic adjustment of the delay amount according to the control signal, adapting to different degrees of duty cycle distortion scenarios. For slight distortion, small-step fine adjustment can be selected; for severe distortion, large-step coarse adjustment can be selected, significantly improving the flexibility and adaptability of calibration. Meanwhile, the generation of a fixed delay ensures the stability of the delay signal, provides a reliable input for the precise adjustment of the DCA positive / negative circuit 14, reduces the adjustment deviation caused by the fluctuation of the delay signal, further improves the overall accuracy of the duty cycle calibration, and meets the stringent requirements of high-speed memory for signal delay control.

[0059] In one implementation, the delay chain circuit 13 is used to acquire the rising and falling edges of the clock signal to obtain the start and end times of the high and low levels. Based on the start and end times, the duration of the high and low levels is calculated to obtain their respective durations. The durations of the high and low levels are then compared to obtain duration difference data, which is then verified. The verified duration difference data is then fed back to the duty cycle calibration configuration logic module 12.

[0060] In this embodiment, the rising and falling edges of the clock signal are captured by a D flip-flop array, and the start and end times correspond to the triggering states of the flip-flop array. The duration of the high and low levels is calculated by statistically analyzing the transition points of the triggering states, and the duration difference is the absolute difference between the high and low level durations. The verification process ensures the accuracy of the feedback data through data redundancy verification. The feedback signal is transmitted in real time to the duty cycle calibration configuration logic module as the basis for the next adjustment.

[0061] The embodiments of this application realize accurate quantitative measurement of duty cycle distortion, and the feedback data provides a clear direction for calibration adjustment, avoiding blind adjustment. At the same time, the verification mechanism ensures data reliability and improves the convergence speed and accuracy of closed-loop calibration.

[0062] This embodiment constructs a key feedback closed loop in the calibration process by providing real-time measurement and feedback functions to the delay chain circuit 13, providing data support for precise adjustment. Technically, this circuit first captures the rising and falling edges of the clock signal to accurately pinpoint the start and end times of the high and low levels. This is the foundation for duration measurement; the accuracy of edge positioning directly determines the accuracy of duration calculation. The use of a built-in measurement circuit avoids delays and interference from external measurements. Subsequently, the duration of the high and low levels is calculated and the difference is calculated to quantify the duty cycle distortion, while data verification ensures the reliability of the feedback data. Finally, the verified duration difference is fed back to the duty cycle calibration configuration logic module 12, providing a clear basis for subsequent adjustments. Compared to related technologies that lack real-time measurement feedback, this embodiment achieves closed-loop control of adjustment, measurement, feedback, and readjustment. The configuration logic module can dynamically optimize the control signal based on the feedback duration difference, avoiding inefficient or failed calibration caused by blind adjustments. For example, when the feedback indicates that the high-level duration is significantly longer than the low-level duration, the configuration logic can immediately adjust the control signal to drive the DCA negative circuit to delay the rising edge and shorten the high-level duration. This dynamic feedback mechanism significantly improves the convergence speed and accuracy of calibration, ensuring that the duty cycle can quickly approach the ideal value of 50%, effectively addressing the problem of dynamic duty cycle drift caused by factors such as PVT changes in high-speed memory.

[0063] In one implementation, the DCA positive / negative circuit 14 receives the delayed signal output from the delay chain circuit 13, determines the clock edge delay direction, and obtains a delayed execution command for either the rising or falling edge. Based on the delayed execution command, it selects to delay either the falling edge or the rising edge of the original clock signal to obtain a target clock signal with an adjusted duty cycle. It collects the duty cycle data of the target clock signal to determine the calibration result, obtaining status information indicating whether calibration is complete or requires further adjustment. This status information is then fed back to the power-on control module 11.

[0064] In this embodiment, the determination of the clock edge delay direction is based on the phase information of the delayed signal and the decision instructions of the duty cycle configuration logic. The DCA positive circuit delays the falling edge of the original clock signal through a logical OR operation, extending the high-level duration. The DCA negative circuit delays the rising edge of the original clock signal through a logical AND operation, extending the low-level duration. The calibration result is determined by comparing the duty cycle of the target clock signal with a target range of 50% ± 2%, and the status information is fed back to the power-on control module in the form of a level signal to update the module's status output.

[0065] This application embodiment achieves bidirectional precise adjustment of the duty cycle by selecting a delayed clock edge, avoids circuit conflicts through a mutual exclusion enable mechanism, and ensures that the system keeps track of the calibration progress in a timely manner, ultimately stabilizing the duty cycle within the ideal range and ensuring the signal integrity of the high-speed memory.

[0066] This embodiment achieves precise duty cycle correction and real-time feedback of calibration status by designing a selection delay mechanism for the DCA positive / negative circuit 14, completing the final execution and closed-loop termination of the calibration process. In the technical derivation process, the circuit first determines the clock edge delay direction based on the delay signal, clarifying whether it is a delay of the rising or falling edge. This determination directly corresponds to the duty cycle adjustment direction; delaying the falling edge extends the high-level duration (positive adjustment), and delaying the rising edge extends the low-level duration (negative adjustment), achieving bidirectional precise control of the duty cycle. Subsequently, the original clock signal is specifically adjusted according to the delay execution command to generate a target clock signal, ensuring the accuracy of the adjustment action. Simultaneously, the duty cycle data of the target clock signal is collected for result determination, clarifying whether the calibration is complete and avoiding over-adjustment or under-adjustment. Finally, the status information is fed back to the power-on control module 11 to update the module status, realizing a complete closed loop of the calibration process. Compared to the single-direction adjustment scheme in related technologies, this bidirectional adjustment mechanism can adapt to different types of duty cycle distortion, such as excessively long high and low levels, significantly improving the system's adaptability. Real-time feedback on the calibration status ensures that the power-on control module 11 can promptly grasp the calibration progress, avoiding repeated calibration or calibration interruption, thus improving the system's controllability. In practical applications, this circuit can quickly respond to control signals, correcting the distorted duty cycle to the ideal range. Simultaneously, the status feedback ensures the integrity of the calibration process, providing a stable, high-quality clock signal for the high-speed memory. This significantly reduces the timing margin problem caused by duty cycle distortion, ensuring the reliability of high-speed data transmission.

[0067] In this application, the signal duty cycle calibration system may also include a power consumption monitoring module.

[0068] The power consumption monitoring module is used to collect key energy consumption-related data in real time during the calibration process, including system operating voltage, operating current, and the number of activated delay units in the delay chain circuit. This multi-dimensional real-time data is then transmitted to the duty cycle calibration configuration logic module. Simultaneously, a built-in energy consumption integration algorithm calculates the real-time power consumption value of the calibration process based on the real-time change curves of voltage and current and the energy consumption model of activated delay units, providing accurate data support for determining the system's power consumption status.

[0069] The power consumption monitoring module achieves real-time monitoring of power consumption during the calibration process through multi-dimensional energy consumption data collection and accurate power consumption calculation. Combined with subsequent power consumption threshold determination and parameter adjustment strategies, it effectively reduces system energy consumption in low-power mode without significantly sacrificing calibration accuracy, improves the energy efficiency ratio of the calibration system, and is suitable for energy-sensitive application scenarios such as mobile devices and low-power servers.

[0070] In this embodiment, the newly added power consumption monitoring module can collect real-time data such as voltage, current, and the number of activated delay chain units during the calibration process, and calculate the real-time power consumption value of the calibration process through an energy consumption integral algorithm. The power-on control module compares this real-time power consumption value with a preset low-power threshold, completes the power consumption threshold determination, and outputs the determination result of whether the system is currently in a low-power mode. The duty cycle calibration configuration logic module receives the determination result. If it is determined to be in a low-power mode, it adjusts the calibration parameters and generates a power consumption calibration strategy that reduces the number of activated delay chain units, extends the calibration interval, and prioritizes the coarse adjustment mode. If it is determined to be in a normal mode, it maintains the original calibration parameters. Finally, based on the generated power consumption calibration strategy, the duty cycle calibration configuration logic module optimizes the state transition timing of the main control finite state machine, while reducing the number of clock toggles in the idle state to avoid ineffective energy consumption, ultimately obtaining a target execution scheme that balances calibration accuracy and power consumption control.

[0071] For example, in a memory duty cycle calibration scenario, the power consumption monitoring module collected real-time data during the calibration process, showing a voltage of 1.2V, a current of 50mA, and 8192 delayed chain active units. The calculated real-time power consumption was 60mW, while the power-on control module's preset low-power threshold was 50mW, indicating the system was in low-power mode. Based on this, the duty cycle calibration configuration logic module generated a power consumption calibration strategy, reducing the number of delayed chain active units to 4096, doubling the calibration interval, and prioritizing an 8-step coarse-tuning mode. Subsequently, the module optimized the state machine timing, reducing the idle clock toggle frequency from 100MHz to 20MHz, reducing the number of idle clock toggles by approximately 80%. Ultimately, while ensuring the duty cycle calibration difference met the ±5ps accuracy requirement, the overall power consumption of the calibration process was reduced to 45mW, achieving a balance between calibration accuracy and power consumption.

[0072] Related technologies allow memory controllers to fine-tune the duty cycle of the WDQS signal inside the DRAM in limited steps through mode registers, but this has obvious limitations: Limited adjustment accuracy and range: Existing DCA typically only supports limited steps such as -7 to +7, and its single-step adjustment accuracy (e.g., 2-5 ps) and maximum offset may be insufficient to meet the fine calibration requirements at extreme PVT changes or higher rates.

[0073] Lack of a systematic calibration process: While the standard provides adjustment capabilities, it does not clearly define an efficient, reliable, and adaptive system-level calibration process. The key to achieving optimal performance lies in how to seamlessly embed this function into the memory initialization sequence and work in conjunction with other training steps (such as WDQS-to-CK aligned training).

[0074] Application limitations: Existing solutions may not be supported or need to be disabled below a certain clock frequency, lacking a full-frequency range or more adaptive enablement strategy.

[0075] Therefore, traditional duty cycle calibration techniques still struggle to guarantee consistent signal quality in high-speed memory during mass production, failing to meet the stringent signal integrity requirements of future higher data rate memories. The industry urgently needs a duty cycle calibration solution with higher adjustment accuracy, wider range, better integration, and a complete adaptive training process.

[0076] This application designs a configurable delay chain containing a conventional 65536-stage delay unit, supporting multiple step modes from ±1 and ±2 to ±256. While maintaining the conventional 2-5ps adjustment accuracy per step, it greatly expands the adjustment range. Furthermore, it accurately captures signal edges through a bidirectional boundary scanning digital measurement method, enabling fine calibration of the duty cycle. This can address the calibration requirements of extreme PVT variations and high-speed scenarios, thus solving the problem of limited adjustment accuracy and range.

[0077] This application explicitly embeds the duty cycle calibration process into the memory power-on initialization sequence. It is executed after the mode register is configured and before the traditional alignment training of WDQS-to-CK. The state machine of the power-on control module precisely controls the start time. Combined with the closed-loop scheduling of the duty cycle calibration configuration logic module, a complete system-level process of triggering, measurement, decision-making, adjustment, and feedback is formed, which enables collaborative work with other training steps and can solve the problem of lacking a systematic calibration process.

[0078] This application has a built-in frequency adaptive mechanism. When the duty cycle is severely distorted and cannot be sampled stably, the clock frequency can be reduced in traditional 200MHz steps until the measurement is completed. It also supports automatic and manual mode switching and global enable / disable traditional functions, adapting to different frequency ranges and application scenarios. It does not need to be disabled at specific low frequencies, which can solve the problem of application condition limitations.

[0079] According to an embodiment of this application, a method for calibrating the signal duty cycle is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.

[0080] This embodiment provides a method for calibrating the signal duty cycle, which is applied to the aforementioned signal duty cycle calibration system. Figure 2 This is a flowchart of a signal duty cycle calibration method according to an embodiment of this application, such as... Figure 2 As shown, the process includes the following steps: Step S101: Monitor the input signal, determine whether the system meets the electrical stability and configuration completion conditions based on the input signal, and output the duty cycle calibration enable signal when the electrical stability and configuration completion conditions are met.

[0081] Step S102: Configure calibration parameters according to preset parameters to respond to and schedule the duty cycle calibration enable signal, and output control signal.

[0082] In step S103, a delay signal is generated by selecting a delay tap according to the control signal, the duration of the high and low levels of the clock is measured and the result is fed back, and the duty cycle is adjusted by selecting the delay clock edge according to the delay signal. The delay chain circuit will feed back the calibration status.

[0083] In one embodiment, the method for calibrating the signal duty cycle further includes: Energy consumption is calculated based on real-time data during the calibration process to obtain the real-time power consumption value of the calibration process.

[0084] In this embodiment, real-time data refers to multi-dimensional parameters directly related to energy consumption during the calibration process, including system operating voltage, operating current, and the number of activated delay units in the delay chain circuit. This data is collected in real-time by the power consumption monitoring module. The energy consumption integration algorithm is based on the real-time change curves of voltage and current, combined with a preset energy consumption model for activated delay units (the power consumption of a single-stage delay unit is a known fixed value). By integrating the energy consumption per unit time, the total energy consumption is accumulated to obtain the real-time power consumption value of the calibration process. This real-time power consumption value is synchronously transmitted to the power-on control module and the duty cycle calibration configuration logic module, serving as the core basis for subsequent power consumption determination.

[0085] The embodiments of this application achieve precise quantification of power consumption during the calibration process, avoiding the blind pursuit of accuracy without regard to energy consumption in traditional calibration, providing data support for subsequent differentiated power consumption control, and ensuring that power consumption adjustment is based on evidence.

[0086] By using real-time power consumption values ​​to determine the power consumption threshold, the system can determine whether it is currently in a low-power mode.

[0087] In this embodiment, the low-power threshold is a pre-stored value in the power-on control module configuration register, which can be flexibly configured according to the application scenario (such as mobile devices, high-performance servers). For example, the threshold for low-power scenarios can be set to 50mW, and for normal scenarios it can be set to 80mW. The power-on control module compares the real-time power consumption value with the low-power threshold. If the real-time power consumption value is greater than or equal to the low-power threshold, the system is determined to be in low-power mode; if the real-time power consumption value is less than the low-power threshold, it is determined to be in normal mode. The determination result is fed back to the duty cycle calibration configuration logic module in real time, triggering the corresponding parameter adjustment strategy.

[0088] The embodiments of this application clearly define the system power consumption status and realize the dynamic identification of power consumption modes, providing a basis for subsequent differential calibration strategies that prioritize accuracy or power consumption, and improving the system's adaptability to different energy consumption scenarios.

[0089] Based on the judgment results, the calibration process parameters are adjusted to obtain the power consumption calibration strategy.

[0090] In this embodiment, if the system is determined to be in a low-power mode, the duty cycle calibration configuration logic module will adjust the calibration parameters accordingly to generate a power-optimized calibration strategy. This strategy includes reducing the number of activation units in the delay chain (e.g., from 8192 to 4096), extending the calibration interval (e.g., doubling the interval), and prioritizing the use of large-step coarse-tuning modes (e.g., ±8 or ±16 steps) to reduce energy consumption without significantly sacrificing calibration accuracy. If the system is determined to be in a normal mode, the original calibration parameters will be maintained (e.g., activating all delay units, using small-step fine-tuning, and standard calibration interval) to ensure that calibration accuracy is prioritized.

[0091] The embodiments of this application realize dynamic adaptation of calibration parameters. In low power mode, energy consumption is reduced by reasonably sacrificing non-core accuracy requirements, while in normal mode, calibration accuracy is guaranteed. This takes into account the core requirements in different scenarios and improves the energy efficiency ratio of the system.

[0092] The state machine timing is optimized based on the power consumption calibration strategy, and the number of idle state clock toggles is reduced to obtain a target execution scheme that balances calibration accuracy and power consumption.

[0093] In this embodiment, the duty cycle calibration configuration logic module optimizes the state transition timing of the main control finite state machine based on a power consumption calibration strategy, shortening invalid waiting periods (e.g., reducing state switching intervals); simultaneously, it reduces the number of clock toggles in idle states (e.g., from 100MHz to 20MHz) through clock gating technology, avoiding meaningless energy consumption. The target execution scheme must meet the core requirement of balancing calibration accuracy and power consumption, for example, ensuring that the duty cycle calibration difference is ≤ ±5ps in low-power mode, while controlling power consumption below the low-power threshold.

[0094] The embodiments of this application effectively reduce the system's ineffective energy consumption in low-power mode without significantly sacrificing calibration accuracy, improve the energy efficiency ratio of the calibration system, and enable the calibration system to adapt to energy-sensitive application scenarios such as mobile devices and low-power servers, thus expanding the applicability of the technical solution.

[0095] Further functional descriptions of the above steps are the same as those in the corresponding embodiments described above, and will not be repeated here.

[0096] This application also provides a computer device having the above-described features. Figure 1 The signal duty cycle calibration system shown.

[0097] Please see Figure 3 , Figure 3 This is a schematic diagram of the structure of a computer device provided in an optional embodiment of this application, such as... Figure 3 As shown, the computer device includes one or more processors 10, memory 20, and interfaces for connecting the components, including high-speed interfaces and low-speed interfaces. The components communicate with each other via different buses and can be mounted on a common motherboard or otherwise installed as needed. The processors can process instructions executed within the computer device, including instructions stored in or on memory to display graphical information of a GUI on external input / output devices (such as display devices coupled to the interfaces). In some alternative implementations, multiple processors and / or multiple buses can be used with multiple memories and multiple memory modules, if desired. Similarly, multiple computer devices can be connected, each providing some of the necessary operations (e.g., as a server array, a group of blade servers, or a multiprocessor system). Figure 3 Take a processor 10 as an example.

[0098] Processor 10 may be a central processing unit, a network processor, or a combination thereof. Processor 10 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The programmable logic device may be a complex programmable logic device (CAMP), a field-programmable gate array (FPGA), a general-purpose array logic (GPA), or any combination thereof.

[0099] The memory 20 stores instructions executable by at least one processor 10 to cause at least one processor 10 to perform the method shown in the above embodiments.

[0100] The memory 20 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function. The data storage area may store data created based on the use of the computer device as shown by a landing page for an app. Furthermore, the memory 20 may include high-speed random access memory and may also include non-transient memory, such as at least one disk storage device, flash memory device, or other non-transient solid-state storage device. In some alternative embodiments, the memory 20 may optionally include memory remotely located relative to the processor 10, which can be connected to the computer device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0101] Memory 20 may include volatile memory, such as random access memory. Memory may also include non-volatile memory, such as flash memory, hard disk, or solid-state drive. Memory 20 may also include combinations of the above types of memory.

[0102] Input device 30 can receive input numerical or character information, and generate key signal inputs related to user settings and function control of the computer device, such as a touchscreen, keypad, mouse, trackpad, touchpad, joystick, one or more mouse buttons, trackball, joystick, etc. Output device 40 may include display devices, auxiliary lighting devices (e.g., LEDs), and haptic feedback devices (e.g., vibration motors). The aforementioned display devices include, but are not limited to, liquid crystal displays, light-emitting diodes, displays, and plasma displays. In some optional embodiments, the display device may be a touchscreen. The computer device also includes a communication interface 30 for communication between the computer device and other devices or communication networks.

[0103] This application also provides a computer-readable storage medium. The methods described in this application can be implemented in hardware or firmware, or implemented as recordable on a storage medium, or implemented as computer code downloaded over a network and originally stored on a remote storage medium or a non-transitory machine-readable storage medium and subsequently stored on a local storage medium. Thus, the methods described herein can be processed by software stored on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. The storage medium can be a magnetic disk, optical disk, read-only memory, random access memory, flash memory, hard disk, or solid-state drive, etc. Further, the storage medium may also include combinations of the above types of memory. It is understood that computers, processors, microprocessor controllers, or programmable hardware include storage components capable of storing or receiving software or computer code, which, when accessed and executed by the computer, processor, or hardware, implements the methods shown in the above embodiments.

[0104] Although embodiments of this application have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of this application, and all such modifications and variations fall within the scope defined by the appended claims.

Claims

1. A signal duty cycle calibration system, characterized in that, The system includes a power-on control module, a duty cycle calibration configuration logic module, a delay chain circuit, and a DCA positive / negative circuit. The power-on control module is used to monitor the input signal, determine whether the system meets the electrical stability and configuration completion conditions based on the input signal, and output the duty cycle calibration enable signal when the electrical stability and configuration completion conditions are met, and transmit the duty cycle calibration enable signal to the duty cycle calibration configuration logic module. The duty cycle calibration configuration logic module is used to receive the duty cycle calibration enable signal, configure calibration parameters according to preset parameters to respond to and schedule the duty cycle calibration enable signal, output a control signal, and transmit the control signal to the delay chain circuit. The delay chain circuit is used to select the corresponding delay tap according to the step mode set by the control signal to generate a delay signal and transmit it to the DCA positive / negative circuit; and to measure the high and low level durations of the adjusted clock signal in real time through the built-in measurement circuit, calculate the duration difference and feed it back to the duty cycle calibration configuration logic module. The DCA positive / negative circuit is used to select the delayed clock edge according to the delayed signal to complete the duty cycle adjustment. The delay chain circuit feeds back the calibration status to the power-on control module and updates the module status output signal.

2. The system according to claim 1, characterized in that, The power-on control module is specifically used to receive input signals, perform real-time status monitoring based on the input signals, and obtain real-time status data of the system; based on the status data, it determines whether the core voltage is stable, whether the reset is released, and whether the initialization is completed, and obtains the judgment result of whether the system meets the requirements of electrical stability and configuration completion. If the determination result is that the condition is met, the duty cycle calibration start logic is triggered to generate an enable signal, resulting in a high-level active duty cycle calibration enable signal.

3. The system according to claim 1, characterized in that, The duty cycle calibration configuration logic module includes: a main control finite state machine and a memory-mapped register; The main control finite state machine is used to receive the duty cycle calibration enable signal, perform calibration process start judgment, and obtain calibration process start command. The memory-mapped register is used to read preset calibration parameters, parse and store the parameters to obtain calibration configuration parameters including step mode and termination condition; and generate and encode control signals according to the calibration configuration parameters and start command to obtain the tap selection and working mode control signals of the delay chain circuit. The main control finite state machine is used to output the encoded control signal, schedule the calibration process, and obtain a control signal that can drive the delay chain circuit to perform duty cycle adjustment.

4. The system according to claim 1, characterized in that, The delay chain circuit is specifically used to receive the control signal output by the duty cycle calibration configuration logic module, perform step mode parsing on the control signal to obtain a tap selection instruction; select and combine delay units according to the tap selection instruction to obtain a target delay path; transmit the original clock signal through the target delay path to obtain a clock signal with a fixed delay; output the delayed clock signal, perform signal distribution, and obtain a delayed signal to be transmitted to the DCA positive / negative circuit.

5. The system according to claim 3, characterized in that, The delay chain circuit is used to acquire the rising edge and falling edge of the clock signal to obtain the start and end times of the high and low levels; and to calculate the duration of the high and low levels based on the start and end times to obtain their respective durations. The high and low level durations are calculated to obtain duration difference data, which is then verified. The verified duration difference data is then fed back to the duty cycle calibration configuration logic module.

6. The system according to claim 5, characterized in that, The DCA positive / negative circuit is used to receive the delay signal output by the delay chain circuit, determine the clock edge delay direction, and obtain the delay execution instruction of rising edge or falling edge; select the falling edge of the original clock signal or select the rising edge of the original clock signal to delay according to the delay execution instruction, and obtain the target clock signal with adjusted duty cycle. The duty cycle data of the target clock signal is collected to determine the calibration result, and the status information of calibration completion or need for further adjustment is obtained; the status information is fed back to the power-on control module.

7. A method for calibrating the duty cycle of a signal, characterized in that, The method is applied to the signal duty cycle calibration system according to any one of claims 1-6, and the method includes: Monitor the input signal, determine whether the system meets the electrical stability and configuration completion conditions based on the input signal, and output the duty cycle calibration enable signal when the electrical stability and configuration completion conditions are met; The calibration parameters are configured according to preset parameters to respond to and schedule the duty cycle calibration enable signal, and output a control signal. The delay signal is generated by selecting a delay tap based on the control signal, the duration of the high and low levels of the clock is measured and the result is fed back, and the duty cycle is adjusted by selecting a delay clock edge based on the delay signal. The delay chain circuit feeds back the calibration status.

8. The method according to claim 7, characterized in that, The method further includes: Energy consumption is calculated based on real-time data during the calibration process to obtain the real-time power consumption value of the calibration process. The power consumption threshold is determined using the real-time power consumption value to obtain a result indicating whether the system is currently in a low-power mode. Based on the judgment results, the calibration process parameters are adjusted to obtain the power consumption calibration strategy; Based on the power consumption calibration strategy, the state machine timing is optimized and the number of idle state clock toggles is reduced to obtain a target execution scheme that balances calibration accuracy and power consumption.

9. A computer device, characterized in that, include: A memory and a processor, the memory and the processor being communicatively connected to each other, the memory storing computer instructions, the processor executing the computer instructions to perform the method of any one of claims 7 to 8.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions for causing a computer to perform the method of any one of claims 7 to 8.

Images