Data checking method and system based on solid state disk master control chip

Abstract

The application relates to the technical field of data storage, in particular to a data checking method and system based on a solid state disk master control chip, which solves the technical problem that in the prior art, LDPC decoding may occur in a NAND flash deep aging scene, leading to silent data damage. The method comprises the following steps: obtaining error-corrected data obtained after error correction decoding when a solid state disk reads data, and determining the current environmental drift direction of a flash memory unit in the solid state disk; based on a preset mapping relationship, determining the physical voltage change direction corresponding to the logical flip type of a target bit in the error-corrected data; based on the environmental drift direction and the physical voltage change direction of the target bit, performing risk assessment on the error-corrected data to determine whether the error-corrected data is untrustworthy data with a risk of silent data damage.

Description

Technical Field

[0001] This application relates to the field of data storage technology, specifically to a data verification method and system based on a solid-state drive controller chip. Background Technology

[0002] Solid-state drives (SSDs) are storage devices based on NAND flash memory, offering advantages such as high read / write speeds, good shock resistance, and low power consumption. Among the core components of an SSD, the controller chip is responsible for managing critical functions such as data read / write, error correction, and wear leveling. Its performance and reliability directly affect the data integrity and service stability of the entire storage system. As NAND flash memory manufacturing processes evolve towards high-density multi-layer stacking (such as 3D TLC / QLC), the wear and tear on the oxide layer of flash cells and the degradation of charge retention capabilities are becoming increasingly prominent, placing higher demands on the data error correction capabilities of the controller chip.

[0003] In existing solid-state drive (SSD) data reading processes, controller chips generally employ Low-Density Parity Check (LDPC) algorithms to perform error correction decoding on data read from NAND flash memory. The LDPC algorithm is essentially a mathematical convergence process based on probability likelihood ratios, attempting to recover erroneous data from the original data being written through iterative calculations. However, in the deep aging scenarios of long-term NAND flash memory use, the threshold voltage distribution of flash cells undergoes significant drift, and the deterioration of the channel environment leads to a decrease in the signal-to-noise ratio. At this point, although the LDPC decoder may mathematically converge to a solution satisfying the check equation, this solution may not be the original, true data being written—a phenomenon known as false convergence. This false convergence can cause erroneous data to be accepted by the system and transmitted to the host, resulting in silent data corruption, severely impacting the data reliability and consistency of the storage system. Therefore, effectively identifying and intercepting falsely converged data that may pose a risk of silent data corruption at the critical moment of successful LDPC decoding has become a pressing technical problem for current SSD data verification technologies. Summary of the Invention

[0004] To address the technical problem in existing technologies where LDPC decoding may result in false convergence and corruption of silent data under deep aging NAND flash memory scenarios, this application aims to provide a data verification method based on a solid-state drive controller chip. The specific technical solution adopted is as follows: Obtain the error-corrected data obtained by the solid-state drive after error correction and decoding when reading data, and determine the current environmental drift direction of the flash memory cells in the solid-state drive; Based on a preset mapping relationship, the physical voltage change direction corresponding to the logical flip type of the target bit in the error-corrected data is determined; whereby the target bit is at least one bit in the error-corrected data that has flipped relative to the original read data; the mapping relationship is used to characterize the statistical correlation between the logical flip type and the physical voltage change direction. Based on the direction of environmental drift and the direction of physical voltage change of the target bit, a risk assessment is performed on the error-corrected data to determine whether the error-corrected data is unreliable data with the risk of silent data corruption.

[0005] In one possible implementation, determining the current environmental drift direction of the flash memory cell in the solid-state drive includes: responding to the low-density parity-check decoder adjusting the read reference voltage and completing error correction decoding of the original read data, locking the voltage offset index used for the current successful decoding; querying a preset voltage offset specification table according to the voltage offset index to obtain the corresponding reference voltage offset value, the reference voltage offset value being a signed numerical value used to characterize the magnitude and direction of the voltage drift; and determining the environmental drift direction based on the sign of the reference voltage offset value.

[0006] In one possible implementation, based on a preset mapping relationship, the physical voltage change direction corresponding to the logical flip type of the target bit in the error-corrected data is determined, including: comparing the original read data and the error-corrected data, identifying all target bits that have undergone bit flips, and determining the flip type of each target bit; the flip type is used to characterize whether the bit value changes from 0 to 1 or from 1 to 0; according to the physical page type to which the flash memory cell belongs and the flip type of each target bit, the preset mapping relationship is queried to obtain the physical voltage change direction corresponding to each target bit.

[0007] In one possible implementation, a risk assessment is performed on the error-corrected data based on the environmental drift direction and the physical voltage change direction of the target bit to determine whether the error-corrected data is untrusted data with the risk of silent data corruption. This includes: for each target bit, determining whether the target bit is a risk bit based on the environmental drift direction and the corresponding physical voltage change direction; counting all risk bits and generating a risk score to characterize the credibility of the error-corrected data based on the distribution and number of risk bits; and determining whether the error-corrected data is untrusted based on the comparison between the risk score and a preset threshold.

[0008] In one possible implementation, determining whether a target bit is a risk bit based on the direction of environmental drift and the corresponding direction of physical voltage change includes: calculating the product of the direction of environmental drift and the direction of physical voltage change; if the product is positive, then the direction of environmental drift and the direction of physical voltage change are the same, and the target bit is identified as a risk bit.

[0009] In one possible implementation, all risk bits are counted, and a risk score is generated to characterize the reliability of the corrected data based on the distribution and quantity of risk bits. This includes: obtaining the absolute value of the reference voltage offset value, and determining a weighting coefficient positively correlated with the environmental offset amplitude based on the absolute value and a preset normalization step size constant; dividing the corrected data into multiple consecutive logical sectors, and counting the number of risk bits contained in each logical sector; for each logical sector, if the number of risk bits it contains exceeds a preset background noise filtering threshold, then accumulating the weighting coefficients of each risk bit in the logical sector to obtain the sector risk value of the logical sector; and summing the sector risk values ​​of each logical sector to obtain the risk score.

[0010] In one possible implementation, the determination of whether the corrected data is untrusted data is based on the comparison between the risk score and a preset threshold, including: comparing the risk score with a preset risk interception threshold; if the risk score is less than or equal to the risk interception threshold, the corrected data is determined to be trustworthy data and output; if the risk score is greater than the risk interception threshold, the corrected data is determined to be untrustworthy data and blocked, and a heterogeneous data recovery process is triggered.

[0011] In one possible implementation, before determining that the corrected data is untrusted and blocking it, the method further includes: maintaining the total number of times data blocking is triggered within a preset time window; comparing the total number of times with a preset maximum interception frequency threshold; if the total number of times is less than the maximum interception frequency threshold, then executing the blocking and triggering heterogeneous data recovery process steps; if the total number of times has reached the maximum interception frequency threshold, then triggering circuit breaker protection and stopping the execution of the blocking and triggering heterogeneous data recovery process steps.

[0012] In one possible implementation, the heterogeneous data recovery process includes: locating the internal independent disk redundant array stripe to which the blocked data belongs based on its physical address; initiating read operations on other associated data pages and check pages in the stripe; using the read associated data pages and check pages, reconstructing the original bit information corresponding to the blocked data through XOR operation, and outputting the reconstructed data.

[0013] This application also provides a data verification system based on a solid-state drive controller chip, the system comprising: The acquisition unit is used to acquire the error-corrected data obtained by the solid-state drive after error correction and decoding when reading data, and to determine the current environmental drift direction of the flash memory cells in the solid-state drive. The behavior analysis unit is used to determine the physical voltage change direction corresponding to the logical flip type of the target bit in the error-corrected data based on a preset mapping relationship; wherein, the target bit is at least one bit in the error-corrected data that has flipped relative to the original read data; the mapping relationship is used to characterize the statistical correlation between the logical flip type and the physical voltage change direction. The risk assessment and verification unit is used to perform risk assessment on the error-corrected data based on the direction of environmental drift and the direction of physical voltage change of the target bit, and to determine whether the error-corrected data is unreliable data with the risk of silent data corruption.

[0014] This application offers the following advantages: By introducing the physical voltage drift direction of flash memory cells as a verification dimension, it maps the logical flipping behavior of LDPC error correction decoding to the voltage change direction in the physical domain. Furthermore, by comparing the vector consistency between the environmental drift direction and the data correction direction, it identifies potential false convergence phenomena in the LDPC decoder. Compared to traditional schemes that solely rely on the mathematical convergence of LDPC, this application utilizes the directional physical drift characteristics generated by NAND flash memory aging as a third-party verification benchmark, verifying the physical rationality of the error correction results. This effectively fills the verification blind spot in probabilistic decoding under deep aging scenarios, significantly improving the data reliability of the storage system and preventing silent data corruption. Simultaneously, this application employs a statistical probability-based mapping table mechanism to replace costly real-time physical detection. This can be implemented on existing main control chip architectures with only firmware upgrades, without increasing hardware costs or read latency, demonstrating good engineering feasibility. Attached Figure Description

[0015] To more clearly illustrate the technical solutions and advantages in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a flowchart illustrating a data verification method based on a solid-state drive controller chip, provided as an embodiment of this application. Figure 2 This is a schematic diagram of the system architecture of a data verification system based on a solid-state drive controller chip, provided as an embodiment of this application. Detailed Implementation

[0017] To further illustrate the technical means and effects adopted by this application to achieve the intended purpose of the invention, the following, in conjunction with the accompanying drawings and preferred embodiments, details the specific implementation, structure, features, and effects of a data verification method based on a solid-state drive controller chip proposed in this application. In the following description, different "one embodiment" or "another embodiment" do not necessarily refer to the same embodiment. Furthermore, specific features, structures, or characteristics in one or more embodiments can be combined in any suitable form.

[0018] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.

[0019] The following description, in conjunction with the accompanying drawings, details a specific scheme for a data verification method based on a solid-state drive controller chip provided in this application.

[0020] Please see Figure 1 It illustrates a flowchart of a data verification method based on a solid-state drive controller chip according to an embodiment of this application, such as... Figure 1 As shown, the method includes the following steps: Step 101: Obtain the error-corrected data obtained by the solid-state drive after error correction decoding when reading data, and determine the current environmental drift direction of the flash memory cells in the solid-state drive.

[0021] In some embodiments, the error-corrected data refers to the successfully decoded data output by the LDPC decoder through iterative calculation. The environmental drift direction is used to characterize the dominant noise direction of the current physical channel, i.e., the offset direction of the NAND flash memory cell threshold voltage distribution relative to a standard value.

[0022] It should be noted that in deep aging scenarios of long-term NAND flash memory use, the center of the threshold voltage distribution of the flash memory cell will shift relative to the factory standard value. This shift usually manifests as unidirectional charge leakage or charge coupling interference. When the LDPC decoder activates the soft decision reread mechanism in such a high signal-to-noise ratio deterioration environment, there is a certain probability that the decoder will converge to an erroneous codeword that satisfies the check equation but is not the original written data, i.e., false convergence occurs.

[0023] Optionally, the process of acquiring the error-corrected data and determining the direction of environmental drift includes: during the data reading operation performed by the solid-state drive controller chip, the decoder first attempts to perform hard-decision decoding using the default voltage; when the hard-decision LDPC decoder fails to converge, the system triggers a soft-decision recovery process; before initiating a soft-decision reread attempt, the controller chip completely copies the original read data that caused the hard decision failure to a dedicated buffer in Static Random-Access Memory (SRAM) for freezing, which is recorded as the original hard-decision bitstream. This bitstream remains static throughout the subsequent soft-decision iteration cycle to ensure the stability of the comparison benchmark; when the LDPC soft-decision decoder outputs a verification pass signal, the successfully decoded error-corrected data is acquired, and the voltage offset index used for the current successful decoding is locked, thereby determining the direction of environmental drift.

[0024] Step 102: Based on the preset mapping relationship, determine the physical voltage change direction corresponding to the logical flip type of the target bit in the error-corrected data.

[0025] The target bit is at least one bit in the error-corrected data that has been flipped relative to the original read data. The mapping relationship characterizes the statistical correlation between the logical flip type and the physical voltage change direction. The logical flip type characterizes whether the bit value changes from 0 to 1 or from 1 to 0. The physical voltage change direction characterizes the trend of flash memory cell level changes corresponding to this logical flip at the physical level.

[0026] In high-density NAND (such as TLC / QLC) architectures, directly and accurately probing the direction of voltage changes in physical cells using single-page data is either impractical or prohibitively expensive in hardware. Therefore, this application employs a lookup table mapping method based on statistical probability to interpret bit-flipping behavior in the logic domain as voltage tendencies in the physical domain, facilitating subsequent risk assessment.

[0027] Optionally, the process of determining the physical voltage change direction based on the preset mapping relationship includes: obtaining the error-corrected bitstream from the output buffer of the LDPC decoding engine and reading the original hard decision bitstream from the SRAM dedicated buffer; performing descrambling operations on both using the scrambling seed corresponding to the current physical page address to restore the error-corrected data and the original data in the physical write domain; comparing the error-corrected data and the original data bit by bit to identify all bit indices that have flipped and to determine the flipping type of each target bit; and querying the preset flipping tendency mapping table according to the type of the current page being read (Page Type, such as Lower Page, Middle Page, Upper Page of TLC) and the flipping type of each target bit to obtain the physical voltage change direction corresponding to the flipping behavior.

[0028] Step 103: Based on the direction of environmental drift and the direction of physical voltage change of the target bit, conduct a risk assessment on the error-corrected data to determine whether the error-corrected data is unreliable data with the risk of silent data corruption.

[0029] Optionally, the risk assessment process includes: for each target bit that has flipped, calculating the product of the environmental drift direction and the physical voltage change direction of the bit to generate a forward drift risk identifier; if the product is positive, it indicates that the correction direction of the bit is the same as the environmental drift direction, and it is determined to be a forward drift risk bit; if the product is negative, it indicates that the correction direction is opposite to the environmental drift direction, and it is determined to be a valid correction bit; counting all risk bits, and combining the distribution and number of risk bits, generating a risk score to characterize the reliability of the data after error correction; comparing the risk score with a preset threshold, if the risk score is less than or equal to the preset threshold, the data after error correction is determined to be reliable data and output; if the risk score is greater than the preset threshold, the data after error correction is determined to be unreliable data and blocked.

[0030] Understandably, in a channel dominated by a single physical mechanism, effective error correction should reverse the deviation of the data state back to the original distribution center; that is, the error correction direction should be opposite to the direction of environmental drift. Conversely, if the LDPC decoding algorithm outputs a correction in the same direction as the environmental drift, it means that the algorithm has determined that the flash memory cell has experienced an abnormal drift far exceeding the average level, which is likely a miscorrection caused by the decoder converging to the erroneous codeword.

[0031] Based on the above technical solution, this application establishes a benchmark for physical verification by acquiring the corrected data and determining the direction of environmental drift; it maps logic flips to physical voltage change directions through a preset mapping relationship, realizing the conversion from the logic domain to the physical domain; and it conducts risk assessment on the corrected data through vector consistency analysis, identifying high-risk bits that need to be corrected along the direction of environmental drift. Compared with traditional schemes that rely solely on LDPC mathematical verification, the physical direction alignment mechanism introduced in this application can capture the misjudgment behavior of the LDPC decoder in deep aging scenarios, avoiding silent data corruption from the source and significantly improving the data reliability of solid-state drives in harsh channel environments. Furthermore, by using a statistical probability-based mapping table mechanism instead of real-time physical detection, it can be implemented on existing main control chip architectures with only firmware upgrades, without increasing hardware costs or read latency.

[0032] In one possible implementation, the process of determining the current environmental drift direction of the flash memory cells in the solid-state drive in step 101 above specifically includes: Step 201: In response to the low-density parity check code decoder, the low-density parity check code decoder adjusts the reading reference voltage, completes error correction decoding of the original reading data, and locks the voltage offset index used for the current successful decoding.

[0033] Optionally, the voltage offset index represents the voltage level number currently in effect for the master control soft decision, directly reflecting the current aging state and drift characteristics of the physical channel. When the LDPC soft decision decoder outputs a verification pass signal, the Flash Interface Module (FIM) locks the currently effective voltage offset index within the same clock cycle.

[0034] Step 202: Query the preset voltage offset specification table according to the voltage offset index to obtain the corresponding reference voltage offset value.

[0035] The reference voltage offset value is a signed numerical value used to characterize the magnitude and direction of voltage drift.

[0036] Optionally, the Voltage Offset SpecTable records the specific voltage adjustment for each voltage offset index. The reference voltage offset value is a signed millivolt (mV) level value; a positive value indicates that the read voltage is shifted to a higher potential, and a negative value indicates that it is shifted to a lower potential.

[0037] Step 203: Determine the direction of environmental drift based on the sign of the reference voltage offset value.

[0038] As an example, the logic for determining the environmental drift direction indicator satisfies the following rules: If the reference voltage offset value is less than zero, it indicates that the current channel characteristic is dominated by charge leakage (threshold voltage shifted to the left), and the environment drift direction is assigned as -1.

[0039] If the reference voltage offset value is greater than zero, it indicates that the current channel characteristic is dominated by interference coupling (threshold voltage shifted to the right), and the environment drift direction is assigned a value of +1.

[0040] If the reference voltage offset value is equal to zero, it indicates that there is no significant directional drift, and the environmental drift direction is assigned as 0.

[0041] Based on the above technical solution, this application obtains the quantized parameters characterizing the channel state by locking the voltage offset index; converts the index into specific voltage offset values ​​by querying the voltage offset specification table; and determines the environmental drift direction through sign determination. This solution fully utilizes the voltage offset index already generated during the LDPC soft decision process, obtaining the physical verification benchmark without additional hardware probing. It tightly integrates the quantized characterization of the channel state with the error correction decoding process, making the acquisition of the physical verification benchmark real-time and accurate, without increasing additional reading latency or hardware costs, and has good engineering practicality.

[0042] In one possible implementation, step 102 above, which determines the physical voltage change direction corresponding to the logical flip type of the target bit in the error-corrected data based on a preset mapping relationship, specifically includes: Step 301: Compare the original read data with the error-corrected data, identify all target bits that have undergone bit flipping, and determine the flipping type of each target bit.

[0043] The flip type is used to characterize whether the bit value changes from 0 to 1 or from 1 to 0.

[0044] In some embodiments, the main control chip obtains the successfully decoded error-corrected bitstream from the output buffer of the LDPC decoding engine and reads the original hard decision bitstream from the SRAM dedicated buffer. Using the scrambling seed corresponding to the current physical page address, it performs descrambling operations on both to restore the error-corrected data and the original data in the physical write field. Then, it compares and identifies all bit indices that have flipped bit by bit.

[0045] Step 302: Based on the physical page type of the flash memory cell and the flip type of each target bit, query the preset mapping relationship to obtain the physical voltage change direction corresponding to each target bit.

[0046] Optionally, the default mapping relationship is the FlipTendencyMap, which is an empirical database built based on extensive offline characteristic analysis of NAND flash memory chips. It defines the direction of physical voltage change that is statistically highly probable for a specific logical flip type under a specific physical page type.

[0047] As an example, taking 3DTLC particles as an example, this mapping table can be configured as follows: For LowerPage: Logical flip 1→0: Statistically, this mainly corresponds to a physical state transition from L0(111) to L1(110) or higher, with the voltage tending to increase, and the mapping value is +1. Logical flip 0→1: Statistically, this mainly corresponds to a physical state rollback, with the voltage tending to decrease, and the mapping value is -1.

[0048] For MiddlePage: A logical flip 1→0: Based on Gray code characteristics, this may correspond to a voltage decrease (e.g., L1→L2), with a mapping value of -1. A logical flip 0→1: This may correspond to a voltage increase, with a mapping value of +1.

[0049] For UpperPage (high-order page): Based on the characteristics of Gray code encoding, the mapping relationship between logical flip and physical voltage change direction is determined according to the specific threshold voltage state transition. The corresponding physical voltage change direction is obtained through a preset known state transition lookup table (for specific implementation, please refer to relevant technologies, which will not be elaborated here).

[0050] Based on the type of the currently read page and the toggle type of each target bit, the main control chip queries the aforementioned toggle tendency mapping table to directly obtain the cell level change direction corresponding to the toggle behavior. If the lookup result is +1, it means that the flip of this bit statistically tends to increase the physical voltage; if the lookup result is -1, it means that the flip of this bit statistically tends to decrease the physical voltage.

[0051] Based on the above technical solution, this application accurately identifies the target bit and its flip type by comparing the original data with the error-corrected data. By introducing a flip tendency mapping table based on statistical probability, the complex physical detection problem is transformed into an efficient table lookup operation. This solution avoids the hardware limitation of not being able to accurately determine the voltage direction per page under the TLC / QLC architecture. Without reading data from sibling pages, it completes the alignment from logical error correction behavior to physical voltage transition tendency with extremely low computational cost, providing an implementable engineering benchmark for subsequent vector consistency audits, while ensuring the deployability of the solution on existing main control chips.

[0052] In one possible implementation, step 103 above, which involves performing a risk assessment on the corrected data based on the environmental drift direction and the physical voltage change direction of the target bit, to determine whether the corrected data is untrusted data at risk of silent data corruption, specifically includes: Step 401: For each target bit, determine whether the target bit is a risk bit based on the direction of environmental drift and the corresponding direction of physical voltage change.

[0053] Optionally, this step can be implemented as follows: calculate the product of the environmental drift direction and the physical voltage change direction; if the product is positive, determine that the environmental drift direction and the physical voltage change direction are the same, and identify the target bit as the risk bit.

[0054] As an example, drift risk identification Satisfy the following formula: in, This indicates the forward drift risk flag for the i-th flipped bit; This indicates the direction of environmental drift, with a value of +1, -1, or 0. This indicates the direction of the level change of the i-th flipped bit, and its value is +1 or -1.

[0055] It serves as an environmental drift direction identifier, representing the channel-dominated voltage movement direction, and as a reference for physical verification; it is a signed integer. The direction of the unit level change represents the statistical physical voltage change direction corresponding to the logic flip, and is obtained by looking up a probability table. It is a signed integer. This is a drift risk indicator, representing whether the correction direction is in the same direction as the environmental drift, and is an integer.

[0056] Step 402: Count all risk bits and generate a risk score to characterize the credibility of the data after error correction based on the distribution and quantity of risk bits.

[0057] Optionally, this step can be implemented as follows: obtain the absolute value of the reference voltage offset value, and determine the weighting coefficient positively correlated with the environmental offset amplitude based on the absolute value and a preset normalization step size constant; divide the error-corrected data into multiple consecutive logical sectors, and count the number of risk bits contained in each logical sector; for each logical sector, if the number of risk bits it contains exceeds a preset background noise filtering threshold, then accumulate the weighting coefficients of each risk bit in the logical sector to obtain the sector risk value of the logical sector; sum the sector risk values ​​of each logical sector to obtain the risk score.

[0058] As an example, weighting coefficients Satisfy the following formula: in, , is the offset amplitude weighting coefficient, which characterizes the degree of influence of environmental stress on the risk of miscorrection. Its value increases monotonically with the degree of channel degradation and is a dimensionless parameter. The absolute value of the reference voltage offset, in millivolts (mV), characterizes the degree of channel offset. This is a normalized step size constant, the value of which is set according to the read retry voltage adjustment step size of the NAND flash memory, for example, 15mV or 20mV; This is a parameter tuning coefficient, with a value that is an extremely small positive number (e.g., 0.001). It is used to prevent abnormal situations where the denominator is zero due to configuration errors. The dimensions are consistent.

[0059] This formula converts the physical voltage offset into a dimensionless relative multiple by dividing the absolute value of the voltage offset by the normalization step size, and then adds 1 to ensure that the weighting coefficient is always greater than or equal to 1. With The increase of leads to an increase in the numerator, resulting in Linear growth. In the denominator... Used for calibrating dimensions to ensure that differences in voltage characteristics between different flash memory chips do not lead to an imbalance in the weighting coefficients. The addition of provides numerical stability protection, avoiding division-by-zero errors in extreme cases.

[0060] This characterizes the impact of environmental stress on error correction risk, and its value increases monotonically with the degree of channel degradation. When the channel environment is good (…),… When it is smaller, When the value is close to 1, the risk contribution is basically unaffected by weighting; when the channel environment deteriorates ( When it is relatively large, A value significantly greater than 1 indicates that the same number of risk bits will produce a higher risk score, enabling the risk decision sensitivity to automatically adapt to changes in channel state.

[0061] As an example, cumulative risk score ( The following formula is satisfied: in, The cumulative risk score represents the total risk of incorrect error correction across the entire page and serves as the basis for the final judgment. M The number of logical sectors is determined by the LDPC codeword size and sector granularity. Count the risk of the k-th sector; This is the noise floor filtering threshold, used to tolerate occasional random physical fluctuations, and is typically set to 2 to 4 bits. This is the set of indices for risk bits within the k-th sector; (⋅) is an indicator function used to implement conditional judgments; This is the weighting factor for the aforementioned offset magnitude.

[0062] The formula first counts the risk bits for each logical sector and then compares them with the background noise filtering threshold. Only when the risk bit density of a sector exceeds the background noise threshold is the risk within that sector considered a valid signal, and the weighted contribution of the risk bits in that sector is added to the total score; otherwise, that sector is considered background noise and filtered out. Finally, the risk values ​​of all valid sectors are summed to obtain the comprehensive risk index after direction filtering, amplitude weighting, and spatial filtering.

[0063] It is a comprehensive risk quantification index after multi-dimensional filtering and weighting, which takes into account the directional consistency of risk bits, the magnitude of environmental stress, and spatial distribution characteristics. The higher the value, the greater the risk of silent data corruption on the page. This indicator provides a reliable quantitative basis for subsequent threshold determinations, achieving an effective mapping from micro-level bit-scale risk to macro-level data-scale credibility.

[0064] Step 403: Based on the comparison between the risk score and the preset threshold, determine whether the corrected data is unreliable data.

[0065] Optionally, this step can be implemented as follows: compare the risk score with a preset risk interception threshold; if the risk score is less than or equal to the risk interception threshold, determine that the corrected data is trustworthy data and output it; if the risk score is greater than the risk interception threshold, determine that the corrected data is untrustworthy data and block it, and trigger the heterogeneous data recovery process.

[0066] Among them, the risk interception threshold ( ) is a fixed empirical constant, the value of which is set according to the system's error correction tolerance requirements. For example, in an embodiment of an enterprise-level SSD controller, It can be set to 150 points.

[0067] Based on the above technical solutions, this application achieves rapid determination of the physical rationality of single-bit error correction behavior by calculating the product of the environmental drift direction and the physical voltage change direction; by introducing a weighting coefficient based on the offset amplitude, it solves the problem that simple bit counting cannot reflect the degree of signal-to-noise ratio degradation, and realizes automatic adjustment of risk judgment sensitivity; through logical sector division and density filtering, it effectively eliminates the interference of discrete random noise; and by comparing the accumulated risk score with a fixed threshold, it realizes a binary judgment of the credibility of the error-corrected data. This solution ensures the security of high-risk data while avoiding misjudgment and performance loss in low-noise environments, and solves the problem of read performance degradation caused by over-protection in existing technologies.

[0068] In one possible implementation, before determining that the corrected data is untrustworthy and blocking it in step 403 above, the method further includes: Maintain the total number of times data blocking is triggered within the preset time window; compare the total number with the preset maximum interception frequency threshold; if the total number is less than the maximum interception frequency threshold, execute the blocking and triggering heterogeneous data recovery process steps; if the total number has reached the maximum interception frequency threshold, trigger circuit breaker protection and stop executing the blocking and triggering heterogeneous data recovery process steps.

[0069] For example, the preset time window is usually set to 1 second, and the maximum interception frequency threshold is ( For example, it can be set to 10 times / second. The main control chip maintains a time-window-based interception counter, recording the total number of interceptions triggered by this risk assessment mechanism within the most recent unit time window. .

[0070] Before generating a blocking signal, the system checks the current... Has it exceeded? .like Execute the normal blocking logic and trigger the subsequent heterogeneous data recovery process, while incrementing the counter by 1. If This triggers the circuit breaker protection. At this point, the system determines that the frequent interceptions may stem from extensive physical damage to the media or an uncorrectable systemic failure, and continuing RAID recovery can no longer guarantee service quality. Therefore, the system forcibly stops interception, directly reports the uncorrectable error to the host, or allows data to pass through in degraded mode and marks a critical warning in the log to avoid the system getting stuck in the recovery loop.

[0071] Based on the above technical solutions, this application introduces an interception, rate limiting, and circuit breaker protection mechanism to ensure data security while also considering system availability and service quality. This mechanism prevents endless interception-recovery loops caused by overly sensitive algorithms or complete media damage, avoids read performance avalanche, and ensures that the storage system can maintain basic read and write service capabilities even in the face of large-scale media damage, demonstrating the engineering robustness and practicality of the solution.

[0072] In one possible implementation, the heterogeneous data recovery process includes: locating the internal independent disk redundant array stripe to which the blocked data belongs based on its physical address; initiating a read operation on other associated data pages and check pages in the stripe; using the read associated data pages and check pages, reconstructing the original bit information corresponding to the blocked data through an XOR operation, and outputting the reconstructed data.

[0073] Specifically, an internal RAID stripe typically spans different flash dies or planes and consists of N data pages and one or more parity pages. In response to a blocking signal, the main controller activates the internal RAID controller: first, it locates the RAID stripe to which the intercepted data page belongs based on its target physical address; then, it suspends the current transmission request for the target page and initiates read operations on all other associated data pages and parity pages on that stripe. The data of these associated pages is recovered through their respective independent LDPC decoding paths; the RAID controller uses the collected associated page data to perform an XOR operation, and reconstructs the original bit information of the target page through inverse operations according to RAID principles; finally, it uses the reconstructed data stream as the final output, replacing the discarded error-corrected data transmission to the host interface, completing the read request response.

[0074] Since RAID recovery is based on deterministic algebraic operations at the stripe dimension, its results are completely independent of the LDPC probabilistic convergence characteristics of the target page itself. Therefore, it can mathematically avoid the silent errors caused by LDPC misconvergence.

[0075] Based on the above technical solution, this application utilizes the existing RAID resources within the SSD to reconstruct the original data losslessly after intercepting LDPC erroneous data, avoiding IO interruptions caused by direct errors. This solution achieves seamless integration of data verification and data recovery, maintaining high availability of storage services while ensuring data correctness, forming a complete closed loop from risk identification to data recovery, and further improving the practicality and reliability of the entire data verification method.

[0076] Please see Figure 2 The diagram illustrates a system architecture of a data verification system based on a solid-state drive (SSD) controller chip, according to an embodiment of the present invention. This system includes an acquisition unit 201, a behavior analysis unit 202, and a risk assessment and verification unit 203. The units communicate bidirectionally via a communication link to ensure real-time interaction of collected data and analysis results. The communication link can employ a bus connection or an internal data path to meet the communication needs between units within the controller chip.

[0077] The acquisition unit 201 is used to acquire the error-corrected data obtained by the solid-state drive after error correction decoding when reading data, and to determine the current environmental drift direction of the flash memory cells in the solid-state drive.

[0078] The behavior analysis unit 202 is used to determine the physical voltage change direction corresponding to the logical flip type of the target bit in the error-corrected data based on a preset mapping relationship; wherein, the target bit is at least one bit in the error-corrected data that has flipped relative to the original read data; the mapping relationship is used to characterize the statistical correlation between the logical flip type and the physical voltage change direction.

[0079] The risk assessment and verification unit 203 is used to perform risk assessment on the error-corrected data based on the direction of environmental drift and the direction of physical voltage change of the target bit, and to determine whether the error-corrected data is unreliable data with the risk of silent data corruption.

[0080] It should be noted that the order of the embodiments described above is merely for descriptive purposes and does not represent the superiority or inferiority of the embodiments. The processes depicted in the accompanying drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0081] The various embodiments in this specification are described in a progressive manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.

Claims

1. A data verification method based on a solid-state drive controller chip, characterized in that, The method includes: Obtain the error-corrected data obtained by the solid-state drive after error correction and decoding when reading data, and determine the current environmental drift direction of the flash memory cells in the solid-state drive; Based on a preset mapping relationship, the physical voltage change direction corresponding to the logical flip type of the target bit in the error-corrected data is determined; wherein, the target bit is at least one bit in the error-corrected data that has flipped relative to the original read data; the mapping relationship is used to characterize the statistical correlation between the logical flip type and the physical voltage change direction. Based on the environmental drift direction and the physical voltage change direction of the target bit, a risk assessment is performed on the error-corrected data to determine whether the error-corrected data is unreliable data with the risk of silent data corruption.

2. The data verification method based on a solid-state drive controller chip according to claim 1, characterized in that, Determining the current environmental drift direction of the flash memory cells in the solid-state drive includes: In response to the low-density parity-check code decoder, the original read data is corrected and decoded by adjusting the read reference voltage, and the voltage offset index used for the current successful decoding is locked. The reference voltage offset value is obtained by querying the preset voltage offset specification table according to the voltage offset index. The reference voltage offset value is a signed value used to characterize the magnitude and direction of voltage drift. The direction of environmental drift is determined based on the sign of the reference voltage offset value.

3. The data verification method based on a solid-state drive controller chip according to claim 1, characterized in that, Based on a preset mapping relationship, the physical voltage change direction corresponding to the logical flip type of the target bit in the error-corrected data is determined, including: By comparing the original read data with the error-corrected data, all target bits that have undergone bit flipping are identified, and the flipping type of each target bit is determined; the flipping type is used to characterize whether the bit value changes from 0 to 1 or from 1 to 0. Based on the physical page type to which the flash memory cell belongs and the flip type of each target bit, the preset mapping relationship is queried to obtain the physical voltage change direction corresponding to each target bit.

4. The data verification method based on a solid-state drive controller chip according to claim 1, characterized in that, Based on the environmental drift direction and the physical voltage change direction of the target bit, a risk assessment is performed on the error-corrected data to determine whether the error-corrected data is unreliable data with a risk of silent data corruption, including: For each target bit, it is determined whether the target bit is a risk bit based on the environmental drift direction and the corresponding physical voltage change direction; All risk bits are counted, and a risk score is generated to characterize the reliability of the corrected data based on the distribution and quantity of the risk bits. Based on the comparison between the risk score and the preset threshold, it is determined whether the corrected data is unreliable data.

5. The data verification method based on a solid-state drive controller chip according to claim 4, characterized in that, Based on the environmental drift direction and the corresponding physical voltage change direction, determine whether the target bit is a risky bit, including: Calculate the product of the environmental drift direction and the physical voltage change direction; If the product is positive, it is determined that the direction of environmental drift is the same as the direction of physical voltage change, and the target bit is identified as a risk bit.

6. The data verification method based on a solid-state drive controller chip according to claim 4, characterized in that, All risk bits are counted, and based on the distribution and quantity of the risk bits, a risk score is generated to characterize the reliability of the corrected data, including: Obtain the absolute value of the reference voltage offset, and determine the weighting coefficient that is positively correlated with the environmental offset amplitude based on the absolute value and a preset normalization step size constant. The corrected data is divided into multiple consecutive logical sectors, and the number of risk bits contained in each logical sector is counted. For each logical sector, if the number of risk bits it contains exceeds a preset background noise filtering threshold, the weighting coefficients of each risk bit in the logical sector are summed to obtain the sector risk value of the logical sector. The risk score is obtained by summing the sector risk values ​​of each logical sector.

7. The data verification method based on a solid-state drive controller chip according to claim 4, characterized in that, Based on the comparison between the risk score and a preset threshold, it is determined whether the corrected data is unreliable, including: The risk score is compared with a preset risk interception threshold. If the risk score is less than or equal to the risk interception threshold, the corrected data is determined to be reliable data and is output. If the risk score is greater than the risk interception threshold, the corrected data is determined to be untrustworthy and blocked, and the heterogeneous data recovery process is triggered.

8. The data verification method based on a solid-state drive controller chip according to claim 7, characterized in that, Before determining that the corrected data is untrustworthy and blocking it, the method further includes: Maintain the total number of times data blocking is triggered within the preset time window; The total number of interceptions is compared with a preset maximum interception frequency threshold. If the total number of times is less than the maximum interception frequency threshold, then the steps of blocking and triggering the heterogeneous data recovery process are executed; If the total number of attempts has reached the maximum interception frequency threshold, the circuit breaker protection is triggered, and the steps of blocking and triggering the heterogeneous data recovery process are stopped.

9. The data verification method based on a solid-state drive controller chip according to claim 7, characterized in that, The heterogeneous data recovery process includes: Based on the physical address of the blocked data, locate the internal independent disk redundant array stripe to which it belongs; Initiate read operations on other associated data pages and verification pages in the stripe; Using the read associated data page and check page, the original bit information corresponding to the blocked data is reconstructed through XOR operation, and the reconstructed data is output.

10. A data verification system based on a solid-state drive controller chip, characterized in that, The system includes: The acquisition unit is used to acquire the error-corrected data obtained by the solid-state drive after error correction decoding when reading data, and to determine the current environmental drift direction of the flash memory cells in the solid-state drive. The behavior analysis unit is used to determine the physical voltage change direction corresponding to the logical flip type of the target bit in the error-corrected data based on a preset mapping relationship; wherein, the target bit is at least one bit in the error-corrected data that has flipped relative to the original read data; the mapping relationship is used to characterize the statistical correlation between the logical flip type and the physical voltage change direction; The risk assessment and verification unit is used to perform a risk assessment on the error-corrected data based on the environmental drift direction and the physical voltage change direction of the target bit, and to determine whether the error-corrected data is unreliable data with the risk of silent data corruption.

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