A memory test command generation method

Abstract

The application discloses a memory test command generation method. By redesigning the command generator, the command generator has the capability of automatically generating, self-defining generating and mixedly generating test commands. The command generator can not only automatically generate test commands for common scenes by one key, but also generate test commands with strong purpose by self-defining programming. The command generator can also combine the automatic generation and the self-defining generation to generate more flexible test commands. The command generator can be completely compatible with common storage protocols such as DDR, LPDDR and GDDR, and can generate test commands for multiple protocols by using one set of tools. The command generator is flexible to use and simple to operate, and can cover a wide range of test scenes.

Description

Technical Field

[0001] This invention belongs to the field of memory technology, and more specifically, relates to a method for generating memory test commands. Background Technology

[0002] As memory chip storage density and manufacturing processes gradually improve, manufacturing defects in memory chips are becoming increasingly frequent, such as cell stuck (0 / 1), adjacent row coupling interference, address decoder errors, and analog circuit manufacturing defects. These defects directly affect yield and require screening before use. Memory chip screening equipment typically generates a test pattern with certain patterns, which is injected into the chip through pins for testing, and the test results are used to determine the chip's quality. Currently, data buffer memory (DBM) testing equipment is commonly used for chip screening. This is a store-and-playback device that requires pre-generated test patterns containing various operations on the chip. These patterns are then injected into the DBM's memory, and the DBM reads the pattern line by line and converts it into memory chip operation timings.

[0003] Traditionally, DBM patterns are obtained by capturing waveforms from Register-Transfer Level (RTL) pre-simulation waveforms. The main drawback is the need to process large simulation waveform dump files, compress them according to specific algorithms, and insert special markers at certain pattern locations to control the testing process. If the test address range of the particles is large, simulation needs to be performed several days in advance, consuming significant time and space resources. Later, a method was proposed using pseudocode for memory operations, which is then translated into patterns by software. The main drawback is the need to write the pseudocode in advance; if the testing process is complex, the pseudocode will also be complex, and testers must be familiar with memory operation protocols, obviously raising the barrier to entry. Summary of the Invention

[0004] To address the aforementioned deficiencies or improvement needs of existing technologies, this invention provides a method for generating memory test commands. This method aims to solve the problems of traditional DBM pattern generators, which typically rely on writing and translating pseudocode for memory operations, resulting in limited applicability, low generation efficiency, and high technical barriers.

[0005] To achieve the above objectives, the present invention provides a method for generating memory test commands, comprising: Generate a command sequence based on the configuration parameters; Insert delay information between any two objects in a command sequence; The synchronization domain of the clock synchronization command in the command sequence is calibrated; Insert refresh commands into the command sequence.

[0006] In some implementations, command sequences can be generated automatically using typical scenario generation methods, including: Read the configuration parameters and test scenario information, and create a blank sequence based on the configuration parameters and test scenario information; Generate a read / write sequence containing definite address information using a blank sequence; Scan the read and write sequence in ascending order from beginning to end, and insert an activation command and a clock synchronization command before the write command of the first address combination that appears in the read and write sequence. Scan the read and write sequence in reverse order from tail to head, and insert a precharge command after the read command of the first address combination that appears in the read and write sequence; The read and write sequence is scanned in ascending order from beginning to end. Between two read and write commands that cause a row switch, a precharge command, an activation command, and a clock synchronization command are inserted in sequence.

[0007] In some implementations, a random scenario can also be automatically generated to generate command sequences, including: Read the configuration parameters and test scenario information, and create a blank sequence based on the configuration parameters and test scenario information; A sequence of write commands with completely random address information is generated using a blank sequence. Then, the write command sequence is scanned from beginning to end, and a read command with matching address information is inserted at a random position after each write command to generate a read-write sequence. Scan the read and write sequence in ascending order from beginning to end, and insert the activation command and clock synchronization command at any position before the write command of the first address combination that appears in the read and write sequence. Scan the read and write sequence in reverse order from tail to head, and insert a precharge command at any position after the read command for the first occurrence of the address combination; The read and write sequence is scanned in ascending order from beginning to end. Between two read and write commands that cause a row switch, a precharge command, an activation command, and a clock synchronization command are inserted in sequence.

[0008] In some implementations, a custom generation method can also be used to generate command sequences, including: Read the configuration parameters, test scenario information, and memory operation pseudocode program file, and create an empty sequence based on the configuration parameters and test scenario information; Scan the pseudocode, read from the pseudocode, and calculate the values ​​of the initial variables; Scan all flow control structure characters, record the position of the flow control structure characters, calculate the conditional expression, and mask the positions occupied by branches that do not meet the conditions and the positions of individual comment lines. The pseudocode is scanned again, automatically avoiding the blocked lines of code. When the command operation function name is detected, the line containing the command operation function name is split into strings, the valid information is extracted, and it is converted into a command object and stored in the blank sequence. When the end character of the for loop is detected, it is determined whether the current number of iterations is less than the number of iterations defined at the beginning of the for loop. If the current number of iterations is less than the defined number of iterations, the loop jumps to the line below the corresponding for loop beginning and continues to repeat the operation. Otherwise, the loop body is exited and the next line of code is executed until the loop ends.

[0009] In some implementations, a hybrid generation method can also be used to generate command sequences, including: Create a two-dimensional array, with rows corresponding to test scenarios and columns corresponding to the configuration parameters carried by each scenario; Scan each row of the two-dimensional array from beginning to end, and call the command sequence generation method corresponding to each scene in turn to generate the operation command set for each scene, and combine them to form a command sequence; among them, the sequence generation method corresponding to the scene can be the automatic generation method for typical scenes, the automatic generation method for random scenes, or a custom generation method.

[0010] In some implementations, inserting delay information between any two objects in a command sequence includes: scanning the command sequence in ascending order from beginning to end, determining the type of the current command and the next command, and inserting delay information within the timing parameter range required by the protocol.

[0011] In some implementations, the delay information includes minimum delay, random delay, and custom delay; wherein, the minimum delay is inserted according to the minimum value of AC timing in the protocol, the random delay is inserted according to a random value larger than the minimum value, and the custom delay is a characteristic value specified according to test requirements.

[0012] In some implementations, calibrating the synchronization domain of the clock synchronization command in the command sequence includes: Scan the entire command sequence of non-empty objects in ascending order from beginning to end; Upon finding a clock synchronization command, complete the synchronization domain calibration of the clock synchronization command; Continue scanning the command sequence to find the next clock synchronization command; When a clock synchronization command is found, the synchronization domain calibration of the clock synchronization command is completed. This process is repeated until the synchronization domain calibration of all clock synchronization commands in the command sequence is completed.

[0013] In some implementations, upon finding a clock synchronization command, completing the synchronization domain calibration of the clock synchronization command includes: Continue searching for non-empty objects from the position where the clock synchronization command is located, gradually accumulating the delay, and comparing it with the initial synchronization domain time of the clock synchronization command; If the accumulated delay is less than the initial synchronization domain time and a new clock synchronization command is detected, delete the new clock synchronization command. If the accumulated delay is less than the initial synchronization domain time and a new read / write command is detected, the synchronization domain of the current clock synchronization command is expanded to the initial synchronization domain time plus the current accumulated delay. When the accumulated delay exceeds the initial synchronization domain time and a new read / write command is detected, a new clock synchronization command is inserted before the new read / write command.

[0014] In some implementations, inserting a refresh command into the command sequence includes: Scan the entire command sequence of non-empty objects in ascending order from beginning to end, and gradually accumulate the delay; When the accumulated delay is greater than or equal to tREFIe, insert a precharge command and a refresh command after the current non-empty object, adjust the delay value of the current non-empty object, and clear the accumulated delay. Continue scanning the command sequence from the current non-empty object, gradually accumulating the delay; When the accumulated delay is greater than or equal to tREFIe, a precharge command and a refresh command are inserted after the current non-empty object, the delay value of the current non-empty object is adjusted, and the accumulated delay is cleared. This process is repeated until the entire sequence has been filled with precharge commands and refresh commands; where tREFIe is the internal effective refresh interval.

[0015] Overall, compared with the prior art, the above-described technical solution conceived by this invention has the following beneficial effects: By redesigning the command generator, it is equipped with the ability to automatically generate, customize, and hybrid generate test commands. It can not only automatically generate test commands for common scenarios with one click, but also generate highly targeted test commands through custom programming. Furthermore, it can combine automatic generation and custom generation to generate more flexible test commands. It is fully compatible with common memory protocols such as DDR, LPDDR, and GDDR, realizing the generation of test commands for multiple protocols using a single tool. It is flexible to use, easy to operate, and covers a wide range of test scenarios. Attached Figure Description

[0016] Figure 1 This is a flowchart of the memory test command generation method according to an embodiment of the present invention; Figure 2 This is a flowchart illustrating the automatic generation method for generating command sequences according to an embodiment of the present invention; Figure 3 This is a flowchart illustrating the generation of command sequences using a custom generation method according to an embodiment of the present invention; Figure 4 This is a flowchart illustrating the hybrid generation method for generating command sequences according to an embodiment of the present invention; Figure 5 This is a schematic diagram illustrating the correspondence between the command line of the sequence and the sub-scenes of the two-dimensional array in the hybrid generation method of this invention. Figure 6 This is a flowchart illustrating the calibration of the synchronization domain of a clock synchronization command in a command sequence according to an embodiment of the present invention. Figure 7 This is a flowchart illustrating the synchronization domain calibration process for completing a clock synchronization command according to an embodiment of the present invention. Figure 8 This is a schematic diagram illustrating the specific operation methods of three scenarios during the synchronization domain calibration process of completing the clock synchronization command according to an embodiment of the present invention. Figure 9 This is a flowchart of inserting a refresh command into a command sequence according to an embodiment of the present invention. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. As those skilled in the art will recognize, the described embodiments can be modified in various ways without departing from the spirit or scope of this application. Therefore, the drawings and description are considered exemplary in nature and not restrictive.

[0018] The command generator is the core component of the DBM pattern generator. Once the command operation is determined, the contents of the clock (clk) and data (data), as well as the delay, are essentially determined according to the storage protocol. Therefore, this invention focuses on providing a detailed description of the method for generating test commands.

[0019] The generation of memory test commands mainly includes setting configuration parameters and generating command (cmd) sequences.

[0020] The configuration parameter settings mainly include the acquisition and calculation of protocol-related parameters and test scenario-related parameters. Protocol-related parameters primarily include command-to-command timing parameters, command-to-clock timing parameters, and command-to-data timing parameters. Some of these timing parameters can be obtained through mode register configuration, some can be calculated from the selected operating mode, rate, bit width, etc., and the remainder can be obtained from the protocol's electrical parameter information. Test scenario-related parameters are obtained directly by specifying the test scenario. These parameters guide the generation of test command sequences.

[0021] The CMD sequence is represented as a two-dimensional matrix. Rows correspond to objects in the sequence, and the number of rows represents the number of objects in the sequence (sequence length). Columns correspond to the fields contained in each object, and the number of columns represents the number of fields such as memory operation commands, addresses, and delay information contained in each object. Objects in the sequence exist not only in time intervals (delays) but also in spatial intervals, meaning the objects in the sequence are sparse. This ensures that when generating the clk and data sequences later, objects in the sequence can be correctly aligned at certain points, and the delay information is correct. The generation of CMD sequences is closely related to the test scenarios, such as basic read / write scenarios, low-power input / output scenarios, and frequency switching scenarios. Therefore, to comprehensively cover various test scenarios, three CMD sequence generation modes are proposed: automatic generation, custom generation, and hybrid generation.

[0022] The automatic generation method includes typical scenarios and random scenarios. Typical scenarios define several typical test scenarios, such as checkerboard tests, hammer tests, and Bank Group interleaving tests. Random scenarios define a random command sequence, where adjacent commands can have any combination specified by the protocol, covering various AC timing tests. The custom generation method uses pseudocode programming to generate highly targeted test patterns to cover peripheral scenarios. Combining the automatic and custom generation methods arbitrarily through an association vector creates a new hybrid generation method, greatly expanding the flexibility of testing. Command operations generated by these three methods are uniformly stored in a cmd sequence for subsequent test pattern generation.

[0023] The memory test command generation method of the present invention will be described in detail below. The specific example section uses the LPDDR5 protocol as a background, but the method of the present invention is compatible with other DDR protocols.

[0024] like Figure 1 As shown, the memory test command generation method of this embodiment includes the following steps: Step S101: Set configuration parameters.

[0025] The configuration parameters mainly include protocol-related parameters and test scenario-related parameters, which are used to guide the generation of test command sequences.

[0026] Step S103: Generate a command sequence based on the configuration parameters.

[0027] Command sequences can be generated in three ways: automatic generation, custom generation, and hybrid generation. You can choose the method that best suits your testing needs.

[0028] Specifically, such as Figure 2 As shown, when the command sequence generation method is set to automatic generation, the command sequence generation process includes the following steps: Step S201: Read the configuration parameters and test scenario information, and create an empty sequence based on the configuration parameters and test scenario information; The automatic generation method can automatically generate command sequences based on the selected scenario without requiring pseudocode programs, including typical and random scenarios.

[0029] For typical scenarios, including dozens of specific test scenarios, the core of the generation algorithm is to create a basic read-write sequence, and then insert commands such as activation, precharge, synchronization, and refresh, executing the following steps: Step S203: Generate a read / write sequence containing definite address information using the blank sequence;

[0031] The address information of the write sequence matches the read sequence, ensuring that the data written to a certain storage unit (cell) can be read out. The read and write sequence includes the following information: starting address, address mode (incrementing or decrementing), address interval, number of reads and writes, and read and write mode (write first and then read or write and read simultaneously).

[0032] For example, the resulting read / write sequence is shown in Table 1, where WR is the write command, RD is the read command, and the combined address of rank, bg, and bank is an address combination, including the rank address, bank group address, and bank address.

[0033] Step S205: Scan the read / write sequence in forward order from beginning to end, and insert an activation command and a clock synchronization command before the write command of the first address combination that appears in the read / write sequence; Step S207: Scan the read / write sequence in reverse order from end to beginning, and insert a precharge command after the read command of the first address combination that appears in the read / write sequence; For example, insert the activation command ACT and the clock synchronization command CAS into the sequence shown in Table 1, and then insert the precharge command PRE into the formed sequence to obtain the sequences shown in Tables 2 and 3.

[0034]

[0035] Step S209: Continue scanning the read and write sequence from beginning to end in ascending order, and insert the precharge command, activation command and clock synchronization command in sequence between the two read and write commands that cause row switching.

[0036] Specifically, if any two read / write commands have the same bank address but different row addresses, it is determined that a row switch has occurred between the two read / write commands.

[0037] For example, by inserting the precharge command PRE, the activation command ACT, and the clock synchronization command CAS into the sequences shown in Tables 2 and 3, the sequences shown in Tables 4 and 5 are obtained.

[0038]

[0039] For random scenarios, the core of the generation algorithm is also to create a read-write sequence. However, the read command corresponding to the write command is randomly delayed after the write command. The positions of subsequent inserted activation, precharge, synchronization, refresh, and other commands are also random, and the following steps are performed: Step S204: Use the blank sequence to generate a write command sequence with completely random address information, then scan the write command sequence from beginning to end, and insert a read command with matching address information at a random position after each write command to generate a read-write sequence. For example, the resulting read / write sequences are shown in Table 6.

[0040] Step S206: Scan the read and write sequence in ascending order from beginning to end, and insert the activation command and clock synchronization command at any position before the write command of the first address combination that appears in the read and write sequence; This arbitrary position appears at a random location between the first command and the current write command.

[0041] Step S208: Scan the read / write sequence in reverse order from tail to head, and insert a precharge command at any position after the read command of the first occurrence of the address combination; wherein, this arbitrary position appears at a random position between the current read command and the last command.

[0042] For example, insert the activation command ACT and the clock synchronization command CAS into the sequence shown in Table 6, and then insert the precharge command PRE into the resulting sequence to obtain the sequences shown in Tables 7, 8 and 9.

[0043]

[0044] Step S210: Continue scanning the read and write sequence from beginning to end in ascending order, and insert the precharge command, activation command and clock synchronization command in sequence between the two read and write commands that cause row switching.

[0045] Specifically, if any two read / write commands have the same bank address but different row addresses, it is determined that a row switch has occurred between the two read / write commands.

[0046]

[0047] For example, inserting the precharge command PRE, the activation command ACT, and the clock synchronization command CAS into the sequences shown in Tables 7, 8, and 9 yields the sequences shown in Tables 10, 11, and 12.

[0048] Custom memory generation methods first require defining the syntax of memory operation commands. For example, all command operations, including write, read, activate, and refresh commands, should be encapsulated into functions, with the information within each command serving as function parameters. Then, flow control structures should be defined, including if-else structures, for loops, and the `break` and `continue` characters. Variables should also be defined to store initialization and intermediate calculation results. Before executing the custom generation method, pseudocode programs for memory operations must be written based on the defined syntax. These pseudocode programs need to be parsed before executing the custom generation method.

[0049] Specifically, such as Figure 3 As shown, when the command sequence generation method is selected as the custom generation method, the command sequence generation includes the following steps: Step S301: Read the configuration parameters, test scenario information, and memory operation pseudocode program file; create an empty sequence based on the configuration parameters and test scenario information. Step S303: Scan the pseudocode, read and calculate the values ​​of the initial variables from the pseudocode; Step S305: Scan all flow control structure characters, record the position of the flow control structure characters, calculate the conditional expression of the if / elseif branch, and mask the branch line number (i.e. the position occupied by the branch) that does not meet the condition and record it in the mask array. At the same time, record the position of the individual comment line in the mask array. Step S307: Scan the pseudocode again, automatically avoid the blocked code lines, and when the command operation function name is identified, split the line containing the command operation function name into strings, extract the valid information, convert it into a command object, and store it in the blank sequence; Specifically, when the end character of the for loop is detected, it is determined whether the current number of iterations is less than the number of iterations defined at the beginning of the for loop. If the current number of iterations is less than the defined number of iterations, the loop jumps to the line below the corresponding for loop beginning and continues to repeat the operation. Otherwise, the loop body is exited and the next line of code is executed until the loop ends.

[0050] The hybrid generation method effectively combines the two generation methods mentioned above, making the pattern generation more flexible. For example, in a low-power entry / exit test case, basic read / write operations before entering and after exiting low-power mode use an automatic generation method, while low-power entry and exit commands use a custom generation method. Figure 4 As shown, when the hybrid generation method is selected for generating the command sequence, the generation of the command sequence includes the following steps: Step S401: Create a two-dimensional array, where rows correspond to test scenarios, the number of rows represents the number of test scenarios, and columns correspond to the configuration parameters carried by each scenario, with the number of columns representing the number of configuration parameters carried by each scenario.

[0051] For example, test scenarios include random, typical, and custom scenarios. The first typical scenario and its configuration parameters are written into the first row of a two-dimensional array, the custom scenario and its configuration parameters are written into the second row of a two-dimensional array, and the second typical scenario and its configuration parameters are written into the third row of a two-dimensional array, as shown in Table 13.

[0052]

[0053] Step S403: Scan each row of the two-dimensional array from beginning to end, call the command sequence generation method corresponding to each scene in turn, generate the operation command set for each scene, and combine them to form a command sequence.

[0054] The scenarios include at least two of the following: typical scenarios, random scenarios, and custom scenarios. The command sequence generation method for typical scenarios is the automatic generation method for typical scenarios, the command sequence generation method for random scenarios is the automatic generation method for random scenarios, and the command sequence generation method for custom scenarios is the custom generation method.

[0055]

[0056] For example, scanning each row of the two-dimensional array shown in Table 13 from beginning to end, and sequentially calling the automatic generation method for typical scenes, the custom generation method, and the automatic generation method for typical scenes, the resulting command sequence is shown in Table 14. The correspondence between the command lines of the sequence shown in Table 14 and the rows of the sub-scenes in the two-dimensional array shown in Table 13 is as follows: Figure 5 As shown.

[0057] Continue to refer to Figure 1 The memory test command generation method of this embodiment further includes the following steps: Step S105: Insert delay information between any two objects in the command sequence.

[0058] Delay information is inserted as follows: the command sequence is scanned in ascending order from beginning to end, the types of the current command and the next command are determined, and then delay information is inserted within the timing parameter range required by the protocol.

[0059] The inserted delay information includes: minimum delay, random delay, and custom delay. Minimum delay is inserted according to the minimum value of AC timing in the protocol, in which case the commands are closely arranged and memory operation efficiency is high; random delay is inserted according to a random value larger than the minimum value, which can simulate the real scenario when the bandwidth efficiency is not high to a certain extent; custom delay is specified as a characteristic value according to the test requirements, which is usually used for AC timing test scenarios.

[0060] For random scenarios generated automatically, the inserted delay information is a random delay.

[0061] Step S107: Calibrate the synchronization domain of the clock synchronization command in the command sequence.

[0062] Calibrate the synchronization domain of clock synchronization commands (CAS) in the command sequence by deleting redundant clock synchronization commands (extra clock synchronization commands that appear within the synchronization domain of the current clock synchronization command) and inserting new clock synchronization commands before read and write commands that exceed the synchronization domain of the clock synchronization command.

[0063] Specifically, such as Figure 6 As shown, the calibration of the synchronization domain of the clock synchronization command in the command sequence according to an embodiment of the present invention includes the following steps: Step S601: Scan the entire command sequence of non-empty objects in ascending order from beginning to end; When a clock synchronization command is found, step S603 is executed: complete the synchronization domain calibration of the clock synchronization command; Furthermore, such as Figure 7 As shown, the synchronization domain calibration for completing the clock synchronization command in this embodiment of the invention includes the following steps: Step S701: Continue searching for non-empty objects from the location of the clock synchronization command, gradually accumulating the delay, and comparing it with the initial synchronization domain time of the clock synchronization command; Three possible scenarios will then emerge.

[0064] Scenario 1: When the accumulated delay is less than the initial synchronization domain time and a new clock synchronization command is detected, execute step S703: delete the new clock synchronization command; Scenario 2: When the accumulated delay is less than the initial synchronization domain time and a new read / write command is detected, execute step S705: expand the synchronization domain of the current clock synchronization command to the initial synchronization domain time plus the current accumulated delay; wherein, the new read / write command is not the read / write command immediately following the clock synchronization command.

[0065] Scenario 3: When the accumulated delay is greater than the initial synchronization domain time and a new read / write command is detected, execute step S707: insert a new clock synchronization command before the new read / write command; wherein, the new read / write command is not the read / write command immediately following the clock synchronization command.

[0066] For specific instructions on scenarios one, two, and three, please refer to [link / reference]. Figure 8 The example shown.

[0067] Continue to refer to Figure 6 The calibration of the synchronization domain of the clock synchronization command in the command sequence in this embodiment of the invention further includes the following steps: Step S605: Continue scanning the command sequence backward to find the next clock synchronization command.

[0068] Upon finding a clock synchronization command, return to step S603 to complete the synchronization domain calibration of the clock synchronization command. Repeat this process until the synchronization domain calibration of all clock synchronization commands in the command sequence is completed.

[0069] Continue to refer to Figure 1 The memory test command generation method of this embodiment further includes the following steps: Step S109: Insert a refresh command into the command sequence.

[0070] Specifically, such as Figure 9 As shown, inserting a refresh command into a command sequence according to an embodiment of the present invention includes the following steps: Step S901: Scan the non-empty objects in the entire command sequence from beginning to end in ascending order, and gradually accumulate the delay; When the accumulated delay is greater than or equal to tREFIe, execute step S903: insert a precharge command and a refresh command after the current non-empty object, adjust the delay value of the current non-empty object, and clear the accumulated delay; Step S905: Continue scanning the command sequence from the current non-empty object, gradually accumulating the delay; When the accumulated delay is greater than or equal to tREFIe, return to step S903. This process repeats until the entire sequence has been filled with precharge and refresh commands.

[0071] Where tREFIe is the internal effective refresh interval.

[0072] This invention redesigns the command generator, enabling it to automatically generate, customize, and hybrid generate test commands. It can not only automatically generate test commands for common scenarios with a single click, but also generate highly targeted test commands through custom programming. Furthermore, it can combine automatic and custom generation methods to generate more flexible test commands. It is fully compatible with common memory protocols such as DDR, LPDDR, and GDDR, enabling the generation of test commands for multiple protocols using a single tool. It is flexible, easy to operate, and covers a wide range of test scenarios.

[0073] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of those different embodiments or examples.

[0074] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0075] Any process or method description in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more (two or more) executable instructions for implementing a particular logical function or process. Furthermore, the scope of the preferred embodiments of this application includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the functionality involved.

[0076] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus or device (such as a computer-based system, a processor-included system or other system that can fetch and execute instructions from, an instruction execution system, apparatus or device).

[0077] It should be understood that various parts of this application can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented using software or firmware stored in memory and executed by a suitable instruction execution system. All or part of the steps of the methods in the above embodiments can be implemented by a program instructing related hardware, the program being stored in a computer-readable storage medium, which, when executed, includes one or a combination of the steps of the method embodiments.

[0078] Furthermore, the functional units in the various embodiments of this application can be integrated into a processing module, or each unit can exist physically separately, or two or more units can be integrated into a module. The integrated module can be implemented in hardware or as a software functional module. If the integrated module is implemented as a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. This storage medium can be a read-only memory, a disk, or an optical disk, etc.

[0079] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various variations or substitutions within the technical scope disclosed in this application, and these should all be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for generating memory test commands, characterized in that, include: Generate a command sequence based on the configuration parameters; Insert delay information between any two objects in a command sequence; The synchronization domain of the clock synchronization command in the command sequence is calibrated; Insert refresh commands into the command sequence.

2. The memory test command generation method as described in claim 1, characterized in that, It can automatically generate command sequences using typical scenario generation methods, including: Read the configuration parameters and test scenario information, and create a blank sequence based on the configuration parameters and test scenario information; Generate a read / write sequence containing definite address information using a blank sequence; Scan the read and write sequence in ascending order from beginning to end, and insert an activation command and a clock synchronization command before the write command of the first address combination that appears in the read and write sequence. Scan the read and write sequence in reverse order from tail to head, and insert a precharge command after the read command of the first address combination that appears in the read and write sequence; The read and write sequence is scanned in ascending order from beginning to end. Between two read and write commands that cause a row switch, a precharge command, an activation command, and a clock synchronization command are inserted in sequence.

3. The memory test command generation method as described in claim 2, characterized in that, It can also automatically generate command sequences using random scenarios, including: Read the configuration parameters and test scenario information, and create a blank sequence based on the configuration parameters and test scenario information; A sequence of write commands with completely random address information is generated using a blank sequence. Then, the write command sequence is scanned from beginning to end, and a read command with matching address information is inserted at a random position after each write command to generate a read-write sequence. Scan the read and write sequence in ascending order from beginning to end, and insert the activation command and clock synchronization command at any position before the write command of the first address combination that appears in the read and write sequence. Scan the read and write sequence in reverse order from tail to head, and insert a precharge command at any position after the read command for the first occurrence of the address combination; The read and write sequence is scanned in ascending order from beginning to end. Between two read and write commands that cause a row switch, a precharge command, an activation command, and a clock synchronization command are inserted in sequence.

4. The memory test command generation method as described in claim 3, characterized in that, It can also generate command sequences using a custom generation method, including: Read the configuration parameters, test scenario information, and memory operation pseudocode program file, and create an empty sequence based on the configuration parameters and test scenario information; Scan the pseudocode, read from the pseudocode, and calculate the values ​​of the initial variables; Scan all flow control structure characters, record the position of the flow control structure characters, calculate the conditional expression, and mask the positions occupied by branches that do not meet the conditions and the positions of individual comment lines. The pseudocode is scanned again, automatically avoiding the blocked lines of code. When the command operation function name is detected, the line containing the command operation function name is split into strings, the valid information is extracted, and it is converted into a command object and stored in the blank sequence. When the end character of the for loop is detected, it is determined whether the current number of iterations is less than the number of iterations defined at the beginning of the for loop. If the current number of iterations is less than the defined number of iterations, the loop jumps to the line below the corresponding for loop beginning and continues to repeat the operation. Otherwise, the loop body is exited and the next line of code is executed until the loop ends.

5. The memory test command generation method as described in claim 4, characterized in that, It can also use a hybrid generation method to generate command sequences, including: Create a two-dimensional array, with rows corresponding to test scenarios and columns corresponding to the configuration parameters carried by each scenario; Scan each row of the two-dimensional array from beginning to end, and call the command sequence generation method corresponding to each scene in turn to generate the operation command set for each scene, and combine them to form a command sequence; among them, the sequence generation method corresponding to the scene can be the automatic generation method for typical scenes, the automatic generation method for random scenes, or a custom generation method.

6. The memory test command generation method according to any one of claims 1 to 5, characterized in that, Inserting delay information between any two objects in a command sequence includes: scanning the command sequence in ascending order from beginning to end, determining the type of the current command and the next command, and inserting delay information within the timing parameter range required by the protocol.

7. The memory test command generation method as described in claim 6, characterized in that, The delay information includes minimum delay, random delay, and custom delay. The minimum delay is inserted according to the minimum value of AC timing in the protocol, the random delay is inserted according to a random value larger than the minimum value, and the custom delay is a characteristic value specified according to the test requirements.

8. The memory test command generation method as described in any one of claims 1 to 5, characterized in that, Calibrate the synchronization domain of the clock synchronization command in the command sequence, including: Scan the entire command sequence of non-empty objects in ascending order from beginning to end; Upon finding a clock synchronization command, complete the synchronization domain calibration of the clock synchronization command; Continue scanning the command sequence to find the next clock synchronization command; When a clock synchronization command is found, the synchronization domain calibration of the clock synchronization command is completed. This process is repeated until the synchronization domain calibration of all clock synchronization commands in the command sequence is completed.

9. The memory test command generation method as described in claim 7, characterized in that, When a clock synchronization command is found, the synchronization domain calibration for the clock synchronization command includes: Continue searching for non-empty objects from the position where the clock synchronization command is located, gradually accumulating the delay, and comparing it with the initial synchronization domain time of the clock synchronization command; If the accumulated delay is less than the initial synchronization domain time and a new clock synchronization command is detected, delete the new clock synchronization command. If the accumulated delay is less than the initial synchronization domain time and a new read / write command is detected, the synchronization domain of the current clock synchronization command is expanded to the initial synchronization domain time plus the current accumulated delay. When the accumulated delay exceeds the initial synchronization domain time and a new read / write command is detected, a new clock synchronization command is inserted before the new read / write command.

10. The memory test command generation method according to any one of claims 1 to 5, characterized in that, Inserting refresh commands into the command sequence includes: Scan the entire command sequence of non-empty objects in ascending order from beginning to end, and gradually accumulate the delay; When the accumulated delay is greater than or equal to tREFIe, insert a precharge command and a refresh command after the current non-empty object, adjust the delay value of the current non-empty object, and clear the accumulated delay. Continue scanning the command sequence from the current non-empty object, gradually accumulating the delay; When the accumulated delay is greater than or equal to tREFIe, a precharge command and a refresh command are inserted after the current non-empty object, the delay value of the current non-empty object is adjusted, and the accumulated delay is cleared. This process is repeated until the entire sequence has been filled with precharge commands and refresh commands; where tREFIe is the internal effective refresh interval.

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