FPGA-based ultra-high-speed intelligent communication protocol switching method and system

Abstract

The application discloses a kind of based on FPGA's super-speed intelligent communication protocol switching method and system, belong to data communication technical field, including obtaining current upload data, according to current upload data obtains protocol switching instruction;According to the transmission state information of protocol switching instruction and current data frame transmission progress counter value, obtain;According to the configuration completion signal of protocol switching instruction and preset fragment package storage mapping table, obtain;According to configuration completion signal, obtain check pass signal and complete data frame, the present application obtains protocol switching instruction by current upload data and decision model, avoids transmission interruption caused by invalid switching;According to the configuration completion signal of protocol switching instruction and preset fragment package storage mapping table, reduce protocol reconstruction delay;According to configuration completion signal, obtain check pass signal and complete data frame by executing cyclic check and iteration operation, solve the problem that error compensation and check disjoint and data integrity are poor.

Description

Technical Field

[0001] This invention relates to the field of data communication technology, and more specifically to an FPGA-based ultra-high-speed intelligent communication protocol switching method and system. Background Technology

[0002] The large-scale development of smart agriculture has driven the construction and application of ultra-large-scale automated plant production factories. These factories, as the core carriers of smart agriculture, generate and transmit massive amounts of data during daily operation, including terabytes of environmental monitoring data, crop growth image data, and equipment control commands. This places extremely high demands on the speed, stability, and integrity of data transmission. Meanwhile, ultra-large-scale automated plant production factories in the industrial internet scenario have data transmission networks encompassing fixed sensor nodes, mobile monitoring robots, FPGAs, and cloud servers. These networks face numerous physical layer transmission problems, such as signal crosstalk from long-distance cabling, signal obstruction and attenuation during wireless transmission, interference from industrial electromagnetic environments, and signal distortion caused by temperature and humidity fluctuations. These issues pose serious challenges to stable data transmission. Furthermore, the industrial internet places extremely high demands on the real-time performance, reliability, and multi-protocol compatibility of data transmission. FPGAs, as industrial-grade programmable hardware, with their parallel computing capabilities, nanosecond-level response speeds, and reconfigurability, should ideally be the core carrier for solving these problems. However, existing multi-protocol transmission solutions do not fully leverage the industrial adaptability advantages of FPGAs, resulting in inaccurate protocol switching trigger determination and high reconfiguration latency. This fails to meet the transmission needs of massive heterogeneous data in the industrial internet, thus indicating shortcomings in existing technologies. Summary of the Invention

[0003] To address the shortcomings of existing technologies, the present invention aims to provide an ultra-high-speed intelligent communication protocol switching method and system based on FPGA. This method accurately determines protocol switching requirements and obtains protocol switching instructions through a decision model, avoiding transmission interruptions caused by invalid switching. Furthermore, it performs iterative operations based on configuration completion signals to solve the problem of poor data integrity.

[0004] To achieve the above objectives, the present invention provides the following technical solution:

[0005] This invention provides an FPGA-based ultra-high-speed intelligent communication protocol switching method, comprising:

[0006] Get the currently uploaded data and obtain the protocol switching instruction based on the currently uploaded data;

[0007] Based on the protocol switching instruction and the transmission progress counter value of the current data frame, the transmission status information is obtained;

[0008] Based on the protocol switching command and the preset fragment packet storage mapping table, a configuration completion signal is obtained;

[0009] Based on the configuration completion signal, a verification pass signal and a complete data frame are obtained.

[0010] As a further improvement of the present invention, the step of obtaining the protocol switching instruction based on the currently uploaded data includes:

[0011] Based on the currently uploaded data, obtain the data frame feature three-parameter set and the communication link status three-parameter set;

[0012] The decision model is invoked based on preset decision weights;

[0013] The weight score is obtained based on the decision model, the three-parameter set of data frame features, and the three-parameter set of communication link status.

[0014] The target protocol is matched based on the weight score to obtain the protocol switching instruction.

[0015] As a further improvement of the present invention, a set of three parameters for data frame features and a set of three parameters for communication link status are obtained based on the currently uploaded data, including:

[0016] Based on the frame header bytes, frame length, and transmission direction fields corresponding to the currently uploaded data, the set of three parameters of the data frame characteristics is obtained;

[0017] Based on the current signal strength, bit error rate, and transmission delay, the three-parameter set of the communication link status is obtained.

[0018] As a further improvement of the present invention, transmission status information is obtained based on the protocol switching instruction and the transmission progress counter value of the current data frame, including:

[0019] Based on the transmission progress counter, the current transmission data frame and the completed transmission data frame are obtained;

[0020] Obtain the intermediate checksum and compensation coefficient corresponding to the completed transmission data frame;

[0021] The transmission status information is obtained based on the current transmitted data frame, the intermediate check value, and the compensation coefficient.

[0022] As a further improvement of the present invention, a configuration completion signal is obtained according to the protocol switching instruction and the preset fragment packet storage mapping table, including:

[0023] The dual-port read address is calculated based on the target protocol identifier in the protocol switching instruction and the preset fragmented packet storage mapping table;

[0024] Verification is performed based on the dual-port read address to obtain high-priority fragments;

[0025] Based on the high-priority fragmentation and configuration header parsing logic, a configuration completion signal is obtained.

[0026] As a further improvement of the present invention, based on the configuration completion signal, a verification pass signal and a complete data frame are obtained, including:

[0027] Based on the configuration completion signal, the module status is detected to obtain the module linkage ready signal;

[0028] Based on the module linkage readiness signal and the preset data frame template, a lookup table is retrieved to obtain the compensation and adaptation feature vector;

[0029] The breakpoint address is obtained based on the transmission status information and the preset data transmission breakpoint packet encoding rules;

[0030] Based on the compensation adaptation feature vector and the breakpoint address, the verification pass signal and the complete data frame are obtained.

[0031] As a further improvement of the present invention, a compensation adaptation feature vector is obtained by retrieving a lookup table based on the module linkage readiness signal and a preset data frame template, including:

[0032] The data frame template is obtained by searching a lookup table based on the module linkage readiness signal and the preset data frame template.

[0033] Based on the data frame template and the currently transmitted data frame, a corrected data frame is obtained;

[0034] The compensation and adaptation feature vector is obtained based on the key parameters corresponding to the corrected data frame.

[0035] As a further improvement of the present invention, the verification pass signal and the complete data frame are obtained based on the compensation adaptation feature vector and the breakpoint address, including:

[0036] The breakpoint information is obtained based on the module linkage ready signal and the breakpoint address;

[0037] Based on the breakpoint information and data priority rules, a resume scheduling instruction is obtained;

[0038] Based on the resume scheduling instruction and the compensation adaptation feature vector, the verification pass signal and the complete data frame are obtained.

[0039] As a further improvement of the present invention, the process from the resume scheduling instruction and the compensation adaptation feature vector to the verification pass signal and the complete data frame includes:

[0040] According to the resume scheduling instruction and the compensation adaptation feature vector, an iterative operation is performed. The iterative operation includes updating the current amplitude coefficient and the current phase coefficient corresponding to the compensation adaptation feature vector according to the received signal and the current convergence factor corresponding to the current transmitted data frame, obtaining the updated amplitude coefficient and the updated phase coefficient, obtaining the compensation signal according to the updated amplitude coefficient and the updated phase coefficient, obtaining the verification result according to the compensation signal, and if the verification result is unsuccessful, updating the convergence factor until the verification result is successful, thereby obtaining the verification successful signal and the complete data frame.

[0041] This invention provides an FPGA-based ultra-high-speed intelligent communication protocol switching system, including a decision control module, an FPGA programmable logic area, a cache module, and an interface module;

[0042] The decision control module and the interface module are used to obtain the currently uploaded data and obtain the protocol switching instruction based on the currently uploaded data;

[0043] The FPGA programmable logic area and the cache module are used to obtain transmission status information according to the protocol switching instruction and the transmission progress counter value of the current data frame, obtain a configuration completion signal according to the protocol switching instruction and the preset fragmented packet storage mapping table, and obtain a verification pass signal and a complete data frame according to the configuration completion signal.

[0044] This invention first obtains a protocol switching instruction based on the currently uploaded data and the decision model, avoiding transmission interruptions caused by invalid switching. Then, based on the protocol switching instruction and the transmission progress counter value of the current data frame, it obtains transmission status information, providing basic data for subsequent resuming transmission. It then obtains a configuration completion signal based on the protocol switching instruction and a preset fragmented packet storage mapping table, reducing protocol reconstruction latency. Finally, it performs cyclic verification and iterative operations based on the configuration completion signal to obtain a verification pass signal and a complete data frame, solving the problems of disconnect between error compensation and verification and poor data integrity. Through the adaptation of FPGA to industrial Internet transmission scenarios, it achieves stable transmission of heterogeneous data such as image data and environmental data. Attached Figure Description

[0045] Figure 1 This is a schematic diagram of the method steps of the present invention;

[0046] Figure 2 A schematic diagram illustrating the steps to obtain the verification pass signal and the complete data frame;

[0047] Figure 3 A schematic diagram illustrating the steps to obtain the compensated and adapted feature vectors;

[0048] Figure 4 This is a schematic diagram of the steps involved in the iterative operation. Detailed Implementation

[0049] The technical solution of the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the embodiments of the present invention and the specific features in the embodiments are detailed descriptions of the technical solution of the present invention, rather than limitations thereof.

[0050] The term "and / or" in the following text is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. Additionally, the character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0051] like Figure 1 As shown in the figure, this application provides an FPGA-based ultra-high-speed intelligent communication protocol switching method, including:

[0052] Get the currently uploaded data and obtain the protocol switching instruction based on the currently uploaded data;

[0053] Based on the protocol switching command and the transmission progress counter value of the current data frame, the transmission status information is obtained;

[0054] Based on the protocol switching instructions and the preset fragment packet storage mapping table, a configuration completion signal is obtained;

[0055] Based on the configuration completion signal, a verification pass signal and a complete data frame are obtained.

[0056] The method provided in this embodiment is applied to an ultra-large-scale automated plant production factory. An Internet sensor network is constructed within the factory, which includes multiple production areas. Each production area includes multiple growth chambers, and each growth chamber is equipped with multiple sensors to collect environmental data such as temperature and humidity. Each growth chamber also includes multiple monitoring robots to capture image data such as the growth status of the plants. The sensors and monitoring robots need to transmit the collected environmental data and image data to the corresponding FPGA sub-control unit. Each FPGA sub-control unit can correspond to multiple growth chambers. Finally, the FPGA sub-control unit summarizes the data and transmits it to the FPGA server in the control center through the industrial Internet backbone network to complete the data transmission.

[0057] Because different types of data have different transmission characteristics, different transmission protocols are needed to match different types of data. For example, compared to image data, environmental data has fewer bytes but higher frequency, and it is collected by fixed sensors. Therefore, the Serial Port protocol can be used, which has the advantages of low overhead, adaptability to short frame transmission, and being a wired protocol with good compatibility with long-distance wiring of fixed sensors. It can stably carry high-frequency, small-data-volume transmissions at a lower cost. Compared to environmental data, image data has more bytes and higher frequency, and it is collected by mobile monitoring robots. Therefore, the Wi-Fi 6 protocol can be used for transmission. Wi-Fi 6 is a high-speed wireless protocol that can support high-bandwidth transmission of long-frame images. At the same time, the robot is a mobile device, and the wireless protocol does not require wiring, adapting to its mobile scenarios across production areas, balancing transmission speed and mobility. The aggregated data has more bytes than image data and needs to be transmitted across networks. Therefore, the TCP / IP protocol can be used to ensure the reliability of the aggregated data transmission from the factory intranet to the cloud. However, this embodiment is not limited to this, and those skilled in the art can also choose other protocols for multi-protocol collaboration.

[0058] Specifically, before implementing the method provided in this embodiment, it is first necessary to obtain the corresponding verification rules and compensation parameters for each protocol based on its transmission characteristics. The verification rules are used to verify whether data errors occur during transmission due to physical interference (crosstalk, attenuation, electromagnetic interference, etc.). For example, for environmental data, the corresponding verification rules are used to accurately detect single-bit errors and burst errors in short frame transmission without increasing the transmission burden excessively. For image data, the corresponding verification rules are used to cover more complex errors in long frame transmission, such as consecutive byte errors caused by Wi-Fi 6 wireless attenuation, ensuring data integrity. For instance, since environmental data has a smaller number of bytes, using long check bits would increase the transmission burden; therefore, a CRC16-based verification rule can be selected. Image data has a larger number of bytes, and the probability of consecutive and multi-bit errors is higher; therefore, longer check bits can be used to detect more complex error types, such as a CRC32-based verification rule.

[0059] The compensation parameters include amplitude compensation weight, phase compensation weight, and convergence factor. These parameters are used to correct signal distortion and reduce errors. Errors refer to errors in the service data that occur during transmission due to physical signal distortion, causing the receiver to misread the original data. Each protocol has its corresponding compensation parameters. Specifically, during signal transmission, amplitude and phase distortion can occur. When calculating amplitude and phase compensation weights, the percentage of amplitude and phase distortion in the signal under the given protocol is first measured. This percentage is then converted into corresponding compensation weights; the higher the percentage, the greater the corresponding compensation weight. For example, the Serial Port protocol is for long-distance wired transmission, and the main problem is crosstalk, where signals from adjacent cables interfere with each other. After measuring 1000 frames of data with an oscilloscope, it was found that 70% of the errors were amplitude distortion, and 30% were phase distortion, indicating that amplitude distortion is the primary issue. In this case, the amplitude compensation weight can be set to 0.7, and the phase compensation weight to 0.3. Similarly, the compensation parameters for other protocols can be obtained. The above values ​​are merely examples, and this embodiment does not impose any limitations.

[0060] In subsequent iterations, the convergence factor is used to control the degree of adjustment of the phase and amplitude coefficients each time, determining the speed and stability of the compensation. The purpose of the iterative operation is to make the output signal approach the ideal signal through gradient descent. This embodiment does not limit the specific value of the convergence factor. Preferably, to further ensure the stability of the iterative operation, the convergence factor... The range of values ​​should satisfy .

[0061] Specifically, in this embodiment, the mean square value of the error is used to measure the degree of closeness. The smaller the mean square value of the error, the closer the signal is to the ideal signal. An ideal signal is a correct signal without physical distortion, which can be obtained through a preset template signal. This embodiment does not limit the method of obtaining it. First, the signal output by the FPGA server after compensation is defined as follows:

[0062]

[0063] in, This indicates the received distorted signal. This refers to the current compensation coefficients, including the current phase coefficient and amplitude coefficient. For example, when the amplitude compensation weight is 0.7 and the phase compensation weight is 0.3, , For the current phase coefficient, This represents the current amplitude coefficient.

[0064] error It can be represented as Mean square error value The partial derivative (gradient) can be expressed as: , Representing mathematical expectation, in iterative operations The update rule is to adjust in the opposite direction of the gradient, that is:

[0065]

[0066] in In order to be in The compensation coefficients obtained after one iterative update are based on the convergence factor. Since it is an adjustable parameter, the constant in the gradient can be incorporated into the convergence factor, and when the expected value of multiple iterations cannot be obtained, a single iteration can be used. Replace Expected Value The simplified update formula is finally obtained as follows:

[0067]

[0068] Furthermore, in order to make the compensation coefficient converge to the optimal value... The compensation coefficient deviation can be defined as... , When the compensation coefficient is optimal, signal distortion is completely corrected. Substituting the above error From the formula, we can obtain:

[0069]

[0070] And the optimal value satisfy , Because of noise error, therefore Then combine it with Substituting into the simplified update formula, we get:

[0071]

[0072] In real-world scenarios, the intensity of noise is much smaller than the intensity of the signal, so the noise term can be ignored and simplified to... To ensure the convergence of the compensation coefficients, a recursive term for the error is required. The absolute value is less than 1, otherwise It will grow larger and larger, causing the compensation coefficient to run out of control, thus leading to the inequality:

[0073]

[0074] because For random signals, power can be used. This represents its average intensity, and thus the above inequality can be transformed into Solving this inequality will yield the result. The range of values ​​is .

[0075] Before executing the method provided in this embodiment, in addition to obtaining the verification rules and compensation parameters corresponding to each protocol, it is also necessary to construct a fragmented packet storage mapping table and a data frame template retrieval lookup table. Specifically, firstly, it is necessary to define the hardware circuit corresponding to each protocol using a hardware description language, and then use FPGA development tools to convert the circuit described in the code into a configuration file that the FPGA server can load, thus obtaining the core logic bitstream file for each protocol. The bitstream file includes the core functional logic of the protocol (such as the frame header detection of the Serial Port) and auxiliary functional logic (such as the status feedback after the function runs). Based on this, this embodiment performs bitstream fragmentation, placing the core functional logic in the high-priority fragment and the auxiliary functional logic in the low-priority fragment. Furthermore, since the protocol logic needs to call initial parameters to work, such as calling the value of the compensation parameter when performing iterative compensation, this embodiment further encodes the initial parameters into a configuration header and places it at the beginning of the high-priority fragment, so that the FPGA server can directly load the initial parameters while loading the core function, which is convenient for subsequent use. Furthermore, each fragment carries a checksum at the end. When the FPGA server loads a fragment subsequently, it recalculates the checksum of the current fragment and compares it with the checksum at the end of the fragment. If the checksums match, it means the fragment content has not been tampered with and is loaded normally. If they do not match, it means there is a problem with the fragment and a retransmission is requested to ensure that the loaded configuration data is complete and correct. Further, the FPGA contains high-speed memory (such as BRAM), and the FPGA divides large areas of BRAM into multiple banks. Each bank is an independent storage area, and different banks have different physical locations within the FPGA chip. The closer a bank is to the central control logic module, the lower the access latency. In this embodiment, based on the historical usage frequency of each protocol, the fragment packets corresponding to protocols with higher usage frequencies are stored in banks with lower latency, and the storage location corresponding to each fragment is recorded to obtain a fragment packet storage mapping table.

[0076] Next, a data frame template lookup table is constructed. Specifically, the data transmitted in the factory includes environmental data, image data, etc., all of which are binary data packets in frames. Each frame has a fixed structural format. To accurately identify the data type and protocol, this embodiment first extracts the structural features of different types of frames using an oscilloscope, including frame header, frame length, data block offset, and parity bit length. Data is transmitted via electrical signals, and the oscilloscope can capture the timing and level of these waveforms, thereby parsing the binary structure of the frame. The data block offset represents the distance between the frame header and the valid data. After obtaining the structural features corresponding to each type of data, the structural features corresponding to each type are encoded into feature vectors. Then, a data frame template lookup table is generated based on each protocol, its corresponding data type, and the corresponding data vector, facilitating the identification of protocol and data types after the FPGA receives the data.

[0077] Next, this embodiment will use image data as an example for further explanation; environmental data will also be adapted to the subsequent steps. Specifically, the monitoring robot first needs to send the image data to the corresponding FPGA sub-control unit. The FPGA sub-control unit only performs simple data aggregation and transmission, and then sends the aggregated data to the FPGA server in the control center. The FPGA server then generates a protocol switching instruction based on the acquired data. Based on the protocol switching instruction and the transmission progress counter value of the current data frame, it obtains the transmission status information. Based on the protocol switching instruction and the preset fragment packet storage mapping table, it obtains the configuration completion signal. Finally, based on the configuration completion signal, it obtains the verification pass signal and the complete data frame.

[0078] This embodiment first obtains a protocol switching instruction based on the currently uploaded data and the decision model to avoid transmission interruptions caused by invalid switching. Then, based on the protocol switching instruction and the transmission progress counter value of the current data frame, it obtains transmission status information to provide basic data for subsequent resuming transmission. Then, based on the protocol switching instruction and the preset fragmented packet storage mapping table, it obtains a configuration completion signal to reduce protocol reconstruction delay. Finally, based on the configuration completion signal, it performs cyclic verification and iterative operations to obtain a verification pass signal and a complete data frame, solving the problems of disconnect between bit error compensation and verification and poor data integrity.

[0079] Furthermore, this embodiment provides a step for obtaining a protocol switching instruction based on currently uploaded data, including:

[0080] Based on the currently uploaded data, obtain the set of three parameters for data frame characteristics and the set of three parameters for communication link status;

[0081] The decision model is invoked based on preset decision weights;

[0082] The weighted score is obtained based on the decision model, the three-parameter set of data frame features, and the three-parameter set of communication link status.

[0083] The target protocol is matched based on the weight score to obtain the protocol switching instruction.

[0084] Furthermore, this embodiment provides a step for obtaining a set of three parameters of data frame features and a set of three parameters of communication link status based on the currently uploaded data, including:

[0085] Based on the frame header bytes, frame length, and transmission direction fields corresponding to the currently uploaded data, a set of three parameters for data frame characteristics is obtained;

[0086] Based on the current signal strength, bit error rate, and transmission delay, a set of three parameters for the communication link status is obtained.

[0087] Specifically, when the FPGA server receives the currently uploaded data, it first reads the frame header bytes and calls the aforementioned preset data frame template lookup table to retrieve all frame header features. Based on the mapping relationship in the data frame template lookup table, it obtains the type and protocol corresponding to the currently uploaded data. Assuming the data type is image data, the data frame template lookup table then returns the frame length corresponding to the image data. It then determines whether the frame length of the currently uploaded data is equal to the corresponding frame length in the data frame template lookup table. If yes, it proceeds to the next step; otherwise, it requests a retransmission. Next, it identifies the transmission direction field in the currently uploaded data. The transmission direction field is a fixed auxiliary field in the data frame structure that identifies the data's sending source. The sending source is the corresponding production area or growth chamber, set by the robot during data transmission so that the FPGA server can identify the sending source. Finally, it concatenates the data type, frame length, and sending source to obtain the three-parameter set of data frame features. Furthermore, the FPGA server has a built-in link monitoring module that can collect the link status corresponding to the current protocol and calculate the current signal strength, bit error rate, and transmission delay. This embodiment does not limit the specific calculation method of the current signal strength, bit error rate, and transmission delay. Finally, the current signal strength, bit error rate, and transmission delay are concatenated to obtain the three-parameter set of communication link status.

[0088] Furthermore, before executing the method provided in this embodiment, it is necessary to set preset decision weights for each indicator in the data frame feature three-parameter set and the communication link state three-parameter set. For example, since image data has higher real-time requirements, the preset decision weight for image data can be set to 0.3, and the preset decision weight for environmental data can be set to 0.2. Similarly, for different frame lengths, sending sources, current signal strength, bit error rate, and transmission delays, different preset decision weights can be set according to the actual situation. This embodiment does not limit their specific values. For each indicator in the communication link state three-parameter set, a corresponding threshold needs to be set to determine whether the indicator meets the standard for the protocol to work stably. This embodiment does not limit the thresholds and standards. The preset decision weights and thresholds are stored in the BEAM of the FPGA server for easy access at any time. After invoking the preset decision weights and thresholds based on the three-parameter set of communication link status and the three-parameter set of data frame features, the NEON coprocessor in the ARM architecture needs to be further invoked to complete the calculation based on the decision model. Specifically, the decision model first needs to determine whether each indicator meets the standard based on the threshold. If it does not meet the standard, its score is recorded as 0; if it meets the standard, its score is recorded as its corresponding preset decision weight. Then, the preset decision weight corresponding to each indicator in the three-parameter set of data frame features and the score corresponding to each indicator in the three-parameter set of communication link status are added together to obtain the weight score. Then, the availability of the current protocol is determined based on the preset threshold. If each indicator in the three-parameter set of communication link status does not meet the standard, even if the overall score meets the preset threshold, the current protocol is not available. If the current protocol is unavailable, the preset backup protocol mapping rules need to be invoked to match the target protocol and finally obtain the protocol switching instruction to facilitate subsequent protocol switching. For example, the preset backup protocol mapping rules are based on the matching logic between fault scenarios and alternative protocols pre-built according to data transmission requirements and the technical characteristics of each communication protocol. For example, firstly, the core characteristics of all communication protocols involved in the production line (such as Wifi6, Serial Port, ZigBee, etc.) are sorted out. Then, backup protocols are set for each fault type and data type. For example, when the data type is environmental data and the fault type is excessive transmission delay, ZigBee is matched as the backup protocol. Finally, the correspondence between fault scenarios (data type and current protocol fault) and target protocols is stored in the BEAM storage area of ​​the FPGA server in the form of key-value pairs that can be quickly parsed by hardware, forming a fixed mapping rule as the preset backup protocol mapping rule. Subsequently, when the decision model determines that the current protocol is unavailable, it is only necessary to call this rule to directly match the target protocol that is suitable for the current data and link status, thereby achieving an efficient response to protocol switching.

[0089] This embodiment determines whether the current protocol is available by using data stream characteristics and link status data, avoiding data packet loss and bit errors caused by blindly continuing transmission when the link deteriorates. Then, it specifies the switching instruction according to the backup protocol mapping rules to ensure the accuracy of protocol switching.

[0090] Furthermore, this embodiment provides a step for obtaining transmission status information based on a protocol switching instruction and the transmission progress counter value of the current data frame, including:

[0091] Based on the transmission progress counter, obtain the current transmission data frame and the completed transmission data frame;

[0092] Obtain the intermediate checksum and compensation coefficient corresponding to the completed data frame;

[0093] Based on the current transmitted data frame, intermediate check value, and compensation coefficient, the transmission status information is obtained.

[0094] Specifically, firstly, based on the transmission progress counter, the current transmission data frame and the completed transmission data frame are obtained. For example, during data transmission, to reduce the retransmission cost after transmission errors, the entire data is divided into blocks for transmission, such as dividing 1024 bytes of data into blocks, with each block corresponding to 8 bytes. Based on the transmission progress counter, the data corresponding to the multiple blocks that have been transmitted and completed is recorded as the completed transmission data frame, and the block that is currently being prepared for transmission is recorded as the current transmission data frame. Then, the intermediate checksum corresponding to each block in the completed transmission data frame is extracted, and the current compensation coefficient is obtained. The intermediate checksum is an independent checksum corresponding to each block, used for verification after receiving data. As mentioned earlier, the compensation coefficient needs to be updated in real time. After each block is transmitted and completed, the compensation coefficient needs to be updated. Therefore, the current compensation coefficient is the compensation coefficient after multiple iterations and updates. Then, the block corresponding to the current transmission data frame, the block corresponding to the completed transmission data frame, each intermediate checksum, and the compensation coefficient are combined to obtain the transmission status information.

[0095] Next, the data transmission breakpoint data packet and breakpoint address need to be obtained according to the transmission status information and the preset data transmission breakpoint data packet encoding rules. This embodiment does not restrict the data transmission breakpoint data packet encoding rules. For example, a fixed 32-byte format can be selected to encode the transmission status information to obtain the data transmission breakpoint data packet. The breakpoint address can be set according to the specific protocol and data type. This embodiment does not restrict it.

[0096] Furthermore, this embodiment provides a step of obtaining a configuration completion signal based on a protocol switching instruction and a preset fragment packet storage mapping table, including:

[0097] The dual-port read address is calculated based on the target protocol identifier in the protocol switching instruction and the preset fragmented packet storage mapping table;

[0098] Verification is performed based on the dual-port read address to obtain the high-priority fragment;

[0099] Based on the high-priority fragmentation and configuration header parsing logic, the configuration completion signal is obtained.

[0100] Specifically, the fragments corresponding to the target protocol can be obtained based on the target protocol identifier in the protocol switching instruction and the preset fragment packet storage mapping table. As analyzed above, the fragments corresponding to the target protocol include high-priority fragments and low-priority fragments. The FPGA server's BRAM has a dual-port structure, which can read data from two independent ports simultaneously. For example, port A corresponds to the high-priority fragments, and port B corresponds to the low-priority fragments. The dual-port read address is the address where the fragment corresponding to the target protocol is located, which is used to quickly call the fragment packets.

[0101] Furthermore, the parity value corresponding to each parcel is pre-stored at the end of the parcel packet. After reading each parcel, its corresponding parity value needs to be calculated in real time and compared with the parity value at the end to obtain the high-priority parcels and low-priority parcels that can be used safely.

[0102] The configuration completion signals include the protocol module configuration completion signal, the verification module configuration completion signal, and the compensation module configuration completion signal. After obtaining a usable fragment, the core logic corresponding to the fragment needs to be loaded into the protocol processing module. The protocol processing module has a configuration status register. After the loading logic operation is completed, the register outputs the protocol module configuration completion signal. Then, the checksum in the configuration header corresponding to the fragment needs to be written into the polynomial register of the verification module to check whether the data has been successfully written. The polynomial register contains a detection circuit, which is used to output the verification module configuration completion signal after the data is written. Then, the current compensation coefficient needs to be obtained, written into the DSP register inside the compensation module, and the compensation module configuration completion signal is output.

[0103] Furthermore, such as Figure 2 As shown, this embodiment provides a step for obtaining a verification pass signal and a complete data frame based on a configuration completion signal, including:

[0104] Based on the configuration completion signal, the module status is detected to obtain the module linkage ready signal;

[0105] The compensation and adaptation feature vector is obtained by searching the lookup table based on the module linkage readiness signal and the preset data frame template.

[0106] The breakpoint address is obtained based on the transmission status information and the preset data transmission breakpoint packet encoding rules;

[0107] Based on the compensation and adaptation feature vector and the breakpoint address, the verification pass signal and the complete data frame are obtained.

[0108] Specifically, after receiving the configuration completion signal, a test task needs to be sent to each module to ensure that it can successfully execute the corresponding function. For example, the frame parsing logic of the protocol module can simulate receiving one frame of Serial Port data. If the module can correctly identify and output the frame header identifier, it means that the module is ready. When the test of each module passes, the module linkage ready signal is output to execute the subsequent steps.

[0109] Furthermore, such as Figure 3 As shown, this embodiment provides a step for obtaining a compensation adaptation feature vector by retrieving a lookup table based on a module linkage readiness signal and a preset data frame template, including:

[0110] The data frame template is obtained by searching the lookup table based on the module linkage readiness signal and the preset data frame template;

[0111] Based on the data frame template and the currently transmitted data frame, the corrected data frame is obtained;

[0112] Based on the key parameters corresponding to the corrected data frame, the compensation and adaptation feature vector is obtained.

[0113] Specifically, different protocols have different requirements for the format of data frames. First, the corresponding data frame template for the target protocol needs to be retrieved from the lookup table according to the preset data frame template. Then, the format of the currently transmitted data frame is compared with the format in the data frame template. If the formats are inconsistent, the format of the currently transmitted data frame needs to be adjusted according to the data frame template, such as correcting the starting address of the data block and deleting additional fields, to obtain a corrected data frame. Then, key parameters such as frame length, data block length, parity bit start position and transmission rate are extracted from the corrected data frame. Finally, the key parameters are encoded according to the preset encoding rules to obtain the compensation adaptation feature vector.

[0114] Furthermore, this embodiment provides a step for obtaining the verification pass signal and the complete data frame based on the compensation adaptation feature vector and the breakpoint address, including:

[0115] The breakpoint information is obtained based on the module's linkage ready signal and the breakpoint address;

[0116] Based on the breakpoint information and data priority rules, the resume scheduling instruction is obtained;

[0117] Based on the continuation scheduling instruction and the compensation adaptation feature vector, the verification pass signal and complete data frame are obtained.

[0118] Specifically, after receiving the module linkage ready signal, the system first reads and parses the data transmission breakpoint data packet and breakpoint address to obtain the breakpoint information. Then, it obtains the data priority rules. In this embodiment, the data priority rules are not restricted. For example, the data can be transmitted in the order of data fragment number and data frame identifier number. The system then generates a resume scheduling instruction based on the data priority rules so that the transmission module can transmit data in that order.

[0119] Furthermore, such as Figure 4 As shown, this embodiment provides a step from the continuation scheduling instruction and the compensation adaptation feature vector to the verification pass signal and the complete data frame, including:

[0120] Based on the continuation scheduling instruction and the compensation adaptation feature vector, an iterative operation is performed. The iterative operation includes updating the current amplitude coefficient and the current phase coefficient corresponding to the compensation adaptation feature vector based on the received signal and the current convergence factor corresponding to the current transmitted data frame, obtaining the updated amplitude coefficient and the updated phase coefficient, obtaining the compensation signal based on the updated amplitude coefficient and the updated phase coefficient, obtaining the verification result based on the compensation signal, and if the verification result is unsuccessful, updating the convergence factor until the verification result is successful, obtaining the verification successful signal and the complete data frame.

[0121] Specifically, the update method of the compensation coefficients (amplitude coefficient and phase coefficient) is the same as described above, and will not be repeated in this embodiment. For each data block (segment), the current amplitude coefficient and the current phase coefficient need to be updated during transmission to obtain the updated amplitude coefficient and the updated phase coefficient. The current data block is then compensated for amplitude and phase based on the updated amplitude coefficient and the updated phase coefficient to obtain a compensation signal that the receiver can correctly identify. Then, a check value is calculated based on the compensation signal and compared with the check value corresponding to the data block preset by the sender to obtain the check result. If the check result is not passed, it means that the compensated signal has not been correctly identified. The convergence factor needs to be adjusted and the calculation repeated until the check passes. This embodiment does not limit the update method of the convergence factor. For example, it can be updated according to the preset learning rate until each data block passes the check, and a check pass signal and a complete data frame are obtained.

[0122] This embodiment first verifies the module's functionality by using a module linkage ready signal to eliminate interference from old protocols. Simultaneously, it resolves cross-protocol incompatibility issues by generating compensation adaptation feature vectors. Then, it accurately locates breakpoints and plans data transmission by combining data transmission breakpoint packets and data priority rules. Finally, it updates compensation parameters in real time through iterative steps to ensure the real-time performance and accuracy of data transmission.

[0123] Furthermore, this embodiment provides an FPGA-based ultra-high-speed intelligent communication protocol switching system, including a decision control module, an FPGA programmable logic area, a cache module, and an interface module;

[0124] The decision control module and interface module are used to obtain the currently uploaded data and get the protocol switching instruction based on the currently uploaded data;

[0125] The FPGA programmable logic area and cache module are used to obtain transmission status information based on the protocol switching instruction and the transmission progress counter value of the current data frame, obtain the configuration completion signal based on the protocol switching instruction and the preset fragmented packet storage mapping table, and obtain the verification pass signal and complete data frame based on the configuration completion signal.

[0126] This application provides an FPGA-based ultra-high-speed intelligent communication protocol switching method and system. First, based on the currently uploaded data and the decision model, a protocol switching instruction is obtained to avoid transmission interruption caused by invalid switching. Then, based on the protocol switching instruction and the transmission progress counter value of the current data frame, transmission status information is obtained to provide basic data for subsequent transmission. Based on the protocol switching instruction and the preset fragmented packet storage mapping table, a configuration completion signal is obtained to reduce protocol reconstruction delay. Finally, based on the configuration completion signal, a cyclic verification and iterative operation are performed to obtain a verification pass signal and a complete data frame, solving the problems of disconnect between bit error compensation and verification and poor data integrity.

[0127] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0128] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0129] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0130] The above description is merely a preferred embodiment of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions falling within the scope of the present invention's concept are within the scope of protection of the present invention. It should be noted that for those skilled in the art, any improvements and modifications made without departing from the principles of the present invention should also be considered within the scope of protection of the present invention.

Claims

1. A method for switching ultra-high-speed intelligent communication protocols based on FPGA, characterized in that, include: Get the currently uploaded data and obtain the protocol switching instruction based on the currently uploaded data; Based on the protocol switching instruction and the transmission progress counter value of the current data frame, the transmission status information is obtained; Based on the protocol switching command and the preset fragment packet storage mapping table, a configuration completion signal is obtained; Based on the configuration completion signal, a verification pass signal and a complete data frame are obtained.

2. The FPGA-based ultra-high-speed intelligent communication protocol switching method according to claim 1, characterized in that, The step of obtaining the protocol switching instruction based on the currently uploaded data includes: Based on the currently uploaded data, obtain the data frame feature three-parameter set and the communication link status three-parameter set; The decision model is invoked based on preset decision weights; The weight score is obtained based on the decision model, the three-parameter set of data frame features, and the three-parameter set of communication link status. The target protocol is matched based on the weight score to obtain the protocol switching instruction.

3. The FPGA-based ultra-high-speed intelligent communication protocol switching method according to claim 2, characterized in that, Based on the currently uploaded data, a set of three parameters for data frame features and a set of three parameters for communication link status are obtained, including: Based on the frame header bytes, frame length, and transmission direction fields corresponding to the currently uploaded data, the set of three parameters of the data frame characteristics is obtained; Based on the current signal strength, bit error rate, and transmission delay, the three-parameter set of the communication link status is obtained.

4. The FPGA-based ultra-high-speed intelligent communication protocol switching method according to claim 1, characterized in that, Based on the protocol switching instruction and the transmission progress counter value of the current data frame, the transmission status information is obtained, including: Based on the transmission progress counter, the current transmission data frame and the completed transmission data frame are obtained; Obtain the intermediate checksum and compensation coefficient corresponding to the completed transmission data frame; The transmission status information is obtained based on the current transmitted data frame, the intermediate check value, and the compensation coefficient.

5. The FPGA-based ultra-high-speed intelligent communication protocol switching method according to claim 1, characterized in that, Based on the protocol switching command and the preset fragment packet storage mapping table, a configuration completion signal is obtained, including: The dual-port read address is calculated based on the target protocol identifier in the protocol switching instruction and the preset fragmented packet storage mapping table; Verification is performed based on the dual-port read address to obtain high-priority fragments; Based on the high-priority fragmentation and configuration header parsing logic, a configuration completion signal is obtained.

6. The FPGA-based ultra-high-speed intelligent communication protocol switching method according to claim 1, characterized in that, Based on the configuration completion signal, a verification pass signal and a complete data frame are obtained, including: Based on the configuration completion signal, the module status is detected to obtain the module linkage ready signal; Based on the module linkage readiness signal and the preset data frame template, a lookup table is retrieved to obtain the compensation and adaptation feature vector; The breakpoint address is obtained based on the transmission status information and the preset data transmission breakpoint packet encoding rules; Based on the compensation adaptation feature vector and the breakpoint address, the verification pass signal and the complete data frame are obtained.

7. The FPGA-based ultra-high-speed intelligent communication protocol switching method according to claim 6, characterized in that, Based on the module linkage readiness signal and the preset data frame template, a lookup table is retrieved to obtain the compensation adaptation feature vector, including: The data frame template is obtained by searching a lookup table based on the module linkage readiness signal and the preset data frame template. Based on the data frame template and the currently transmitted data frame, a corrected data frame is obtained; The compensation and adaptation feature vector is obtained based on the key parameters corresponding to the corrected data frame.

8. The FPGA-based ultra-high-speed intelligent communication protocol switching method according to claim 6, characterized in that, Based on the compensation adaptation feature vector and the breakpoint address, the verification pass signal and the complete data frame are obtained, including: The breakpoint information is obtained based on the module linkage ready signal and the breakpoint address; Based on the breakpoint information and data priority rules, a resume scheduling instruction is obtained; Based on the resume scheduling instruction and the compensation adaptation feature vector, the verification pass signal and the complete data frame are obtained.

9. The FPGA-based ultra-high-speed intelligent communication protocol switching method according to claim 8, characterized in that, According to the resume scheduling instruction and the compensation adaptation feature vector, the process from the verification pass signal to the complete data frame includes: According to the resume scheduling instruction and the compensation adaptation feature vector, an iterative operation is performed. The iterative operation includes updating the current amplitude coefficient and the current phase coefficient corresponding to the compensation adaptation feature vector according to the received signal and the current convergence factor corresponding to the current transmitted data frame, obtaining the updated amplitude coefficient and the updated phase coefficient, obtaining the compensation signal according to the updated amplitude coefficient and the updated phase coefficient, obtaining the verification result according to the compensation signal, and if the verification result is unsuccessful, updating the convergence factor until the verification result is successful, thereby obtaining the verification successful signal and the complete data frame.

10. An FPGA-based ultra-high-speed intelligent communication protocol switching system, used to implement the FPGA-based ultra-high-speed intelligent communication protocol switching method as described in any one of claims 1-9, characterized in that, It includes a decision control module, an FPGA programmable logic area, a cache module, and an interface module; The decision control module and the interface module are used to obtain the currently uploaded data and obtain the protocol switching instruction based on the currently uploaded data; The FPGA programmable logic area and the cache module are used to obtain transmission status information according to the protocol switching instruction and the transmission progress counter value of the current data frame, obtain a configuration completion signal according to the protocol switching instruction and the preset fragmented packet storage mapping table, and obtain a verification pass signal and a complete data frame according to the configuration completion signal.

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