Baseband board and network device

Abstract

Embodiments of the present application provide a baseband board and a network device. The baseband board comprises a switching chip and a plurality of processing chips, wherein the plurality of processing chips comprise a first processing chip and an auxiliary processing chip; the switching chip is connected with each of the plurality of processing chips; the first processing chip is configured to send a resource request to the switching chip; and the switching chip is configured to determine an auxiliary processing chip corresponding to the first processing chip according to the resource request, and the auxiliary processing chip is configured to assist the first processing chip in data processing, so that the communication performance of the network device can be improved.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to a baseband board and network device. Background Technology

[0002] A network device may include multiple baseband boards, and each baseband board may include multiple processing chips, which can be used to provide signal processing resources.

[0003] In related technologies, the basic unit of wireless service is the cell, and each processing chip can provide service processes for its corresponding cell. However, since each processing chip independently provides communication services to user terminals, the communication performance provided by network devices is relatively low. Summary of the Invention

[0004] This application provides a baseband board and a network device to improve the communication performance of the network device.

[0005] In a first aspect, embodiments of this application provide a baseband board, the baseband board including a switching chip and a plurality of processing chips, wherein the plurality of processing chips includes a first processing chip and an auxiliary processing chip;

[0006] The switching chip is connected to each of the plurality of processing chips;

[0007] The first processing chip is used to send resource requests to the switching chip;

[0008] The switching chip is used to determine the auxiliary processing chip corresponding to the first processing chip according to the resource request. The auxiliary processing chip is used to assist the first processing chip in data processing.

[0009] In one possible implementation, the auxiliary processing chip is used to assist the first processing chip in performing physical layer PHY data processing; or,

[0010] The auxiliary processing chip is used to assist the first processing chip in performing Media Access Control (MAC) data processing and PHY data processing.

[0011] In one possible implementation, the auxiliary processing chip assists the first processing chip in PHY data processing; the resource request includes the resource request amount of the first processing chip; the switching chip is specifically used for:

[0012] Based on the resource request, the amount of idle resources of the second processing chip is determined, wherein the second processing chip is one of the other processing chips besides the first processing chip among the plurality of processing chips.

[0013] The auxiliary processing chip is determined based on the amount of idle resources of the second processing chip, wherein the amount of idle resources of the auxiliary processing chip is greater than or equal to the amount of resource requests.

[0014] In one possible implementation, the auxiliary processing chip is used to assist the first processing chip in performing MAC data processing and PHY data processing.

[0015] The first processing chip is further configured to determine the identifier of the neighboring cell corresponding to the first processing chip, and send the identifier of the neighboring cell to the switching chip;

[0016] The switching chip is also used to determine the auxiliary processing chip based on the neighboring cell identifier, wherein the neighboring cell is the cell corresponding to the auxiliary processing chip.

[0017] In one possible implementation, the first processing chip is further configured to receive a first notification sent by the switching chip and send cell configuration information corresponding to the first processing chip to the switching chip; wherein, the first notification is configured to instruct the first processing chip to send the cell configuration information corresponding to the first processing chip;

[0018] The switching chip is further configured to receive the cell configuration information, send the cell configuration information to the auxiliary processing chip, receive a response message sent by the auxiliary processing chip, and create cooperation information between the first processing chip and the auxiliary processing chip based on the response message. The cooperation information is used to indicate the correspondence between the auxiliary processing chip and the first processing chip.

[0019] In one possible implementation, the first processing chip is further configured to send the cell address corresponding to the first processing chip to the switching chip;

[0020] The switching chip is also used to store the cell addresses of the plurality of processing chips to enable routing between the first processing chip and the auxiliary processing chip.

[0021] In one possible implementation, the baseband board further includes a field-programmable gate array (FPGA), the FPGA including multiple uplink interfaces and multiple downlink interfaces, wherein...

[0022] The FPGA is connected to multiple processing chips corresponding to the baseband board through the multiple uplink interfaces;

[0023] The FPGA is also used to connect to the downstream device corresponding to each of the plurality of downstream interfaces through each of the downstream interfaces.

[0024] In one possible implementation, each uplink interface corresponds to multiple first channels, and the multiple first channels correspond to multiple processing modules, wherein...

[0025] For any given processing module, the processing module receives downlink data through the first channel corresponding to the processing module, and the processing module is used to perform framing processing on the downlink data;

[0026] The downlink data is framed using the multiple processing modules to obtain at least one frame of data.

[0027] In one possible implementation, each downlink interface corresponds to multiple second channels, and a selection module is connected to the front end of each second channel, wherein...

[0028] The selection module is used to determine the frame data of the second channel corresponding to the selection module in the at least one frame data.

[0029] Each of the plurality of second channels is used to send the frame data to the downstream device.

[0030] In a second aspect, embodiments of this application provide a network device, including at least two baseband boards as described in the first aspect and / or the first aspect, wherein...

[0031] The switching chips in the at least two baseband boards are connected in communication.

[0032] In one possible implementation, the at least two baseband boards include a first baseband board and a second baseband board, wherein the switching chip of the first baseband board is used for:

[0033] The second baseband board is determined, and the second baseband board is the auxiliary baseband board corresponding to the first baseband board;

[0034] In the second baseband board, an auxiliary processing chip is determined, which is used to assist the first processing chip of the first baseband board.

[0035] The baseband board and network device provided in this application embodiment may include a first processing chip and an auxiliary processing chip among the multiple processing chips on the baseband board. The auxiliary processing chip can assist the first processing chip in data processing and can improve the communication performance of the base station. Attached Figure Description

[0036] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0037] Figure 1 A schematic diagram illustrating the application scenarios provided in this application;

[0038] Figure 2 A schematic diagram of a single baseband board architecture provided in this application embodiment. Figure 1 ;

[0039] Figure 3 A schematic diagram of a single baseband board architecture provided in this application embodiment. Figure 2 ;

[0040] Figure 4 A schematic diagram of the architecture of a network device provided for an embodiment of the application;

[0041] Figure 5 A schematic diagram of a single baseband board architecture provided for embodiments of this application. Figure 3 ;

[0042] Figure 6A A schematic diagram of the architecture of a downlink data mapping process provided in an embodiment of this application;

[0043] Figure 6B This is a schematic diagram of an uplink radio frequency merging process provided in an embodiment of this application.

[0044] The accompanying drawings have illustrated specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to specific embodiments. Detailed Implementation

[0045] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0046] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and are not used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and are not limited in number; for example, a first object can be one or more.

[0047] Furthermore, the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0048] The terms "at least one," "at least one of," etc., used in the specification and claims of this application refer to any one, any two, or a combination of two or more of the included items. For example, at least one of a, b, and c can mean: "a," "b," "c," "a and b," "a and c," "b and c," and "a, b, and c," where a, b, and c can be single or multiple. Similarly, "at least two" refers to two or more items, and its meaning is similar to that of "at least one."

[0049] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application.

[0050] Figure 1 A schematic diagram illustrating the application scenarios provided in this application. Please refer to [link / reference]. Figure 1 This can include a network device 101 and multiple user terminals 102 in each cell. The network device 101 can be a base station. The network device 101 can provide communication services to multiple cells. For any given cell, each user terminal 102 within that cell can send signals to the network device 101, and each user terminal 102 can also receive signals from the network device 101. Figure 1 The dashed circles in the diagram represent the service area of ​​a cell, with different circles representing different cells.

[0051] Network device 101 may include multiple baseband boards, each baseband board may carry multiple processing chips and switching chips. The switching chip is connected to each of the multiple processing chips, and each processing chip can provide signal processing resources for at least one cell corresponding to it. The switching chip can coordinate the processing resources of the multiple processing chips.

[0052] The system includes multiple processing chips, including a first processing chip and auxiliary processing chips. The first processing chip can send resource requests to the switching chip, and the switching chip can determine the corresponding auxiliary processing chip based on the resource requests. The auxiliary processing chip can assist the first processing chip in data processing.

[0053] In related technologies, the basic unit of wireless service is the cell, and each processing chip can provide service flow for its corresponding cell. However, since each processing chip independently provides communication services to user terminals, the communication performance provided by the base station is relatively low.

[0054] The baseband board provided in this application embodiment may include a first processing chip and an auxiliary processing chip among the multiple processing chips on the baseband board. The auxiliary processing chip can assist the first processing chip in data processing and can improve the communication performance of the base station.

[0055] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will now be described with reference to the accompanying drawings.

[0056] After the baseband board is started, the first processing chip and the switching chip can establish an interactive interface. The first processing chip can send the cell address corresponding to the first processing chip to the switching chip. The switching chip can store the cell address of each processing chip to realize routing between the first processing chip and the auxiliary processing chip.

[0057] The first processing chip and the auxiliary processing chip can be used for data processing of the physical layer (PHY) and / or data processing of media access control (MAC).

[0058] The PHY can handle data transmission scheduling, resource allocation, error detection, and retransmission, while the MAC can control data transmission.

[0059] The auxiliary processing chip can be used to assist the first processing chip in PHY data processing; or, the auxiliary processing chip can be used to assist the first processing chip in Media Access Control (MAC) data processing and PHY data processing.

[0060] Figure 2 A schematic diagram of a single baseband board architecture provided in this application embodiment. Figure 1 Please see. Figure 2 The baseband board 200 may include a switching chip 201 and multiple processing chips, namely processing chip 202, processing chip 203 and processing chip 204. The switching chip 201 may be connected to each of the multiple processing chips.

[0061] When configuring the auxiliary processing chip corresponding to the first processing chip, the first processing chip can receive resource requests sent by the network management system, which can be used for network management and resource configuration functions. Based on the resource requests, the first processing chip configures the auxiliary processing chip corresponding to it. The first processing chip can also send resource requests to the switching chip. After receiving the resource requests, the switching chip can determine the auxiliary processing chip corresponding to the first processing chip based on the resource requests.

[0062] when Figure 2 When the baseband board serves a large number of cells, each cell has a small coverage area, and overlapping coverage between cells leads to significant interference, resulting in decreased throughput for user terminals. Furthermore, due to the small coverage area of ​​each cell, frequent cell handovers occur when user terminals move in overlapping coverage areas, potentially causing dropped calls and impacting user experience. Cell merging can address these issues by combining multiple independent cells operating on the same frequency and bandwidth into a single logical cell. From the user terminal's perspective, these independent cells form a single logical cell. When the user terminal moves between these independent cells, no cell handover occurs, thus improving the user experience.

[0063] In the cell merging scheme, the baseband board may include multiple processing chips, including a first processing chip and an auxiliary processing chip corresponding to the first processing chip. The cell served by the first processing chip and the cell served by the auxiliary processing chip are merged into a single logical cell. After cell merging, the user terminal will not experience cell handover, thereby improving the user experience.

[0064] Specifically, the switching chip can determine the amount of idle resources of the second processing chip based on the resource request, and then determine the auxiliary processing chip based on the amount of idle resources of the second processing chip.

[0065] The amount of free resources can be used to indicate the amount of PHY resources remaining in the processing chip.

[0066] There can be one or more auxiliary processing chips. If there is only one auxiliary processing chip, its idle resource amount is greater than or equal to the resource request amount. If there are multiple auxiliary processing chips, the sum of their idle resource amounts is greater than or equal to the resource request amount.

[0067] The second processing chip can be any of the multiple processing chips other than the first processing chip.

[0068] The resource request may include the amount of resources requested by the first processing chip.

[0069] Please see Figure 2Each processing chip includes a MAC and a PHY. Processing chip 202 is the first processing chip. The first processing chip may include a MAC and a PHY. Processing chip 202 can receive resource processing and send resource requests to switching chip 201. After receiving the resource request, switching chip 201 can determine the auxiliary processing chip corresponding to processing chip 202 as processing chip 203 based on the resource request.

[0070] In some possible embodiments, the auxiliary processing chip may include only the PHY and not the MAC.

[0071] After determining the auxiliary processing chip, the switching chip can send a first notification to the first processing chip. The first processing chip can receive the first notification sent by the switching chip and send the cell configuration information corresponding to the first processing chip to the switching chip.

[0072] The first notification is used to instruct the first processing chip to send the cell configuration information corresponding to the first processing chip.

[0073] The switching chip can receive cell configuration information, send cell configuration information to the auxiliary processing chip, receive response messages sent by the auxiliary processing chip, and create cooperation information between the first processing chip and the auxiliary processing chip based on the response messages. The cooperation information is used to indicate the correspondence between the auxiliary processing chip and the first processing chip.

[0074] The switching chip can also route the cell configuration information of the first processing chip to the physical layer module of the auxiliary processing chip corresponding to the first processing chip. The auxiliary processing chip can respond to the switching chip to construct a logical cell and provide communication resources to the first processing chip through the logical cell.

[0075] Please see Figure 2 The switching chip 201 can store the cooperation information between the processing chip 202 and the processing chip 203. The switching chip 201 can also send the cell configuration information of the processing chip 202 to the processing chip 203. After storing the cell configuration information, the processing chip 203 can assist the processing chip 202 in PHY data processing.

[0076] When processing chip 202 needs to perform PHY data processing on the data to be processed, the MAC of processing chip 202 can coordinate between the PHY of processing chip 202 and the PHY of processing chip 203. If the data to be processed is to be processed by the PHY of processing chip 203, then processing chip 202 can send the data to be processed to switching chip 201. Switching chip 201 can determine that the auxiliary processing chip corresponding to processing chip 202 is processing chip 203, and switching chip 201 can send the data to be processed to processing chip 203, and processing chip 203 can perform PHY data processing on the data to be processed.

[0077] The baseband board provided in this application embodiment includes a first processing chip and an auxiliary processing chip. The auxiliary processing chip can provide PHY data processing assistance to the first processing chip through a switching chip, which can improve the communication performance of the base station.

[0078] In cellular networks, such as 5G networks, co-frequency networking is commonly used. When using co-frequency networking, adjacent cells often have overlapping coverage areas, leading to significant interference, especially in the overlapping coverage areas of adjacent cells, resulting in a poor user experience. To improve the user experience at the edge, a Coordinated Multipoint Transmission / Reception (CoMP) scheme can be adopted. With CoMP, when serving user terminals, the service data of the serving cell and its corresponding co-frequency neighboring cells are jointly processed, improving the experience for users at the cell edge. During uplink, the base station performs inter-cell joint reception of uplink data from user terminals; during downlink, the base station performs inter-cell joint transmission of downlink data from user terminals.

[0079] When configuring the CoMP scheme, combine Figure 3 This section explains how the auxiliary processing chip assists the first processing chip in performing MAC and PYH processing. For example... Figure 3 As shown, the first processing chip may include MAC and PYH, and the auxiliary processing chip may include MAC in addition to PYH. The auxiliary processing chip can also simultaneously assist the first processing chip in MAC data processing and PYH data processing. Below,

[0080] Figure 3 A schematic diagram of a single baseband board architecture provided in this application embodiment. Figure 2 Please see. Figure 3 The baseband board 300 may include a switching chip 301 and multiple processing chips, namely processing chip 302, processing chip 303 and processing chip 304. Each processing chip includes a MAC and a PHY.

[0081] When determining the auxiliary processing chip corresponding to the first processing chip, the first processing chip can determine the identifier of the neighboring cell corresponding to the first processing chip and send the identifier of the neighboring cell to the switching chip. The switching chip can determine the auxiliary processing chip based on the identifier of the neighboring cell, and the neighboring cell is the cell corresponding to the auxiliary processing chip.

[0082] The neighboring cell can include one or more. If there is only one neighboring cell, then that neighboring cell can be identified as the auxiliary processing chip.

[0083] If there are N neighboring cells, where N is an integer greater than or equal to 2, the signal strength of each neighboring cell can be determined. If there is only one auxiliary processing chip, the processing chip corresponding to the neighboring cell with the strongest signal strength is designated as the auxiliary processing chip. There can be M auxiliary processing chips, where M is an integer greater than or equal to 2. If N is greater than M, the N neighboring cells can be sorted according to their signal strength, and the processing chips corresponding to the top M sorted neighboring cells are designated as the M auxiliary processing chips. If N is less than or equal to M, the processing chips corresponding to the N neighboring cells are designated as the N auxiliary processing chips; otherwise, the resource request fails.

[0084] Please see Figure 3 The processing chip 302 is the first processing chip. The processing chip 302 sends the identifier of the neighboring cell to the switching chip 301. The neighboring cell is the cell corresponding to the processing chip 303. The switching chip 301 can identify the processing chip 303 as an auxiliary processing chip. The processing chip 303 can assist the processing chip 302 in performing MAC data processing and PHY data processing.

[0085] When the processing chip 302 needs to perform MAC data processing and PHY data processing on the data to be processed, the processing chip 302 can send the data to be processed to the switching chip 301. The switching chip 301 can determine that the auxiliary processing chip corresponding to the processing chip 302 is the processing chip 303. The switching chip 301 can send the data to be processed to the processing chip 303, and the processing chip 303 can perform MAC data processing and PHY data processing on the data to be processed.

[0086] The baseband board provided in this application embodiment may include a first processing chip and an auxiliary processing chip. For configuring the auxiliary processing chip, please refer to... Figure 2 The auxiliary processing chip can provide auxiliary PHY data processing to the primary processing chip through the switching chip, thereby improving the communication performance of network devices. Please see [link to relevant documentation]. Figure 3 The configured auxiliary processing chip can provide auxiliary MAC data processing and PHY data processing to the first processing chip, which can further improve the communication performance of the network device.

[0087] Please combine Figure 2 and Figure 3 To illustrate the technical effects, the baseband board provided in this application embodiment can be configured in different ways to enable the auxiliary processing chip to assist the first processing chip in PHY data processing, or to assist the first processing chip in both MAC data processing and PHY data processing, thus allowing for flexible configuration of the auxiliary processing chip's functions. Furthermore, the first processing chip and the auxiliary processing chip can also perform their corresponding basic functions.

[0088] In network devices, at least two baseband boards can be carried in a chassis-type baseband unit (BBU). The baseband boards in the network device are responsible for processing the communication signals received from the user terminal (e.g., mobile phone) and determining the frame data to be sent to the user device.

[0089] In this configuration, the switching chips in at least two baseband boards are communicatively connected. In some embodiments, the at least two baseband boards can be communicatively connected via a backplane. The at least two baseband boards may include a first baseband board and a second baseband board. When configuring an auxiliary processing chip corresponding to a first processing chip on the first baseband board, the second baseband board can be an auxiliary baseband board corresponding to the first baseband board. The second baseband board can be used to determine the auxiliary processing chip, and the auxiliary processing chip can be used to assist the first processing chip on the first baseband board.

[0090] Figure 4 This is a schematic diagram of the architecture of a network device provided for an embodiment of the application. Please refer to [link / reference]. Figure 4 The network device 400 may include a baseband board 401 and a baseband board 402, where baseband board 401 is a first baseband board and baseband board 402 is a second baseband board. Baseband board 401 may include processing chips 4011, 4012, 4013, and a switching chip 4014, while baseband board 402 may include processing chips 4021, 4022, 4023, and a switching chip 4024. The first processing chip may be processing chip 4011 of baseband board 401, and the auxiliary chip may be processing chip 4021 of baseband board 402.

[0091] For any given processing chip, it may include a MAC and a PHY; please refer to [link / reference]. Figure 4If the processing chip 4021 assists the processing chip 4011 in performing PHY data processing, then when the processing chip 4011 needs to perform PHY data processing on the data to be processed, the processing chip 4011 can send the data to be processed to the switching chip 4014. The switching chip 4014 can send the data to be processed to the switching chip 4024 of the baseband board 402, and the switching chip 4024 can send the data to be processed to the processing chip 4021, and the processing chip 4021 can then perform PHY data processing on the data to be processed.

[0092] If the processing chip 4021 assists the processing chip 4011 in performing MAC data processing and PHY data processing, then when the processing chip 4011 needs to perform MAC data processing and PHY data processing on the data to be processed, the processing chip 4011 can send the data to be processed to the switching chip 4014. The switching chip 4014 can send the data to be processed to the switching chip 4024 of the baseband board 402, and the switching chip 4024 can send the data to be processed to the processing chip 4021. The processing chip 4021 can then perform MAC data processing and PHY data processing on the data to be processed.

[0093] The baseband board provided in this application embodiment can assist the first processing chip on the first baseband board in data processing through the auxiliary processing chip on the second baseband board, thereby improving the communication performance of the base station. Simultaneously, the auxiliary processing chip can be determined on the second baseband board, increasing the flexibility in configuring the auxiliary processing chip for the first processing chip.

[0094] Figure 5 A schematic diagram of a single baseband board architecture provided for embodiments of this application. Figure 3 Please see. Figure 5 The baseband board 500 includes a switching chip, multiple processing chips, and a Field-Programmable Gate Array (FPGA). An FPGA is a highly flexible integrated circuit that allows users to program and reconfigure its hardware functions after product deployment. The FPGA includes multiple uplink interfaces and multiple downlink interfaces. The FPGA connects to the corresponding processing chips on the baseband board through the uplink interfaces, and connects to the corresponding downlink device through each of the downlink interfaces.

[0095] The uplink and downlink interfaces can be Common Public Radio Interface (CPRI) interfaces.

[0096] The downlink interface can connect to downlink devices, which can be either remote radio units (RRUs) or hubs. Hubs can be used to connect and manage multiple RRUs.

[0097] FPGAs enable flexible networking between auxiliary processing chips and primary processing chips. Flexible networking refers to dynamically adjusting the communication paths between processing chips. FPGAs can control downlink data mapping and uplink RF merging processes. Downlink devices can connect to any one of the multiple downlink interfaces on the FPGA, and the FPGA can adjust the downlink interface connected to the downlink device to the corresponding processing chip.

[0098] The FPGA can obtain the first downlink data from the first processing chip and the second downlink data from the auxiliary processing chip through the uplink interface. The FPGA can perform frame processing on the first downlink data and the second downlink data to obtain frame data, and send the frame data to the remote radio frequency unit through the downlink interface.

[0099] Each uplink interface can correspond to multiple first channels, and these multiple first channels can transmit data in parallel. Multiple first channels can correspond to multiple processing modules, which can be downlink processing (PROC) modules. These processing modules can map the received downlink data to their corresponding frames based on the cell configuration table, thus obtaining frame data.

[0100] Each downlink interface can correspond to multiple second channels, and these multiple second channels can transmit data in parallel. A selection module is connected to the front end of each second channel. The selection module can be a downlink switching (SW) module. For any given selection module, it can receive all frame data after multiple processing modules have grouped them. The selection module can then select the frame data required by the remote RF unit connected to the second channel from all the frame data.

[0101] The downlink SW module can be configured with registers for switching control, enabling flexible mapping from any dual-channel processing chip to any downlink port.

[0102] Below, in conjunction with Figure 6A The following is a further explanation of the downlink data mapping process controlled by FPGA provided in the embodiments of this application.

[0103] Figure 6A This is a schematic diagram illustrating the architecture of a downlink data mapping process provided in an embodiment of this application. Please refer to [link / reference]. Figure 6A For the baseband board, please refer to Figure 2As shown, there are three processing chips: processing chip 201, processing chip 202, and processing chip 203. The FPGA can be configured with three uplink interfaces: uplink interface 601, uplink interface 602, and uplink interface 603. Uplink interface 601 can be connected to processing chip 602, uplink interface 602 can be connected to processing chip 603, and uplink interface 603 can be connected to processing chip 604.

[0104] Please see Figure 6A Each uplink interface can correspond to four first channels, namely channels 0 / 1, 2 / 3, 4 / 5, and 6 / 7. Each first channel has its corresponding processing module, namely downlink PROC module 0, downlink PROC module 1, ..., downlink PROC module 11. Figure 6A and Figure 6B The PROC indicator in the text refers to the downstream PROC module.

[0105] The downlink PROC module can map the received downlink data to its corresponding frame according to the cell configuration table to obtain frame data.

[0106] Please see Figure 6A The FPGA has six downlink interfaces, designated 601-606. Each downlink interface can include two second channels: channel 0 / 1 and channel 2 / 3. Each second channel has its corresponding selection module, totaling 12 selection modules: downlink SW module 0, downlink SW module 1, ..., downlink SW module 11. Figure 6A and Figure 6B The SW in the middle is used to indicate the downlink SW module. The downlink SW module can be used to select the frame data corresponding to the downlink interface from multiple frame data.

[0107] FPGAs also allow for flexible networking of uplink data. Below, we will combine... Figure 6B The present application provides a further explanation of the uplink RF merging process controlled by FPGA in the embodiments of this application.

[0108] Figure 6B This is a schematic diagram of an uplink radio frequency merging process provided in an embodiment of this application. Please refer to... Figure 6B The FPGA has three uplink interfaces: uplink interface 601, uplink interface 602, and uplink interface 603. Uplink interface 601 can be connected to processing chip 602, uplink interface 602 can be connected to processing chip 2, and uplink interface 603 can be connected to processing chip 3.

[0109] Please see Figure 6BThe FPGA has six downstream CPRI interfaces, designated as downstream interfaces 601-606. Each downstream interface can include two second channels: channel 0 / 1 and channel 2 / 3. These downstream interfaces can connect to a fronthaul hub or a remote RF unit. Uplink data can be received through these second channels, and each second channel can have its corresponding processing module: Uplink PROC Module 0, Uplink PROC Module 1, ..., Uplink PROC Module 11.

[0110] The uplink PROC module can determine the in-phase and quadrature (IQ) data, automatic gain control (AGC) information, compression information, and cyclic redundancy check (CRC) information corresponding to each uplink data according to the cell configuration table.

[0111] Please see Figure 6B It can include 12 uplink selection modules, namely uplink SW module 0, uplink SW module 1, ..., uplink SW module 11. For any uplink SW module, the uplink SW module can select the corresponding connected uplink PROC module from multiple uplink PROC modules, and send the uplink data corresponding to the uplink PROC module to the first channel corresponding to the uplink SW module, and send the uplink data to the processing chip through the first channel.

[0112] The baseband board provided in this application embodiment may include an FPGA. The FPGA can dynamically adjust the communication path between the first processing chip and the auxiliary processing chip. The FPGA can adjust the processing chip corresponding to the downstream device in the downstream interface, and can not restrict the downstream device connected to the downstream interface, thereby improving the flexibility of the downstream device connecting to the downstream interface.

[0113] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0114] The above are merely embodiments of this application and are not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. A baseband board, characterized in that, The baseband board includes a switching chip and multiple processing chips, wherein the multiple processing chips include a first processing chip and an auxiliary processing chip; The switching chip is connected to each of the plurality of processing chips; The first processing chip is used to send resource requests to the switching chip; The switching chip is used to determine the auxiliary processing chip corresponding to the first processing chip according to the resource request. The auxiliary processing chip is used to assist the first processing chip in data processing.

2. The baseband board according to claim 1, characterized in that, The auxiliary processing chip is used to assist the first processing chip in performing physical layer PHY data processing; or... The auxiliary processing chip is used to assist the first processing chip in performing Media Access Control (MAC) data processing and PHY data processing.

3. The baseband board according to claim 2, characterized in that, The auxiliary processing chip assists the first processing chip in PHY data processing; the resource request includes the resource request amount of the first processing chip; the switching chip is specifically used for: Based on the resource request, the amount of idle resources of the second processing chip is determined, wherein the second processing chip is one of the other processing chips besides the first processing chip among the plurality of processing chips. The auxiliary processing chip is determined based on the amount of idle resources of the second processing chip, wherein the amount of idle resources of the auxiliary processing chip is greater than or equal to the amount of resource requests.

4. The baseband board according to claim 2, characterized in that, The auxiliary processing chip is used to assist the first processing chip in performing MAC data processing and PHY data processing. The first processing chip is further configured to determine the identifier of the neighboring cell corresponding to the first processing chip, and send the identifier of the neighboring cell to the switching chip; The switching chip is also used to determine the auxiliary processing chip based on the neighboring cell identifier, wherein the neighboring cell is the cell corresponding to the auxiliary processing chip.

5. The baseband board according to any one of claims 1-4, characterized in that, The first processing chip is further configured to receive a first notification sent by the switching chip and send cell configuration information corresponding to the first processing chip to the switching chip; wherein, the first notification is configured to instruct the first processing chip to send the cell configuration information corresponding to the first processing chip; The switching chip is further configured to receive the cell configuration information, send the cell configuration information to the auxiliary processing chip, receive a response message sent by the auxiliary processing chip, and create cooperation information between the first processing chip and the auxiliary processing chip based on the response message. The cooperation information is used to indicate the correspondence between the auxiliary processing chip and the first processing chip.

6. The baseband board according to any one of claims 1-5, characterized in that, The first processing chip is also used to send the cell address corresponding to the first processing chip to the switching chip; The switching chip is also used to store the cell addresses of the plurality of processing chips to enable routing between the first processing chip and the auxiliary processing chip.

7. The baseband board according to any one of claims 1-6, characterized in that, The baseband board also includes a field-programmable gate array (FPGA), which includes multiple uplink interfaces and multiple downlink interfaces. The FPGA is connected to multiple processing chips corresponding to the baseband board through the multiple uplink interfaces; The FPGA is also used to connect to the downstream device corresponding to each of the plurality of downstream interfaces through each of the downstream interfaces.

8. The baseband board according to claim 7, characterized in that, Each uplink interface corresponds to multiple first channels, and the multiple first channels correspond to multiple processing modules, wherein... For any given processing module, the processing module receives downlink data through the first channel corresponding to the processing module, and the processing module is used to perform framing processing on the downlink data; The downlink data is framed using the multiple processing modules to obtain at least one frame of data.

9. The baseband board according to claim 8, characterized in that, Each downlink interface corresponds to multiple second channels, and a selection module is connected to the front end of each second channel. The selection module is used to determine the frame data of the second channel corresponding to the selection module in the at least one frame data. Each of the plurality of second channels is used to send the frame data to the downstream device.

10. A network device, characterized in that, Includes at least two baseband plates as described in any one of claims 1-9, wherein, The switching chips in the at least two baseband boards are connected in communication.

11. The network device according to claim 10, characterized in that, The at least two baseband boards include a first baseband board and a second baseband board, wherein the switching chip of the first baseband board is used for: The second baseband board is determined, and the second baseband board is the auxiliary baseband board corresponding to the first baseband board; In the second baseband board, an auxiliary processing chip is determined, which is used to assist the first processing chip of the first baseband board.

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