A double mesa double trench thyristor and a preparation method thereof
By introducing a double-mesa double-trench structure into a traditional double-mesa thyristor, the electric field distribution is optimized, the problem of electric field concentration on the trench sidewalls is solved, the withstand voltage and conduction performance of the device are improved, and the on-state voltage drop and switching losses are reduced.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- JIANGSU JIEJIE MICROELECTRONICS
- Filing Date
- 2026-04-29
- Publication Date
- 2026-05-29
AI Technical Summary
In traditional dual-mesa thyristor structures, the electric field is concentrated on the sidewalls and corners of the trench, which limits the device's voltage withstand capability and leads to problems such as increased device cost, increased on-resistance, and slower turn-off speed.
The design employs a dual-mesa dual-trench structure, which includes symmetrically setting first and second trench structures on both sides of an N-type silicon substrate, and forming a P-type short base region and an N+ type emitter region on the silicon wafer surface. Combined with the fabrication methods of glass films and metal electrodes, the electric field distribution is optimized.
It significantly improves the withstand voltage performance of the device, reduces the on-state voltage drop and switching losses, and optimizes the static and dynamic performance of the device.
Smart Images
Figure CN122121192A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, specifically to a mesa thyristor with dual mesa and dual trench and its fabrication method. Background Technology
[0002] The performance of the passivation layer of the mesa silicon controlled rectifier directly determines the mechanical stability, electrical reliability, and long-term operating life of the device.
[0003] The shortcomings of existing technology: Currently, traditional dual-mesa thyristor structures have the following key drawbacks: First, the electric field concentration at the trench sidewalls and corners is significant, limiting further improvement in the device's withstand voltage. To achieve high withstand voltage, a thick and highly resistive N-type drift region must be used, which not only pushes the device's withstand voltage close to the theoretical limit of the "one-dimensional parallel plate junction" and makes it difficult to break through, but also increases manufacturing costs. Second, an excessively thick drift region introduces a large on-resistance, resulting in an excessively high on-state voltage drop and increased power consumption. Third, increasing the thickness of the drift region also increases the amount of minority carriers stored, leading to slower turn-off speed, increased switching losses, and affecting the device's dynamic performance. Summary of the Invention
[0004] The purpose of this invention is to provide a mesa thyristor with dual mesa and dual trench and its fabrication method, so as to solve the problems mentioned in the background art.
[0005] To achieve the above objectives, the present invention provides the following technical solution: a mesa-type thyristor with dual mesa and dual trenches, comprising a silicon wafer and an N-type silicon substrate, wherein the N-type silicon substrate is disposed on the front side of the silicon wafer, and both the top and bottom of the N-type silicon substrate are configured as P-type short base regions, the P-type short base regions extending through the front and back sides of the silicon wafer, one of the P-type short base regions being configured with an N+ type emitter region, and dual trench structures symmetrically disposed on both sides of the top and bottom of the N-type silicon substrate, the dual trench structure comprising a first trench and a second trench.
[0006] Preferably, an anode electrode is disposed on the lower side of the silicon wafer, a cathode electrode is disposed at the N+ type emitter region, and a gate electrode is disposed on the upper side of the silicon wafer away from the N+ type emitter region.
[0007] Preferably, the depth of the P-type short base region is set to 90-110 μm, the depth of the N+ type emitter region is set to 10-20 μm, the depth of the first trench is set to 50-100 μm, and the depth of the second trench is set to 70-150 μm.
[0008] This invention also provides a method for fabricating a mesa thyristor with dual mesa and dual trench surfaces, the method specifically comprising: S1. Select an N-type silicon substrate; S2, forming a P-type short base region; S3, forming an N+ type emission region; S4. Forms a double-groove structure; S5 forms the gate electrode, cathode electrode, and anode electrode.
[0009] Preferably, step S2 specifically includes: a1. Doping with P-type phosphorus impurities: P-type impurities are doped into the surface of an N-type silicon substrate by diffusion or implantation. a2. Place the silicon wafer in a diffusion furnace, introduce the protective gas N2, and diffuse and push the junction at high temperature to form a P-type short base region on the silicon wafer and generate a silicon dioxide thin film on the surface of the N-type silicon substrate.
[0010] Preferably, step S3 specifically includes: b1. Photolithography of N+ type emitter region: Photoresist is evenly coated on the front side of the silicon wafer using a spin coater. After pre-baking, exposure, development and hardening, the N+ type emitter region window is opened. The silicon wafer is placed in BOE buffer etching solution to etch away the silicon dioxide film in the window. Then, the photoresist is removed, cleaned and dried. b2. Incorporate N-type impurities into the front side of the silicon wafer through diffusion or implantation; b3. Place the silicon wafer in a diffusion furnace, introduce a protective gas, and diffuse and push the junction at high temperature to form an N+ type emitter region and generate a silicon dioxide thin film.
[0011] Preferably, step S4 specifically includes: c1. Photoresist is uniformly coated on the front side of the silicon wafer using a spin coater. After pre-baking, exposure, development, and hardening, the first trench window is opened. The silicon dioxide film of the first trench window is etched away using BOE buffer etching solution, and then cleaned and dried. c2. Etch the silicon in the first trench window with HF-HNO3 etching solution to form a mesa with a depth of 50-100um, and then remove the adhesive, clean and spin dry. c3. Based on the first trench, photoresist is uniformly coated into the first trench using a spin coater. After pre-baking, exposure, development and hardening, the second trench window is opened. c4. Etch the silicon in the second trench window with HF-HNO3 etching solution to form a mesa with a depth of 70-150um, then remove the adhesive, clean and spin dry.
[0012] Preferably, step S5 specifically includes: d1. Deposit SIPOS thin films on the front and back sides of a silicon wafer using an LPCVD device; d2. An adhesive is prepared using ethyl cellulose and butyl carbitol, which is then mixed with glass powder to form a glass paste. The glass paste is then filled into the first and second grooves by a scraping method, and a glass film is formed by low-temperature sintering. d3. Deposit silicon dioxide thin films on the front and back sides of the silicon wafer using an LPCVD device, with the silicon dioxide film thickness set to 0.3-0.5 μm; d4. Photoresist is evenly coated on the front and back sides of the silicon wafer using a spin coater. After pre-baking, exposure, development and hardening, lead windows are opened. BOE buffer etchant and HF-HNO3 etchant are used to etch away the silicon dioxide film and SIPOS film in the window in sequence. The photoresist is then removed, cleaned and dried. d5. A thin metal film is deposited on the front and back sides of the silicon wafer using a high-vacuum electron beam evaporation device; d6. Photoresist is uniformly coated on the front side of the silicon wafer using a spin coater. After pre-baking, exposure, development and hardening, a reverse etching window is opened. The metal film inside the reverse etching window is removed using a metal etching solution. The photoresist is then removed, cleaned and dried to form the gate electrode, cathode electrode and anode electrode. d7. Silicon forms alloy points with metals, reducing the pressure drop.
[0013] Preferably, the pre-baking, exposure, development, and hardening processes in step b1 are specifically manifested as follows: Pre-baking: Removes 50%-80% of the solvent in the photoresist, allowing the photoresist film to dry and cure, enhancing its adhesion to the silicon wafer, and releasing the internal stress generated during the coating process; Exposure: The process of shining a light source through a mask onto the photoresist, causing a change in the chemical properties of the photoresist in the exposed area; Development: Using a developer, the photoresist that needs to be removed is selectively dissolved, thereby revealing a three-dimensional photoresist pattern on the silicon wafer; Hardening film: Removes all residual solvent.
[0014] Compared with the prior art, the beneficial effects of the present invention are: This invention discloses a mesa-type thyristor with dual mesa and dual trench design, and its fabrication method. By introducing a dual-trench mesa design, the electric field concentration effect on the trench sidewalls in traditional processes is effectively alleviated, optimizing the internal electric field distribution of the device and significantly improving its withstand voltage performance. Compared to traditional dual-mesa thyristors, the forward blocking voltage of the dual-mesa dual-trench thyristor is increased by 19.1%, and the reverse blocking voltage is increased by 14.1%, effectively improving the breakdown voltage of the device. Under the same breakdown voltage design specifications, compared to the traditional dual-mesa structure, the dual-mesa dual-trench thyristor effectively reduces the thickness of the silicon wafer by introducing the dual-trench structure. This structural optimization significantly shortens the length of the drift region, thereby reducing the drift region resistance, which in turn reduces the forward voltage drop and reduces switching losses. Therefore, this invention improves withstand voltage while simultaneously reducing forward voltage drop and switching losses, achieving overall optimization of the device's static and dynamic performance. Attached Figure Description
[0015] Figure 1 This is a schematic cross-sectional view of the present invention; Figure 2 This is a comparison diagram of the forward and reverse breakdown voltages of the present invention and a traditional dual-mesa thyristor; Figure 3 The diagram shows the two-dimensional electric field distribution of the dual-mesa dual-trench thyristor of the present invention and the conventional dual-mesa thyristor during forward blocking. Figure 4 This is a one-dimensional electric field distribution diagram of the depletion layer of the dual-mesa dual-trench thyristor of the present invention and the conventional dual-mesa thyristor under forward blocking conditions. In the figure: 1. N-type silicon substrate; 2. P-type short base region; 3. N+ type emitter region; 4. First trench; 5. Second trench; 6. Anode electrode; 7. Cathode electrode; 8. Gate electrode; 9. Glass film. Detailed Implementation
[0016] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0017] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.
[0018] In the description of this patent, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "setting" should be interpreted broadly. For example, they can refer to a fixed connection or setting, a detachable connection or setting, or an integrated connection or setting. Those skilled in the art can understand the specific meaning of the above terms in this patent according to the specific circumstances.
[0019] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a number" means two or more, unless otherwise explicitly specified.
[0020] Example Please see Figure 1-4 As shown, this invention provides a mesa-type thyristor technology solution with dual mesa and dual trenches: It includes a silicon wafer and an N-type silicon substrate 1. The N-type silicon substrate 1 is disposed on the front side of the silicon wafer. Both the top and bottom of the N-type silicon substrate 1 are configured with P-type short base regions 2, which penetrate both the front and back sides of the silicon wafer. The depth of the P-type short base regions 2 is set to 90-110 μm. One of the P-type short base regions 2 is configured with an N+ type emitter region 3, with a depth of 10-20 μm. Symmetrical dual trench structures are arranged on both sides of the top and bottom of the N-type silicon substrate 1. The dual trench structures include a first trench 4 and a second trench 5. The depth of the first trench 4 is set to 50-100 μm, and the depth of the second trench 5 is set to 70-150 μm. An anode electrode 6 is disposed on the lower side of the silicon wafer, a cathode electrode 7 is disposed at the N+ type emitter region 3, and a gate electrode 8 is disposed on the upper side of the silicon wafer away from the N+ type emitter region 3.
[0021] This invention also provides a method for fabricating a mesa thyristor with dual mesa and dual trench surfaces, the method specifically including: S1. Select an N-type silicon substrate 1; S2, forming a P-type short base region 2; a1. Doping with P-type phosphorus impurities: P-type impurities are doped into the surface of N-type silicon substrate 1 by diffusion or implantation. a2. Place the silicon wafer in a diffusion furnace, introduce protective gas N2, and diffuse and push the junction at high temperature to form P-type short base regions 2 on the silicon wafer and generate a silicon dioxide film on the surface of N-type silicon substrate 1. S3, forming an N+ type emission region 3; b1. Photolithography of N+ type emitter region 3: Photoresist is evenly coated on the front side of the silicon wafer using a spin coater. After pre-baking, exposure, development and hardening, the N+ type emitter region 3 window is opened. The silicon wafer is placed in BOE buffer etching solution to etch away the silicon dioxide film in the window. The photoresist is then removed, cleaned and dried. Specifically, pre-baking, exposure, development, and hardening are manifested as follows: Pre-baking: Removes 50%-80% of the solvent in the photoresist, allowing the photoresist film to dry and cure, enhancing its adhesion to the silicon wafer, and releasing the internal stress generated during the coating process; Exposure: The process of shining a light source through a mask onto the photoresist, causing a change in the chemical properties of the photoresist in the exposed area; Development: Using a developer, the photoresist that needs to be removed is selectively dissolved, thereby revealing a three-dimensional photoresist pattern on the silicon wafer; Hardening: Removes all residual solvents, further improving the chemical stability and etching resistance of the photoresist; b2. Incorporate N-type impurities into the front side of the silicon wafer through diffusion or implantation; b3. Place the silicon wafer in a diffusion furnace, introduce a protective gas, and diffuse and push the junction at high temperature to form an N+ type emitter region 3 and generate a silicon dioxide thin film. S4. Forms a double-groove structure; c1. Photoresist is uniformly coated on the front side of the silicon wafer using a spin coater. After pre-baking, exposure, development, and hardening, the first trench 4-window is opened. The silicon dioxide film of the first trench 4-window is etched away using BOE buffer etching solution, and then cleaned and dried. Specifically, pre-baking, exposure, development, and hardening are manifested as follows: Pre-baking: Removes 50%-80% of the solvent in the photoresist, allowing the photoresist film to dry and cure, enhancing its adhesion to the silicon wafer, and releasing the internal stress generated during the coating process; Exposure: The process of shining a light source through a mask onto the photoresist, causing a change in the chemical properties of the photoresist in the exposed area; Development: Using a developer, the photoresist that needs to be removed is selectively dissolved, thereby revealing a three-dimensional photoresist pattern on the silicon wafer; Hardening: Removes all residual solvents, further improving the chemical stability and etching resistance of the photoresist; c2. Etch the silicon in the first trench 4 window with HF-HNO3 etching solution to form a mesa with a depth of 50-100um, and then remove the adhesive, clean and spin dry. c3. Based on the first trench 4, photoresist is uniformly coated into the first trench 4 using a spin coater. After pre-baking, exposure, development and hardening, the second trench 5 window is opened. Specifically, pre-baking, exposure, development, and hardening are manifested as follows: Pre-baking: Removes 50%-80% of the solvent in the photoresist, allowing the photoresist film to dry and cure, enhancing its adhesion to the silicon wafer, and releasing the internal stress generated during the coating process; Exposure: The process of shining a light source through a mask onto the photoresist, causing a change in the chemical properties of the photoresist in the exposed area; Development: Using a developer, the photoresist that needs to be removed is selectively dissolved, thereby revealing a three-dimensional photoresist pattern on the silicon wafer; Hardening: Removes all residual solvents, further improving the chemical stability and etching resistance of the photoresist; c4. Etch the silicon in the second trench 5 window with HF-HNO3 etching solution to form a mesa with a depth of 70-150um, remove the adhesive, clean and spin dry; S5 forms the gate electrode 8, the cathode electrode 7, and the anode electrode 6; d1. Deposit SIPOS thin films on the front and back sides of a silicon wafer using an LPCVD device; d2. An adhesive is prepared using ethyl cellulose and butyl carbitol, which is then mixed with glass powder to form a glass paste. The glass paste is then filled into the first groove 4 and the second groove 5 by a scraping method, and a glass film 9 is formed by low-temperature sintering. d3. Deposit silicon dioxide thin films on the front and back sides of the silicon wafer using an LPCVD device, with the silicon dioxide film thickness set to 0.3-0.5 μm; d4. Photoresist is evenly coated on the front and back sides of the silicon wafer using a spin coater. After pre-baking, exposure, development and hardening, lead windows are opened. BOE buffer etchant and HF-HNO3 etchant are used to etch away the silicon dioxide film and SIPOS film in the window in sequence. The photoresist is then removed, cleaned and dried. Specifically, pre-baking, exposure, development, and hardening are manifested as follows: Pre-baking: Removes 50%-80% of the solvent in the photoresist, allowing the photoresist film to dry and cure, enhancing its adhesion to the silicon wafer, and releasing the internal stress generated during the coating process; Exposure: The process of shining a light source through a mask onto the photoresist, causing a change in the chemical properties of the photoresist in the exposed area; Development: Using a developer, the photoresist that needs to be removed is selectively dissolved, thereby revealing a three-dimensional photoresist pattern on the silicon wafer; Hardening: Removes all residual solvents, further improving the chemical stability and etching resistance of the photoresist; d5. A thin metal film is deposited on the front and back sides of the silicon wafer using a high-vacuum electron beam evaporation device; d6. Photoresist is uniformly coated on the front side of the silicon wafer using a spin coater. After pre-baking, exposure, development and hardening, a reverse etching window is opened. The metal film inside the reverse etching window is removed using a metal etching solution. The photoresist is then removed, cleaned and dried to form the gate electrode 8, the cathode electrode 7 and the anode electrode 6. Specifically, pre-baking, exposure, development, and hardening are manifested as follows: Pre-baking: Removes 50%-80% of the solvent in the photoresist, allowing the photoresist film to dry and cure, enhancing its adhesion to the silicon wafer, and releasing the internal stress generated during the coating process; Exposure: The process of shining a light source through a mask onto the photoresist, causing a change in the chemical properties of the photoresist in the exposed area; Development: Using a developer, the photoresist that needs to be removed is selectively dissolved, thereby revealing a three-dimensional photoresist pattern on the silicon wafer; Hardening: Removes all residual solvents, further improving the chemical stability and etching resistance of the photoresist; d7. Silicon forms alloy points with metals, reducing the pressure drop.
[0022] Furthermore, through comparison and verification of simulation and fabrication results, this invention achieves a 200 V increase in breakdown voltage and a 0.9 mA reduction in gate trigger current compared to the traditional double-mesa structure. Further analysis shows that this invention optimizes the internal electric field distribution of the device, thereby effectively reducing on-state voltage drop and turn-off losses. Figure 2 It can be seen that the forward blocking voltage of the present invention is 1540V, which is 19.1% higher than that of the traditional dual-mesa thyristor, and the reverse blocking voltage is 1520V, which is 14.1% higher than that of the traditional dual-mesa thyristor. Figure 3 The electric field distribution during forward blocking is shown. Compared with the traditional dual-mesa thyristor, the electric field distribution of the dual-trench dual-mesa thyristor is more uniform on the trench sidewall, which effectively alleviates the phenomenon of electric field concentration on the trench sidewall. Figure 4 The maximum breakdown electric field of the medium-duration double-trench double-mesa thyristor is increased by 1×10 compared to the conventional double-mesa thyristor. 5 The voltage rating was increased by V / cm, and the depletion layer width was increased, which optimized the average electric field and thus improved the device's breakdown voltage performance.
[0023] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely preferred examples and are not intended to limit the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the present invention as claimed. The scope of protection of the present invention is defined by the appended claims and their equivalents.
Claims
1. A mesa-type thyristor with dual mesa and dual trench, comprising a silicon wafer and an N-type silicon substrate (1), characterized in that: The N-type silicon substrate (1) is disposed on the front side of the silicon wafer. The top and bottom of the N-type silicon substrate (1) are both configured as P-type short base regions (2). The P-type short base regions (2) penetrate the front and back sides of the silicon wafer. One of the P-type short base regions (2) is provided with an N+ type emitter region (3). The top and bottom sides of the N-type silicon substrate (1) are symmetrically provided with a double trench structure. The double trench structure includes a first trench (4) and a second trench (5).
2. The mesa thyristor with double mesa and double trench as described in claim 1, characterized in that: An anode electrode (6) is provided on the lower side of the silicon wafer, a cathode electrode (7) is provided at the N+ type emission region (3), and a gate electrode (8) is provided on the upper side of the silicon wafer away from the N+ type emission region (3).
3. The mesa thyristor with dual mesa and dual trench as described in claim 1, characterized in that: The depth of the P-type short base region (2) is set to 90-110 μm, the depth of the N+ type emitter region (3) is set to 10-20 μm, the depth of the first trench (4) is set to 50-100 μm, and the depth of the second trench (5) is set to 70-150 μm.
4. A method for fabricating a mesa thyristor with dual mesa and dual trench as described in any one of claims 1-3, characterized in that: The preparation method specifically includes: S1. Select an N-type silicon substrate (1); S2, forming a P-type short base region (2); S3, forming an N+ type emission region (3); S4. Forms a double-groove structure; S5 forms the gate electrode (8), the cathode electrode (7), and the anode electrode (6).
5. The method for fabricating a mesa thyristor with dual mesa and dual trench as described in claim 4, characterized in that: Step S2 specifically includes: a1. Doping with P-type phosphorus impurities: P-type impurities are doped into the surface of an N-type silicon substrate (1) by diffusion or implantation. a2. Place the silicon wafer in a diffusion furnace and introduce the protective gas N2. Diffusion and bonding are carried out at high temperature to form P-type short base regions (2) on the silicon wafer and generate a silicon dioxide thin film on the surface of the N-type silicon substrate (1).
6. The method for fabricating a mesa thyristor with dual mesa and dual trench as described in claim 4, characterized in that: Step S3 specifically includes: b1. Photolithography of N+ type emitter region (3): Photoresist is uniformly coated on the front side of the silicon wafer using a spin coater. After pre-baking, exposure, development and hardening, the N+ type emitter region (3) window is opened. The silicon wafer is placed in BOE buffer etching solution to etch away the silicon dioxide film in the window. The photoresist is then removed, cleaned and dried. b2. Incorporate N-type impurities into the front side of the silicon wafer through diffusion or implantation; b3. Place the silicon wafer in a diffusion furnace, introduce a protective gas, and diffuse and push the junction at high temperature to form an N+ type emitter region (3) and generate a silicon dioxide thin film.
7. The method for fabricating a mesa thyristor with dual mesa and dual trench as described in claim 4, characterized in that: Step S4 specifically includes: c1. Photoresist is uniformly coated on the front side of the silicon wafer using a spin coater. After pre-baking, exposure, development, and hardening, the first trench (4) window is opened. The silicon dioxide film of the first trench (4) window is etched away using BOE buffer etching solution, and then cleaned and dried. c2. Etch the silicon in the first trench (4) window with HF-HNO3 etching solution to form a mesa with a depth of 50-100um, and remove the adhesive, clean and spin dry; c3. Based on the first trench (4), the photoresist is uniformly coated in the first trench (4) using a spin coater. After pre-baking, exposure, development and hardening, the second trench (5) window is opened. c4. Etch the silicon in the second trench (5) window with HF-HNO3 etching solution to form a mesa with a depth of 70-150um, remove the adhesive, clean and spin dry.
8. The method for fabricating a mesa thyristor with dual mesa and dual trench as described in claim 4, characterized in that: Step S5 specifically includes: d1. Deposit SIPOS thin films on the front and back sides of a silicon wafer using an LPCVD device; d2. An adhesive is prepared by using ethyl cellulose and butyl carbitol, which is then mixed with glass powder to form a glass paste. The glass paste is then filled into the first groove (4) and the second groove (5) by scraping with a knife, and a glass film is formed by low-temperature sintering. d3. Deposit silicon dioxide thin films on the front and back sides of the silicon wafer using an LPCVD device, with the silicon dioxide film thickness set to 0.3-0.5 μm; d4. Photoresist is evenly coated on the front and back sides of the silicon wafer using a spin coater. After pre-baking, exposure, development and hardening, lead windows are opened. BOE buffer etchant and HF-HNO3 etchant are used to etch away the silicon dioxide film and SIPOS film in the window in sequence. The photoresist is then removed, cleaned and dried. d5. A thin metal film is deposited on the front and back sides of the silicon wafer using a high-vacuum electron beam evaporation device; d6. Photoresist is uniformly coated on the front side of the silicon wafer using a spin coater. After pre-baking, exposure, development and hardening, a reverse etching window is opened. The metal film inside the reverse etching window is removed using a metal etching solution. The photoresist is then removed, cleaned and dried to form the gate electrode (8), cathode electrode (7) and anode electrode (6). d7. Silicon forms alloy points with metals, reducing the pressure drop.
9. The method for fabricating a mesa thyristor with dual mesa and dual trench as described in claim 6, characterized in that: The pre-baking, exposure, development, and hardening processes in step b1 are specifically manifested as follows: Pre-baking: Removes 50%-80% of the solvent in the photoresist, allowing the photoresist film to dry and cure, enhancing its adhesion to the silicon wafer, and releasing the internal stress generated during the coating process; Exposure: The process of shining a light source through a mask onto the photoresist, causing a change in the chemical properties of the photoresist in the exposed area; Development: Using a developer, the photoresist that needs to be removed is selectively dissolved, thereby revealing a three-dimensional photoresist pattern on the silicon wafer; Hardening film: Removes all residual solvent.