Isolation schemes for iii-n devices

Abstract

Isolation schemes for III-N devices are described. In one arrangement, a semiconductor device (100) includes a semiconductor substrate (102) including an isolation region (123A, 123B) laterally surrounding a device region (155) including a gate region (105B), a source region (105A), and a drain region (105D). The semiconductor device (100) further includes a III-N heterojunction structure (106) over the semiconductor substrate (102) including a buffer layer (104) over the semiconductor substrate (102) and a barrier layer (110) over the buffer layer (104). The semiconductor device (100) further includes a p-doped III-N gate (113) in the gate region (105B) over the barrier layer (110), and a passivation layer (116A, 116B) over the barrier layer (110) and the p-doped III-N gate (113). The passivation layer (116A, 116B) extends across the device region (155) and the isolation region (123A, 123B), where the passivation layer (116A, 116B) does not include an isolation implant species.

Description

Technical Field

[0001] The disclosed implementation schemes generally relate to the field of III-N semiconductor devices and their manufacture. Background Technology

[0002] Group III nitride materials (also known as III-N materials) possess a unique combination of physical and electrical properties that have proven beneficial in modern microelectronics and optoelectronics. These properties include wide bandgap, high saturation drift velocity and breakdown voltage, high thermal conductivity, and robust chemical and thermal stability. Due to these characteristics, III-N materials are considered promising for fabricating powerful high-frequency transistors capable of operating in high-temperature and harsh environments. Despite the continued rapid development of III-N devices and their fabrication, several shortcomings remain, necessitating further innovations as described below. Summary of the Invention

[0003] The following is a simplified overview to provide a basic understanding of some examples of this disclosure. This summary is not a broad overview of the examples and is neither intended to identify key or essential elements of the examples nor to indicate their scope. In fact, the main purpose of this summary is to present some concepts of this disclosure in a simplified form as a prelude to the more detailed description that will follow in subsequent sections.

[0004] In one example, a method for manufacturing a semiconductor device is disclosed, wherein the method particularly includes: forming a buffer layer over a semiconductor substrate; and forming a barrier layer over the buffer layer, the barrier layer avoiding contact with isolation implantation photoresist during an isolation implantation stage, wherein the isolation implantation photoresist is patterned to expose an isolation region of the semiconductor substrate. The isolation region laterally surrounds a device region of the semiconductor substrate, the device region comprising a gate region, a source region, and a drain region. The method further includes forming a source electrode in the source region, a drain electrode in the drain region, and a gate electrode over a p-GaN gate formed in the gate region.

[0005] In one example, a method for manufacturing a semiconductor device is disclosed. The method particularly includes: forming a III-N heterojunction structure over a semiconductor substrate, the III-N heterojunction structure including a buffer layer over the semiconductor substrate and a barrier layer over the buffer layer; and forming a p-GaN layer over the III-N heterojunction structure. The method further includes: forming a dielectric cap over the p-GaN layer, the dielectric cap covering the p-GaN layer in a gate region of the semiconductor substrate; and forming a patterned photoresist layer over the dielectric cap and the p-GaN layer, the patterned photoresist layer being patterned to expose an isolation region of the semiconductor substrate, wherein the isolation region laterally surrounds a device region of the semiconductor substrate. The device region includes the gate region, source region, and drain region. The method further includes: implanting isolation implantation species in the isolation region to form the isolation region relative to the region; removing the patterned photoresist layer; removing the p-GaN layer outside the dielectric cap to form a p-GaN gate in the gate region above the barrier layer; removing the dielectric cap; and forming a source electrode in the source region, a drain electrode in the drain region, and a gate electrode above the p-GaN gate. In an example arrangement, the dielectric cap may be used as a hard mask to etch the p-GaN material outside the dielectric cap in a removal process.

[0006] In one example, a semiconductor device is disclosed, comprising: a semiconductor substrate including an isolation region laterally surrounding a device region, the device region including a gate region, a source region, and a drain region; and a III-N heterojunction structure above the semiconductor substrate, the III-N heterojunction structure including a buffer layer above the semiconductor substrate and a barrier layer above the buffer layer. The semiconductor device further includes a p-doped III-N gate in the gate region and above the barrier layer; and a passivation layer above the barrier layer and the p-doped III-N gate, the passivation layer extending across the device region and the isolation region, wherein the passivation layer does not contain isolation implanted species. Attached Figure Description

[0007] In the accompanying figures, embodiments of the present disclosure are shown by way of example and not limitation. Different references to “a” or “an” embodiment in this disclosure do not necessarily refer to the same embodiment, and such references may mean at least one. Furthermore, when a particular feature, structure, or characteristic is described in connection with an embodiment, whether or not it is explicitly described, such feature, structure, or characteristic may be combined with other embodiments.

[0008] To illustrate one or more exemplary embodiments of this disclosure, the accompanying drawings are incorporated in and form a part of the specification. Various advantages and features of this disclosure are described in the following detailed description, taking into account the appended claims and the accompanying drawings, in which:

[0009] Figures 1A to 1H Cross-sectional views of a semiconductor device including a GaN device according to an example of this disclosure are depicted at various stages of a process flow including device isolation; and

[0010] Figure 2A and 2B This is a flowchart of a method for manufacturing a semiconductor device according to some examples of this disclosure. Detailed Implementation

[0011] Examples of this disclosure are described with reference to the accompanying drawings, in which similar reference numerals are generally used to refer to similar elements. The drawings are not drawn to scale and are provided merely for illustrative purposes. Numerous specific details, relationships, and methods are set forth below to provide an understanding of one or more examples. However, some examples may be practiced without such specific details. In other examples, well-known subsystems, components, structures, and techniques are not shown in detail to avoid obscuring the understanding of the examples. Therefore, examples of this disclosure may be practiced without such specific components.

[0012] Additionally, terms such as “coupled” and “connected”, and their derivatives, may be used in the following description, the appended claims, or both. It should be understood that these terms are not necessarily intended to be synonyms with each other. “Coupled” can be used to indicate that two or more elements (which may or may not be in direct physical or electrical contact with each other) cooperate or interact with each other. “Connected” can be used to indicate the establishment of communication, i.e., a communication relationship, between two or more coupled elements. Furthermore, in one or more instances set forth herein, generally, if an element can be programmed to perform or otherwise structurally arranged to perform a certain function, then the element, component, or module can be configured to perform said function.

[0013] Without limitation, examples of this disclosure will be set forth below in the context of improving the performance characteristics of semiconductor devices based on group III nitride materials (also known as III-N materials), such as gallium nitride (GaN) devices.

[0014] GaN devices (e.g., GaN transistors) offer certain performance advantages over silicon, including lower on-state resistance (e.g., drain-source resistance or R0). DSONGaN transistors offer advantages such as lower switching losses and improved breakdown voltage. They comprise a heteroepitaxial structure (e.g., a heterojunction structure) with a junction between materials with different bandgap (e.g., aluminum gallium nitride (AlGaN) and gallium nitride (GaN)) to provide a 2D electron gas (2DEG) formed within the AlGaN / GaN heteroepitaxial structure for device operation (e.g., forming a channel for a GaN device). The 2D electron gas (2DEG) may be referred to as a 2DEG channel. Depletion-mode (DMODE) GaN transistors are normally on, while enhancement-mode (EMODE) GaN transistors are normally off. In some instances, EMODE GaN transistors comprise a gate stack with a gallium nitride (p-GaN) layer containing a p-type dopant, such as magnesium (Mg) or other suitable p-type dopant. When the p-type dopant is activated, the p-GaN layer can deplete the 2DEG beneath the gate stack under zero or negative gate bias. Applying a positive gate voltage enhances the 2DEG below the gate and enables the EMODE GaN device to allow current to flow between the source and drain.

[0015] In some instances, GaN devices may have one or more GaN layers formed over a suitable semiconductor substrate (e.g., a silicon substrate). One or more GaN layers may form a heterojunction structure over the semiconductor substrate, wherein a p-GaN layer covers the heterojunction structure to achieve EMODE device functionality. The p-GaN layer may contain an appropriate amount of p-type dopant to control the threshold voltage (V) of the GaN device. T or V TH Typically, a higher threshold voltage is desired to reduce the likelihood of accidental EMODE activation, increase operating margin, and reduce leakage current (e.g., in the off-state I). DS )wait.

[0016] In some instances, the GaN process flow may include an implantation stage for achieving field isolation of the device, in which suitable implantation species are implanted into a defined region of the substrate, such as an exposed region of the substrate. This region may laterally surround a region where one or more GaN devices may be formed (e.g., a device region or an active region). The implanted species impair the crystallinity of the heterojunction structure in the defined region, thereby disrupting or preventing the formation of 2DEG in the defined region. Therefore, the defined region is no longer used to form a GaN device, resulting in an isolation region used to electrically isolate the region where the GaN device is located (e.g., a region that retains the crystallinity of the heterojunction structure).

[0017] In some process flows, photoresist (PR) can be patterned over a patterned p-GaN layer to facilitate isolation implantation within a defined region of the semiconductor substrate during GaN device formation. In an example embodiment, the photoresist can be patterned to expose an isolation region in the semiconductor substrate, wherein the isolation region laterally surrounds a device region of the semiconductor substrate. The device region (also referred to as the active region) contains a patterned p-GaN layer in the gate region of the device region. In such arrangements, the photoresist can directly contact the barrier layer of a heterojunction structure, such as an AlGaN layer exposed after the p-GaN layer has been patterned. Therefore, there is a risk that components of the photoresist (e.g., organic compounds comprising carbon-based materials) may contaminate the surface of the barrier layer in contact with the photoresist. In some arrangements, such organic compounds (also referred to herein as organic contaminants) may cause electron trapping in the barrier layer under certain operating conditions (e.g., in high-voltage applications). In this way, organic contaminants in the barrier layer may lead to performance degradation of the GaN device.

[0018] To avoid barrier layer contamination, some arrangements may include a dielectric layer, such as a silicon nitride (SiN) layer, formed over a patterned p-GaN layer and extending across the barrier layer before the formation of the patterned photoresist. Thus, the dielectric layer serves as a barrier layer to prevent direct contact between the photoresist and the barrier layer. While protecting the barrier layer from photoresist contamination, dielectric layers extending beyond the active region boundary can be damaged by exposure to isolation implantation. Damaged dielectric layers can adversely affect device reliability, especially in some instances where the dielectric layer also functions as a passivation layer. Although damaged dielectric layers can be removed and new dielectric layers can be deposited, this process introduces additional complexity. Furthermore, the barrier layer needs to be exposed to additional thermal cycling during the re-deposition stage, which can negatively impact device performance. Additionally, in some embodiments, because the barrier dielectric layer is positioned over the exposed region, implanted species may have to penetrate the barrier dielectric layer, potentially requiring higher energy isolation implantation.

[0019] In some instances, isolation implantation can be performed before patterning the p-GaN layer covering the barrier layer of the heterojunction structure. In such arrangements, photoresist is formed over the unpatterned p-GaN layer, which shields the underlying barrier layer, preventing it from contacting the photoresist. However, the lack of a patterned p-GaN layer can make photoresist lithography challenging, as the lithography stage for patterning the isolation-implanted photoresist may require patterned features on the wafer for alignment. To overcome this problem, a separate mask with alignment marks or references may be needed to facilitate pattern recognition and alignment, thereby forming the patterned photoresist. Therefore, while the barrier layer is protected from photoresist contamination, this can introduce additional process complexity and manufacturing costs in such instances.

[0020] This disclosure recognizes the aforementioned challenges and provides solutions to mitigate various issues associated with the isolation implantation process step in the GaN process flow, such as barrier layer contamination and passivation layer damage. In some arrangements, a dielectric layer is disposed over an unpatterned p-GaN layer covering the barrier layer. As described in more detail herein, at least a portion of the p-GaN layer remains over the barrier layer during subsequent isolation implantation process steps, thereby avoiding undesirable contact between the barrier layer and the photoresist. After the dielectric layer is formed, it can be patterned using a p-GaN photomask process to form a dielectric cap over the p-GaN layer in the gate region of the GaN device. In the examples herein, the dielectric cap may have a sufficiently vertical topography to facilitate alignment with a subsequent photoresist mask. The dielectric cap may also serve as a hard mask for patterning the p-GaN layer in a subsequent stage after the isolation implantation process step. Because the dielectric cap can be used for pattern recognition and alignment in subsequent photolithography steps, a separate mask with alignment marks is unnecessary, for example, to facilitate isolation implantation lithography. When the dielectric cap is formed over the p-GaN layer, the isolation implantation process can be performed with lower implantation energy because the dielectric layer has been removed from the isolation region. While the examples in this document provide various structures, materials, and processes that can produce these and other beneficial effects, specific results are not required unless explicitly described in a particular technical solution.

[0021] Refer to the diagram. Figures 1A to 1H Cross-sectional views of the semiconductor device 100 at various stages of the process flow are depicted. The semiconductor device 100 includes a GaN device 101 having an isolation region (which may be referred to as a device isolation region) according to an example of this disclosure.

[0022] Figure 1AAn intermediate stage of a semiconductor device 100 formed on a portion of a semiconductor substrate 102 is depicted. The semiconductor substrate may be provided as a silicon wafer, a silicon-on-sapphire wafer, or a silicon carbide wafer, and / or as a semiconductor substrate comprising a core configured to match the coefficient of thermal expansion (CTE), etc. A buffer layer 104 comprising one or more layers of III-N semiconductor material is formed on the substrate 102. In some instances where the substrate 102 is implemented as a silicon wafer or a sapphire wafer, the buffer layer 104 may comprise a nucleation layer having a stoichiometry of aluminum to match the lattice constant of the substrate 102. In some instances, the buffer layer 104 may further comprise an aluminum gallium nitride (AlGaN) layer / sublayer with reduced aluminum content, and in some arrangements, an unintentionally doped (UID) GaN sublayer is included. For the purposes of the examples herein, the individual layers / sublayers of the buffer layer (e.g., buffer layer 104) are not specifically shown in the figures of this disclosure.

[0023] Depending on the implementation, buffer layer 104 may have a thickness of about 1 micrometer (µm) to several micrometers (e.g., 3.5 µm to 7.0 µm), and the buffer layer may be formed by a suitable epitaxial process, such as metal-organic vapor phase epitaxy (MOVPE), utilizing several operations to form the individual layers and / or sublayers. In some arrangements, buffer layer 104 may comprise a stack of multiple layers / sublayers of suitable materials and compositions (e.g., GaN, AlGaN, etc.) as described above. In some arrangements, depending on the technology and device application, the layers / sublayers of buffer layer 104 may have variable thicknesses. In some arrangements, buffer layer 104 may include an AlGaN-based transition layer, an epitaxial layer with a strained layer superlattice (SLS) structure, etc.

[0024] Buffer layer 104 may be formed as part of an epitaxial III-N heterojunction structure (e.g., heterojunction structure 106) above substrate 102. Substrate 102 includes isolation regions laterally surrounding the device region. For the purposes of this disclosure, the term "device region" may also refer to a region of substrate 102 covered by patterned photoresist during isolation implantation. The device region may also be referred to as an active region. The device region may include different regions of GaN device 101, such as source region 105A, gate region 105B, drain region 105D, and drain access region 105C between gate region 105B and drain region 105D. Source region 105A may be considered to include a source access region (not specifically shown in the figure), which may refer to a source electrode (e.g., Figure 1H The region between the source electrode 122A and the gate region 105B shown is similar to the drain access region 105C, which will be described below.

[0025] For the purposes of this disclosure, an isolation region is a region or portion of a semiconductor substrate that is exposed during the isolation implantation stage and implanted with a suitable implantation species, such that the crystallinity of the heterojunction structure within the isolation region is damaged or destroyed. In some instances, the crystallinity of the heterojunction structure within the isolation region is sufficiently disturbed that the materials constituting the buffer and barrier layers in the exposed region may be in an amorphous or semi-amorphous state. According to the examples herein, the degree of amorphization or semi-amorphization of the buffer and barrier layers in the isolation region is sufficient to prevent the formation of conductive channels (e.g., 2DEG) within the isolation region. Furthermore, the implantation species may cause various structural and / or morphological changes in the isolation region, as will be further described below. Conversely, the active or device regions (or areas) of the semiconductor substrate are not exposed to the isolation implantation, for example, by being covered by photoresist disposed over the active or device regions. Therefore, the crystallinity of the heterojunction structure in the device region is preserved. In this way, the ability of the heterojunction structure in the device region to support the formation of conductive channels (e.g., 2DEG) is preserved.

[0026] A channel layer may be provided as part of buffer layer 104, for example, the top portion of buffer layer 104 near barrier layer 110. While the channel layer may primarily comprise GaN material, in some embodiments, optional trace amounts of other Group III elements, such as aluminum or indium, may be present. Barrier layer 110, comprising III-N semiconductor material and of suitable thickness, is formed over buffer layer 104. In example arrangements, barrier layer 110 may have a thickness ranging from about 1 nanometer (nm) to about 60 nm and may comprise aluminum and nitrogen. In some versions of this example, barrier layer 110 may comprise gallium with an atomic percentage less than aluminum. In some versions, barrier layer 110 may also comprise indium. In some examples, barrier layer 110 comprises an AlGaN layer.

[0027] The barrier layer 110 above the buffer layer 104 can be used as part of the heterojunction structure 106 to form a 2DEG (e.g.,) near the interface between the barrier layer 110 and the buffer layer 104. Figure 1E The 2DEG 108 shown is illustrated. In some instances, the stoichiometry and thickness of the barrier layer 110 can be configured to provide a suitable free charge carrier density for the 2DEG (e.g., 3 × 10⁻⁶). 12 cm -2 Up to 2×10 13 cm -2 ( ), to facilitate device operation.

[0028] For the purpose of realizing EMODE functionality, a p-doped III-N layer 114, comprising one or more layers of III-N material, is formed above the barrier layer 110, such as... Figure 1AAs shown. In some instances, the p-doped III-N layer 114 may also be referred to as a p-III-N layer or a p-GaN layer. In this example version, the p-doped III-N layer 114 may comprise a GaN layer doped with magnesium (Mg) or other suitable p-type dopant. In some instances, the p-doped GaN layer 114 may contain approximately 1 × 10⁻⁶ g⁻¹. 17 atoms / cm 3 Up to 1×10 21 atoms / cm 3 The p-doped concentration can be adjusted, and the thickness can range from about 10 nm to 200 nm. In some additional and / or alternative arrangements, an additional layer, such as an AlGaN capping layer (e.g., without p-doping; not shown in the figure), can be disposed above the p-GaN layer 114.

[0029] In subsequent processing stages, the p-GaN layer 114 can be patterned to form a p-GaN gate as part of a gate stack, including the gate electrode in gate region 105B. In the examples herein, prior to gate formation, the p-GaN layer 114 can also serve as a photoresist (PR) barrier layer to shield the barrier layer 110 from direct contact with the photoresist during the isolation implantation stage, as will be explained below. Furthermore, the p-GaN layer 114 can be patterned using a dielectric cap as a hard mask after the isolation implantation stage. In this way, the barrier layer 110 avoids contact with the photoresist during isolation implantation. Therefore, the barrier layer 110 advantageously does not contain organic photoresist material, which can cause barrier layer contamination in some process flows as described above.

[0030] Figure 1B The process of forming a dielectric layer 115 over an unpatterned p-GaN layer 114 to facilitate the formation of a dielectric cap is depicted. In some versions of this example, the dielectric layer 115 may comprise a SiN layer with a thickness of about 50 nm to about 200 nm. In example embodiments, the dielectric layer 115 may be formed using a suitable precursor (e.g., dichlorosilane (DCS) and ammonia (NH3)) via a high-temperature LPCVD process (e.g., at temperatures in the range of about 700°C to about 850°C). In some arrangements, the dielectric layer 115 may comprise different materials, such as silicon dioxide (SiO2), silicon oxynitride (SiON), aluminum oxide (Al2O3), aluminum nitride (AlN), etc., and may be formed using other techniques such as ALD. In some arrangements, the dielectric layer 115 may be referred to as a first dielectric layer or a sacrificial dielectric layer relative to other dielectric layers that may be formed in subsequent stages during manufacturing.

[0031] Figure 1CThe process described follows a sequence after the dielectric layer 115 is patterned using a mask (e.g., a p-GaN mask) and a combination of photolithography and etching processes (e.g., a SiN etching process) to form a dielectric cap 117 over the p-GaN layer 114 in the gate region 105B. Depending on the implementation, the dielectric layer 115 can be etched using dry etching, wet etching, or a combination thereof, thus providing ideal selectivity for III-N semiconductor materials. In example process flows, for example, SiN etching may also remove a portion (e.g., the top portion) of the p-GaN layer 114 due to over-etching, while simultaneously removing the dielectric layer 115 outside the gate region 105B.

[0032] Figure 1D An isolation implantation stage using photoresist 119 is depicted, the photoresist being patterned through suitable photolithographic steps configured to expose regions 123A, 123B. Although regions 123A, 123B are... Figure 1D The cross-sectional view shows two separate regions, but regions 123A and 123B laterally surround device region 155 relative to GaN device 101. As depicted, device region 155 surrounded by regions 123A and 123B includes source region 105A, drain region 105D, gate region 105B, and drain access region 105C disposed between gate region 105B and drain region 105D. In one example, the isolation process step may include implanting a suitable implantation species (e.g., implantation species 121) into semiconductor device 100. Implantation species 121 may have sufficient energy to damage the crystallinity of heterojunction structure 106 in regions 123A and 123B. Regions 123A and 123B may also be referred to as isolation regions 123A and 123B. In some arrangements, energies between 100 keV and 300 keV and implantation doses of 1 × 10⁻⁶ may be implemented. 14 ions / cm 2 Up to 1×10 16 ions / cm 2 Isolation injection is used to achieve device isolation. In some embodiments, the injected species may include argon, silicon, fluorine, nitrogen, etc. Other injected species and injection energies are within the range of the examples herein.

[0033] According to the examples in this paper, the implantation of species 121 may randomize the distances between the constituent atoms (e.g., Ga, N, and Al) of the barrier layer 110 and buffer layer 104 in regions 123A and 123B. In some arrangements, the distances between constituent atoms corresponding to their respective lattice constants may be disturbed in a random manner due to the perturbation caused by bombarding the implanted species 121. Therefore, the barrier layer material and buffer layer material in isolation regions 123A and 123B may include substances in a disordered state, resulting in no clear boundary between the layer boundaries. As a result, the interface between the barrier layer 110 and buffer layer 104 in isolation regions 123A and 123B may become hazy, blurred, etc., due to the mixing of constituent atoms during the implantation step. In some arrangements, this mixing of the constituent atoms of the buffer layer material and the barrier layer material may produce wavy surfaces within isolation regions 123A and 123B.

[0034] Furthermore, the mixing of constituent atoms of the buffer layer material and barrier layer material in isolation regions 123A and 123B can produce amorphous or semi-amorphous materials therein. In some arrangements, the amorphous or semi-amorphous materials in isolation regions 123A and 123B may contain isolation-implanted species. In some arrangements, the amorphous or semi-amorphous materials may lead to increased resistance because they suppress (or reduce) the formation of 2DEGs in isolation regions 123A and 123B, as previously described. Therefore, according to the examples herein, isolation regions 123A and 123B surrounding device region 155 of GaN device 101 can be considered as not containing 2DEGs (or free charge carriers, such as electrons and / or holes). For the purposes of this disclosure, the terms "amorphous" and "amorphized" may include material states that can be considered "semi-amorphous" or "semi-amorphous," and are not necessarily limited to any particular degree of crystallization damage in isolation regions 123A and 123B.

[0035] like Figure 1DAs shown, the barrier layer 110 in device region 155 is protected by the overlying p-GaN layer 114 during the implantation phase, whereby the p-GaN layer 114 serves as a barrier shield between the barrier layer 110 and the patterned photoresist 119. This avoids direct contact between the barrier layer 110 and the patterned photoresist 119. In this way, a contamination-free surface 111 of the barrier layer 110 is obtained, which advantageously reduces or eliminates adverse consequences such as electron trapping during device operation. Because the dielectric cap 117 has a sufficiently vertical topography (e.g., a step height 127 along the Z-axis) relative to the remaining p-GaN layer 114, it can be used for pattern recognition and alignment during the formation of the patterned photoresist 119, thus eliminating the need for a separate mask with alignment marks to facilitate isolated implantation lithography. Therefore, in the examples herein, the patterned photoresist 119 can be aligned based on the dielectric cap 117 to define isolation regions 123A, 123B.

[0036] Following the isolation implantation stage, the patterned photoresist 119 can be removed by a removal process (e.g., a plasma process using oxygen radicals and ions, such as an ashing process), followed by a suitable wet cleaning process. Thereafter, the p-GaN layer 114 can be patterned using a dielectric cap 117 as a hard mask in conjunction with a suitable p-GaN etching process to form... Figure 1E The p-GaN gate 113 is shown. As previously described, the p-GaN gate 113 may be formed as part of the gate stack 112, including the gate electrode to be formed subsequently (e.g., Figure 1H (Gate electrode 122C in the middle). As a result of patterning the p-GaN layer 114 (e.g., removing the portion of the p-GaN layer 114 outside the gate region 105B), a 2DEG 108 can be formed outside the gate region 105B, such as Figure 1E As shown. Furthermore, 2DEG 108 is kept reduced in the gate region 105B, for example, it is absent in some cases, to achieve the normally off mode.

[0037] In some versions of the examples herein, the p-GaN gate 113 may be asymmetrically positioned in device region 155 relative to source region 105A (where the source electrode or contact is to be formed) and drain region 105D (where the drain electrode or contact is to be formed), but this is not necessary. For example, the lateral distance between gate region 105B and drain region 105D may be greater than the lateral distance between gate region 105B and source region 105A by means of a access region (e.g., drain access region 105C) disposed between gate region 105B and drain region 105D. In some additional and / or alternative arrangements, the source access region may also be disposed similarly between source region 105A and gate region 105B, while still having source / drain region asymmetry relative to gate region 105B.

[0038] Figure 1F The stages following the removal of the dielectric cap 117 using a suitable removal process are depicted. In the case where the dielectric cap 117 comprises SiN, an example removal process could be SiN wet etching, which involves maintaining a solution of 85% phosphoric acid (H3PO4) and 15% deionized water at a high temperature (e.g., about 150°C to 180°C). In another example, diluted hydrogen fluoride (HF) can be used to remove the dielectric cap 117 in a SiN wet etching process.

[0039] After removing the dielectric cap 117, one or more dielectric layers 116 (individually designated as dielectric layers 116A, 116B) that can be used as passivation layers can be formed over the p-GaN gate 113 and the barrier layer 110, such as... Figure 1G As shown. Because this type of passivation layer is in Figure 1D Formed after the isolation implantation stage, it does not contain isolation implanted species. Passivation layer 116 extends across the boundary between device region 155 and isolation regions 123A, 123B. At least a portion of passivation layer 116 (e.g., passivation layer 116A) directly contacts (e.g., touches) barrier layer 110. In some versions of this example, the dielectric layer that can be used as a passivation layer may be referred to as a second dielectric layer, a third dielectric layer, etc., relative to a first dielectric layer 115 configured to provide a dielectric cap (e.g., dielectric cap 117), as described above. In some instances, the surface passivation layer may comprise one or more LPCVD SiN layers with a thickness of about 10 nm to about 100 nm. In example embodiments, the passivation layer may be configured to provide desired electrical characteristics of GaN device 101, such as dynamic on-state resistance (R0). DSON Time-dependent dielectric breakdown (TDDB), etc. In some arrangements, the passivation layer may comprise different materials, such as SiO2, SiON, Al2O3, AlN, etc., and may be formed using other techniques such as ALD. Additional details regarding the formation of dielectric layers (which may serve as passivation layers in some instances) using LPCVD processes can be found in U.S. Patent Application Publication No. 2023 / 0094094, which is incorporated herein by reference in its entirety for all purposes.

[0040] Figure 1H A more complete depiction of the semiconductor device 100, including the GaN device 101, is shown, illustrating representative passivation layers 116A and 116B. As depicted, the first passivation layer 116A is disposed directly on a barrier layer 110 having a contaminant-free surface 111. The second passivation layer 116B is disposed over the first passivation layer 116A. Figure 1HIn the example shown, passivation layers 116A and 116B span device region 155 and extend over isolation regions 123A and 123B. As previously stated, passivation layers 116A and 116B do not contain isolated injected species.

[0041] Furthermore, the GaN device 101 includes source electrodes, drain electrodes, and gate electrodes 122A to 122C formed respectively in a first gate process (e.g., where the source / drain electrodes are formed after the gate stack is formed). Alternatively, the GaN device 101 may include source electrodes, drain electrodes, and gate electrodes 122A to 122C formed respectively in a final gate process (e.g., where the source / drain electrodes are formed before the gate stack is formed). The GaN device 101 also includes a source terminal 142A formed through an insulator 150, a gate terminal ( Figure 1H (not shown) and drain terminal 142B, the insulator comprising, for example, interlayer dielectric (ILD) and / or metal front dielectric (PMD) materials for facilitating electrical contact with source electrode 122A, drain electrode 122B and gate electrode 122C respectively.

[0042] Figure 2A and 2B This is a flowchart of a method for manufacturing a semiconductor device according to some examples of this disclosure. Figure 2A The method 200A shown may begin by forming a III-N heterojunction structure over a semiconductor substrate. The III-N heterojunction structure may include a buffer layer over the semiconductor substrate and a barrier layer over the buffer layer, as illustrated in box 202. At least some aspects of box 202 may relate to those described above. Figure 1A The manufacturing stages are shown. At box 204, a p-GaN layer can be formed over the III-N heterojunction structure, which may involve... Figure 1A Some aspects described above. At block 206, a dielectric cap may be formed over the p-GaN layer in the gate region of the semiconductor substrate, which may relate to the aspects described above. Figure 1B and 1C Some aspects of the manufacturing process are shown.

[0043] At box 208, a patterned photoresist (PR) layer may be formed over the dielectric cap and the p-GaN layer. The patterned photoresist layer exposes an isolation region of the semiconductor substrate, wherein the isolation region laterally surrounds a device region of the semiconductor substrate. As previously described, the device region may include a gate region, a source region, and a drain region. In some arrangements, the process illustrated at box 208 may involve the procedures described above. Figure 1D In terms of [specific aspects], at box 210, one or more isolation implantation species may be implanted into the isolation region surrounding the device region. As previously described, the implanted species may amorphize at least a portion of the III-N heterojunction material in the isolation region. At least some aspects of box 210 may relate to [specific aspects]. Figure 1D The isolation injection phase is shown.

[0044] At frame 212, the patterned photoresist layer can be removed, which may involve the process described above. Figure 1E Some aspects associated with the manufacturing stages shown. Subsequently, the p-GaN layer can be patterned, for example, using a dielectric cap as a hard mask, to remove the p-GaN layer outside the dielectric cap. Thus, as illustrated in block 214, a p-GaN gate is formed in the gate region above the barrier layer. At least some aspects of block 214 relate to... Figure 1E The manufacturing stage. After forming the p-GaN gate, the dielectric cap can be removed (box 216). Furthermore, in some arrangements, one or more dielectric layers that can serve as surface passivation layers can be formed over the p-GaN gate and the barrier layer. As previously mentioned, the one or more surface passivation layers may not contain isolation implantation species. Subsequently, a source electrode can be formed in the source region, a drain electrode in the drain region, and a gate electrode over the p-GaN gate using a suitable process flow (e.g., depending on the embodiment, using a gate first flow or a gate last flow) (box 218). At least some aspects of boxes 216 and 218 may relate to those described above. Figures 1F to 1H The manufacturing stages are shown.

[0045] Figure 2B The method 200B shown may begin by forming a buffer layer over a semiconductor substrate, as illustrated in box 220, which may involve Figure 1A Some aspects of the manufacturing stage are shown. At box 222, a barrier layer is formed over the buffer layer. According to the example herein, direct contact between the barrier layer and the isolation implantation photoresist is avoided during isolation implantation. The isolation implantation photoresist may be patterned to expose isolation regions of the semiconductor substrate, wherein the isolation regions laterally surround device regions of the semiconductor substrate. As previously described, the device regions may include gate regions, source regions, and drain regions. At least some aspects of box 222 may relate to Figures 1A to 1D The manufacturing stages are shown. At block 224, the source electrode can be formed in the source region, the drain electrode in the drain region, and the gate electrode above the p-GaN gate, similar to the process described in block 218 above.

[0046] While various examples of this disclosure have been described above, these examples are presented by way of illustration only and not as a limitation. Numerous changes may be made to the disclosed examples in accordance with the disclosure herein without departing from the spirit or scope of this disclosure. Therefore, the breadth and scope of this disclosure should not be limited to any of the examples described above. In fact, the scope of this disclosure should be defined by the appended claims and their equivalents.

[0047] For example, in this disclosure and the appended claims, unless otherwise stated and / or specified to the contrary, any one or more layers set forth herein may be formed in any number of suitable manners, such as using spin coating, sputtering (e.g., magnetron and / or ion beam sputtering), (thermal) growth techniques, or deposition techniques such as chemical vapor deposition (CVD), physical vapor deposition (PVD), PECVD, or atomic layer deposition (ALD). As another example, silicon nitride may be silicon-rich silicon nitride or oxygen-rich silicon nitride. Silicon nitride may contain some oxygen, but not so much that the dielectric constant of the material is significantly different from that of high-purity silicon nitride.

[0048] Furthermore, in at least some additional or alternative embodiments, the functions / actions described in the boxes may not occur in the order shown in the flowchart. For example, depending on the functionality / action involved, two boxes shown consecutively may actually be performed substantially simultaneously, or the boxes may sometimes be performed in reverse order. Additionally, the functionality of a given box in a flowchart and / or block diagram may be divided into multiple boxes, and / or the functionality of two or more boxes in a flowchart and / or block diagram may be at least partially integrated. Also, some boxes in the flowchart may optionally be omitted. Furthermore, although some diagrams include arrows on communication paths to indicate the main direction of communication, it should be understood that communication may occur in the direction opposite to the depicted arrows. Finally, additional boxes may be added / inserted between the shown boxes.

[0049] The order or sequence of actions, steps, functions, components, or blocks shown in any of the flowcharts and / or block diagrams depicted in the accompanying drawings of this disclosure may be modified, altered, replaced, customized, or otherwise rearranged within a particular flowchart or block diagram, including the deletion or omission of specific actions, steps, functions, components, or blocks. Furthermore, actions, steps, functions, components, or blocks shown in a particular flowchart may be mixed with or otherwise arranged or rearranged with actions, steps, functions, components, or blocks shown in another flowchart to achieve additional changes, modifications, and configurations relative to one or more processes for the purpose of practicing the teachings of this disclosure. Similarly, although various examples have been illustrated herein, not all features of a particular example are necessarily limited to and / or necessary for this purpose.

[0050] At least some of the foregoing description may contain specific directional terms, such as “upper,” “lower,” “top,” “bottom,” “left,” “right,” “front,” “rear,” “vertical,” “horizontal,” etc., which may be used with reference to the orientation of some of the described figures or their illustrative elements. Since components in some instances may be positioned in several different orientations, the directional terms are used for illustrative purposes and are by no means limiting. Similarly, references to features referred to as “first,” “second,” etc., do not indicate any particular order, importance, etc., and such references are interchangeable depending on the context, embodiment, etc. Furthermore, terms such as “above,” “below,” “under,” etc., relative to the spatial orientation of two components do not necessarily mean that one component is adjacent to or directly above another component, or that one component is adjacent to or directly below another component. Moreover, unless otherwise specifically indicated, features and / or components of the instances described herein may be combined with each other.

[0051] Although various embodiments have been shown and described in detail, the claims are not limited to any particular embodiment or instance. The above specific embodiments should not be construed as implying that any particular component, element, step, action, or function is essential and must be included within the scope of the claims. Where phrases such as "at least one of A and B" or similar phrases are used, such phrases should be understood to mean "only A, only B, or both A and B." Unless explicitly stated otherwise, references to singular elements are not intended to mean "one and only one," but rather "one or more." Similarly, depending on the context, phrases such as "a plurality" or "multiple" may mean "one or more" or "at least one." All structural and functional equivalents of the elements of the embodiments described above are expressly incorporated herein by reference and are intended to be covered by the appended claims.

Claims

1. A method comprising: A III-N heterojunction structure is formed above a semiconductor substrate, the III-N heterojunction structure comprising a buffer layer above the semiconductor substrate and a barrier layer above the buffer layer; A p-GaN layer is formed above the III-N heterojunction structure; A dielectric cap is formed above the p-GaN layer, and the dielectric cap covers the p-GaN layer in the gate region of the semiconductor substrate; A patterned photoresist layer is formed over the dielectric cap and the p-GaN layer, the patterned photoresist layer exposing an isolation region of the semiconductor substrate, wherein the isolation region laterally surrounds a device region of the semiconductor substrate, the device region including the gate region, source region and drain region; Inject the isolated species into the isolation zone; Remove the patterned photoresist layer; Remove the p-GaN layer outside the dielectric cap to form a p-GaN gate in the gate region above the barrier layer; Remove the dielectric cap; as well as A source electrode is formed in the source region, a drain electrode is formed in the drain region, and a gate electrode is formed above the p-GaN gate.

2. The method according to claim 1, further comprising: A dielectric layer is formed above the p-GaN layer; as well as The dielectric layer is patterned to form the dielectric cap.

3. The method of claim 2, wherein the patterning of the dielectric layer comprises removing a portion of the p-GaN layer.

4. The method of claim 1, wherein the dielectric cap comprises low-pressure chemical vapor deposition (LPCVD) silicon nitride (SiN).

5. The method of claim 1, wherein the dielectric cap has a thickness in the range of about 50 nanometers to about 200 nm.

6. The method of claim 1, wherein the patterned photoresist layer is aligned based on the dielectric cap.

7. The method of claim 1, wherein the isolated injected species comprises at least one of argon, silicon, fluorine, and nitrogen.

8. The method of claim 1, further comprising: After removing the dielectric cap, one or more surface passivation layers are formed over the barrier layer and the p-GaN gate.

9. The method of claim 8, wherein the one or more surface passivation layers do not contain isolated injected species.

10. The method of claim 8, wherein the one or more surface passivation layers comprise at least one of a SiN layer, a SiO2 layer, a SiON layer, an Al2O3 layer, an AlN layer, or a combination thereof.

11. A semiconductor device comprising: A semiconductor substrate comprising an isolation region laterally surrounding a device region, the device region comprising a gate region, a source region, and a drain region; A III-N heterojunction structure is located above the semiconductor substrate, and the III-N heterojunction structure includes a buffer layer above the semiconductor substrate and a barrier layer above the buffer layer; p-doped III-N gate, which is located in the gate region and above the barrier layer; as well as A passivation layer is disposed above the barrier layer and the p-doped III-N gate, the passivation layer extending across the device region and the isolation region, wherein the passivation layer does not contain isolation implanted species.

12. The semiconductor device of claim 11, wherein the barrier layer extends over the device region and the isolation region, and the barrier layer does not contain photoresist contaminants.

13. The semiconductor device of claim 12, wherein the photoresist contaminant comprises a carbon-based compound.

14. The semiconductor device of claim 11, wherein the barrier layer is an AlGaN layer.

15. The semiconductor device of claim 11, wherein the passivation layer is directly on the barrier layer.

16. The semiconductor device of claim 11, wherein the passivation layer is at least one of a SiN layer, a SiO2 layer, a SiON layer, an Al2O3 layer, an AlN layer, or a combination thereof.

17. The semiconductor device of claim 11, wherein the isolation implantation species comprises at least one of argon, silicon, fluorine, and nitrogen.

18. The semiconductor device of claim 11, wherein the isolation region comprises a portion of the III-N heterojunction structure containing isolation implanted species.

19. The semiconductor device of claim 11, wherein the isolation region does not have a 2DEG channel.

20. The semiconductor device of claim 11, wherein the isolation region comprises the amorphous portion of the III-N heterojunction structure.

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