A gallium oxide insulated gate bipolar transistor power device
By introducing P-type nickel oxide or copper oxide regions into gallium oxide IGBT devices to form a heterojunction structure with N-type gallium oxide, the p-type doping problem of gallium oxide IGBT devices is solved, achieving high current density and low on-state voltage drop, and improving the device's withstand voltage performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- UNIV OF ELECTRONICS SCI & TECH OF CHINA
- Filing Date
- 2022-10-11
- Publication Date
- 2026-05-26
Smart Images
Figure CN115548109B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of semiconductor technology, specifically providing gallium oxide (Ga2O3) insulated gate bipolar transistor power devices, including vertical devices and horizontal devices. Background Technology
[0002] Gallium oxide (GaO), as a fourth-generation semiconductor material, boasts an ultrawide bandgap (~4.8 eV) larger than that of silicon carbide (SiC), a third-generation semiconductor (~3.3 eV). This allows it to exhibit more stable performance under harsher operating environments, such as high voltage and irradiation. Furthermore, GaO's theoretical critical breakdown electric field is ~8 MV / cm, significantly higher than SiC's ~3 MV / cm. Therefore, GaO can be used at ultra-high voltages. For devices with the same voltage rating, GaO devices exhibit much lower on-resistance than SiC devices, greatly reducing power consumption. Additionally, due to GaO's unique photoelectric effect, GaO devices are also used in blue light and ultraviolet light devices. Consequently, GaO devices have attracted significant attention from researchers.
[0003] Insulated gate bipolar transistors (IGBTs) have many advantages such as easy driving, low on-state voltage, and high current density, and are widely used in silicon-based power devices. However, as of now, there is still a significant challenge in fabricating IGBT devices because there is no effective p-type doping in gallium oxide. Summary of the Invention
[0004] The purpose of this invention is to fill the gap in the field of gallium oxide power devices by providing a gallium oxide insulated gate bipolar transistor (IGBT) power device. Based on the principle of heterojunction, this invention proposes the concept of gallium oxide IGBT for the first time, providing a new approach for the research of gallium oxide high voltage and high current power devices.
[0005] To achieve the above objectives, the technical solution adopted by the present invention is as follows:
[0006] A vertical gallium oxide insulated gate bipolar transistor power device includes:
[0007] An N-type gallium oxide drift region 1-1, an N-type gallium oxide buffer layer 1-8 disposed under the N-type gallium oxide drift region 1-1, a heavily doped P-type nickel oxide substrate 1-9 disposed under the N-type gallium oxide buffer layer, and a metallized collector electrode 1-10 disposed under the heavily doped P-type nickel oxide substrate; the heavily doped P-type nickel oxide substrate 1-9 forms a heterojunction structure with the N-type gallium oxide buffer layer 1-8 and forms an ohmic contact with the metallized collector electrode 1-10;
[0008] Two symmetrical grooves are formed on the surface of the N-type gallium oxide drift region 1-1, located on both sides. The groove walls are provided with an oxide layer 1-5, and the grooves are filled with heavily doped P-type nickel oxide regions 1-2. A metallized gate 1-7 is provided on the heavily doped P-type nickel oxide regions. Two heavily doped N-type gallium oxide regions 1-3 are symmetrically arranged in the N-type gallium oxide drift region between the two grooves and are adjacent to the grooves. A heavily doped P-type nickel oxide region 1-4 is also provided on the N-type gallium oxide drift region 1-1 and is located between the two heavily doped N-type gallium oxide regions. A metallized emitter 1-6 is provided on the two heavily doped N-type gallium oxide regions 1-3 and the heavily doped P-type nickel oxide region 1-4, forming an ohmic contact. The heavily doped P-type nickel oxide region 1-4 and the N-type gallium oxide drift region 1-1 form a heterojunction structure.
[0009] Furthermore, the heavily doped P-type nickel oxide substrates 1-9 are replaced with copper oxide substrates, and the copper oxide substrates and N-type gallium oxide buffer layers form a heterojunction structure.
[0010] Furthermore, the heavily doped P-type nickel oxide regions 1-2 are replaced with diamond regions or metal regions, and metallized gates 1-7 are disposed on the diamond regions or metal regions.
[0011] Furthermore, the heavily doped P-type nickel oxide regions 1-4 are replaced with copper oxide regions, and the copper oxide regions and the N-type gallium oxide drift regions 1-1 form a heterojunction structure.
[0012] A lateral gallium oxide insulated gate bipolar transistor power device includes:
[0013] N-type gallium oxide drift region 2-1, unintentionally doped or undoped buffer layer 2-9 disposed under N-type gallium oxide drift region 1-1, and semi-insulating or high-purity gallium oxide substrate 2-10 disposed under unintentionally doped or undoped buffer layer;
[0014] A trench gate is formed on the surface of the N-type gallium oxide drift region 2-1. The trench gate consists of an oxide layer 2-5 located on the trench wall and a polysilicon gate 2-6 filled in the trench. A first heavily doped p-type nickel oxide region 2-2 and a second heavily doped p-type nickel oxide region 2-3 are formed on the N-type gallium oxide drift region 2-1 and are located on both sides of the trench gate. A heavily doped N-type gallium oxide region 2-4 is formed in the N-type gallium oxide drift region 2-1. The heavily doped N-type gallium oxide region is located between the second heavily doped p-type nickel oxide region 2-3 and the trench gate and is adjacent to the trench gate. A metallized collector 2-7 is formed on the first heavily doped p-type nickel oxide region 2-2 and forms an ohmic contact. A metallized emitter 2-8 is formed on the second heavily doped p-type nickel oxide region 2-3 and the heavily doped N-type gallium oxide region 2-4 and forms an ohmic contact. The first heavily doped p-type nickel oxide region 2-2 and the second heavily doped p-type nickel oxide region 2-3 form a heterojunction structure with the N-type gallium oxide drift region 2-1.
[0015] Furthermore, the first heavily doped P-type nickel oxide region 2-2 and the second heavily doped P-type nickel oxide region 2-3 are both replaced with copper oxide regions, and the copper oxide regions and the N-type gallium oxide drift regions form a heterojunction structure.
[0016] Furthermore, a P-type nickel oxide region 2-11 is also provided on the N-type gallium oxide drift region 2-1, and is located between the trench gate and the first heavily doped P-type nickel oxide region 2-2. An oxide layer is provided between the P-type nickel oxide region 2-11 and the N-type gallium oxide drift region 2-1, the first heavily doped P-type nickel oxide region 2-2 and the metallized collector 2-7 thereon.
[0017] Furthermore, the P-type nickel oxide regions 2-11 are replaced with diamond regions.
[0018] Based on the above technical solution, the beneficial effects of the present invention are as follows:
[0019] This invention provides a gallium oxide insulated gate bipolar transistor (IGBT) power device, comprising a vertical device and a horizontal device. Specifically, it uses nickel oxide (NiO), copper oxide (Cu2O), or diamond as the P-type region. The introduced P-type nickel oxide or P-type copper oxide forms a heterojunction structure with the N-type gallium oxide. During normal operation, the heterojunction on the high-potential side is forward biased and turned on. At this time, a large number of holes are injected into the N-type gallium oxide drift region, thereby introducing a conductivity modulation effect in the drift region to obtain high current density and low on-state voltage drop, thus realizing the basic working principle of the IGBT device. Based on this, the concept of gallium oxide IGBT is proposed. At the same time, in the horizontal IGBT, the introduction of P-type nickel oxide or P-type diamond with the N-type gallium oxide to form a superjunction structure in the drift region can achieve a higher withstand voltage with the same drift region length, further improving the performance of the device. Attached Figure Description
[0020] Figure 1 This is a schematic diagram of the vertical gallium oxide insulated gate bipolar transistor device in Example 1.
[0021] Figure 2 This is a schematic diagram of the structure of the lateral gallium oxide insulated gate bipolar transistor device in Example 2.
[0022] Figure 3 This is a schematic diagram of the structure of the lateral superjunction gallium oxide insulated gate bipolar transistor device in Example 3. Detailed Implementation
[0023] To make the objectives, technical solutions, and beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments.
[0024] Example 1
[0025] This embodiment provides a vertical gallium oxide insulated gate bipolar transistor device, the structure of which is as follows: Figure 1 As shown, it specifically includes:
[0026] An N-type gallium oxide drift region 1-1, an N-type gallium oxide buffer layer 1-8 disposed under the N-type gallium oxide drift region 1-1, a heavily doped P-type nickel oxide substrate 1-9 disposed under the N-type gallium oxide buffer layer, and a metallized collector 1-10 disposed under the heavily doped P-type nickel oxide substrate; the heavily doped P-type nickel oxide substrate 1-9 forms a heterojunction structure with the N-type gallium oxide buffer layer 1-8 and forms an ohmic contact with the metallized collector 1-10;
[0027] Two symmetrical grooves are formed on the surface of the N-type gallium oxide drift region 1-1, located on both sides. The groove walls are provided with an oxide layer 1-5, and the grooves are filled with heavily doped P-type nickel oxide regions 1-2. A metallized gate (G) 1-7 is provided on the heavily doped P-type nickel oxide regions. Two heavily doped N-type gallium oxide regions 1-3 are symmetrically arranged in the N-type gallium oxide drift region between the two grooves and are adjacent to the grooves. A heavily doped P-type nickel oxide region 1-4 is also provided on the N-type gallium oxide drift region 1-1 and is located between the two heavily doped N-type gallium oxide regions. A metallized emitter 1-6 is provided on the two heavily doped N-type gallium oxide regions 1-3 and the heavily doped P-type nickel oxide region 1-4, and an ohmic contact is formed. The heavily doped P-type nickel oxide region 1-4 and the N-type gallium oxide drift region 1-1 form a heterojunction structure.
[0028] Furthermore, the heavily doped P-type nickel oxide substrate 1-9 can be replaced with a copper oxide substrate, and the copper oxide substrate and the N-type gallium oxide buffer layer form a heterojunction structure; the heavily doped P-type nickel oxide region 1-2 can be replaced with a diamond region or a metal region, and a metallized gate (G) 1-7 is disposed on the diamond region or the metal region; the heavily doped P-type nickel oxide region 1-4 can be replaced with a copper oxide region, and the copper oxide region and the N-type gallium oxide drift region 1-1 form a heterojunction structure.
[0029] The working principle of this embodiment is as follows:
[0030] When the potential applied to the polysilicon gate (G) 1-7 relative to the emitter (emitter) 1-8 is less than the device threshold voltage, the channel is turned off. The N-type gallium oxide drift region 1-1 between the two heavily doped P-type nickel oxide 1-2 (diamond or metal regions) is depleted and bears the breakdown voltage, and the device is in a blocking state. When the potential applied to the polysilicon gate (G) 1-7 relative to the emitter (emitter) 1-8 is higher than the device threshold voltage, the channel is turned on. At this time, if the metallized collector (collector) 1-10 is connected to a high potential relative to the metallized emitter (emitter) 1-8, the device is forward-biased, and electrons flow from the emitter (emitter)... The current flows through the N-type gallium oxide drift region 1-1 and the channel region 1-8, causing the PNP transistor composed of the heavily doped P-type nickel oxide or copper oxide region 1-4, the N-type gallium oxide drift region 1-1, the buffer layer 1-8, and the heavily doped P-type nickel oxide or copper oxide 1-9 to obtain base current and turn on. At this time, the heterojunction composed of the heavily doped P-type nickel oxide or copper oxide 1-9 and the N-type gallium oxide buffer layer 1-8 is turned on, and a large number of holes flow from the heavily doped P-type nickel oxide or copper oxide 1-9 into the N-type gallium oxide drift region 1-1. The hole and electron concentrations in the drift region are much greater than the N-type doping concentration in the drift region, that is, a conductivity modulation effect is formed in the drift region, thereby giving the device a large current density.
[0031] Example 2
[0032] This embodiment provides a lateral gallium oxide insulated-gate bipolar transistor device, the structure of which is as follows: Figure 2 As shown, it specifically includes:
[0033] N-type gallium oxide drift region 2-1, unintentionally doped or undoped buffer layer 2-9 disposed under N-type gallium oxide drift region 2-1, and semi-insulating or high-purity gallium oxide substrate 2-10 disposed under unintentionally doped or undoped buffer layer;
[0034] A trench gate is formed on the surface of the N-type gallium oxide drift region 2-1. The trench gate consists of an oxide layer 2-5 located on the trench wall and a polysilicon gate (G) 2-6 filled in the trench. A first heavily doped p-type nickel oxide region 2-2 and a second heavily doped p-type nickel oxide region 2-3 are formed on the N-type gallium oxide drift region 2-1 and are located on both sides of the trench gate. A heavily doped N-type gallium oxide region 2-4 is formed in the N-type gallium oxide drift region 2-1. The heavily doped N-type gallium oxide region is located between the second heavily doped p-type nickel oxide region 2-3 and the trench gate. The first heavily doped P-type nickel oxide region 2-2 is provided with a metallized collector 2-7 and forms an ohmic contact. The second heavily doped P-type nickel oxide region 2-3 and the heavily doped N-type gallium oxide region 2-4 are jointly provided with a metallized emitter 2-8 and form an ohmic contact. The first heavily doped P-type nickel oxide region 2-2 and the second heavily doped P-type nickel oxide region 2-3 form a heterojunction structure with the N-type gallium oxide drift region 2-1, respectively.
[0035] Furthermore, the first heavily doped P-type nickel oxide region 2-2 and the second heavily doped P-type nickel oxide region 2-3 can both be replaced with copper oxide regions, and the copper oxide regions and the N-type gallium oxide drift region 2-1 form a heterojunction structure.
[0036] The working principle of this embodiment is as follows:
[0037] During forward conduction, the polysilicon gate (G) 2-6 is applied with a potential greater than the emitter 2-8 relative to the device threshold voltage, and the channel is turned on. If the metallized collector 2-7 is connected to a high potential relative to the metallized emitter 2-8, electrons are emitted from the emitter 2-8 and flow through the channel region below the gate and the N-type gallium oxide drift region 2-1. This turns on the PNP transistor composed of the first heavily doped P-type nickel oxide region 2-2, the N-type gallium oxide drift region 2-1, and the second heavily doped P-type nickel oxide or copper oxide region 2-3. At this time, the heavily doped P-type nickel oxide (or copper oxide) region 2-2 and the N-type gallium oxide drift region 2-3... When the heterojunction composed of 1 is turned on, a large number of holes flow from the heavily doped P-type nickel oxide (or copper oxide) region 2-2 into the N-type gallium oxide drift region 2-1. The hole and electron concentrations in the drift region are much greater than the N-type doping concentration in the drift region, that is, a conductivity modulation effect is formed in the drift region, resulting in a large current density in the device. In the device blocking state, the potential applied to the polysilicon gate (G) 2-6 relative to the emitter 2-8 is less than the threshold voltage of the device, while the metallized collector 2-7 is connected to a high potential relative to the metallized emitter 2-8. At this time, the channel region below the gate and the N-type gallium oxide drift region 2-1 are depleted and withstand the breakdown voltage.
[0038] Example 3
[0039] This embodiment provides a lateral superjunction gallium oxide insulated gate bipolar transistor device, the structure of which is as follows: Figure 3 As shown, the difference between this and Example 2 is that: a P-type nickel oxide region 2-11 is also provided on the N-type gallium oxide drift region 2-1, and is located between the trench gate and the first heavily doped P-type nickel oxide region 2-2. An oxide layer is provided between the P-type nickel oxide region 2-11 and the N-type gallium oxide drift region 2-1, the first heavily doped P-type nickel oxide region 2-2 and the metallized collector 2-7 thereon.
[0040] Furthermore, the P-type nickel oxide region 2-11 can be replaced with a diamond region.
[0041] The working principle of this embodiment is as follows:
[0042] During forward conduction, the polysilicon gate (G) 2-6 is applied with a potential greater than the emitter 2-9 relative to the device threshold voltage, and the channel is turned on. If the metallized collector 2-8 is connected to a high potential relative to the metallized emitter 2-9, electrons flow from the emitter 2-8 through the channel region below the gate and the N-type gallium oxide drift region 2-1, causing the PNP transistor composed of the first heavily doped P-type nickel oxide region 2-2, the N-type gallium oxide drift region 2-1, and the second heavily doped P-type nickel oxide or copper oxide region 2-3 to turn on. At this time, the heterojunction formed by the heavily doped P-type nickel oxide (or copper oxide) region 2-2 and the N-type gallium oxide drift region 2-1 is turned on, and a large number of holes flow from the heavily doped P-type nickel oxide (or copper oxide) region 2-2 into the N-type gallium oxide drift region 2-1. The hole and electron concentrations in the drift region are much greater than those in the N-type gallium oxide drift region. The concentration of type doping creates a conductivity modulation effect in the drift region, resulting in a large current density in the device. In the blocking state, the potential applied to the polysilicon gate (G) 2-6 relative to the emitter 2-9 is less than the threshold voltage. The resulting depletion region pinches off the electron conduction channel of the N-type gallium oxide channel region below the gate, causing the device to turn off. At the same time, since the oxide layer 2-5 is very thin, the N-type gallium oxide drift region 2-1 and the P-type nickel oxide (or diamond) region 2-11 deplete each other. The electric field lines emitted by the ionized donor impurities in the depletion region of the N-type gallium oxide drift region 2-1 all terminate on the ionized acceptors of the P-type nickel oxide (or diamond) region 2-11. Macroscopically, the channel region can be regarded as an intrinsic semiconductor region. This improves the breakdown voltage of the lateral field-effect power transistor under the same drift region length and a higher channel region doping concentration, while reducing the specific on-resistance and improving the device performance.
[0043] The above description is merely a specific embodiment of the present invention. Any feature disclosed in this specification may be replaced by other equivalent or similar features unless otherwise specified. All disclosed features, or steps in all methods or processes, may be combined in any way except for mutually exclusive features and / or steps.
Claims
1. A vertical gallium oxide insulated-gate bipolar transistor power device, characterized in that, include: An N-type gallium oxide drift region (1-1), an N-type gallium oxide buffer layer (1-8) disposed under the N-type gallium oxide drift region, a heavily doped P-type nickel oxide substrate (1-9) disposed under the N-type gallium oxide buffer layer, and a metallized collector electrode (1-10) disposed under the heavily doped P-type nickel oxide substrate; the heavily doped P-type nickel oxide substrate and the N-type gallium oxide buffer layer form a heterojunction structure and form an ohmic contact with the metallized collector electrode; Two grooves are symmetrically formed on the surface of the N-type gallium oxide drift region (1-1) and located on both sides. An oxide layer (1-5) is provided on the groove wall. The groove is filled with a first heavily doped P-type nickel oxide region (1-2). A metallized gate (1-7) is provided on the first heavily doped P-type nickel oxide region. Two heavily doped N-type gallium oxide regions (1-3) are symmetrically arranged in the N-type gallium oxide drift region between the two grooves and are adjacent to the grooves. A second heavily doped P-type nickel oxide region (1-4) is also provided on the N-type gallium oxide drift region (1-1) and is located between the two heavily doped N-type gallium oxide regions. A metallized emitter (1-6) is provided on the two heavily doped N-type gallium oxide regions (1-3) and the second heavily doped P-type nickel oxide region (1-4) and forms an ohmic contact. The second heavily doped P-type nickel oxide region (1-4) and the N-type gallium oxide drift region (1-1) form a heterojunction structure.
2. The vertical gallium oxide insulated gate bipolar transistor power device according to claim 1, characterized in that, The heavily doped P-type nickel oxide substrate (1-9) is replaced with a copper oxide substrate, and the copper oxide substrate and the N-type gallium oxide buffer layer form a heterojunction structure.
3. The vertical gallium oxide insulated gate bipolar transistor power device according to claim 1, characterized in that, The first heavily doped P-type nickel oxide region (1-2) is replaced with a diamond region or a metal region, and a metallized gate (1-7) is disposed on the diamond region or the metal region.
4. The vertical gallium oxide insulated gate bipolar transistor power device according to claim 1, characterized in that, The second heavily doped P-type nickel oxide region (1-4) is replaced by a copper oxide region, and the copper oxide region and the N-type gallium oxide drift region (1-1) form a heterojunction structure.