A modulation type silicon carbide junction termination extension structure, a preparation method and a semiconductor

Abstract

The application relates to the technical field of semiconductor devices, and provides a modulation type silicon carbide junction terminal extension structure, a preparation method and a semiconductor. The modulation type silicon carbide junction terminal extension structure comprises a semiconductor layer and a stepped junction terminal extension region arranged in the semiconductor layer. The stepped junction terminal extension region comprises at least two steps arranged in turn from one side close to an active region to an outer side direction of a terminal region. The thickness of the steps gradually decreases, and the steps are connected through step surfaces between adjacent steps. At least one reverse doped region has semiconductor material of a first conduction type, is embedded in the stepped junction terminal extension region, forms a compensation structure in a vertical direction to a surface of the semiconductor layer and forms a compensation structure in a horizontal direction to the surface of the semiconductor layer. The application realizes two-dimensional regulation of an electric field and effectively smoothes the electric field distribution.

Description

Technical Field

[0001] This application relates to the field of semiconductor device technology, specifically to a modulation-type silicon carbide junction termination extension structure, its fabrication method, and a semiconductor. Background Technology

[0002] In high-voltage power semiconductor devices (especially wide-bandgap silicon carbide devices), junction termination extension (JTE) technology is a key means to alleviate the electric field concentration in the main junction and improve the device breakdown voltage (BVD). Traditional single-region or multi-region JTE structures laterally extend the depletion layer by injecting P-type doped regions around the main junction. However, this structure is extremely sensitive to the doping dose: too high a dose will cause the JTE region to not be completely depleted, leading to premature breakdown; too low a dose will not be able to effectively support the voltage, limiting the improvement of the device's breakdown voltage capability.

[0003] To overcome this challenge, Chinese invention patent CN106252385B proposes an anti-doped JTE structure. This structure introduces N-type anti-doped regions (such as CD1-CD4) into the P-type JTE region, utilizing the charge compensation effect to adjust the net doping concentration in a specific region to an ideal value, thereby optimizing the electric field distribution and improving terminal efficiency. Although this approach significantly improves the process sensitivity of traditional JTEs, its anti-doped regions are typically distributed as independent islands or blocks, leaving room for improvement in adjusting the uniformity of the lateral electric field distribution. Especially in ultra-high voltage (e.g., 3300V and above) applications, how to further smooth surface electric field spikes remains a pressing technical problem.

[0004] Chinese invention patent application CN114883383A proposes to accurately monitor ion implantation concentration and depth by multiple epitaxy and the introduction of secondary ion mass spectrometry (SIMS) technology, which effectively realizes graded modulation of electric field. However, the process is complex and SIMS monitoring is an offline or destructive detection method, making it difficult to achieve online real-time feedback. Summary of the Invention

[0005] To help solve the above-mentioned technical problems, this application provides a modulation-type silicon carbide junction termination extension structure, a fabrication method, and a semiconductor, adopting the following technical solution: A modulation-type silicon carbide junction termination extension structure, comprising: A semiconductor layer having a semiconductor material of a first conductivity type; A stepped junction terminal extension region is disposed in a semiconductor layer. The stepped junction terminal extension region has a semiconductor material of a second conductivity type, and the stepped junction terminal extension region includes at least two steps arranged sequentially from the side near the active region toward the outside of the terminal region. The thickness of the steps decreases step by step, and adjacent steps are connected by a step surface. At least one reverse-doped region is provided, which is a semiconductor material of a first conductivity type. The reverse-doped region is embedded in a stepped junction terminal extension region and extends from the top surface of the step to a predetermined depth inside the stepped junction terminal extension region, such that the bottom and sides of the reverse-doped region are surrounded by the stepped junction terminal extension region. The charge introduced by the reverse-doped region forms charge compensation with the surrounding stepped junction terminal extension region, such that the net doping concentration of the local area where the reverse-doped region is located is lower than the doping concentration of the surrounding junction terminal extension region where no reverse-doped region is provided. The stepped junction terminal extension region and the reverse doped region together constitute a two-dimensional electric field modulation structure. The stepped junction terminal extension region is used to achieve graded depletion in the vertical direction to smooth the vertical electric field distribution, while the reverse doped region is used to form charge compensation in the horizontal direction to adjust local electric field peaks.

[0006] The stepped junction terminal extension region has n steps, where n is a positive integer greater than or equal to 2.

[0007] The reverse doped region is formed on the step surface between adjacent steps.

[0008] There are multiple reverse doped regions, which are set at predetermined positions within the same step and form a compensation pattern with periodic or non-periodic intervals along the transverse direction.

[0009] The stepped junction terminal extension region includes a first JTE region, a second JTE region, a third JTE region, and a fourth JTE region arranged sequentially from the side closest to the active region toward the outside of the terminal region, with the thickness of the first JTE region, the second JTE region, the third JTE region, and the fourth JTE region decreasing stepwise.

[0010] The reverse doped region includes a first reverse doped region, a second reverse doped region, a third reverse doped region and a fourth reverse doped region. The first reverse doped region is embedded in the first JTE region, the second reverse doped region is embedded in the second JTE region, the third reverse doped region is embedded in the third JTE region and the fourth reverse doped region is embedded in the fourth JTE region. Furthermore, the doping concentration and width of the first, second, third, and fourth reverse doped regions increase sequentially.

[0011] Secondly, this application provides a method for preparing a modulation-type silicon carbide junction terminal extension structure as described in any one of the first aspects, comprising the following steps: S1: A silicon carbide substrate is provided, and a drift layer is epitaxially grown on the upper surface of the silicon carbide substrate to form a semiconductor layer; S2: Define the terminal area pattern through the first photolithography process, etch the drift layer to form a stepped area with at least two steps of different thicknesses; S3: Perform the first ion implantation to form a junction terminal extension implantation region in the stepped area, and the junction terminal extension implantation region continuously covers all steps; S4: Perform the second photolithography process to define the region where the reverse doped region needs to be formed, and perform the second ion implantation to form the reverse doped region in a part of the junction terminal extended implantation region. S5: Perform active region doping and implantation process; S6: Perform high-temperature annealing to activate the injected impurities; S7: An oxide layer is grown on the upper surface of the semiconductor layer, and a first electrode is fabricated in the active region. A second electrode is fabricated on the lower surface of the silicon carbide substrate to complete the device fabrication.

[0012] The etching process in S2 employs inductively coupled plasma etching or reactive ion etching, with an etching depth of 0.5 micrometers to 3 micrometers. After etching, the remaining thickness of each step is 5 micrometers to 30 micrometers, and the remaining thickness of the step decreases from the side closest to the active region towards the outside of the terminal region.

[0013] The implantation dose in the reverse doped region is lower than the implantation dose in the junction terminal extended implantation region.

[0014] Thirdly, this application provides a semiconductor structure, wherein: A substrate; An epitaxial layer is disposed on the upper surface of the substrate, and the epitaxial layer has a semiconductor material of a first conductivity type; A P-type doped region is disposed in the epitaxial layer, and the P-type doped region has a semiconductor material of the second conductivity type; A first electrode is disposed on the upper surface of the P-type doped region and is electrically connected to the P-type doped region; The modulated silicon carbide junction terminal extension structure as described in any one aspect is formed in the epitaxial layer and is disposed around the periphery of the P-type doped region. The JTE region with the largest thickness in the stepped junction terminal extension region is in contact with the outer wall of the P-type doped region, and the outer wall of the P-type doped region abuts against the inner wall of the first JTE region. A second electrode is disposed on the lower surface of the substrate.

[0015] In summary, compared with the prior art, this application has the following advantages: 1. Through the synergistic design of vertical stepped structure and lateral anti-doping compensation, two-dimensional control of electric field is achieved. The stepped JTE region achieves graded depletion. The thick steps provide sufficient charge to support high voltage, while the thin steps are easy to completely deplete to avoid charge residue, effectively smoothing the vertical electric field distribution. The selectively introduced N-type doped region and JTE injection region form charge compensation, adjusting the local net doping concentration to the ideal value, further smoothing the lateral electric field distribution. 2. Vertical gradation addresses the large-scale inhomogeneity of the overall electric field distribution, while lateral compensation finely adjusts local electric field spikes. The combination of these two methods increases the breakdown voltage. The process advantage lies in the fact that the JTE implantation dose and the anti-doping implantation dose can be optimized independently, without being constrained by each other. Although the step depth formed by etching may exhibit process fluctuations, subsequent anti-doping compensation can partially offset the impact of step depth deviations. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the first embodiment of a modulation-type silicon carbide junction terminal extension structure according to this application; Figure 2 This is a schematic flowchart of a method for preparing a modulation-type silicon carbide junction terminal extension structure according to this application; Figure 3 This is a schematic diagram of a second embodiment of a modulation-type silicon carbide junction terminal extension structure according to this application; Figure 4 This is a schematic diagram of the third embodiment of a modulation-type silicon carbide junction terminal extension structure according to this application; Figure 5 This is a schematic diagram of the fourth embodiment of a modulation-type silicon carbide junction terminal extension structure according to this application.

[0017] Reference numerals: 11-First electrode; 12-P-type doped region; 13-Semiconductor layer; 14-N-type heavily doped silicon carbide substrate; 15-Second electrode; b1-First JTE region; b2-Second JTE region; b3-Third JTE region; b4-Fourth JTE region; c1-First reverse doped region; c2-Second reverse doped region; c3-Third reverse doped region; c4-Fourth reverse doped region. Detailed Implementation

[0018] The present application will be further described below with reference to the accompanying drawings. The principles of the present application are very clear to those skilled in the art. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

[0019] Figure 1 This is a schematic diagram of the modulation-type silicon carbide junction termination extension structure of this application. Figure 1 As shown, the modulation-type silicon carbide junction termination extension structure of this embodiment includes: a semiconductor layer 13, a stepped junction termination extension region, and at least one reverse doped region.

[0020] Semiconductor layer 13 has a semiconductor material of a first conductivity type. In this embodiment, semiconductor layer 13 is an N-type silicon carbide epitaxial layer disposed on the upper surface of an N-type heavily doped silicon carbide substrate 14.

[0021] A stepped junction termination extension region is disposed in semiconductor layer 13, and the stepped junction termination extension region has a semiconductor material of a second conductivity type. In this embodiment, the stepped junction termination extension region is a P-type junction termination extension region. The stepped junction termination extension region includes at least two steps arranged sequentially from the side closest to the active region toward the outside of the termination region, the thickness of the steps decreasing step by step, and adjacent steps being connected by a step surface.

[0022] Specifically, in this embodiment, the stepped junction terminal extension region includes a first JTE region b1, a second JTE region b2, a third JTE region b3, and a fourth JTE region b4, sequentially arranged from the side closest to the active region outwards towards the terminal region. The thickness of the first JTE region b1, the second JTE region b2, the third JTE region b3, and the fourth JTE region b4 decreases progressively. Adjacent JTE regions are connected by a stepped surface.

[0023] The reverse-doped region is a semiconductor material of a first conductivity type and is embedded within the stepped junction terminal extension region. The reverse-doped region extends from the top surface of the step to a predetermined depth within the stepped junction terminal extension region, such that its bottom and sides are surrounded by the stepped junction terminal extension region. In this embodiment, the reverse-doped region is an N-type doped region. The reverse-doped region forms a superimposed compensation structure with the stepped junction terminal extension region in a direction perpendicular to the surface of semiconductor layer 13, and a laterally spaced compensation structure with the stepped junction terminal extension region in a direction parallel to the surface of semiconductor layer 13. The charge introduced by the reverse-doped region compensates for the charge of the surrounding stepped junction terminal extension region, resulting in a lower net doping concentration in the local area where the reverse-doped region is located than the doping concentration in the surrounding junction terminal extension regions where no reverse-doped region is located.

[0024] Specifically, in this embodiment, the reverse doping region includes a first reverse doping region c1, a second reverse doping region c2, a third reverse doping region c3, and a fourth reverse doping region c4. The first reverse doping region c1 is embedded in the first JTE region b1, the second reverse doping region c2 is embedded in the second JTE region b2, the third reverse doping region c3 is embedded in the third JTE region b3, and the fourth reverse doping region c4 is embedded in the fourth JTE region b4. Furthermore, the doping concentration and width of the first reverse doping region c1, the second reverse doping region c2, the third reverse doping region c3, and the fourth reverse doping region c4 increase sequentially.

[0025] In this application, the stepped junction termination extension region and the reverse doped region together constitute a two-dimensional electric field modulation structure. Specifically, the stepped junction termination extension region, through its progressively decreasing longitudinal thickness, causes the depletion layer to widen sequentially in different thickness step regions when the device withstands reverse breakdown voltage, forming a longitudinally graded depletion effect. According to the depletion layer approximation theory, the lateral electric field distribution of a single-concentration JTE is approximately triangular, with the peak appearing at the edge of the main junction. In this invention, the depth of the stepped JTE decreases stepwise, and the electric field distribution is approximately multiple small triangles. The peak electric field can be significantly reduced. The thick step region near the active region provides sufficient depletion charge to support high voltage, while the thin step region far from the active region is easily completely depleted, avoiding local electric field concentration caused by residual charge, thereby smoothing the longitudinal electric field distribution and improving the overall breakdown voltage capability.

[0026] Meanwhile, the reverse doped region embedded in the stepped junction terminal extension region and the junction terminal extension region form an alternating charge compensation structure in the lateral direction. By selectively injecting doped regions of the first conduction type, the net doping concentration of the local area is adjusted so that the net doping concentration of the local area where the reverse doped region is located is lower than the doping concentration of the junction terminal extension region around it that does not have a reverse doped region, forming a lightly doped intrinsic region. This offsets the local electric field spikes caused by process fluctuations or the stepped structure, making the potential transition smoother.

[0027] This application also provides a method for preparing a modulation-type silicon carbide junction terminal extension structure, which is used to prepare the modulation-type silicon carbide junction terminal extension structure of the above embodiment 1. Figure 2 This is a schematic flowchart illustrating the fabrication method of the modulation-type silicon carbide junction terminal extension structure of this application. Figure 2 As shown, the preparation method includes the following steps: S1: An N-type heavily doped silicon carbide substrate 14 is provided, and a drift layer is epitaxially grown on the upper surface of the N-type heavily doped silicon carbide substrate 14 to form a semiconductor layer 13.

[0028] Specifically, the drift layer is an N-type silicon carbide epitaxial layer, which is grown on the upper surface of the N-type heavily doped silicon carbide substrate 14 by chemical vapor deposition.

[0029] S2: Define the terminal area pattern through the first photolithography process, etch the drift layer to form a stepped area with at least two steps of different thicknesses.

[0030] Specifically, the etching process employs inductively coupled plasma etching or reactive ion etching, with an etching depth of 0.5 micrometers to 3 micrometers. After etching, the remaining thickness of each step is 5 micrometers to 30 micrometers, and the remaining thickness of the step decreases from the side closest to the active region towards the outside of the terminal region.

[0031] S3: Perform the first ion implantation to form a junction terminal extension implantation region in the stepped area, which continuously covers all steps.

[0032] Specifically, the first ion implantation uses aluminum ion implantation to form a P-type junction terminal extension implantation region in a stepped region, and the junction terminal extension implantation region continuously covers all steps.

[0033] S4: Perform the second photolithography process to define the region where the reverse doped region needs to be formed, and perform the second ion implantation to form the reverse doped region in a part of the junction terminal extended implantation region.

[0034] Specifically, the second ion implantation uses nitrogen ion implantation to form an N-type reverse-doped region in a portion of the junction-terminated extended implantation region. The implantation dose in the reverse-doped region is lower than that in the junction-terminated extended implantation region.

[0035] S5: Perform active region doping and implantation process.

[0036] Specifically, ion implantation is performed in the active region to form a P-type doped region 12.

[0037] S6: Perform high-temperature annealing to activate the injected impurities.

[0038] Specifically, high-temperature annealing is performed in an inert gas atmosphere, with a temperature range of 1500°C to 1800°C, to activate the injected impurity ions.

[0039] S7: An oxide layer is grown on the upper surface of the semiconductor layer 13, and a first electrode 11 is fabricated in the active region. A second electrode 15 is fabricated on the lower surface of the N-type heavily doped silicon carbide substrate 14 to complete the device fabrication.

[0040] Specifically, an oxide layer is grown on the upper surface of the semiconductor layer 13 by a thermal oxidation process to serve as a field oxide layer. A metal layer is deposited on the upper surface of the P-type doped region 12 in the active region and annealed to form the first electrode 11, and a metal layer is deposited on the lower surface of the N-type heavily doped silicon carbide substrate 14 and annealed to form the second electrode 15.

[0041] The modulated silicon carbide junction termination extension structure of Example 1 can be prepared using the above preparation method. In this method, the JTE implantation dose and the reverse doping implantation dose can be optimized independently and are not constrained by each other. The step depth formed by etching may have process fluctuations, but the impact of step depth deviation can be partially offset by subsequent reverse doping compensation, thereby reducing process sensitivity and improving the yield and consistency of device fabrication.

[0042] Figure 3 This is a schematic diagram of a second embodiment of a modulation-type silicon carbide junction terminal extension structure according to this application; Figure 4This is a schematic diagram of the third embodiment of a modulation-type silicon carbide junction terminal extension structure according to this application; Figure 5 This is a schematic diagram of the fourth embodiment of a modulation-type silicon carbide junction termination extension structure according to this application. These three embodiments illustrate that the number of steps in the stepped junction termination extension region of this application can be n, where n is a positive integer greater than or equal to 2. The number of steps in the first embodiment (first JTE region b1, second JTE region b2, third JTE region b3, and fourth JTE region b4) should not be interpreted as a limitation on the scope of protection of this application. Those skilled in the art can flexibly set the number of steps according to actual needs when implementing this application.

[0043] The technical scope of this application is not limited to the contents of the above specification. Those skilled in the art can make various modifications and variations to the above embodiments without departing from the technical concept of this application, and all such modifications and variations should fall within the scope of this application.

Claims

1. A modulation-type silicon carbide junction termination extension structure, characterized in that, include: A semiconductor layer having a semiconductor material of a first conductivity type; A stepped junction terminal extension region is disposed in a semiconductor layer. The stepped junction terminal extension region has a semiconductor material of a second conductivity type, and the stepped junction terminal extension region includes at least two steps arranged sequentially from the side near the active region toward the outside of the terminal region. The thickness of the steps decreases step by step, and adjacent steps are connected by a step surface. At least one reverse-doped region is provided, which is a semiconductor material of a first conductivity type. The reverse-doped region is embedded in a stepped junction terminal extension region and extends from the top surface of the step to a predetermined depth inside the stepped junction terminal extension region, such that the bottom and sides of the reverse-doped region are surrounded by the stepped junction terminal extension region. The charge introduced by the reverse-doped region forms charge compensation with the surrounding stepped junction terminal extension region, such that the net doping concentration of the local area where the reverse-doped region is located is lower than the doping concentration of the surrounding junction terminal extension region where no reverse-doped region is provided. The stepped junction terminal extension region and the reverse doped region together constitute a two-dimensional electric field modulation structure. The stepped junction terminal extension region is used to achieve graded depletion in the vertical direction to smooth the vertical electric field distribution, while the reverse doped region is used to form charge compensation in the horizontal direction to adjust local electric field peaks.

2. The modulation-type silicon carbide junction termination extension structure according to claim 1, characterized in that, The stepped junction terminal extension region has n steps, where n is a positive integer greater than or equal to 2.

3. The modulation-type silicon carbide junction termination extension structure according to claim 1, characterized in that, The reverse doped region is formed on the step surface between adjacent steps.

4. The modulation-type silicon carbide junction termination extension structure according to claim 1, characterized in that, There are multiple reverse doped regions, which are set at predetermined positions within the same step and form a compensation pattern with periodic or non-periodic intervals along the transverse direction.

5. The modulation-type silicon carbide junction termination extension structure according to claim 1, characterized in that, The stepped junction terminal extension region includes a first JTE region, a second JTE region, a third JTE region, and a fourth JTE region arranged sequentially from the side closest to the active region toward the outside of the terminal region, with the thickness of the first JTE region, the second JTE region, the third JTE region, and the fourth JTE region decreasing stepwise.

6. The modulation-type silicon carbide junction termination extension structure according to claim 5, characterized in that, The reverse doped region includes a first reverse doped region, a second reverse doped region, a third reverse doped region and a fourth reverse doped region. The first reverse doped region is embedded in the first JTE region, the second reverse doped region is embedded in the second JTE region, the third reverse doped region is embedded in the third JTE region and the fourth reverse doped region is embedded in the fourth JTE region. Furthermore, the doping concentration and width of the first, second, third, and fourth reverse doped regions increase sequentially.

7. A method for preparing a modulation-type silicon carbide junction terminal extension structure as described in any one of claims 1 to 6, characterized in that, Includes the following steps: S1: A silicon carbide substrate is provided, and a drift layer is epitaxially grown on the upper surface of the silicon carbide substrate to form a semiconductor layer; S2: Define the terminal area pattern through the first photolithography process, etch the drift layer to form a stepped area with at least two steps of different thicknesses; S3: Perform the first ion implantation to form a junction terminal extension implantation region in the stepped area, and the junction terminal extension implantation region continuously covers all steps; S4: Perform the second photolithography process to define the region where the reverse doped region needs to be formed, and perform the second ion implantation to form the reverse doped region in a part of the junction terminal extended implantation region. S5: Perform active region doping and implantation process; S6: Perform high-temperature annealing to activate the injected impurities; S7: An oxide layer is grown on the upper surface of the semiconductor layer, and a first electrode is fabricated in the active region. A second electrode is fabricated on the lower surface of the silicon carbide substrate to complete the device fabrication.

8. The preparation method according to claim 7, characterized in that, The etching process in S2 employs inductively coupled plasma etching or reactive ion etching, with an etching depth of 0.5 micrometers to 3 micrometers. After etching, the remaining thickness of each step is 5 micrometers to 30 micrometers, and the remaining thickness of the step decreases from the side closest to the active region towards the outside of the terminal region.

9. The preparation method according to claim 7, characterized in that, The implantation dose in the reverse doped region is lower than the implantation dose in the junction terminal extended implantation region.

10. A semiconductor structure, characterized in that, include: A substrate; An epitaxial layer is disposed on the upper surface of the substrate, and the epitaxial layer has a semiconductor material of a first conductivity type; A P-type doped region is disposed in the epitaxial layer, and the P-type doped region has a semiconductor material of the second conductivity type; A first electrode is disposed on the upper surface of the P-type doped region and is electrically connected to the P-type doped region; The modulated silicon carbide junction termination extension structure as described in claim 6 is formed in the epitaxial layer and is disposed around the periphery of the P-type doped region. The JTE region with the largest thickness in the stepped junction termination extension region is in contact with the outer wall of the P-type doped region, and the outer wall of the P-type doped region abuts against the inner wall of the first JTE region. A second electrode is disposed on the lower surface of the substrate.

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