Method for manufacturing a semiconductor integrated device and semiconductor integrated device

By simultaneously forming the pre-drilled holes and shallow trenches during the etching process, the problem of the difference in etching depth between the IPS and BCD processes for the pre-drilled holes was solved, resulting in a reduction in process steps and costs.

CN122138453APending Publication Date: 2026-06-02SEMICON MFG ELECTRONICS (SHAOXING) CORP
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
SEMICON MFG ELECTRONICS (SHAOXING) CORP
Filing Date
2026-05-06
Publication Date
2026-06-02

AI Technical Summary

Technical Problem

In existing technologies, the difference in the etching depth of the plug holes between IPS and BCD processes makes them impossible to merge, increasing the number of process steps and manufacturing costs.

Method used

The first etching process simultaneously forms the plug pre-reserved hole and shallow trench. The second etching process deepens the shallow trench while forming the gate trench. The third etching process simultaneously forms the plug hole, reducing the use of photomask.

Benefits of technology

This technology enables the simultaneous formation of plug holes, reduces process steps, shortens the production cycle, and lowers manufacturing costs.

✦ Generated by Eureka AI based on patent content.

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Abstract

This application relates to a method for fabricating a semiconductor integrated device and the semiconductor integrated device. The method includes: providing a semiconductor material layer; performing a first etching process to simultaneously form a first plug pre-reserved via and a first shallow trench; performing a second etching process to simultaneously form a gate trench and a first deep trench; forming a first dielectric layer on the semiconductor material layer, the first dielectric layer covering the inner walls of the gate trench and the first deep trench and filling the first plug pre-reserved via; forming a gate structure in the gate trench, forming a deep trench isolation structure in the first deep trench, and forming a body region in the semiconductor material layer adjacent to the gate trench, and forming a source region in the body region, the first plug pre-reserved via penetrating the source region and extending into the body region; forming a second dielectric layer on the semiconductor material layer; and performing a third etching process to simultaneously form the first plug via and the second plug via. This reduces the number of process steps, shortens the production cycle, and lowers manufacturing costs.
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Citation Information

Patent Citations

  • Semiconductor device, manufacturing method thereof and electronic device

    CN117594440A

  • Semiconductor structure and preparation method thereof

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  • Device integrated with deep trench isolation structure and preparation method thereof

    CN120565490A

  • Hall device and manufacturing method thereof

    CN121888864A

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    US20250366183A1