Back contact solar cell and method of manufacturing the same

Abstract

The application provides a back contact solar cell and a preparation method thereof. The back contact solar cell comprises a silicon substrate having a front surface and a back surface arranged oppositely; a tunneling layer arranged on the back surface of the silicon substrate; and a doped layer arranged on the surface of the tunneling layer away from the silicon substrate. The doped layer comprises a first doped part and a second doped part, and an isolation part between the first doped part and the second doped part. The conductive types of the first doped part and the second doped part are opposite. A mask layer is arranged on the surface of the isolation part away from the silicon substrate. The mask layer covers a local area of the surface of the isolation part away from the silicon substrate. The ratio of the width of the mask layer in a first direction to the width of the isolation part in the first direction is greater than or equal to 0.5 and less than or equal to 1. The application can realize stable electrical isolation, a good electrode contact interface and compatibility with subsequent processes simultaneously by optimizing the coverage design of the mask layer on the isolation area without a complex trench process.

Description

Technical Field

[0001] This application relates to the field of photovoltaic technology, and in particular to a back-contact solar cell and its fabrication method. Background Technology

[0002] Back-contact solar cells have become an important development direction in the photovoltaic field due to their advantages of no electrode obstruction on the front side, higher short-circuit current, and higher conversion efficiency. These cells typically consist of a silicon substrate and a tunneling layer and a doped layer located on the back of the silicon substrate. The doped layer contains a first doped portion and a second doped portion with opposite conductivity types, and an electrical isolation structure is required between them to prevent leakage.

[0003] In existing technologies, to achieve electrical isolation between the first and second doped regions, physical isolation structures are typically formed using methods such as trench isolation or localized etching. However, trench etching is complex and costly, requiring additional photolithography, etching, and cleaning steps, which not only increases the process flow and time but also raises the requirements for equipment precision and process control. Secondly, trench etching leads to localized thinning of the silicon wafer, weakening the mechanical strength of the battery and increasing the risk of microcracks during subsequent processing or use, affecting the long-term reliability of the device. Furthermore, the etching process usually involves chemical etching solutions, increasing chemical consumption and wastewater treatment burdens, which is detrimental to green manufacturing.

[0004] On the other hand, in the scheme of using a mask layer for patterned doping to avoid trenches, in order to ensure that the isolation area is completely undoped, the mask layer is usually designed to completely cover and extend beyond the isolation area. Although this conservative design can ensure isolation reliability, it also brings new problems: First, the excessively large coverage area of ​​the mask layer may cause severe shrinkage due to isotropic etching in subsequent front-side texturing, cleaning and other processes, resulting in uneven edge coverage, or even exposing part of the isolation area that should be protected, introducing the risk of doping contamination; Second, the complete and thick mask layer coverage will affect the uniform deposition and adhesion of the subsequent passivation film in this area, which may cause local degradation of optical or electrical performance; Third, the requirements for the precision and dimensional uniformity of the mask layer patterning are extremely high. Any alignment error or dimensional fluctuation may directly lead to isolation failure or loss of effective power generation area, resulting in a narrow process window and challenges to production yield. Summary of the Invention

[0005] This application provides a back-contact solar cell and its fabrication method, which can simultaneously achieve robust electrical isolation, good electrode contact interface, and compatibility with subsequent processes without the need for complex trenching processes, by optimizing the mask layer coverage design on the isolation region.

[0006] In a first aspect, this application provides a back-contact solar cell, comprising:

[0007] A silicon substrate having a front side and a back side arranged opposite to each other;

[0008] A tunneling layer is disposed on the back side of the silicon substrate;

[0009] A doped layer is disposed on the surface of the tunneling layer opposite to the silicon substrate; the doped layer includes a first doped portion and a second doped portion, and an isolation portion located between the two, wherein the first doped portion and the second doped portion have opposite conductivity types.

[0010] A mask layer is disposed on the surface of the isolation portion on the side opposite to the silicon substrate;

[0011] The mask layer covers a local area of ​​the surface of the isolation portion facing away from the silicon substrate, and the ratio of the width of the mask layer in the first direction to the width of the isolation portion in the first direction is greater than or equal to 0.5 and less than or equal to 1. The first direction is the direction in which the first doped portion, the isolation portion and the second doped portion are arranged in sequence.

[0012] In some embodiments, the doping concentration of the isolation portion gradually decreases from the interface adjacent to the first doped portion and the interface adjacent to the second doped portion toward the center of the isolation portion.

[0013] In some embodiments, a portion of the isolation portion is an intrinsic amorphous silicon layer or an intrinsic polycrystalline silicon layer.

[0014] In some embodiments, the width of the isolation portion in the first direction is greater than or equal to 10 micrometers and less than or equal to 500 micrometers; or greater than or equal to 20 micrometers and less than or equal to 200 micrometers; or greater than or equal to 50 micrometers and less than or equal to 150 micrometers; the first direction is the direction in which the first doped portion, the isolation portion, and the second doped portion are arranged sequentially.

[0015] In some embodiments, the mask layer includes one or more combinations of silicon oxide layer, silicon oxynitride layer, and silicon nitride layer.

[0016] In some embodiments, the thickness of the mask layer is greater than or equal to 20 nanometers and less than or equal to 500 nanometers; or greater than or equal to 50 nanometers and less than or equal to 300 nanometers; or greater than or equal to 80 nanometers and less than or equal to 200 nanometers.

[0017] In some embodiments, the mask layer includes a first mask layer and a second mask layer stacked in a direction away from the silicon substrate, wherein the first mask layer includes a silicon oxide layer; and the second mask layer includes one or more combinations of a silicon nitride layer and a silicon oxynitride layer.

[0018] In some embodiments, the surfaces of the first doped portion and the second doped portion facing away from the silicon substrate are textured; the surface of the mask layer facing away from the silicon substrate is smooth.

[0019] Secondly, this application provides a method for fabricating a back-contact solar cell, comprising:

[0020] A tunneling layer and a silicon material layer are sequentially deposited on the back side of a silicon substrate;

[0021] Perform the first annealing treatment;

[0022] The first and second preset regions of the silicon material layer are subjected to a first doping treatment and a second doping treatment, respectively, to form a first doped portion and a second doped portion;

[0023] The first doped portion and the second doped portion have opposite conductivity types; an isolation portion is formed between the first doped portion and the second doped portion.

[0024] In some embodiments, the first and second preset regions of the silicon material layer are subjected to a first doping treatment and a second doping treatment, respectively, including:

[0025] Under heating conditions, the first doped source reacts with the first preset region of the silicon material layer to form a first doped source glass layer;

[0026] Under heating conditions, the second doping source reacts with the second preset region of the silicon material layer to form a second doping source glass layer;

[0027] A second annealing process is performed to allow dopant atoms to enter the underlying silicon material layer from the first and second dopant source glass layers, thereby forming the first doped portion and the second doped portion in the first preset region and the second preset region, respectively.

[0028] In some embodiments, during the first annealing process...

[0029] A first mask layer is formed by oxidation on the surface of the silicon material layer opposite to the silicon substrate;

[0030] Prior to the step of forming the first doped source glass layer, the method further includes:

[0031] A groove is made in the portion of the first mask layer corresponding to the first preset area to expose the silicon material layer in the first preset area;

[0032] Prior to the step of forming the second doped source glass layer, the method further includes:

[0033] A groove is made in the portion of the first mask layer corresponding to the second preset area to expose the silicon material layer in the second preset area.

[0034] In some embodiments, prior to the step of performing the first annealing treatment, the method further includes:

[0035] A second mask layer is formed on the surface of the silicon material layer opposite to the silicon substrate;

[0036] The first mask layer is located between the second mask layer and the silicon material layer;

[0037] In the step of slotting the portion of the first mask layer corresponding to the first preset area, slots are made in both the first mask layer and the second mask layer.

[0038] In the step of slotting the portion of the first mask layer corresponding to the second preset area, slots are made in both the first mask layer and the second mask layer.

[0039] In some embodiments, prior to the step of performing the first annealing treatment, the method further includes:

[0040] A second mask layer is formed on the surface of the silicon material layer opposite to the silicon substrate;

[0041] Prior to the step of forming the first doped source glass layer, the method further includes:

[0042] The portion of the second mask layer corresponding to the first preset area is slotted to expose the first preset area;

[0043] Prior to the step of forming the second doped source glass layer, the method further includes:

[0044] The portion of the second mask layer corresponding to the second preset area is slotted to expose the second preset area.

[0045] In some embodiments, the second mask layer comprises an intrinsic amorphous silicon layer or an intrinsic polycrystalline silicon layer; or...

[0046] The second mask layer includes an amorphous silicon layer or a polycrystalline silicon layer containing doped elements; and the doping concentration of the doped elements is less than the doping concentration of the same doped elements contained in the first doped portion or the second doped portion.

[0047] In some embodiments, the second mask layer is generated in the same apparatus used to deposit the silicon material layer.

[0048] In some embodiments, the temperature of the first annealing treatment is greater than or equal to 1000°C and less than or equal to 1200°C; the duration of the first annealing treatment is greater than or equal to 10 minutes and less than or equal to 3 hours.

[0049] In some embodiments, the maximum temperature of the second annealing treatment is less than 1000°C; or...

[0050] The highest temperature of the second annealing treatment is greater than or equal to 700°C and less than or equal to 950°C; or,

[0051] The maximum temperature of the second annealing process is greater than or equal to 700°C and less than or equal to 900°C.

[0052] In some embodiments, the highest temperature used to form the first doped source glass layer is greater than or equal to 700°C and less than or equal to 920°C; the highest temperature used to form the second doped source glass layer is greater than or equal to 700°C and less than or equal to 920°C; or,

[0053] The highest temperature used to form the first doped source glass layer is greater than or equal to 700°C and less than or equal to 830°C; the highest temperature used to form the second doped source glass layer is greater than or equal to 700°C and less than or equal to 830°C.

[0054] In some embodiments, after the step of performing a first doping treatment on the first preset region and a second preset region of the silicon material layer, respectively, the method further includes:

[0055] Remove each film layer on the front side of the silicon substrate to expose the front side of the silicon substrate;

[0056] The front side of the silicon substrate is texturized and cleaned.

[0057] The cleaning process is further used to at least partially remove the second mask layer; or to remove the second mask layer and partially remove the first mask layer.

[0058] In some embodiments, after the step of performing a first doping treatment on the first preset region and a second preset region of the silicon material layer, respectively, the method further includes:

[0059] Remove each film layer on the front side of the silicon substrate to expose the front side of the silicon substrate;

[0060] The front side of the silicon substrate is texturized and cleaned.

[0061] The cleaning process is also used to remove part of the second mask layer.

[0062] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this application, nor is it intended to limit the scope of this application. Other features of this application will become readily apparent from the following description. Attached Figure Description

[0063] The accompanying drawings are provided to further illustrate the present application and form part of the specification. They are used together with the embodiments of the present application to explain the application and do not constitute a limitation thereof. The above and other features and advantages will become more apparent to those skilled in the art from the detailed example embodiments described with reference to the accompanying drawings, in which:

[0064] Figure 1 A partial cross-sectional view of a back-contact solar cell provided in an embodiment of this application;

[0065] Figure 2 A partial cross-sectional view of another back-contact solar cell provided in an embodiment of this application;

[0066] Figure 3 This is a partial enlarged view of the doped portion and the isolation portion used in the embodiments of this application;

[0067] Figure 4 A flowchart of a back-contact solar cell fabrication method provided in this application embodiment;

[0068] Figure 5 This is a process diagram illustrating the formation of the tunneling layer and silicon material layer in an embodiment of this application;

[0069] Figure 6 This is a flowchart illustrating step S103 in an embodiment of this application.

[0070] Figure 7 This is a process diagram of forming the first type of mask layer in an embodiment of this application;

[0071] Figure 8 This is a process diagram illustrating the formation of the second mask layer in an embodiment of this application.

[0072] Figure 9 This is a process diagram illustrating the formation of the third mask layer in an embodiment of this application;

[0073] Figure 10 This is a diagram illustrating the process of slotting the first mask layer in the first preset area in an embodiment of this application.

[0074] Figure 11 This is a process diagram of the doping reaction of the silicon material layer in the first preset region according to an embodiment of this application;

[0075] Figure 12 This is a diagram illustrating the process of slotting the first mask layer in the second preset area in an embodiment of this application.

[0076] Figure 13 This is a process diagram illustrating the doping reaction of the silicon material layer in the second preset region according to an embodiment of this application;

[0077] Figure 14 This is a process diagram illustrating the second annealing process in this embodiment to form the first and second doped portions. Detailed Implementation

[0078] To enable those skilled in the art to better understand the technical solutions of this application, exemplary embodiments of this application are described below in conjunction with the accompanying drawings, including various details of the embodiments of this application to aid understanding. These should be considered merely exemplary. Therefore, those skilled in the art should recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this application. Similarly, for clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0079] Where there is no conflict, the various embodiments of this application and the features thereof may be combined with each other.

[0080] As used herein, the term “and / or” includes any and all combinations of one or more related enumerated entries.

[0081] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the application. As used herein, the singular forms “a” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that when the terms “comprising” and / or “made of” are used in this specification, the presence of the stated feature, integral, step, operation, element, and / or component is specified, but the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof is not excluded. Terms such as “connected” or “linked” are not limited to physical or mechanical connections but can include electrical connections, whether direct or indirect.

[0082] Unless otherwise specified, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this application, and will not be interpreted as having an idealized or overly formal meaning, unless expressly so defined herein.

[0083] Please see Figure 1The back-contact solar cell provided in this application includes a silicon substrate 1, a tunneling layer 2, a doped layer 3, and a mask layer 6. The silicon substrate 1 has a front side and a back side disposed opposite to each other. The doped layer 3 is disposed on the surface of the tunneling layer 2 opposite to the silicon substrate 1. The doped layer 3 includes a first doped portion 31 and a second doped portion 32, and an isolation portion 33 located between them. The first doped portion 31 and the second doped portion 32 have opposite conductivity types. For example, one of the first doped portion 31 and the second doped portion 32 is an N-type doped portion, and the other is a P-type doped portion.

[0084] A tunneling layer 2 is disposed on the back side of the silicon substrate 1 and covers the regions of the silicon substrate 1 corresponding to the first doped portion 31, the second doped portion 32, and the isolation portion 33. This tunneling layer 2, for example, is a tunneling oxide layer, used to bond with silicon atoms, saturating the dangling bonds across the entire silicon surface and providing interfacial chemical passivation for the battery. The portions of the tunneling layer 2 located at the first doped portion 31 and the second doped portion 32 serve as a quantum tunneling layer, allowing majority carriers to pass through via the quantum tunneling effect, enter the doped polycrystalline silicon above, and be collected by the electrodes. The portion of the tunneling layer 2 located at the isolation portion 33 can be used as a passivation and buffer layer; that is, it provides chemical passivation for the doped layer 3, maintaining a low recombination rate at the silicon interface; simultaneously, it separates the doped layer 3 from the silicon substrate 1, avoiding additional interfacial defects that might be introduced by direct contact between two materials with different crystal structures, thus playing a buffering and isolation role.

[0085] In conventional back-contact solar cell fabrication processes, to achieve electrical isolation between the first doped portion 31 and the second doped portion 32, a physical isolation structure is typically formed on the silicon substrate surface through trench etching. This method is complex and costly, and the etching process uses chemical etching solutions, increasing chemical consumption and wastewater treatment burden. Furthermore, trenches lead to localized thinning of the silicon wafer, reducing mechanical strength and increasing the risk of microcracks. To address this issue, this application provides a mask layer 6 on the surface of the isolation portion 33 facing away from the silicon substrate 1.

[0086] When forming the doped pattern, the mask layer 6 only covers the region of the silicon material layer corresponding to the isolation portion 33. In subsequent doping steps, its dielectric properties (such as silicon oxide, silicon nitride, silicon oxynitride, or a stack thereof) effectively prevent the dopant source gas or paste from contacting the underlying silicon material, thereby preventing dopant atoms from entering this region. Therefore, the isolation portion 33 can maintain an intrinsic or extremely low doping concentration, forming a high-resistance region (i.e., isolation portion 33) between the first doped portion 31 and the second doped portion 32, achieving reliable electrical isolation. This method eliminates the need for any thinning etching of the silicon substrate 1, completely eliminating the risk of local mechanical strength degradation and microcracks caused by trenches, and fundamentally avoiding complex trench etching processes.

[0087] Unlike the rough or recessed surface left after trench etching, the mask layer 6 has a smooth, flat surface. This mask layer 6 serves as the upper interface of the region where the final isolation portion 33 is located, facilitating the uniform and conformal deposition of the subsequent passivation layer 5 (e.g., including a passivation film and an anti-reflection film) on the overall back side, thus improving long-term reliability. Furthermore, the mask layer itself can act as a dielectric passivation layer, further reducing the recombination rate on the isolation portion surface and enhancing the long-term stability of the electrical isolation.

[0088] In summary, by providing a mask layer 6 on the surface of the isolation portion 33 facing away from the silicon substrate 1, this application provides a back-contact solar cell that eliminates the need for trench etching and simplifies the process. While ensuring excellent electrical isolation reliability, the smooth surface and passivation properties of the mask layer 6 itself achieve good interface quality.

[0089] Furthermore, in the fabrication of a back-contact solar cell, the aforementioned mask layer 6 only covers the region of the silicon material layer corresponding to the isolation portion, acting as a physical and chemical diffusion barrier. During subsequent doping, it prevents the boron or phosphorus source gas from contacting the underlying silicon material, thus preventing dopant atoms from being introduced into the isolation portion 33. It is precisely due to the protection of this mask layer that the region of the silicon material layer corresponding to the isolation portion 33 maintains an intrinsic or extremely low doping concentration, thereby forming a high-resistance region between the first doped portion 31 and the second doped portion 32, thus achieving electrical isolation instead of existing trenches.

[0090] In some embodiments, the mask layer 6 covers a local area of ​​the surface of the isolation portion 33 on the side opposite to the silicon substrate 1, and the ratio of the width of the mask layer 6 in the first direction to the width of the isolation portion 33 in the first direction is greater than or equal to 0.5 and less than or equal to 1.

[0091] By designing the mask layer 6 to cover only a localized area of ​​the surface of the isolation portion 33, and controlling the ratio of its width to the width of the isolation portion 33 within the range of 0.5 to 1, the mask layer 6 can cover the critical central area of ​​the isolation portion 33. Even if the edges of the mask layer 6 retract to a certain extent during subsequent isotropic etching processes such as front-side texturing and cleaning, it can still effectively protect the central portion of the isolation portion 33 from exposure and doping contamination. Simultaneously, the aforementioned ratio (≤1) means that the mask layer 6 does not need to completely cover and extend beyond the isolation portion 33, which provides a reasonable process tolerance margin, significantly reducing the extreme requirements for absolute alignment accuracy and dimensional uniformity of the mask layer pattern, thereby widening the process window and improving production yield and reliability.

[0092] Secondly, the partial coverage of the isolation portion 33 by the mask layer 6, especially its coverage rate not exceeding 100% (i.e., a ratio ≤ 1), means that some areas on the surface of the isolation portion 33 (especially the edges) may not be completely covered by the mask layer 6 or the mask layer thickness may be relatively thin. This design is beneficial for the subsequent deposition of the passivation layer 5 (not shown in the figure, but see [reference]). Figure 1 The overall structure enables more direct and stable contact and adhesion with the surface of the isolation section 33 or the thin mask layer, improving the uniformity and interface quality of the passivation film in the isolation area and avoiding localized degradation of optical or electrical performance that may be caused by a complete and thick mask layer.

[0093] Furthermore, in the manufacturing process of the back-contact solar cell adopted in this application, after completing all the key processes on the back side of the cell (first annealing, doping treatment), the electrical structure of the cell (PN junction, passivation contact) has been finalized on the back side. At this point, the parasitic film layers (such as tunneling layers, polycrystalline silicon, doped glass, etc.) that are grown during the deposition process on the front side become redundant and need to be removed to expose the original front side of the silicon substrate 1. At the same time, the edge of the mask layer 6 on the back side may be etched back during this process, resulting in a reduction in its width, so that the final mask layer 6 covers a local area of ​​the surface of the isolation portion 33 facing away from the silicon substrate 1.

[0094] Based on this, this application ensures that the ratio of the width of the mask layer 6 in the first direction to the width of the isolation portion 33 in the first direction is greater than or equal to 0.5 and less than or equal to 1. Even if fluctuations in the cleaning process (such as deviations in time, concentration, and temperature) cause the mask layer 6 to be laterally corroded to varying degrees, the central region of the isolation portion (the most critical region for maintaining electrical isolation) can still be covered and protected by the mask layer 6. It should be noted that the limitation of a ratio less than or equal to 1 acknowledges the practicalities of the process, meaning that the mask layer 6 may not perfectly cover the isolation portion 33, and also leaves room for proactive design.

[0095] In some embodiments, the doping concentration of the isolation portion 33 gradually decreases from the interface adjacent to the first doped portion 31 and the interface adjacent to the second doped portion 32 toward the center of the isolation portion 33.

[0096] If the isolation section 33 is completely intrinsic (with zero doping concentration), or if it forms an atomically steep concentration abrupt change interface with the adjacent heavily doped first and second doped sections, an extremely high built-in electric field and band bending will be generated at the interface. This easily becomes a strong recombination center for charge carriers (especially minority carriers), increasing the interface recombination rate and thus impairing the open-circuit voltage (Voc) of the battery. At the same time, when the battery is operating or subjected to reverse bias, this location may induce local breakdown or leakage channels due to electric field concentration.

[0097] Furthermore, in real-world manufacturing processes, there are fluctuations in the patterning precision of the mask layer and the lateral thermal diffusion of doped atoms during annealing (although suppressed, it cannot be absolutely zero). If the design goal is an absolutely "pure" intrinsic isolation region, any minute process deviation can lead to uncontrollable, discrete doping "contamination points" infiltrating the isolation region. These random, high-concentration doping points can become fatal leakage paths, and in severe cases, directly cause a short circuit in the PN junction, rendering the isolation ineffective.

[0098] In the back-contact solar cell manufacturing process (such as second annealing) employed in this application, dopant atoms inevitably undergo slight lateral thermal diffusion from the formed first doped portion 31 and second doped portion 32 to the adjacent isolation portion 33. This application controls this diffusion within an acceptable range with a gradient distribution by controlling the annealing temperature, time, mask layer thickness, and opening alignment accuracy. Simultaneously, the mask layer 6 covering the isolation portion 33 still plays a primary blocking role, ensuring that diffusion only occurs within a narrow edge region and preventing dopant atoms from reaching the central region of the isolation portion 33.

[0099] This application reduces the band gap and electric field intensity at the interface between the isolation section 33 and the doped section 33 by gradually decreasing the doping concentration from the interface adjacent to the first doped section 31 and the interface adjacent to the second doped section 32 towards the center of the isolation section 33. This effectively suppresses carrier recombination at the interface, improves the passivation effect in this region, and ultimately helps to improve the open-circuit voltage (Voc) and fill factor (FF) of the battery. Simultaneously, by allowing a low concentration gradient region in the isolation section 33, the stringent requirements on the absolute blocking capability of the mask layer and the absolute precision of patterning are relaxed, improving the tolerance and stability of the manufacturing process. Even with minor process fluctuations, the doping concentration at the edge of the isolation section 33 only changes within a preset gradient range, without suddenly appearing destructive high-concentration doped islands. This makes the electrical isolation performance insensitive to process fluctuations, significantly improving product yield and reliability (robustness). Furthermore, the gradually decreasing concentration distribution from the heavily doped region towards the intrinsic / lightly doped center in the isolation section 33 naturally forms a slowly varying electric field at the interface. This electric field helps to "push" minority carriers away from the isolation interface and back into their respective doped regions, thereby physically suppressing leakage current through the isolation region and enhancing the effectiveness of isolation.

[0100] It is important to note that the "gradually decreasing" mentioned above primarily describes the spatial distribution of doping concentration: near the interface between the isolation section 33 and the first doped section 31 and the second doped section 32, due to unavoidable slight thermal diffusion or edge effects during the process, there may be a transition region where the doping concentration gradually decreases from the adjacent heavily doped region to the interior of the isolation section. The width of this transition region is typically very narrow (e.g., much less than 10% of the total width of the isolation section), and its existence precisely optimizes the band structure at the interface, reducing the risk of recombination and leakage.

[0101] Furthermore, in some embodiments, a portion of the isolation section 33 is an intrinsic amorphous silicon layer or an intrinsic polycrystalline silicon layer. The intrinsic amorphous silicon layer or intrinsic polycrystalline silicon layer defines the material nature and electrical state of the main region of the isolation section 33. In the central region or main part of the isolation section 33, due to the effective blocking effect of the mask layer 6 above, doping atoms cannot enter in large quantities, so that the silicon material (whether amorphous silicon or polycrystalline silicon) in this region remains at or very close to the intrinsic extremely low doping concentration, thereby ensuring that the isolation section has extremely high resistance as a whole, achieving reliable electrical isolation.

[0102] As shown above, the main body of the isolation section 33 is an intrinsic or near-intrinsic silicon material layer, ensuring the foundation for high-resistance isolation. Near the interface between it and the doped sections on both sides, there is a controllable transition region with gradually varying concentrations. This transition region optimizes the interface electrical properties and improves the passivation effect and process tolerance. The two complement each other, forming a complete and high-performance trenchless isolation solution.

[0103] By making a portion of the isolation section 33 an intrinsic amorphous silicon layer or an intrinsic polycrystalline silicon layer, the diffusion coefficient of dopants such as boron and phosphorus in both amorphous and polycrystalline silicon structures is lower than that in crystalline silicon. In particular, amorphous silicon, due to its disordered atomic arrangement, can prevent dopant atoms from laterally crossing the isolation section 33, thereby achieving reliable electrical isolation.

[0104] In embodiments where the isolation portion 33 is an intrinsic polycrystalline silicon layer, in the manufacturing process of the back-contact solar cell used in this application, the silicon material layer deposited on the tunneling layer 2 is typically an amorphous silicon layer in the initial stage of deposition. This is because, under low-temperature conditions, silicon films deposited by plasma-enhanced chemical vapor deposition (PECVD) or low-pressure chemical vapor deposition (LPCVD) processes are typically amorphous. After the amorphous silicon layer undergoes its first annealing treatment, it undergoes solid-phase crystallization, transforming into polycrystalline silicon. At this point, the entire amorphous silicon layer transforms into an intrinsic polycrystalline silicon layer. During subsequent doping processes (such as doping reactions and a second annealing process), the portion of the intrinsic polysilicon layer exposed in the trench region of the mask layer (i.e., the region where the future first doped portion 31 or second doped portion 32 is located) reacts with the dopant source (such as a boron source / phosphorus source) to generate a doped source glass layer (BSG / PSG), which covers the intrinsic polysilicon layer. Annealing allows dopant atoms to diffuse from the glass layer into the underlying intrinsic polysilicon layer, forming a heavily doped polysilicon region, i.e., forming the first doped portion 31 and the second doped portion 32. The crystal structure of the first doped portion 31 and the second doped portion 32 remains polysilicon. The intrinsic polysilicon layer is covered by the mask layer 6 in the isolation region (i.e., the region where the future isolation portion 33 is located), and does not contact the dopant source, so no doping reaction occurs, resulting in the final isolation portion 33 being entirely intrinsic polysilicon. Alternatively, a small number of dopant atoms may enter the underlying intrinsic polysilicon layer from the mask layer 6, forming lightly doped polysilicon, resulting in a portion of the final isolation portion 33 being intrinsic polysilicon.

[0105] In embodiments where the isolation portion 33 is an intrinsic amorphous silicon layer, in the manufacturing process of the back-contact solar cell used in this application, the silicon material layer deposited on the tunneling layer 2 is typically an amorphous silicon layer in the initial stage of deposition. A mask layer 6 is first deposited on the intrinsic amorphous silicon layer, followed by a first high-temperature annealing. This mask layer 6 serves not only as a patterning mask for subsequent doping but also as a thermal insulator and hydrogen diffusion barrier during the first annealing. This results in the region of the intrinsic amorphous silicon layer covered by the mask layer 6 corresponding to the isolation portion 33 having its solid-state crystallization process suppressed or delayed due to partial blockage of heat transfer and restriction of hydrogen atoms used to promote the ordering and passivation of intrinsic amorphous silicon. Therefore, after the first annealing, the portion of the intrinsic amorphous silicon layer exposed to the trench region of the mask layer 6 (i.e., the region where the future first doped portion 31 or second doped portion 32 is located) is directly heated and completely crystallizes into intrinsic polycrystalline silicon. The region of the intrinsic amorphous silicon layer covered by the mask layer 6 and corresponding to the isolation portion 33 may only have a partially crystalline surface, while the interior or the whole may still retain an amorphous state, forming an intrinsic amorphous silicon / microcrystalline silicon composite structure, that is, part of the isolation portion 33 is an intrinsic amorphous silicon layer.

[0106] In some embodiments, the width of the isolation portion 33 in a first direction is greater than or equal to 10 micrometers and less than or equal to 500 micrometers. This first direction is the direction in which the first doped portion 31, the isolation portion 33, and the second doped portion 32 are arranged sequentially. Preferably, the width of the isolation portion 33 in the first direction is greater than or equal to 20 micrometers and less than or equal to 200 micrometers; more preferably, the width of the isolation portion 33 in the first direction is greater than or equal to 50 micrometers and less than or equal to 150 micrometers.

[0107] In the doping process, dopant atoms (such as boron and phosphorus) undergo a certain degree of lateral diffusion. If the width of the isolation portion 33 in the first direction is too small, the lateral diffusion edges of adjacent first doped portions 31 and second doped portions 32 may overlap, leading to a decrease in the effective resistivity of the isolation portion 33, or even the formation of local conductive channels, causing electrical short circuits or leakage failures. To avoid this situation, this application ensures the electrical isolation reliability of the isolation portion 33 by making the width of the isolation portion 33 in the first direction greater than or equal to 10 micrometers. Furthermore, by making the width of the isolation portion 33 in the first direction less than or equal to 500 micrometers, it avoids the isolation portion 33 being too wide, resulting in a large dead zone area and a reduced effective power generation area, thereby reducing the short-circuit current and final conversion efficiency of the battery. Preferably, by making the width of the isolation portion 33 in the first direction greater than or equal to 20 micrometers and less than or equal to 200 micrometers, or greater than or equal to 50 micrometers and less than or equal to 150 micrometers, the battery can achieve higher current output and conversion efficiency while ensuring high isolation reliability.

[0108] In some embodiments, the mask layer 6 includes one or more combinations of silicon oxide layer, silicon oxynitride layer, and silicon nitride layer.

[0109] In some embodiments, the thickness of the mask layer 6 is greater than or equal to 20 nanometers and less than or equal to 500 nanometers; preferably, it is greater than or equal to 50 nanometers and less than or equal to 300 nanometers; more preferably, it is greater than or equal to 80 nanometers and less than or equal to 200 nanometers.

[0110] The mask layer 6 serves as a dense physical and chemical barrier during the doping process, preventing dopant source atoms (such as boron and phosphorus) from penetrating into the underlying silicon material in the region where the future isolation portion 33 is located. Based on this, by making the thickness of the mask layer 6 greater than or equal to 20 nanometers, this application avoids the problems of discontinuities or microscopic defects that can easily occur during the formation of the mask layer 6 due to its insufficient thickness. This ensures effective blocking of dopant atom diffusion during the doping process, preventing accidental doping of the isolation portion 33 and electrical isolation failure. Simultaneously, by making the thickness of the mask layer 6 less than or equal to 500 nanometers, not only can the mask quality (such as uniformity and density) be avoided due to excessive thickness, but the film stress can also be strictly controlled within a safe range. Preferably, by making the thickness of the mask layer 6 greater than or equal to 50 nanometers and less than or equal to 300 nanometers, or greater than or equal to 80 nanometers and less than or equal to 200 nanometers, a better balance can be achieved between reliability, process compatibility, and minimizing stress risk.

[0111] In some embodiments, such as Figure 1 As shown, the back-contact solar cell also includes a passivation layer 5, a first electrode 41, and a second electrode 42. The passivation layer 5 is disposed on the surface of the doped layer 3 away from the silicon substrate 1, and has a first opening region exposing the first doped portion 31 and a second opening region exposing the second doped portion 32. The first electrode 41 is electrically connected to the first doped portion 31 through the first opening region, and the second electrode 42 is electrically connected to the second doped portion 32 through the second opening region.

[0112] Furthermore, in some embodiments, the passivation layer 5 includes a passivation film and an antireflection film disposed on the surface of the passivation film away from the silicon substrate 1. The passivation film may include, for example, an aluminum oxide layer to provide field-effect passivation. The passivation film may also include, for example, a silicon nitride layer, or a stack of silicon oxide and silicon nitride layers, or a multilayer dielectric film stack consisting of alternating silicon oxide and silicon nitride layers, to reduce reflection loss when light is emitted from the silicon substrate 1 to the back surface and enhance the back field reflection effect.

[0113] In some embodiments, such as Figure 2 As shown, the mask layer 6 includes a first mask layer 61 and a second mask layer 62 stacked along a direction away from the silicon substrate 1, wherein the first mask layer 61 includes a silicon oxide layer; and the second mask layer 62 includes one or more combinations of a silicon nitride layer and a silicon oxynitride layer.

[0114] The first mask layer 61 (silicon oxide layer) can be generated in situ through thermal oxidation. It can be used directly as a mask layer. For example, in the manufacturing process of the back contact solar cell adopted in this application, during the first high-temperature annealing process, an oxygen-containing atmosphere is introduced to cause thermal oxidation on the surface of the silicon material layer, resulting in the in-situ growth of a dense silicon oxide film. The second mask layer 62 is, for example, one or more combinations of silicon nitride and silicon oxynitride layers pre-deposited on the surface of the silicon material layer by chemical vapor deposition (such as LPCVD, PECVD) before the first high-temperature annealing. That is, the second mask layer 62 is deposited first, and then the first mask layer 61 is grown in situ beneath it during high-temperature annealing.

[0115] During high-temperature annealing, the second mask layer 62 can serve as a source of hydrogen atoms (H), which diffuse to the interface below, further passivating defects and improving the overall passivation effect. Moreover, the second mask layer 62 has low thermal conductivity, which can affect the heat distribution of the underlying silicon material layer during annealing, thereby controlling the crystallization process of amorphous silicon into polycrystalline silicon and optimizing grain size and orientation.

[0116] The first mask layer 61 and the second mask layer 62 are complementary in material properties. The first mask layer 61 has excellent interface passivation quality, significantly improving the open-circuit voltage, while the second mask layer 62 has higher density and hydrogen passivation capability. The combination of the two achieves a dual physicochemical barrier to the diffusion of dopant atoms. The diffusion coefficients of the first mask layer 61 and the second mask layer 62 for boron and phosphorus are extremely low, especially during high-temperature annealing and subsequent doping processes, ensuring that the doping concentration of the isolation part 33 is lower than that of the first doped part 31 and the second doped part 32. A planarized intrinsic isolation part can be achieved without any trench etching, completely eliminating the risk of mechanical microcracks and optical losses caused by etching thinning.

[0117] like Figure 3 As shown, the surfaces of the first doped portion 31 and the second doped portion 32 facing away from the silicon substrate 1 are textured 311; the surface of the mask layer 6 facing away from the silicon substrate 1 is smooth 6a. During the fabrication of the back-contact solar cell, a micro-textured structure with a random pyramid shape (also known as the base of the pyramid) is formed on the back side of the silicon substrate 1 through chemical etching, i.e., a textured surface is formed on the back side of the silicon substrate 1. Since the tunneling layer 2 is relatively thin, it replicates and covers the textured morphology of the silicon substrate 1. The subsequently deposited polycrystalline silicon layer and mask layer 6, as thin film materials, also exhibit conformal growth. They continue to replicate the textured morphology of the tunneling layer 2, ultimately forming a surface as shown in the image. Figure 3 The textured surface 311 is shown. Therefore, the surfaces of the first doped portion 31 and the second doped portion 32 subsequently formed that face away from the silicon substrate 1 can be formed as textured surface 311. Textured surface 311 is used to increase the contact area with the electrodes.

[0118] The smooth surface 6a refers to a flat surface with a surface roughness lower than that of the textured surface 311. The smooth surface 6a is used to provide a uniform passivation interface. In some embodiments, after surface chemical etching (such as alkaline etching) of the silicon substrate 1, a textured surface is formed simultaneously on both the front and back sides of the silicon substrate 1, at which point the entire surface of the silicon substrate is textured. Then, a tunneling layer 2, a polysilicon layer, and a mask layer 6 are sequentially deposited on the back side of the silicon substrate 1, and after high-temperature annealing, trenching, and doping reactions, doped source glass layers (BSG / PSG) are formed in the regions of the polysilicon layer corresponding to the first doped portion 31 and the second doped portion 32, respectively. During this process, the mask layer 6 completely covers the region of the polysilicon layer corresponding to the future isolation portion 33, protecting this region from doping or minimal doping.

[0119] After the doping reaction is completed to form the doped layer 3, the films on the front side of the silicon substrate 1 are removed to expose the front side of the silicon substrate 1. Then, the front side of the silicon substrate 1 is texturized and cleaned. The cleaning process is also used to form a smooth surface 6a on the surface of the mask layer 6 away from the silicon substrate 1. This cleaning process can isotropically and controllably etch the mask layer 6 to remove the sharp tips of the textured structure of the mask layer 6, reduce the surface roughness, and thus form a smooth surface 6a on the surface of the mask layer 6 away from the silicon substrate 1.

[0120] By making the surface of the first doped portion 31 and the second doped portion 32 of the doped layer 3, which faces away from the silicon substrate 1, a textured surface 311 is formed. This electrically increases the effective contact area between the electrode and the semiconductor, thereby reducing the metal-semiconductor contact resistance and improving the absorption of long-wavelength light. At the same time, by making the surface of the mask layer 6, which faces away from the silicon substrate 1, a smooth surface 6a is formed. The flat surface facilitates the deposition of a uniform, dense, high-quality passivation film, achieving the best surface passivation effect and reducing carrier recombination in this region.

[0121] As another technical solution, please refer to Figure 4 The method for fabricating a back-contact solar cell provided in this application includes:

[0122] S101. A tunneling layer and a silicon material layer are sequentially deposited on the back side of a silicon substrate;

[0123] S102, Perform the first annealing treatment;

[0124] S103. Perform a first doping treatment and a second doping treatment on the first preset region and the second preset region of the silicon material layer respectively to form a first doped region and a second doped region.

[0125] The first doped portion and the second doped portion have opposite conductivity types, and an isolation portion is formed between the first doped portion and the second doped portion.

[0126] In step S101, as Figure 5As shown, a tunneling layer 2 and a silicon material layer 3a are sequentially deposited on the back side of a silicon substrate 1. The silicon material layer 3a can be an amorphous silicon layer or a polycrystalline silicon layer, which is used to convert it into doped polycrystalline silicon in subsequent steps, serving as a key layer for passivation contacts and carrier transport.

[0127] Traditional fabrication methods involve directly performing high-temperature doping diffusion (such as boron diffusion or phosphorus diffusion) after depositing the silicon material layer 3a. However, traditional doping processes (including dopant source reaction and propagation) require high temperatures for two purposes: first, to drive dopant atoms through the tunneling layer 2 into the silicon substrate 1 to form an effective doped junction; and second, to achieve sufficient doping concentration within the silicon material layer 3a to form an ohmic contact. However, the high-temperature process causes redistribution of the preceding dopant atoms, easily leading to PN junction failure. Lateral diffusion of dopant atoms is severe at high temperatures, necessitating deep trenches for physical isolation, which is complex and damages the material.

[0128] To address this issue, this application employs a first annealing treatment (step S102) followed by a doping reaction (step S103). This annealing process optimizes the quality of the tunneling layer 2 and the silicon material layer 3a. High-temperature annealing (e.g., >1000℃) is performed in a dopant-free environment. This high-temperature process completes the defect repair and densification of the tunneling layer 2 in a single step, controllably forming an ideal nanoporous structure conducive to carrier tunneling. Simultaneously, this step allows the silicon material layer 3a to fully crystallize, completing the transformation from amorphous silicon to polycrystalline silicon. After this high-temperature pretreatment, the functional objective of the subsequent doping reaction (step S103) is simplified to re-doping only the already crystallized polycrystalline silicon layer. Since the tunneling layer 2 has been pre-prepared, the doping atoms no longer need high temperatures to penetrate or modify the tunneling layer 2, nor do they need high temperatures to drive them deeper into the silicon substrate (inward expansion). Therefore, the temperature of the doping process can be safely and significantly reduced, for example from >950℃ in conventional processes to <920℃, or even <870℃.

[0129] Based on the above principles, lowering the temperature of subsequent doping reactions brings the following technical benefits: First, at low temperatures (e.g., <920℃), the chemical attack activity of dopant atoms such as boron on the tunneling oxide layer is greatly suppressed, thus preserving the high-quality interface formed by the initial high-temperature annealing, ensuring a good surface passivation effect, and directly contributing to the improvement of the battery open-circuit voltage. Moreover, the low temperature greatly suppresses the diffusion rate of dopant atoms in both the lateral and longitudinal directions. Second, the formed doped source glass layer (e.g., BSG) can effectively block the penetration of opposite-type dopants (e.g., phosphorus) in subsequent low-temperature processing. Due to the low temperature, subsequent doping atoms do not have sufficient energy to break through the previously formed glass layer, thus completely avoiding the performance compensation failure of the PN junction caused by cross-diffusion. This greatly broadens the process sequence and temperature parameter window for boron and phosphorus expansion, significantly improving production stability and yield.

[0130] This application employs a process flow of first high-temperature annealing to shape the interface, followed by low-temperature doping to complete the functionality, thereby safely reducing the subsequent doping temperature. This decoupled design not only resolves the fundamental contradiction between high interface quality and reliable doping in back-contact solar cells, but also simultaneously achieves trenchless isolation and compensation-free doping. This improves cell conversion efficiency while simplifying the process flow, reducing manufacturing costs, and increasing product yield.

[0131] In some embodiments, the temperature of the first annealing treatment is greater than or equal to 1000°C and less than or equal to 1200°C; the duration of the first annealing treatment is greater than or equal to 10 minutes and less than or equal to 3 hours.

[0132] In some embodiments, such as Figure 6 As shown, step S103 above, namely, performing a first doping treatment and a second doping treatment on the first and second preset regions of the silicon material layer, respectively, includes:

[0133] S1031. Under heating conditions, the first doped source reacts with the first preset region of the silicon material layer to form a first doped source glass layer;

[0134] S1032. Under heating conditions, the second doped source reacts with the second preset region of the silicon material layer to form a second doped source glass layer;

[0135] S1033. Perform a second annealing process to allow doped atoms to enter the underlying silicon material layer from the first doped source glass layer and the second doped source glass layer, so as to form the first doped portion and the second doped portion of the doped layer in the first preset region and the second preset region, respectively.

[0136] In some embodiments, the back-contact solar cell fabrication method provided in this application further includes, after depositing the silicon material layer 3a:

[0137] A mask layer 6 is formed on the surface of the silicon material layer 3a that is away from the substrate 1.

[0138] In some examples, such as Figure 7 As shown, the above steps can be the same as step S102, that is, while performing the first annealing process, a first mask layer 61 is formed on the surface of the silicon material layer 3a facing away from the substrate 1. That is, the mask layer 6 is composed of the first mask layer 61, which includes a silicon oxide layer.

[0139] In other examples, such as Figure 8As shown, the above steps can also be performed before step S102, that is, a second mask layer 62 is first formed on the surface of the silicon material layer 3a facing away from the substrate 1, followed by a first annealing process. The second mask layer 62 includes, for example, one or more combinations of silicon nitride and silicon oxynitride layers. In this example, the surface of the silicon material layer 3a facing away from the substrate 1 is not oxidized during the annealing process. Compared to the previous embodiment, this embodiment omits the in-situ thermal oxidation step and relies on the pre-deposited second mask layer 62 as the sole mask and passivation layer, achieving further process simplification.

[0140] In some other examples, such as Figure 9 As shown, the above steps can also involve forming a second mask layer 62 on the surface of the silicon material layer 3a away from the substrate 1 before performing the first annealing process; and forming a first mask layer 61 between the surface of the silicon material layer 3a away from the substrate 1 and the second mask layer 62 during the first annealing process, with the first mask layer 61 and the second mask layer 62 constituting the mask layer 6.

[0141] The aforementioned second mask layer 62 can be formed, for example, by depositing the tunneling layer 2 and the silicon material layer 3a (typically amorphous silicon) without breaking the vacuum or within the same equipment chamber, via chemical vapor deposition (such as LPCVD or PECVD) on the surface of the silicon material layer 3a facing away from the substrate 1. This step uses a relatively low deposition temperature (e.g., approximately 700-800°C for LPCVD) to ensure that the silicon material layer 3a remains amorphous.

[0142] As described above, the first mask layer 61 is formed by oxidation on the surface of the silicon material layer 3a away from the silicon substrate 1 during annealing. Specifically, in the thermal field of the first high-temperature annealing (>1000℃), an oxygen-containing atmosphere (such as oxygen or water vapor) is introduced to induce silicon atoms on the surface of the silicon material layer 3a (usually amorphous silicon or microcrystalline silicon at this time) to react with oxygen, thereby growing a silicon oxide film in situ (i.e., the first mask layer 61). This oxidation reaction occurs directly on the surface of the silicon material layer 3a (the future polycrystalline silicon layer). Silicon atoms participate in the reaction directly from the lattice, and the generated silicon oxide has a low interface state density and excellent lattice compatibility with the underlying silicon material layer 3a, which cannot be achieved by other deposition methods (such as PECVD, ALD). At a high temperature of >1000℃, the oxidation reaction rate is moderate and controllable, and the generated silicon oxide film has high density, few defects, and stable electrical properties. At the same time, the high temperature is conducive to the diffusion and annihilation of reaction byproducts (such as interstitial atoms), further ensuring the quality of the film. This high-temperature oxidation process occurs simultaneously with the solid-phase crystallization process of silicon material layer 3a from an amorphous state to a polycrystalline state. During the crystallization process below, silicon oxide plays a role in stress regulation and interface stabilization.

[0143] It should be noted that in the above steps, the mask layer 6 completely covers the surface of the silicon material layer 3a facing away from the substrate 1. In the fabrication process of the back contact solar cell, before forming the first doped portion and the second doped portion respectively, the mask layer 6 needs to be selectively grouted. This grooving step is the step of defining the doped portion and realizing the mask patterning function. After completing the grooving step, the mask layer 6 only covers the area of ​​the silicon material layer 3a corresponding to the future isolation portion.

[0144] When forming the doped pattern, the mask layer 6 only covers the region of the silicon material layer 3a corresponding to the isolation portion 33. In the subsequent doping step (i.e., step S103), its dielectric properties (such as silicon oxide, silicon nitride, silicon oxynitride, or a stack thereof) can effectively prevent the dopant source gas or paste from contacting the underlying silicon material, thereby preventing dopant atoms from entering this region. Therefore, the isolation portion 33 can maintain an intrinsic or extremely low doping concentration, forming a high-resistance region (i.e., isolation portion 33) between the first doped portion 31 and the second doped portion 32, achieving reliable electrical isolation. This method does not require any thinning etching of the silicon substrate 1, completely eliminating the risk of local mechanical strength reduction and microcracks caused by trenches, and fundamentally avoiding complex trench etching processes.

[0145] As described above, before forming the first doped portion and the second doped portion respectively, selective grooving is required on the mask layer 6. In embodiments where the mask layer 6 includes the first mask layer 61, before step S1031, i.e., the step of forming the first doped source glass layer, the following is also included:

[0146] like Figure 10 As shown, a groove is made in the portion of the first mask layer 61 corresponding to the first preset area 611 to expose the silicon material layer 3a in the first preset area 611.

[0147] Then perform step S1031 as described above, such as Figure 11 As shown, the silicon material layer 3a exposed in the first preset area is doped with a first conductivity type. This first conductivity type is, for example, N-type. The doping step specifically involves placing the silicon substrate 1 into a quartz boat within a horizontal or vertical diffusion furnace tube. The furnace temperature is raised to a predetermined reaction temperature, and a reaction gas is introduced. Specifically, the phosphorus source includes phosphorus oxychloride, which is carried into the furnace tube by a carrier gas. The oxidant is oxygen. Under heating and in the presence of oxygen, phosphorus oxychloride undergoes decomposition and oxidation reactions on the exposed polycrystalline silicon surface, generating phosphorus pentoxide and the byproduct chlorine gas. The phosphorus pentoxide then reacts with the silicon, resulting in the in-situ growth of a phosphosilicate glass (PSG) film on the exposed polycrystalline silicon layer 3a. Figure 11 The first doped source glass layer 31a is shown.

[0148] Similarly, in step S1032, that is, before the step of forming the second doped source glass layer, the following is also included:

[0149] like Figure 12 As shown, a groove is made in the portion of the first mask layer 61 corresponding to the second preset region 612 to expose the silicon material layer 3a in the second preset region 612.

[0150] Then perform step S1032 as described above, such as Figure 13 As shown, the silicon material layer 3a exposed in the second preset region 612 is doped with a second conductivity type opposite to the first conductivity type. This second conductivity type is, for example, P-type. After completing step S1032, a borosilicate glass (BSG) thin film is grown in situ on the surface of the silicon material layer 3a in the second preset region 612, i.e. Figure 13 The second doped source glass layer 32a is shown. Its growth process is similar to step S1031 described above, and will not be repeated here.

[0151] Precise patterning ensures that dopants (boron or phosphorus) are introduced only into the designated areas. This results in clear and accurate boundaries between the formed N-type and P-type doped regions, forming the basis for a high-performance back-contact PN junction and directly determining the battery's parallel resistance and leakage current levels. Furthermore, by employing a phosphorus (PSG) followed by boron (BSG) doping sequence (based on phosphorus's higher solid solubility in silicon and the need for heavier doping first), the subsequent low-temperature boron diffusion does not significantly compensate for the previously formed N-type doped region. This is because the first doping source glass layer 31a itself is an excellent diffusion barrier layer, preventing boron from effectively penetrating at low temperatures.

[0152] Specifically, the selective trenching steps for the first mask layer 61 are as follows: A layer of photoresist is spin-coated onto the back side of the silicon substrate that has undergone its first high-temperature annealing and formed the first mask layer 61. Ultraviolet light exposure is performed using a mask with a pattern defined as the first preset area 611. The mask is designed such that only the portion corresponding to the first preset area 611 is a light-transmitting area, while the portions corresponding to the second preset area 612 and the third preset area (located between the first preset area 611 and the second preset area 612) are light-shielding areas. The exposed (positive) or unexposed (negative) photoresist is removed using a chemical developer, thereby forming a window on the photoresist layer that matches the pattern of the first preset area 611. At this point, the photoresist above the first preset area 611 is removed, exposing the first mask layer 61 (which is now a continuous thin film) in that area; the second preset area 612 and the third preset area remain covered and protected by the photoresist.

[0153] Then, the silicon substrate is placed in a dry etching machine (such as reactive ion etching, RIE). Using an etching gas with high selectivity for silicon oxide (typically a fluorine-containing gas), the first mask layer 61 exposed from the photoresist window is etched away. The etching stops when the surface of the underlying silicon material layer 3a (polysilicon) is detected. At this point, the silicon material layer 3a in the first preset region 611 is exposed, while the first mask layer 61 beneath the second preset region 612 and the third preset region remains intact due to the photoresist protection. Ashing and wet cleaning are used to thoroughly remove residual photoresist and its byproducts, resulting in a clean, patterned surface. Afterwards, step S1031 (forming the first doped source glass layer 31a) is performed. After completing step S1031, as... Figure 12 As shown, the portion of the first mask layer 61 corresponding to the second preset area 612 is slotted. The specific process is similar to that of slotting the portion of the first mask layer 61 corresponding to the first preset area 611, and will not be described in detail here.

[0154] Furthermore, in traditional processes, high-temperature annealing (enhancing passivation) and high-temperature doping (which easily leads to boron attack on tunneling layer 2 and phosphorus-boron compensation) cannot be simultaneously achieved. This application addresses this by performing a second annealing process in step S1033, ensuring the maximum temperature is lower than the first annealing process (i.e., step S102), such as <950℃ or even <900℃. At this temperature, dopant atoms (boron or phosphorus) can effectively diffuse from the glass layer (BSG / PSG) into the underlying crystallized polycrystalline silicon layer 3a, forming heavily doped first doped portion 31 and second doped portion 32, completing the ohmic contact fabrication. The low-temperature annealing avoids the severe attack of boron on the underlying tunneling oxide layer at high temperatures, protecting the high-quality interface optimized in step S102. The low-temperature annealing significantly reduces the rate at which dopant atoms diffuse (inward) through tunneling layer 2 into the silicon substrate 1, reducing Auger recombination. Simultaneously, atoms from subsequent doping steps are less likely to penetrate the heavily doped glass layer formed in the preceding steps, effectively preventing the electrical properties of the first and second doped portions from canceling each other out due to cross-diffusion. Under low-temperature annealing, the lateral diffusion ability of doped atoms is very weak. Combined with the blocking effect of mask layer 6, trenchless electrical isolation between the first doped part 31 and the second doped part 32 is easily achieved.

[0155] It should be noted that steps S1031 and S1032 only include the doping reaction step (doping-free propulsion / diffusion), and then an annealing process (doping propulsion / diffusion) is performed in step S1033 to allow dopant atoms to enter the underlying silicon material layer from the first doping source glass layer 31a and the second doping source glass layer 32a. That is, an annealing step is specifically set after the two doping steps, thereby finally forming the desired shape. Figure 14The doped layer 3 shown includes a first doped portion 31, a second doped portion 32, and an isolation portion 33 located between them. This embodiment decouples the doping reaction from the physical processes of doping propagation / diffusion in time. Specifically, a dopant gas is first introduced at a relatively low temperature (e.g., 700-850°C) primarily for chemical reaction to form a doped source glass layer (PSG / BSG) on the exposed silicon surface, rather than for deep diffusion. At this stage, the dopant is mainly enriched in the glass layers. Then, after all glass layers have formed, a uniform annealing process is performed at a potentially higher temperature (e.g., 850-950°C). The core purpose of this step is to use the high temperature to drive the doped atoms in both glass layers to diffuse downwards simultaneously, completing the junction formation.

[0156] However, the embodiments of this application are not limited to this. In other embodiments, the first doping process and the second doping process in step S103 above may include not only the doping reaction, which reacts the dopant source with the silicon material layer to form a doped source glass layer, but also annealing (doping propulsion / diffusion), which allows dopants to move from the doped source glass layer into the underlying silicon material layer, thereby forming a P-type doped region or an N-type doped region. That is, the doping reaction and doping propulsion / diffusion are completed in the same step, i.e., the formation of the first doped portion 31 or the second doped portion 32 is completed in one step.

[0157] In steps S1032 to S1033 above, the mask layer 6 covers the portion of the silicon material layer 3a corresponding to the third preset region located between the first preset region 6a and the second preset region 6b, so that subsequent dopants can only interact with the portion of the silicon material layer 3a exposed in the first preset region 6a and the second preset region 6b. The coverage of the portion of the silicon material layer 3a corresponding to the third preset region by the mask layer 6 can prevent this portion from receiving high concentrations of doping in subsequent doping steps, thereby creating conditions for it to become an intrinsic isolation region (i.e., the aforementioned isolation portion 33).

[0158] In the third preset region, the first mask layer 61 remains intact and ungrooved. As a capping layer, it allows the subsequently introduced dopant source gas to directly contact and react with the exposed silicon material layer 3a through the grooved "window," thereby generating a doped source glass layer (BSG / PSG) in situ. In the ungrooved third preset region, the intact first mask layer 61 acts as a dense chemical and physical barrier, effectively preventing the dopant source gas from contacting the underlying silicon material layer 3a, thus preventing or reducing doping reactions in the silicon material layer 3a within the third preset region. During subsequent low-temperature doping and propagation processes, the dopant atoms, due to their weak low-temperature diffusion ability and being blocked by the first mask layer 61, cannot penetrate into the silicon material layer 3a below the first mask layer 61. Therefore, an intrinsic isolation portion 33 is naturally formed between the first doped portion 31 and the second doped portion 32, replacing the traditional, destructive trench etching isolation method. The first mask layer 61 above the isolation section 33 is a silicon oxide layer, which can itself serve as a passivation layer. It has a low surface recombination rate, can protect the interface of the isolation section 33, and improve the overall passivation level.

[0159] Similar to the grooving steps used in the embodiment where the mask layer 6 includes a first mask layer 61, if the mask layer 6 includes such... Figure 9 The first mask layer 61 and the second mask layer 62 shown need to be slotted each time a slot is made, so that the silicon material layer 3a in the first preset area 611 and the second preset area 612 can be exposed respectively.

[0160] In some embodiments, the second mask layer 62 includes an intrinsic amorphous silicon layer or an intrinsic polycrystalline silicon layer.

[0161] In other embodiments, the second mask layer 62 includes an amorphous silicon layer or a polycrystalline silicon layer containing doped elements; and the doping concentration of the doped elements is less than the doping concentration of the same doped elements contained in the first doped portion 31 or the second doped portion 32.

[0162] In some embodiments, the second mask layer 62 is formed in the same apparatus as the silicon material layer 3a. Both the silicon material layer 3a (typically amorphous or polycrystalline silicon) and the second mask layer 62 (such as intrinsic / lightly doped amorphous silicon, polycrystalline silicon, or one or more combinations of silicon nitride and silicon oxynitride layers) can be deposited using low-pressure chemical vapor deposition (LPCVD). This is the physical basis for achieving "formation in the same apparatus." The key to the continuity of in-situ deposition is continuous deposition without breaking the vacuum. After the silicon material layer 3a is deposited, the reaction chamber is not opened, and the silicon substrate is not exposed to the atmosphere. The system is evacuated, purified, and then directly introduced with the fresh reaction gas required for depositing the second mask layer 62, and the growth of the second mask layer 62 begins under optimized process conditions. This ensures an atomically clean, low-defect interface between the two functional layers. Furthermore, it avoids the silicon material layer 3a being exposed to the atmosphere during transfer to another apparatus, thus preventing the formation of a natural oxide layer or adsorption of contaminants on its surface. It also reduces the need for a separate deposition apparatus.

[0163] In some embodiments, the maximum temperature of the second annealing treatment is less than 1000°C; preferably, the maximum temperature of the second annealing treatment is greater than or equal to 700°C and less than or equal to 950°C; more preferably, the maximum temperature of the second annealing treatment is greater than or equal to 700°C and less than or equal to 900°C.

[0164] In some embodiments, the highest temperature used to form the first doped source glass layer 31a is greater than or equal to 700°C and less than or equal to 920°C; the highest temperature used to form the second doped source glass layer 32a is greater than or equal to 700°C and less than or equal to 920°C. Preferably, the highest temperature used to form the first doped source glass layer 31a is greater than or equal to 700°C and less than or equal to 830°C; the highest temperature used to form the second doped source glass layer 32a is greater than or equal to 700°C and less than or equal to 830°C.

[0165] In some embodiments, after step S103, i.e., the step of performing a first doping treatment and a second doping treatment on the first preset region and the second preset region of the silicon material layer respectively, the method further includes:

[0166] Remove the films on the front side of the silicon substrate 1 to expose the front side of the silicon substrate 1;

[0167] The front side of silicon substrate 1 is texturized and cleaned.

[0168] In embodiments where mask layer 6 includes a first mask layer 61 and a second mask layer 62, the cleaning process is further used to at least partially remove the second mask layer 62; or, to remove the second mask layer 62 and partially remove the first mask layer 61. In the case where the second mask layer 62 is at least partially removed, the final product retains the first mask layer 61, or retains both the first mask layer 61 and a portion of the second mask layer 62. In the case where the second mask layer 62 is removed and the first mask layer 61 is partially removed, the final product retains a portion of the first mask layer 61.

[0169] In embodiments where mask layer 6 includes a second mask layer 62, the cleaning process is further used to remove a portion of the second mask layer 62. The final product retains a portion of the second mask layer 62.

[0170] In embodiments where mask layer 6 includes a first mask layer 61, the cleaning process is further used to remove a portion of the first mask layer 61. The final product retains a portion of the first mask layer 61.

[0171] After completing all the key processes on the back side (two annealings, boron-phosphorus doping), the electrical structure of the battery (PN junction, passivation contact) is finalized on the back side. At this point, the parasitic film layers that grew along with the deposition process on the front side (such as tunneling layers, polycrystalline silicon, doped glass, etc.) become redundant and need to be removed to expose the original silicon substrate 1 on the front side. At the same time, the mask layer 6 on the back side, which has already completed its masking function, can be partially removed, which helps to form a smooth surface morphology, namely smooth surface 6a.

[0172] The back-contact solar cell fabrication method provided in this application embodiment, after completing the above step S103, at least further includes forming such a back-contact solar cell. Figure 1 or Figure 1 The steps of the passivation layer 5, the first electrode 41, and the second electrode 42 shown can be performed using conventional techniques in the art, and will not be described in detail here. For example... Figure 1 or Figure 2 As shown, the passivation layer 5 is disposed on the surface of the doped layer 3 away from the silicon substrate 1, and has a first opening region exposing the first doped portion 31 and a second opening region exposing the second doped portion 32; the first electrode 41 is electrically connected to the first doped portion 31 through the first opening region; the second electrode 42 is electrically connected to the second doped portion 32 through the second opening region.

[0173] Example embodiments have been disclosed herein, and while specific terminology has been used, it is for general illustrative purposes only and should not be construed as limiting. In some instances, it will be apparent to those skilled in the art that features, characteristics, and / or elements described in conjunction with particular embodiments may be used alone, or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless otherwise expressly indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the scope of this application as set forth by the appended claims.

Claims

1. A back-contact solar cell, characterized in that, include: A silicon substrate having a front side and a back side arranged opposite to each other; A tunneling layer is disposed on the back side of the silicon substrate; A doped layer is disposed on the surface of the tunneling layer opposite to the silicon substrate; the doped layer includes a first doped portion and a second doped portion, and an isolation portion located between the two, wherein the first doped portion and the second doped portion have opposite conductivity types. A mask layer is disposed on the surface of the isolation portion on the side opposite to the silicon substrate; The mask layer covers a local area of ​​the surface of the isolation portion facing away from the silicon substrate, and the ratio of the width of the mask layer in the first direction to the width of the isolation portion in the first direction is greater than or equal to 0.5 and less than or equal to 1. The first direction is the direction in which the first doped portion, the isolation portion and the second doped portion are arranged in sequence.

2. The back-contact solar cell according to claim 1, characterized in that, The doping concentration of the isolation section gradually decreases from the interface adjacent to the first doped section and the interface adjacent to the second doped section towards the center of the isolation section.

3. The back-contact solar cell according to claim 2, characterized in that, Some of the isolation portions are intrinsic amorphous silicon layers or intrinsic polycrystalline silicon layers.

4. The back-contact solar cell according to claim 1, characterized in that, The width of the isolation portion in the first direction is greater than or equal to 10 micrometers and less than or equal to 500 micrometers; or greater than or equal to 20 micrometers and less than or equal to 200 micrometers; or greater than or equal to 50 micrometers and less than or equal to 150 micrometers; the first direction is the direction in which the first doped portion, the isolation portion and the second doped portion are arranged in sequence.

5. The back-contact solar cell according to claim 1, characterized in that, The mask layer includes one or more combinations of silicon oxide layer, silicon oxynitride layer, and silicon nitride layer.

6. The back-contact solar cell according to claim 1, characterized in that, The thickness of the mask layer is greater than or equal to 20 nanometers and less than or equal to 500 nanometers; or greater than or equal to 50 nanometers and less than or equal to 300 nanometers; or greater than or equal to 80 nanometers and less than or equal to 200 nanometers.

7. The back-contact solar cell according to claim 1, characterized in that, The mask layer includes a first mask layer and a second mask layer stacked in a direction away from the silicon substrate, wherein the first mask layer includes a silicon oxide layer; and the second mask layer includes one or more combinations of a silicon nitride layer and a silicon oxynitride layer.

8. The back-contact solar cell according to claim 1, characterized in that, The surfaces of the first doped portion and the second doped portion facing away from the silicon substrate are textured; the surface of the mask layer facing away from the silicon substrate is smooth.

9. A method for fabricating a back-contact solar cell, characterized in that, include: A tunneling layer and a silicon material layer are sequentially deposited on the back side of a silicon substrate; Perform the first annealing treatment; The first and second preset regions of the silicon material layer are subjected to a first doping treatment and a second doping treatment, respectively, to form a first doped portion and a second doped portion; The first doped portion and the second doped portion have opposite conductivity types; an isolation portion is formed between the first doped portion and the second doped portion.

10. The method according to claim 9, characterized in that, The first and second preset regions of the silicon material layer are subjected to first doping treatment and second doping treatment, respectively, including: Under heating conditions, the first doped source reacts with the first preset region of the silicon material layer to form a first doped source glass layer; Under heating conditions, the second doping source reacts with the second preset region of the silicon material layer to form a second doping source glass layer; A second annealing process is performed to allow dopant atoms to enter the underlying silicon material layer from the first and second dopant source glass layers, thereby forming the first doped portion and the second doped portion in the first preset region and the second preset region, respectively.

11. The method according to claim 10, characterized in that, In the step of performing the first annealing process A first mask layer is formed by oxidation on the surface of the silicon material layer opposite to the silicon substrate; Prior to the step of forming the first doped source glass layer, the method further includes: A groove is made in the portion of the first mask layer corresponding to the first preset area to expose the silicon material layer in the first preset area; Prior to the step of forming the second doped source glass layer, the method further includes: A groove is made in the portion of the first mask layer corresponding to the second preset area to expose the silicon material layer in the second preset area.

12. The method according to claim 11, characterized in that, Prior to the first annealing step, the process also includes: A second mask layer is formed on the surface of the silicon material layer opposite to the silicon substrate; The first mask layer is located between the second mask layer and the silicon material layer; In the step of slotting the portion of the first mask layer corresponding to the first preset area, slots are made in both the first mask layer and the second mask layer. In the step of slotting the portion of the first mask layer corresponding to the second preset area, slots are made in both the first mask layer and the second mask layer.

13. The method according to claim 10, characterized in that, Prior to the first annealing step, the process also includes: A second mask layer is formed on the surface of the silicon material layer opposite to the silicon substrate; Prior to the step of forming the first doped source glass layer, the method further includes: The portion of the second mask layer corresponding to the first preset area is slotted to expose the first preset area; Prior to the step of forming the second doped source glass layer, the method further includes: The portion of the second mask layer corresponding to the second preset area is slotted to expose the second preset area.

14. The method according to claim 12 or 13, characterized in that, The second mask layer includes an intrinsic amorphous silicon layer or an intrinsic polycrystalline silicon layer; or, The second mask layer includes an amorphous silicon layer or a polycrystalline silicon layer containing doped elements; and the doping concentration of the doped elements is less than the doping concentration of the same doped elements contained in the first doped portion or the second doped portion.

15. The method according to claim 12 or 13, characterized in that, The second mask layer is formed in the same apparatus used to deposit the silicon material layer.

16. The method according to claim 9, characterized in that, The temperature of the first annealing treatment is greater than or equal to 1000℃ and less than or equal to 1200℃; the duration of the first annealing treatment is greater than or equal to 10 minutes and less than or equal to 3 hours.

17. The method according to claim 10, characterized in that, The maximum temperature of the second annealing treatment is less than 1000℃; or... The highest temperature of the second annealing treatment is greater than or equal to 700°C and less than or equal to 950°C; or, The maximum temperature of the second annealing process is greater than or equal to 700°C and less than or equal to 900°C.

18. The method according to claim 10, characterized in that, The highest temperature used to form the first doped source glass layer is greater than or equal to 700°C and less than or equal to 920°C; the highest temperature used to form the second doped source glass layer is greater than or equal to 700°C and less than or equal to 920°C. or, The highest temperature used to form the first doped source glass layer is greater than or equal to 700°C and less than or equal to 830°C; the highest temperature used to form the second doped source glass layer is greater than or equal to 700°C and less than or equal to 830°C.

19. The method according to claim 12, characterized in that, After the steps of performing the first doping treatment on the first preset region and the second preset region of the silicon material layer, respectively, the method further includes: Remove each film layer on the front side of the silicon substrate to expose the front side of the silicon substrate; The front side of the silicon substrate is texturized and cleaned. The cleaning process is further used to at least partially remove the second mask layer; or to remove the second mask layer and partially remove the first mask layer.

20. The method according to claim 13, characterized in that, After the steps of performing the first doping treatment on the first preset region and the second preset region of the silicon material layer, respectively, the method further includes: Remove each film layer on the front side of the silicon substrate to expose the front side of the silicon substrate; The front side of the silicon substrate is texturized and cleaned. The cleaning process is also used to remove part of the second mask layer.

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