Display device

Abstract

A display device according to one exemplary aspect of the present disclosure includes a substrate; a plurality of reflective electrodes disposed on the substrate; a plurality of bonding layers disposed on the plurality of reflective electrodes; a plurality of light emitting elements disposed on the plurality of bonding layers and each including a first electrode, a first semiconductor layer on the first electrode, an active layer on the first semiconductor layer, a second semiconductor layer on the active layer, and a second electrode on the second semiconductor layer; a plurality of scattering layers disposed to respectively correspond to the plurality of light emitting elements, configured to respectively cover the plurality of light emitting elements, and each having a shape with a cross-sectional width decreasing upward; and a black matrix configured to contact at least a portion of a side surface of each of the plurality of scattering layers and having a shape with a cross-sectional width increasing upward. Accordingly, a change in a luminance viewing angle distribution with respect to a transfer position of a light emitting element can be reduced or minimized.

Description

Technical Field

[0001] This disclosure relates to a display device, and more specifically, for example, but not limited to, a display device that can improve light extraction efficiency and maintain viewing angle characteristics even when the position of the light-emitting element is changed. Background Technology

[0002] As display devices used in computer monitors, televisions, mobile phones, etc., there are organic light-emitting displays (OLEDs) that are configured to emit light themselves and liquid crystal displays (LCDs) that require a separate light source.

[0003] The applications of display devices are diverse, ranging from computer monitors and televisions to personal mobile devices, and research is underway on display devices with large display areas and reduced size and weight.

[0004] Furthermore, display devices, including those using light-emitting diodes (LEDs), have recently attracted attention as next-generation display devices. Because LEDs are made of inorganic materials rather than organic materials, they are more reliable and have a longer lifespan than liquid crystal displays or organic light-emitting displays. In addition, LEDs can be quickly switched on and off, possess excellent luminous efficiency, high shock resistance, and high stability, and can display high-brightness images.

[0005] The descriptions provided in the Background section should not be assumed to be prior art simply because they are mentioned in or associated with the Background section. The Background section may include information describing one or more aspects of the subject matter art. Summary of the Invention

[0006] One objective of this disclosure is to provide a display device having improved light extraction efficiency.

[0007] Another objective of this disclosure is to provide a display device that minimizes brightness deviation with respect to viewing angle even when the position of the light-emitting element changes.

[0008] Another objective of this disclosure is to provide a display device in which the bonding layer corresponding to the light-emitting element is further miniaturized.

[0009] The purpose of this disclosure is not limited to the above-described purposes, and other purposes not mentioned above will be clearly understood by those skilled in the art from the following description.

[0010] A display device according to an exemplary aspect of this disclosure includes: a substrate; a plurality of reflective electrodes disposed on the substrate; a plurality of bonding layers disposed on the plurality of reflective electrodes; a plurality of light-emitting elements disposed on the plurality of bonding layers, each including a first electrode, a first semiconductor layer on the first electrode, an active layer on the first semiconductor layer, a second semiconductor layer on the active layer, and a second electrode on the second semiconductor layer; a plurality of scattering layers configured to correspond to the plurality of light-emitting elements respectively, configured to cover the plurality of light-emitting elements respectively, and each having a shape with an upwardly decreasing cross-sectional width; and a black dam configured to contact at least a portion of the side surface of each of the plurality of scattering layers, and having a shape with an upwardly increasing cross-sectional width. Therefore, the variation in the brightness viewing angle distribution with respect to the shifting position of the light-emitting elements can be reduced or minimized.

[0011] A display device according to another exemplary aspect of this disclosure includes: a substrate; a bonding layer disposed on the substrate; a light-emitting element disposed on the bonding layer and including a first electrode, a first semiconductor layer on the first electrode, an active layer on the first semiconductor layer, a second semiconductor layer on the active layer, and a second electrode on the second semiconductor layer; a planarization layer disposed below the active layer and configured to surround a lower portion of the first semiconductor layer; a scattering layer disposed on the planarization layer and configured to cover an upper portion of the first semiconductor layer, the active layer, the second semiconductor layer, and the second electrode, and a side surface of the scattering layer having a shape that slopes upward toward the light-emitting element; and a black dam configured to surround a side surface of the lower portion of the scattering layer, and a side surface of the black dam having a shape that slopes upward toward the light-emitting element. Therefore, the variation in the brightness viewing angle distribution with respect to the shift position of the light-emitting element can be reduced or minimized.

[0012] Further details of the exemplary embodiments are included in the detailed embodiments and the accompanying drawings.

[0013] In the display device disclosed herein, the scattering layer can be configured to cover the upper part of the light-emitting element, thereby improving the light extraction efficiency.

[0014] The light extraction efficiency of the display device disclosed herein is improved, enabling the display device to operate with lower power consumption.

[0015] In the display device of this disclosure, the scattering layer is formed above the black dam, so that the black dam can be formed in a self-aligned manner without positional error even without performing a separate patterning process.

[0016] The display device disclosed herein can reduce or minimize brightness deviation with respect to viewing angle.

[0017] The effects of this disclosure are not limited to the examples above, and many more different effects are included in this disclosure.

[0018] It should be understood that the foregoing general description and the following detailed description are exemplary and illustrative, and are intended to provide further explanation of the claimed inventive concept. Attached Figure Description

[0019] The accompanying drawings, which are included to provide a further understanding of this disclosure and are incorporated in and constitute a part of this application, illustrate embodiments of the disclosure and, together with the textual description, serve to explain the principles of the disclosure. The above and other aspects, features, and other advantages of this disclosure will become more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, wherein:

[0020] Figure 1 This is a schematic configuration diagram of a display device according to an embodiment of the present disclosure;

[0021] Figure 2 This is a top view of the pixels of a display device according to an exemplary embodiment of the present disclosure;

[0022] Figure 3 It is along Figure 2 A cross-sectional view taken by line A-A' in the diagram; and

[0023] Figures 4A to 4G This is a process diagram illustrating a method for manufacturing a sub-pixel of a display device according to an exemplary embodiment of the present disclosure.

[0024] Throughout the accompanying drawings and detailed description, unless otherwise stated, the same reference numerals should be understood to denote the same elements, features, and structures. For clarity, illustration, and convenience, the relative dimensions and depictions of these elements may be exaggerated. Detailed Implementation

[0025] Implementations of this disclosure will now be described in detail, examples of which are illustrated in the accompanying drawings. The described progression of processing steps and / or operations is merely illustrative; however, the order of steps and / or operations is not limited to that described herein and can be varied as is known in the art, except for steps and / or operations that must occur in a specific order. The names of the various elements used in the following description may be chosen solely for ease of writing the specification and may therefore differ from the names used in actual products.

[0026] The advantages and features of this disclosure, as well as methods for achieving these advantages and features, will become clear from the exemplary embodiments described in detail below with reference to the accompanying drawings. However, this disclosure is not limited to the exemplary embodiments disclosed herein, but will be implemented in various forms. Exemplary embodiments are provided by way of example only to enable those skilled in the art to fully understand the disclosure and scope of this disclosure.

[0027] The shapes (e.g., size, length, width, height, thickness, position, radius, diameter, and area), ratios, angles, quantities, etc., shown in the accompanying drawings used to describe exemplary embodiments of this disclosure are merely examples, and this disclosure is not limited thereto. Throughout the disclosure, the same reference numerals generally denote the same elements. Furthermore, in the following description of this disclosure, detailed descriptions of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of this disclosure. Terms such as “comprising,” “having,” and “consisting of” as used herein are generally intended to allow for the addition of other components, unless these terms are used in conjunction with the term “only.” Unless explicitly stated otherwise, references to the singular may also include the plural forms.

[0028] The term “exemplary” is used to indicate that something is used as an example or illustration. A particular aspect is an exemplary aspect. “Implementation,” “example,” “aspect,” etc., should not be construed as being preferred or advantageous over other implementations. Unless otherwise stated, an implementation, example, exemplary implementation, aspect, etc., may refer to one or more implementations, one or more examples, one or more exemplary implementations, one or more aspects, etc. Furthermore, the term “may” includes all the meanings of the term “can.”

[0029] Even if not explicitly stated, components are to be interpreted as including a normal error range. Any implementation described herein as an "example" is not necessarily to be construed as preferred or advantageous over other implementations.

[0030] When using terms such as “above,” “over,” “below,” and “next to” to describe the positional relationship between two parts, one or more parts may be located between the two parts unless these terms are used in conjunction with the terms “immediately adjacent” or “directly.”

[0031] When one element or layer is placed "on" another element or layer, the element or layer can be placed directly on top of the other element or layer, or another element or layer can be inserted in between.

[0032] Terms such as “below,” “lower,” “above,” and “upper” may be used herein to describe the relationships between elements as shown in the accompanying drawings. It should be understood that these terms are spatially relative and based on the orientations shown in the accompanying drawings.

[0033] When describing temporal relationships (e.g., when time sequence is described as such as "after", "following", "next", and "before"), discontinuous situations may be included unless more restrictive terms such as "just", "immediately", or "directly" are used.

[0034] Although the terms "first," "second," "A," "B," "(a)," and "(b)," etc., are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from others. Therefore, the first component mentioned below can be a second component in the technical concept of this disclosure.

[0035] The term “at least one” should be understood to include any and all combinations of one or more of the relevant listed items. For example, “at least one of the first element, the second element and the third element” means a combination of all three listed elements, a combination of any two of the three elements, and each individual element (i.e., the first element, the second element or the third element).

[0036] Throughout the disclosure, the same reference numerals generally denote the same elements.

[0037] The dimensions and thickness of each component shown in the accompanying drawings are illustrated for ease of description, and this disclosure is not limited to the dimensions and thickness of the components shown.

[0038] Features of the various embodiments of this disclosure can be combined or integrated with each other in part or in whole, and can be interlocked and operated in various technical ways, and these embodiments can be implemented independently or in association with each other.

[0039] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the exemplary embodiments pertain. It should also be understood that terms such as those defined in common dictionaries shall be interpreted as having a meaning consistent, for example, with their meaning in the context of the relevant field, and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein. For example, as one of ordinary skill in the art will understand, the terms “component” or “unit” may be applied to, for example, a single circuit or structure, an integrated circuit, a computational block of a circuit arrangement, or any structure configured to perform the described functions.

[0040] In the following, a display device according to an exemplary embodiment of the present disclosure will be described in detail with reference to the accompanying drawings.

[0041] Figure 1 This is a schematic configuration diagram of a display device according to an exemplary embodiment of the present disclosure.

[0042] For ease of description, Figure 1 Only the display panel PN, gating driver GD, data driver DD, and timing controller TC of the various components of the display device 100 are shown.

[0043] Reference Figure 1The display device 100 includes: a display panel PN, which includes a plurality of sub-pixels SP; a gating driver GD configured to provide various types of signals to the display panel PN; and a timing controller TC configured to control the gating driver GD and the data driver DD.

[0044] The gating driver GD responds to multiple gating control signals provided from the timing controller TC to provide multiple scan signals to multiple scan lines GL. Figure 1 The diagram illustrates a single gating driver GD positioned spaced apart from one side of the display panel PN. However, the number and arrangement of gating drivers GDs are not limited to this. As an example, two gating drivers GDs can be positioned spaced apart from two opposite sides of the display panel PN, but are not limited to this.

[0045] The data driver DD responds to multiple data control signals provided by the timing controller TC by converting image data input from the timing controller TC into a data voltage using a reference gamma voltage. The data driver DD can then supply the converted data voltage to multiple data lines DL.

[0046] The timing controller TC aligns the externally input image data and provides the image data to the data driver DD. The timing controller TC can generate gating control signals and data control signals using synchronization signals (i.e., an externally input dot clock signal, data enable signal, and horizontal / vertical synchronization signal). Furthermore, the timing controller TC can control the gating driver GD and the data driver DD by providing the generated gating control signals and data control signals to the gating driver GD and the data driver DD, respectively.

[0047] The display panel PN is configured to display an image to the user and includes multiple subpixels SP. In the display panel PN, multiple scan lines GL and multiple data lines DL intersect each other, and each of the multiple subpixels SP is connected to both scan lines GL and data lines DL. Furthermore, although not shown in the accompanying drawings, the multiple subpixels SP can be connected to high-potential power lines, low-potential power lines, reference lines, etc., respectively.

[0048] The display panel PN may have a display area AA and a non-display area NA. As an example, the non-display area NA may extend from the display area AA. As an example, the non-display area NA may be configured to completely or partially surround the display area AA, but is not limited thereto. As an example, the non-display area NA may be partially or completely invisible from the front side of the display panel PN, for example, by bending towards the rear side of the display panel PN, but is not limited thereto. As an example, the non-display area NA may be flat.

[0049] The display area AA is the area in the display device 100 where an image is displayed. The display area AA may include a plurality of sub-pixels SP constituting a plurality of pixels PX, and circuitry configured to operate the plurality of sub-pixels SP. The plurality of sub-pixels SP is the smallest unit constituting the display area AA. n sub-pixels SP can constitute one pixel PX. As an example, n can be an integer of 1 or greater. As an example, the n sub-pixels SP constituting one pixel PX may emit light of different colors, or at least two of the n sub-pixels SP may emit light of the same color, but are not limited thereto. As an example, a pixel PX may include the same number of sub-pixels SP or a different number of sub-pixels SP, but are not limited thereto. As an example, light-emitting elements, thin-film transistors for operating the light-emitting elements, etc., may be provided in each of the plurality of sub-pixels SP, but are not limited thereto. The plurality of light-emitting elements may be defined differently depending on the type of the display panel PN. For example, in the case where the display panel PN is an inorganic light-emitting display panel PN, the light-emitting element may be a light-emitting diode (LED) or a miniature light-emitting diode (miniature LED), but is not limited thereto.

[0050] Multiple signal lines for transmitting various types of signals to multiple sub-pixels SP are provided in the display area AA. For example, the multiple signal lines may include multiple data lines DL for providing data voltages to the multiple sub-pixels SP and multiple scan lines GL for providing gating voltages to the multiple sub-pixels SP. The multiple scan lines GL may extend in one direction within the display area AA and connect to the multiple sub-pixels SP. The multiple data lines DL may extend in the display area AA in a direction different from that direction and connect to the multiple sub-pixels SP. Furthermore, low-potential power lines, high-potential power lines, etc., may also be provided in the display area AA. However, this disclosure is not limited thereto.

[0051] The non-display area NA can be defined as an area where no image is displayed (i.e., the area extending from the display area AA). As an example, the non-display area NA may include, but is not limited to, link lines and pad electrodes for transmitting signals to sub-pixels SP in the display area AA. Alternatively, as an example, the non-display area NA may include driver ICs such as strobe driver ICs and data driver ICs, but is not limited to.

[0052] Meanwhile, the non-display area NA can be located on the rear surface of the display panel PN (i.e., the surface where no sub-pixels SP exist). Alternatively, the non-display area NA can be excluded. However, this disclosure is not limited to the configuration shown in the accompanying drawings.

[0053] Meanwhile, drivers such as the gate driver GD, data driver DD, and timing controller TC can be connected to the display panel PN in various ways. For example, the gate driver GD can be installed in the non-display area NA using the in-panel gate (GIP) method, or between multiple sub-pixels SP using the effective area gate (GIA) method in the display area AA. For example, the data driver DD and timing controller TC can be formed on separate flexible films and printed circuit boards, and electrically connected to the display panel PN by bonding the flexible film and printed circuit board to pad electrodes formed in the non-display area NA of the display panel PN. When the gate driver GD is installed using the GIP method and the data driver DD and timing controller TC transmit signals to the display panel PN through the pad electrodes in the non-display area NA, it is desirable to ensure sufficient area in the non-display area NA to accommodate the gate driver GD and the pad electrodes, which may increase the bezel size.

[0054] Alternatively, when the gate driver GD is mounted in the display area AA using the GIA method and side lines are formed to connect signal lines located on the front surface of the display panel PN to pad electrodes located on the rear surface of the display panel PN to bond the flexible film and printed circuit board to the rear surface of the display panel PN, the non-display area NA on the front surface of the display panel PN can be reduced or minimized. As an example, when the gate driver GD, data driver DD, and timing controller TC are connected to the display panel PN using the above method, a zero-bezel configuration with virtually no bezel can be achieved. The implementation is not limited to this. As an example, the gate driver GD can be formed separately on a separate film or a separate panel, and can be electrically connected to the display panel PN, for example, using tape auto-bonding (TAB), chip-on-glass (COG), chip-on-panel (COP), or chip-on-film (COF) methods, but is not limited thereto.

[0055] Multiple subpixels SP constitute a pixel. Furthermore, the multiple subpixels SP may include subpixels SP configured to emit light beams of various colors. For example, the multiple subpixels SP may include red subpixels, green subpixels, and blue subpixels. However, this disclosure is not limited thereto. The multiple subpixels SP may also include subpixels SP configured to emit light of another color (e.g., white, cyan, magenta, or yellow), but are not limited thereto.

[0056] As an example, at least some or all of the multiple sub-pixels SP may each include two light-emitting elements. In this case, the two light-emitting elements can emit light of the same color. For example, two light-emitting elements configured to emit red light can be placed in the red sub-pixel, two light-emitting elements configured to emit green light can be placed in the green sub-pixel, and two light-emitting elements configured to emit blue light can be placed in the blue sub-pixel. The implementation is not limited thereto. As an example, at least some or all of the multiple sub-pixels SP may each include one light-emitting element or three or more light-emitting elements. As an example, three or more light-emitting elements can emit light of the same color, but are not limited thereto. As an example, each of the multiple sub-pixels SP may include the same number of light-emitting elements or a different number of light-emitting elements, but is not limited thereto.

[0057] Figure 2 This is a top view of the pixels of a display device according to an exemplary embodiment of the present disclosure. Figure 3 It is along Figure 2 A cross-sectional view taken by line A-A' in the diagram. For example, Figure 2 This is an enlarged top view showing a portion of the pixels PX of a display device 100 according to an exemplary embodiment of the present disclosure. Furthermore, Figure 3 This is a cross-sectional view of a sub-pixel SP of a display device 100 according to an exemplary embodiment of the present disclosure.

[0058] Refer to together Figure 2 and Figure 3 A display device 100 according to an exemplary embodiment of the present disclosure may include a substrate 110, a buffer layer 111, a gate insulating layer 112, an interlayer insulating layer 113, a first planarization layer 114, a second planarization layer 115, a plurality of transistors TR, a plurality of light-emitting elements LED, a plurality of bonding layers BL, a plurality of reflective electrodes RE, a power line VL, a connection electrode CE, a plurality of scattering layers SL, and a black dam BB. The embodiments are not limited thereto. As an example, one or more of the above components may be omitted, or one or more additional components may be included.

[0059] First, the substrate 110 is an assembly for supporting the various components included in the display device 100, and may be made of an insulating material. For example, the substrate 110 may be made of glass, resin, etc., but is not limited thereto. In addition, the substrate 110 may include plastics such as polymers, and may be made of a flexible material or a rigid material.

[0060] A light-blocking layer LS may be disposed on the substrate 110. The light-blocking layer LS prevents light from entering the active layer ACT of the transistor TR, which will be described below, from the underside of the substrate 110. The light-blocking layer LS can prevent light from entering the active layer ACT of the transistor TR, thereby reducing or minimizing leakage current. As an example, the light-blocking layer LS may at least partially overlap with the active layer ACT of the transistor TR, but is not limited thereto. For example, the light-blocking layer LS may be omitted depending on the design.

[0061] Furthermore, a power line VL can be disposed on the substrate 110. Specifically, as an example, the power line VL can be disposed on the same layer as the light-blocking layer LS and spaced apart from the light-blocking layer LS, or it can be disposed on a different layer from the light-blocking layer LS. Furthermore, the power line VL can be made of the same material as the light-blocking layer LS. However, this disclosure is not limited thereto. The power line VL can be a low-potential power line. In this case, a low-potential voltage can be supplied to the power line VL. However, this disclosure is not limited thereto. The power line VL can be a high-potential power line. In this case, a high-potential voltage can be supplied to the power line VL.

[0062] A buffer layer 111 may be disposed on the power line VL and the light-blocking layer LS. The buffer layer 111 can reduce the penetration of moisture or impurities through the substrate 110. For example, the buffer layer 111 may be configured as a single layer or multiple layers made of silicon oxide (SiOx) or silicon nitride (SiNx). However, this disclosure is not limited thereto. However, depending on the type of substrate 110 or the type of transistor, the buffer layer 111 may not be included. However, this disclosure is not limited thereto. The buffer layer 111 may include contact holes for connecting the power line VL and the first reflective electrode RE1, which will be described below.

[0063] Multiple transistors TR can be disposed on buffer layer 111. Transistor TR may include active layer ACT, gate GE, source SE, and drain DE.

[0064] The active layer ACT can be disposed on the buffer layer 111. The active layer ACT can be made of semiconductor materials such as oxide semiconductors, amorphous silicon or polycrystalline silicon, compound semiconductors, organic semiconductors, etc. However, this disclosure is not limited thereto.

[0065] A gate insulating layer 112 may be disposed on the active layer ACT. The gate insulating layer 112 is an insulating layer used to insulate the active layer ACT and the gate GE. Therefore, the gate insulating layer 112 may be disposed only between the gate GE and the active layer ACT. However, this disclosure is not limited thereto. For example, the maximum width of the gate insulating layer 112 may be less than the maximum width of the active layer ACT. Alternatively, the gate insulating layer 112 may be disposed on the active layer ACT and completely overlap with the active layer ACT. Furthermore, the gate insulating layer 112 may be spaced apart from the source SE and drain DE, which will be described below. For example, the gate insulating layer 112 may be configured as a single layer or multiple layers made of silicon oxide (SiOx) or silicon nitride (SiNx). However, this disclosure is not limited thereto.

[0066] The gate GE may be disposed on the gate insulating layer 112. The gate GE may be made of a conductive material (e.g., copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof). However, this disclosure is not limited thereto.

[0067] Interlayer insulating layer 113 may be disposed on gate insulating layer 112 and gate GE. Interlayer insulating layer 113 may include contact holes for connecting source SE and active layer ACT, and / or contact holes for connecting drain DE and active layer ACT. Interlayer insulating layer 113 may be an insulating layer for protecting components disposed beneath interlayer insulating layer 113. Interlayer insulating layer 113 may be configured as a single layer or multiple layers made of silicon oxide (SiOx) or silicon nitride (SiNx). However, this disclosure is not limited thereto.

[0068] The source electrode SE and drain electrode DE, electrically connected to the active layer ACT, can be disposed on the interlayer insulating layer 113. The source electrode SE and drain electrode DE can be disposed on the same layer and spaced apart from each other, but are not limited thereto. The source electrode SE can be connected to the active layer ACT through contact holes included in the interlayer insulating layer 113. The drain electrode DE can be connected to the active layer ACT through contact holes included in the interlayer insulating layer 113. The source electrode SE and drain electrode DE can each be made of a conductive material (e.g., copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof). However, this disclosure is not limited thereto.

[0069] The first planarization layer 114 can be disposed on the source SE and drain DE. The first planarization layer 114 can planarize the upper part of the pixel circuit including the transistor TR. The first planarization layer 114 can be configured as a single layer or multiple layers, and is made of, for example, benzocyclobutene or acrylic-based organic materials. However, this disclosure is not limited thereto.

[0070] Multiple reflective electrodes RE are disposed on the first planarization layer 114. For example, the multiple reflective electrodes RE may include a first reflective electrode RE1 and a second reflective electrode RE2. The first reflective electrode RE1 and the second reflective electrode RE2 may be spaced apart from each other.

[0071] For example, in a sub-pixel SP, the first reflective electrode RE1 can overlap with multiple bonding layers BL and multiple light-emitting elements LED. Specifically, the top surface of the first reflective electrode RE1 can contact the bottom surface of the multiple bonding layers BL. At the same time, the first reflective electrode RE1 can be connected to the power line VL through the contact holes of the first planarization layer 114, the interlayer insulating layer 113, and the buffer layer 111. Therefore, the first reflective electrode RE1 can electrically connect the power line VL, the multiple bonding layers BL, and the multiple light-emitting elements LED.

[0072] The second reflective electrode RE2 can be connected to the transistor TR through the contact holes of the first planarization layer 114. For example, the second reflective electrode RE2 can be connected to the drain DE of the transistor TR. However, this disclosure is not limited thereto. Furthermore, the second reflective electrode RE2 can be connected to the second electrode E2 of each of the plurality of light-emitting elements by the connection electrode CE described below.

[0073] The first reflective electrode RE1 and the second reflective electrode RE2 may include various conductive layers, taking into account light reflection efficiency and resistance. For example, the first reflective electrode RE1 and the second reflective electrode RE2 may each be made by using an opaque conductive layer made of silver (Ag), aluminum (Al), molybdenum (Mo), titanium (Ti), or alloys thereof, and a transparent conductive layer made of indium tin oxide (ITO). However, this disclosure is not limited thereto. As an example, although the plurality of reflective electrodes RE are referred to as reflective electrodes, at least one or each of the plurality of reflective electrodes may be made of a conductive material having or not having reflective properties, and is not limited thereto. As an example, the plurality of reflective electrodes RE may also be referred to as intermediate electrodes.

[0074] Multiple bonding layers BL are disposed on the first reflective electrode RE1. These bonding layers are used to fix multiple light-emitting elements (LEDs). Therefore, the multiple bonding layers BL can be spaced apart from each other. Specifically, the multiple bonding layers BL can each correspond to a different multiple light-emitting element (LED). Thus, the multiple bonding layers BL can be used to fix multiple light-emitting elements (LEDs).

[0075] As an example, the width of the bonding layer BL can be greater than the maximum width of the light-emitting element LED, but is not limited thereto. Therefore, the light-emitting element LED can completely overlap with the bonding layer BL. For example, the light-emitting element LED can be disposed on and inside the bonding layer BL, so as not to deviate from the bonding layer BL. The implementation is not limited thereto. As an example, the width of the bonding layer BL can be equal to or less than the maximum width of the light-emitting element LED. As an example, the width of the bonding layer BL can be greater than, equal to, or less than the maximum width of the first electrode E1 of the light-emitting element LED (described later), while being less than the maximum width of the light-emitting element LED, but is not limited thereto. As an example, the bonding layer BL can at least partially overlap with the light-emitting element LED or the first electrode E1. As an example, the bonding layer BL can at least partially contact the light-emitting element LED or the first electrode E1, but is not limited thereto. As an example, the light-emitting element LED can be disposed at the center portion of the bonding layer BL, or it can be disposed away from the center portion of the bonding layer BL, but is not limited thereto.

[0076] The bonding layer BL may include a conductive material. As an example, the bonding layer BL may include a black component and have a black color, but is not limited thereto. For example, the conductive material may include carbon. For example, the bonding layer BL may be formed by dispersing a conductive material including carbon into an acrylic resin. However, this disclosure is not limited thereto. As described above, the bonding layer BL includes a conductive material such that the first reflective electrode RE1 and the first electrode E1 can be electrically connected.

[0077] Multiple light-emitting elements (LEDs) are disposed on multiple bonding layers (BL). (See reference...) Figure 2 Multiple light-emitting elements (LEDs) can be arranged in a pixel PX. In this case, as an example, the multiple LEDs can emit light beams of different colors. For example, in a pixel PX, the multiple LEDs can include a red light-emitting element configured to emit red light, a green light-emitting element configured to emit green light, and a blue light-emitting element configured to emit blue light.

[0078] Furthermore, in a plan view, as an example, at least some of the multiple light-emitting elements (LEDs) can be arranged in the same column. Additionally, at least some of the multiple LEDs can be arranged to be spaced apart from each other, for example, with equal intervals. However, this disclosure is not limited thereto. For example, at least some of the multiple LEDs can be arranged to be spaced apart from each other with different intervals.

[0079] The light-emitting element LED includes a first electrode E1, a first semiconductor layer L1, an active layer EL, a second semiconductor layer L2, and a second electrode E2.

[0080] The first electrode E1 can be disposed on and in contact with the bonding layer BL. For example, the bottom surface of the first electrode E1 can contact the top surface of the bonding layer BL. Therefore, the first electrode E1 can be electrically connected to the power line VL through the bonding layer BL and the first reflective electrode RE1. The first electrode E1 can be a cathode for injecting electrons into the active layer EL. However, this disclosure is not limited thereto. As an example, the first electrode E1 can be used as a reflective layer for reflecting light emitted from the active layer EL upwards, but is not limited thereto. The first electrode E1 can be made of a conductive material (e.g., a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), or a reflective conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or alloys thereof). However, this disclosure is not limited thereto.

[0081] A first semiconductor layer L1 is disposed on the first electrode E1. The first semiconductor layer L1 may be a layer formed by doping with an n-type impurity. However, this disclosure is not limited thereto. For example, the first semiconductor layer L1 may be a layer formed by doping with a material such as gallium nitride (GaN), indium aluminum phosphide (InAlP), or gallium arsenide (GaAs) with an n-type impurity. The n-type impurity may be silicon (Si), germanium, tin (Sn), etc. However, this disclosure is not limited thereto.

[0082] As an example, the width of the bottom surface of the first semiconductor layer L1 may be greater than the width of the top surface of the first electrode E1. Therefore, at least a portion of the bottom surface of the first semiconductor layer L1 may be exposed by the first electrode E1. Furthermore, the exposed bottom surface of the first semiconductor layer L1 may be spaced apart from the top surface of the bonding layer BL by the first electrode E1. Therefore, the side surface of the first electrode E1 may be exposed. The implementation is not limited to this. As an example, the width of the bottom surface of the first semiconductor layer L1 may be equal to the width of the top surface of the first electrode E1, but is not limited to this. As an example, the bottom surface of the first semiconductor layer L1 may not be exposed by the first electrode E1, but is not limited to this.

[0083] An active layer EL is disposed on a first semiconductor layer L1. The active layer EL emits light by receiving electrons and holes from the first semiconductor layer L1 and the second semiconductor layer L2. The active layer EL can be configured as a single-layer or multiple quantum well (MQW) structure. For example, the active layer EL can be made of indium gallium nitride (InGaN), gallium arsenide (GaAs), gallium nitride (GaN), etc. However, this disclosure is not limited thereto.

[0084] A second semiconductor layer L2 is disposed on the active layer EL. The second semiconductor layer L2 may be a layer formed by doping a specific material with a p-type impurity. However, this disclosure is not limited thereto. For example, the second semiconductor layer L2 may be a layer formed by doping a material such as gallium nitride (GaN), indium aluminum phosphide (InAlP), or gallium arsenide (GaAs) with a p-type impurity. In this case, the p-type impurity may be magnesium, zinc (Zn), beryllium (Be), etc. However, this disclosure is not limited thereto.

[0085] The second electrode E2 is disposed on the second semiconductor layer L2. The second electrode E2 can be an anode for injecting positive holes into the active layer EL. However, this disclosure is not limited thereto. The second electrode E2 can be made of a conductive material (e.g., a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), or an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or alloys thereof). However, this disclosure is not limited thereto.

[0086] Next, an encapsulation film PAS can be provided around the first semiconductor layer L1, the active layer EL, the second semiconductor layer L2, and the second electrode E2. As an example, the encapsulation film PAS can surround the entirety or a portion of the first semiconductor layer L1. As an example, the encapsulation film PAS can surround the upper part of the first semiconductor layer L1 while exposing the lower part of the first semiconductor layer L1, but is not limited thereto. As an example, the encapsulation film PAS can be spaced apart from the bonding layer BL.

[0087] The encapsulation film PAS can be made of an insulating material and protects the first semiconductor layer L1, the active layer EL, and the second semiconductor layer L2. Furthermore, the encapsulation film PAS has a second electrode E2 through its exposed contact hole, thereby allowing the connection electrode CE, described below, to be electrically connected to the second electrode E2.

[0088] Multiple light-emitting elements (LEDs) of a pixel PX can be disposed on the bonding layer BL and located at the same position. Alternatively, the light-emitting elements (LEDs) can be disposed on the bonding layer BL and located at different positions. For example, see reference... Figure 2 The centers of the LEDs in the first column, the second column, and the third column do not necessarily have to be in the same column.

[0089] The second planarization layer 115 can be disposed on multiple bonding layers BL and multiple reflective electrodes RE. The second planarization layer 115 can planarize the upper parts of the first reflective electrode RE1, the second reflective electrode RE2 and the multiple bonding layers BL disposed below the second planarization layer 115.

[0090] The second planarization layer 115 may cover the first reflective electrode RE1, the second reflective electrode RE2, and at least some of the bonding layers BL. For example, the second planarization layer 115 may cover at least a portion of the top surface of each of the bonding layers BL. Furthermore, the second planarization layer 115 may cover the entire side surface of each of the bonding layers BL. Therefore, the second planarization layer 115 may be configured to surround the bonding layers BL. The second planarization layer 115 may fill the regions where the bonding layers BL and the first semiconductor layer L1 are spaced apart from each other. At least a portion of the second planarization layer 115 may be disposed between the bonding layers BL and the first semiconductor layer L1. Furthermore, as an example, the second planarization layer 115 may contact the exposed side surface of the first electrode E1. As an example, at least a portion of the second planarization layer 115 may be disposed between the bonding layers BL and the first semiconductor layer L1 without contacting the exposed side surface of the first electrode E1.

[0091] The second planarization layer 115 may be configured to surround the lower portion of each of the plurality of light-emitting elements (LEDs). For example, the second planarization layer 115 may be configured to surround at least a portion of the side surface of each of the plurality of light-emitting elements (LEDs). Furthermore, the second planarization layer 115 may contact at least a portion of the side surface of the first semiconductor layer L1 exposed by the encapsulation film PAS. The second planarization layer 115 may be positioned below the active layer EL. Specifically, the top surface of the second planarization layer 115 may be disposed below the bottom surface of the active layer EL. The second planarization layer 115 may include a plurality of contact holes CH for connecting a plurality of connection electrodes CE and a plurality of second reflective electrodes RE2.

[0092] For example, the first planarization layer 114 and the second planarization layer 115 may each be made of benzocyclobutene or an acrylic-based organic material. However, this disclosure is not limited thereto. For example, the first planarization layer 114 and the second planarization layer 115 may be made of the same material or different materials.

[0093] A connecting electrode CE can be disposed on the second planarization layer 115. The connecting electrode CE can electrically connect the light-emitting element LED and the second reflective electrode RE2. Specifically, one end of the connecting electrode CE can be connected to the light-emitting element LED, and the other end of the connecting electrode CE can be connected to the second reflective electrode RE2. In this case, the connecting electrode CE can be connected to the second reflective electrode RE2 through the contact hole CH of the second planarization layer 115. Therefore, the connecting electrode CE can electrically connect the drain DE of the transistor TR and the second electrode E2 of the light-emitting element LED.

[0094] The connecting electrode CE can be made of a conductive material (e.g., a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) or an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or alloys thereof). However, this disclosure is not limited thereto.

[0095] As an example, multiple scattering layers SL are disposed on the connecting electrode CE. The multiple scattering layers SL are configured to correspond to multiple light-emitting elements (LEDs).

[0096] As an example, the cross-sectional width of the scattering layer SL decreases upwards, but is not limited to this. Therefore, the width of the top surface of the scattering layer SL can be smaller than the width of the bottom surface of the scattering layer SL. Furthermore, the side surfaces of the scattering layer SL can have a shape that slopes upwards in the direction toward the light-emitting element LED. As an example, the width of the top surface of the scattering layer SL can be greater than the width of the bonding layer BL, or can be equal to or less than the width of the bonding layer BL, but is not limited to this.

[0097] Furthermore, the scattering layer SL is configured to cover the light-emitting element LED. Specifically, the scattering layer SL is configured to cover the upper part of the light-emitting element LED. The scattering layer SL is configured to surround the side surface of the upper part of the light-emitting element LED. Therefore, as an example, the minimum width of the scattering layer SL can be greater than the maximum width of the light-emitting element LED, but is not limited thereto. As an example, at the same height, the width of the scattering layer SL can be greater than the width of the light-emitting element LED, but is not limited thereto. As an example, at a height above the light-emitting element LED, the width of the scattering layer SL can be equal to, less than, or greater than the maximum width of the light-emitting element LED, but is not limited thereto. As an example, the scattering layer SL is configured to surround the side surface of the upper part of the light-emitting element LED exposed by the second planarization layer 115. As an example, the scattering layer SL can contact the upper surface of the connecting electrode CE and the upper surface of the second planarization layer 115, but is not limited thereto.

[0098] The scattering layer SL is configured to cover the upper portion of the first semiconductor layer L1, the active layer EL, the second semiconductor layer L2, and the second electrode E2. For example, the scattering layer SL can be configured to surround the upper side surface of the first semiconductor layer L1. Furthermore, the scattering layer SL can be configured to surround the entire side surface of the second semiconductor layer L2. In this case, the bottom surface of the scattering layer SL can be configured to be lower than the bottom surface of the active layer EL. Therefore, the scattering layer SL can be configured to surround the entire side surface of the active layer EL.

[0099] The scattering layer SL may overlap with a portion of the connecting electrode CE. Therefore, at least a portion of the connecting electrode CE may be located between the second planarization layer 115 and the scattering layer SL.

[0100] The scattering layer SL may cover at least one end of the connecting electrode CE. In this case, the other end of the connecting electrode CE may extend outward from one end of the scattering layer SL. For example, one end of the scattering layer SL may be disposed outside the one end of the connecting electrode CE. Furthermore, the other end of the scattering layer SL may be disposed on the connecting electrode CE. As an example, the scattering layer SL may not overlap with the contact hole CH of the second planarization layer 115, but is not limited thereto.

[0101] Reference Figure 2 In a pixel PX, multiple scattering layers SL can correspond to multiple light-emitting elements (LEDs). For example, multiple scattering layers SL can be arranged in the same column and spaced apart from each other. The scattering layers SL can be configured to cover the entire top surface of the light-emitting elements (LEDs). For example, the outer perimeter of the scattering layers SL can have a shape surrounding the outer perimeter of the light-emitting elements (LEDs). Furthermore, in a planar view, the light-emitting elements (LEDs) can be disposed inside the scattering layers SL. The planar shape of the scattering layers SL can correspond to the planar shape of the light-emitting elements (LEDs). However, this disclosure is not limited to this. Furthermore, in a planar view, the light-emitting elements (LEDs) may or may not be located at the center of the scattering layers SL. For example, in a planar view, the center of the light-emitting elements (LEDs) and the center of the scattering layers SL may coincide or not coincide with each other. Therefore, the light-emitting elements (LEDs) may or may not be located at the center of the light-emitting region EA defined by the black embankment BB. The implementation is not limited to this. As an example, while the light-emitting elements (LEDs) can be disposed inside the scattering layers SL, the planar shape of the scattering layers SL may differ from the planar shape of the light-emitting elements (LEDs), but this is not a limitation. As an example, in a planar view, the center of the scattering layers SL may coincide with the center of the bonding layer BL, but this is not a limitation.

[0102] The scattering layer SL may include scattering particles. For example, the scattering particles included in the scattering layer SL may include one or more of TiO2, ZrO2, Al2O3, In2O3, ZnO, SnO2, Sb2O3, and ITO. However, this disclosure is not limited thereto.

[0103] The black dam BB is disposed on the second planarization layer 115 and the connecting electrode CE. The black dam BB is a component used to separate adjacent sub-pixels SP. The black dam BB can be configured not to overlap with the active layer EL of the light-emitting element LED.

[0104] The black dam BB is configured to contact at least a portion of the side surface of each of the plurality of scattering layers SL. In this case, as an example, the height of the top surface of the highest portion of the black dam BB may be lower than the height of the top surface of the scattering layer SL, but is not limited thereto. Therefore, as an example, the side surface of the black dam BB may contact the lower portion of the side surface of the scattering layer SL, and the end of the top surface of the black dam BB may contact the side surface of the scattering layer SL. Furthermore, the upper portion of the side surface of the scattering layer SL may be exposed by the black dam BB. Additionally, stepped portions may be formed on the surfaces of the scattering layers SL and the black dam BB that are in contact with each other.

[0105] As an example, the black dam can have a shape that increases in width upwards, but is not limited to this. Therefore, the side surfaces of the black dam BB can have an upwardly sloping shape, making the side surfaces of the black dam BB closer to the light-emitting element LED. For example, the end of the top surface of the black dam BB can be closer to the light-emitting element LED than the end of the bottom surface of the black dam BB. Furthermore, the end of the top surface of the black dam BB can be located outside the end of the top surface of the scattering layer SL. Additionally, the end of the top surface of the black dam BB can be located between the end of the top surface of the scattering layer SL and the end of the bottom surface of the scattering layer SL. The end of the top surface of the black dam BB does not need to overlap with the bonding layer BL and the light-emitting element LED.

[0106] As an example, the black dam BB may overlap with a portion of the connecting electrode CE, but is not limited thereto. Furthermore, the black dam BB may cover one end of the connecting electrode CE. Therefore, the black dam BB may cover at least a portion of the top surface of the connecting electrode CE. Additionally, the black dam BB may fill the contact hole CH of the second planarization layer 115. The black dam BB may include a recess disposed in the region overlapping with the contact hole CH. However, this disclosure is not limited thereto.

[0107] Black BB can be made from acrylic resins, benzocyclobutene (BCB) resins, or polyimides, and may also include a black component. However, this disclosure is not limited thereto.

[0108] In the following text, reference will be made to Figures 4A to 4G A method for manufacturing a display device 100 according to an exemplary embodiment of the present disclosure is described in detail.

[0109] Figures 4A to 4G A process diagram illustrating a method for manufacturing a sub-pixel of a display device according to an exemplary embodiment of the present disclosure.

[0110] First, refer to Figure 4AFirst reflective electrode RE1 and second reflective electrode RE2 can be disposed on substrate 110. Next, bonding material for forming multiple bonding layers BL can be applied to the first reflective electrode RE1. In this case, the bonding material may include, but is not limited to, a carbon-containing conductive material. Furthermore, multiple bonding layers BL can be formed by patterning the applied bonding material. Multiple light-emitting elements LED can be transferred to the multiple formed bonding layers BL respectively. In this case, the bonding layers BL can be formed to be wider than the light-emitting elements LED.

[0111] Meanwhile, during the process of transferring the light-emitting element (LED) onto the bonding layer BL, a transfer process can be performed at the desired location on the bonding layer BL. However, alignment errors may occur where the LED is set to a position deviating from the desired location. Therefore, as in Figure 2 As shown in the example, the centers of the multiple light-emitting elements (LEDs) can be located in different columns instead of in the same column. Furthermore, in another example, the centers of the multiple LEDs can be located in different rows instead of in the same row. As described above, the multiple LEDs can be randomly arranged on multiple bonding layers BL. As described above, when an error occurs in the transfer position of the LEDs, the LEDs may be transferred to a position deviating from the bonding layers BL, and bonding defects of the LEDs may occur. Therefore, in the display device 100 according to an exemplary embodiment of this disclosure, the bonding layers BL have a larger width than the LEDs, so that even if alignment errors occur during the process of transferring the LEDs, the LEDs can be stably transferred to the bonding layers BL.

[0112] Furthermore, in the display device 100 according to an exemplary embodiment of the present disclosure, as an example, the bonding layer BL may include a carbon-containing conductive material, and the conductive black material may include a black component, but is not limited thereto. Moreover, multiple bonding layers BL may be patterned and disposed simultaneously, each corresponding to a multiple light-emitting element LED. As described above, the display device 100 according to the exemplary embodiment of the present disclosure does not include conductive balls with relatively large sizes, thereby further reducing the size of the multiple bonding layers BL. Therefore, the overall size of the pixel PX, including the multiple bonding layers BL, can be reduced. Furthermore, because the size of the pixel PX is reduced as described above, a larger number of pixel PX can be disposed while maintaining the same area, thereby enabling a display device 100 with a higher resolution.

[0113] Next, refer to Figure 4BA material for forming the second planarization layer 115 can be applied. In this case, the second planarization layer 115 can be applied to completely cover the light-emitting element LED. Next, a patterning process can be performed to form a contact hole CH that exposes a portion of the second reflective electrode RE2. A portion of the second reflective electrode RE2 can be formed through its exposed contact hole CH by a patterning process.

[0114] Next, refer to Figure 4C An ashing process can be performed on the second planarization layer 115 to expose the upper part of the light-emitting element LED. The top surface of the light-emitting element LED can be fully exposed through the ashing process. Specifically, the second electrode E2 can be exposed. In addition, the side surface of the upper part of the light-emitting element LED can be exposed. In this case, the ashing process is formed such that the height of the top surface of the second planarization layer 115 is lower than that of the active layer EL, so that the side surface of the active layer EL is not covered by the second planarization layer. As an example, the height of the top surface of the second planarization layer 115 can be higher than, equal to or lower than the bottom surface of the encapsulation film PAS, but is not limited thereto. As an example, the side surface of the first semiconductor layer L1 can be covered by the encapsulation film PAS or the second planarization layer 115 and not exposed. However, this disclosure is not limited thereto.

[0115] Next, refer to Figure 4D The connecting electrode CE can be disposed on the second planarization layer 115. In this case, the connecting electrode CE can be connected to the second electrode E2 of the light-emitting element LED. Furthermore, the connecting electrode CE can be disposed along the contact hole CH of the second planarization layer 115. Additionally, the connecting electrode CE can be configured to contact the second reflective electrode RE2 through the contact hole CH of the second planarization layer 115. Therefore, the connecting electrode CE can electrically connect the light-emitting element LED and the second reflective electrode RE2.

[0116] Next, refer to Figure 4E A scattering layer SL can be disposed on the connecting electrode CE and the second planarization layer 115, covering multiple light-emitting elements (LEDs). In this case, the scattering layer SL can be formed by applying a material including a scattering material and then patterning the material, but is not limited to this. The scattering layer SL can be formed to cover the upper side surface and top surface of the light-emitting elements (LEDs). Furthermore, the scattering layer SL can be configured to completely cover the active layer EL of the light-emitting elements (LEDs). At the same time, the scattering layer SL can be removed from areas other than the areas overlapping with the light-emitting elements (LEDs) by the aforementioned patterning process. Therefore, the second planarization layer 115 and the connecting electrode CE can be partially exposed. In this case, the scattering layer SL can be formed in a conical shape.

[0117] At the same time, as referenced Figure 4AAs mentioned above, alignment errors may occur during the process of transferring the light-emitting element (LED). In this case, depending on the position of the LED, a brightness asymmetry relative to the left and right viewing angles may occur. For example, if the LED is positioned to the right of the bonding layer BL in cross-section, the brightness on the left side may be increased and the brightness on the right side may be decreased based on the center of the LED. This brightness difference can be mitigated by designing a longer distance between the LED and the black dam BB. However, when the distance between the LED and the black dam BB is designed to be longer, the ratio of the area occupied by the black dam BB to the area of ​​the pixel PX decreases. Furthermore, when the area occupied by the black dam BB decreases, an increase in external light reflectivity may occur.

[0118] Therefore, in the display device 100 according to an exemplary embodiment of the present disclosure, the scattering layer SL is formed around the top surface and side surface of the upper part of the light-emitting element LED. Furthermore, the scattering layer SL may be configured to surround the active layer EL. As described above, the scattering layer SL may be configured to cover the upper part of the light-emitting element and scatter the light emitted from the light-emitting element LED. Therefore, the light extraction efficiency of the light-emitting element LED can be improved. Furthermore, because the light emitted from the light-emitting element LED is scattered in various directions, the dependence on the size of the opening overlapping the light-emitting element LED in the black dam BB can be reduced. Therefore, regardless of the transfer position of the light-emitting element LED, the asymmetry of the brightness viewing angle can be mitigated.

[0119] Meanwhile, both the top and side surfaces of the light-emitting element can be covered by a scattering layer. However, when both the top and side surfaces of the light-emitting element are covered by the scattering layer, in order to connect the transistor and the light-emitting element, a portion of the upper part of the scattering layer needs to be removed, and the second electrode needs to be exposed. Next, an additional process is required to connect the exposed second electrode and the transistor via a connection electrode and to cover the top surface of the light-emitting element with the scattering layer.

[0120] However, in the display device 100 according to an exemplary embodiment of the present disclosure, the lower portion of the light-emitting element LED located below the active layer EL is fixed by the second planarization layer 115. In this case, a connection electrode CE for connecting the transistor TR to the exposed second electrode E2 of the light-emitting element LED is first provided, and then a scattering layer SL is provided on the connection electrode CE. Therefore, in the display device 100 according to an exemplary embodiment of the present disclosure, the scattering layer SL is provided after the connection electrode CE is provided. Therefore, a scattering layer SL covering a portion of the top surface and side surface of the light-emitting element LED can be formed without the need for a separate additional process.

[0121] Furthermore, in the display device 100 according to an exemplary embodiment of the present disclosure, the second planarization layer is formed such that the top surface of the second planarization layer 115 is disposed below the active layer EL of the light-emitting element LED. Furthermore, a scattering layer disposed on the second planarization layer 115 can cover the entire active layer EL of the light-emitting element LED. Therefore, light emitted from the active layer EL towards the side surface can also be scattered. Therefore, the light extraction efficiency of the light-emitting element LED can be further improved. As described above, the light extraction efficiency of the display device 100 according to the exemplary embodiment of the present disclosure is improved, enabling the display device 100 to operate with low power consumption.

[0122] Next, refer to Figure 4F The material used to form the black dam BB can be applied to completely cover the second planarization layer 115, the connecting electrode CE, and the multiple scattering layers SL. In this case, the material used to form the black dam BB can be applied to completely cover the top surface of the scattering layers SL.

[0123] Finally, refer to Figure 4G A process of ashing the black embankment (BB) can be performed to expose the top surface of the scattering layer (SL). In this case, the ashing process can be performed until the height of the top surface of the black embankment (BB) becomes lower than the height of the top surface of the scattering layer (SL). As described above, a portion of the upper side surface and the top surface of the scattering layer (SL) can be exposed by the process of ashing the black embankment (BB).

[0124] Because the black dam is a component used to distinguish adjacent sub-pixels, it can be configured not to overlap with the light-emitting element. In this case, the transfer position of the light-emitting element may not always be constant during the transfer process. If the black dam is formed around the light-emitting element regardless of its transfer position, the light-emitting element may therefore be positioned biased to one side within the opening of the black dam, which is the area overlapping with the light-emitting element. When the light-emitting element is positioned biased to one side within the opening of the black dam as described above, the brightness may be asymmetrical relative to the left and right viewing angles, as mentioned above. Therefore, the opening exposing the light-emitting element is formed by applying a material for forming the black dam and then performing an additional precise patterning process based on the position of the transferred light-emitting element.

[0125] However, in the display device 100 according to an exemplary embodiment of the present disclosure, a scattering layer SL for covering the light-emitting element LED is first formed, then a material for forming a black dam BB is applied, and then the material is simply etched. In this case, the etching material is such that the top surface of the black dam BB is lower than the top surface of the scattering layer SL, thereby forming the black dam BB. That is, the final arrangement position of the black dam BB can be naturally determined by the scattering layer SL, regardless of the transfer position of the light-emitting element LED. As described above, in the display device 100 according to an exemplary embodiment of the present disclosure, the black dam BB can be self-aligned without additional precise patterning processes.

[0126] Exemplary embodiments of this disclosure can also be described as follows:

[0127] A display device according to an exemplary aspect of the present disclosure includes: a substrate; a plurality of reflective electrodes disposed on the substrate; a plurality of bonding layers disposed on the plurality of reflective electrodes; a plurality of light-emitting elements disposed on the plurality of bonding layers, each including a first electrode, a first semiconductor layer on the first electrode, an active layer on the first semiconductor layer, a second semiconductor layer on the active layer, and a second electrode on the second semiconductor layer; a plurality of scattering layers configured to correspond to the plurality of light-emitting elements respectively, configured to cover the plurality of light-emitting elements respectively, and each having a shape with an upwardly decreasing cross-sectional width; and a black dam configured to contact at least a portion of the side surface of each of the plurality of scattering layers, and having a shape with an upwardly increasing cross-sectional width.

[0128] The top surface of the black embankment can be lower than the top surface of each of the multiple scattering layers.

[0129] The display device may further include: a planarization layer disposed on a plurality of bonding layers and configured to surround at least a portion of the side surface of each of a plurality of light-emitting elements; and a plurality of connecting electrodes disposed on the planarization layer and connected to a second electrode, wherein the planarization layer may be positioned below the active layer.

[0130] The scattering layer can be disposed on the planarization layer and multiple connecting electrodes, and can be configured to surround the side surface of the active layer.

[0131] The scattering layer may be configured to surround a portion of the upper part of the first semiconductor layer and the entire side surface of the second semiconductor layer, wherein the planarization layer may be configured to surround another portion of the side surface of the first semiconductor layer.

[0132] The scattering layer may cover at least one end of each of the multiple connecting electrodes.

[0133] Multiple bonding layers may include a conductive black material.

[0134] Multiple light-emitting elements can be randomly arranged on multiple bonding layers.

[0135] Among multiple light-emitting elements, those that are adjacent to each other along the column direction can be configured such that their centers are located in different columns.

[0136] Among multiple light-emitting elements, those that are adjacent to each other along the row direction can be configured such that their centers are located in different rows.

[0137] A display device according to another aspect of this disclosure includes: a substrate; a bonding layer disposed on the substrate; a light-emitting element disposed on the bonding layer and including a first electrode, a first semiconductor layer on the first electrode, an active layer on the first semiconductor layer, a second semiconductor layer on the active layer, and a second electrode on the second semiconductor layer; a planarization layer disposed below the active layer and configured to surround the lower portion of the first semiconductor layer; a scattering layer disposed on the planarization layer and configured to cover the upper portion of the first semiconductor layer, the active layer, the second semiconductor layer, and the second electrode, and having a side surface having a shape that is inclined upward in the direction toward the light-emitting element; and a black dam configured to surround the side surface of the lower portion of the scattering layer, and having a side surface having a shape that is inclined upward in the direction toward the light-emitting element.

[0138] The top surface of the black embankment can be set below the top surface of the scattering layer.

[0139] Stepped sections can be formed on the surfaces of the scattering layers that are in contact with each other and on the surfaces of the embankment.

[0140] The width of the top surface of the scattering layer can be smaller than the width of the bottom surface of the scattering layer, and the width of the top surface of the scattering layer can be greater than the width of each of the multiple bonding layers.

[0141] The display device may further include: a transistor disposed below the bonding layer; and a connecting electrode configured to electrically connect the transistor and the light-emitting element, wherein the connecting electrode may be disposed between the planarization layer and the scattering layer.

[0142] Multiple light-emitting elements can be randomly arranged on multiple bonding layers.

[0143] Although exemplary embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto and may be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the exemplary embodiments of the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above exemplary embodiments are illustrative in all respects and do not limit the present disclosure. All technical concepts within the equivalent scope of the present disclosure should be construed as falling within the scope of the present disclosure.

[0144] Cross-references to related applications

[0145] This application claims priority and benefit to Korean Patent Application No. 10-2024-0175677, filed on November 29, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety for all purposes, as if fully set forth herein.

Claims

1. A display device, the display device comprising: substrate; Multiple bonding layers are disposed above the substrate; Multiple light-emitting elements are respectively disposed on the multiple bonding layers; Multiple scattering layers, wherein the multiple scattering layers are respectively configured to correspond to the multiple light-emitting elements and are respectively configured to cover the multiple light-emitting elements; as well as A black dam, which is configured to contact at least a portion of the side surface of each of the plurality of scattering layers.

2. The display device according to claim 1, wherein, The top surface of the black embankment is lower than the top surface of each of the plurality of scattering layers.

3. The display device according to claim 1, wherein, Each of the plurality of light-emitting elements includes a first electrode, a first semiconductor layer on the first electrode, an active layer on the first semiconductor layer, a second semiconductor layer on the active layer, and a second electrode on the second semiconductor layer.

4. The display device according to claim 3, further comprising: A planarization layer is disposed on the plurality of bonding layers and is configured to surround a side surface of each of the plurality of light-emitting elements; as well as Multiple connecting electrodes are disposed on the planarization layer and connected to the second electrode. The planarization layer is positioned below the active layer.

5. The display device according to claim 4, wherein, The scattering layer is disposed on the planarization layer and the plurality of connecting electrodes, and is configured to surround the side surface of the active layer.

6. The display device according to claim 5, wherein, The scattering layer is configured to surround the upper part of the side surface of the first semiconductor layer and the entire side surface of the second semiconductor layer, and The planarization layer is configured to surround another portion of the side surface of the first semiconductor layer.

7. The display device according to claim 5, wherein, Each of the plurality of light-emitting elements further includes an encapsulation film surrounding a side surface of the active layer, a side surface of the second semiconductor layer, a side surface of the second electrode, and an upper portion of the side surface of the first semiconductor layer. The planarization layer is configured to surround the remaining portion of the side surface of the first semiconductor layer, such that the side surface of the first semiconductor layer is covered by the encapsulation film and the planarization layer and is not exposed.

8. The display device according to claim 4, wherein, The scattering layer is configured to contact the upper surface of the connecting electrode and the upper surface of the planarization layer.

9. The display device according to claim 4, wherein, The scattering layer covers at least one end of each of the plurality of connecting electrodes.

10. The display device according to claim 4, wherein, The width of the bottom surface of the first semiconductor layer is greater than the width of the top surface of the first electrode, and At least a portion of the planarization layer is disposed between the bonding layer and the first semiconductor layer to contact the exposed side surface of the first electrode.

11. The display device according to claim 1, wherein, The plurality of bonding layers comprise a conductive black material.

12. The display device according to claim 1, wherein, Each of the plurality of light-emitting elements is randomly disposed on a corresponding bonding layer among the plurality of bonding layers.

13. The display device according to claim 12, wherein, Among the plurality of light-emitting elements, the light-emitting elements that are adjacent to each other along the column direction are configured such that their centers are located in different columns.

14. The display device according to claim 12, wherein, Among the plurality of light-emitting elements, the light-emitting elements that are adjacent to each other along the row direction are configured such that their centers are located in different rows.

15. The display device according to claim 1, further comprising: Multiple reflective electrodes are disposed on the substrate. The plurality of bonding layers are disposed on the plurality of reflective electrodes.

16. The display device according to claim 1, wherein, The plurality of scattering layers have a shape in which the cross-sectional width decreases upward, and The black embankment has a cross-sectional width that increases upwards.

17. The display device according to claim 1, wherein, In the plan view, the light-emitting element is disposed inside the scattering layer.

18. The display device according to claim 1, wherein, The center of the scattering layer coincides with the center of the bonding layer.

19. A display device, the display device comprising: substrate; A bonding layer disposed on the substrate; A light-emitting element is disposed on the bonding layer and includes a first electrode, a first semiconductor layer on the first electrode, an active layer on the first semiconductor layer, a second semiconductor layer on the active layer, and a second electrode on the second semiconductor layer. A planarization layer is disposed below the active layer and configured to surround the lower portion of the first semiconductor layer; A scattering layer is disposed on the planarization layer and configured to cover the upper part of the first semiconductor layer, the active layer, the second semiconductor layer and the second electrode, and the side surface of the scattering layer has a shape that is inclined upward in the direction toward the light-emitting element; as well as A black dam is configured to surround the lower side surface of the scattering layer, and the side surface of the black dam has a shape that slopes upward in the direction toward the light-emitting element.

20. The display device according to claim 19, wherein, The top surface of the black embankment is located below the top surface of the scattering layer.

21. The display device according to claim 20, wherein, Stepped sections are formed on the surfaces of the scattering layer and the black embankment that are in contact with each other.

22. The display device according to claim 19, wherein, The width of the top surface of the scattering layer is smaller than the width of the bottom surface of the scattering layer, and the width of the top surface of the scattering layer is greater than the width of each of the plurality of bonding layers.

23. The display device according to claim 19, further comprising: A transistor disposed beneath the bonding layer; as well as A connecting electrode is configured to electrically connect the transistor and the light-emitting element. The connecting electrode is disposed between the planarization layer and the scattering layer.

24. The display device according to claim 19, wherein, Each of the multiple light-emitting elements is randomly disposed on a corresponding bonding layer among the multiple bonding layers.

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