Display substrate, preparation method thereof and display device

Abstract

A display substrate includes a substrate and a first active layer, a first functional layer, a second active layer, a second functional layer and an interlayer dielectric layer which are sequentially arranged on the substrate. The display substrate further includes a first via, a second via and a third via. The first via penetrates at least part of the second functional layer and at least part of the first functional layer and exposes part of the surface of the first active layer. The second via penetrates the interlayer dielectric layer and communicates with the first via. The third via penetrates the interlayer dielectric layer and at least part of the second functional layer and exposes part of the surface of the second active layer. In the display substrate, the first via is formed earlier than the interlayer dielectric layer and the third via is formed later than the interlayer dielectric layer. The aperture of the first via is smaller than the aperture of the second via and the aperture of the first via is smaller than the aperture of the third via.

Description

[0001] This application is a divisional application. The original application has the application number 202280001108.5 and the original application date is April 29, 2022. The entire contents of the original application are incorporated herein by reference. Technical Field

[0002] This disclosure relates to the field of display technology, and in particular to a display substrate, a method for preparing the same, and a display device. Background Technology

[0003] OLED (Organic Light Emitting Diode) displays are devices made using organic light-emitting diodes. OLED displays have excellent characteristics such as no need for a backlight, high contrast, thinness, wide viewing angle, fast response speed, applicability to flexible panels, wide operating temperature range, and simpler construction and manufacturing process, and are currently widely used. Summary of the Invention

[0004] On one hand, a display substrate is provided. The display substrate includes a substrate and a first active layer, a first functional layer, a second active layer, a second functional layer, and an interlayer dielectric layer stacked on the substrate. The display substrate further includes a first via, a second via, and a third via. The first via penetrates at least a portion of the second functional layer and at least a portion of the first functional layer, and exposes a portion of the surface of the first active layer. The second via penetrates the interlayer dielectric layer and communicates with the first via. The third via penetrates the interlayer dielectric layer and at least a portion of the second functional layer, and exposes a portion of the surface of the second active layer; wherein the diameter of the first via is smaller than the diameter of the second via, and the diameter of the first via is smaller than the diameter of the third via.

[0005] In some embodiments, the display substrate has a display area and a non-display area. The display area includes a pixel circuit area, and the display substrate further includes a fifth recess and a first recess. The fifth recess penetrates at least a portion of the second functional layer and at least a portion of the first functional layer, and is located between two adjacent pixel circuit areas. The first recess penetrates at least a portion of the second functional layer and at least a portion of the first functional layer. The depth of the second via is less than or equal to the depth of the third via. The depth of the third via is less than the depth of the first via. The depth of the first via is less than the depth of the fifth recess. The depth of the fifth recess is equal to the depth of the first recess.

[0006] On the other hand, a method for fabricating a display substrate is provided. The method includes providing a substrate. A first active layer, a first functional layer, a second active layer, and a second functional layer are sequentially formed on the substrate. A first via is formed penetrating at least a portion of the second functional layer and at least a portion of the first functional layer, the first via exposing a portion of the surface of the first active layer. An interlayer dielectric layer is formed on the second functional layer, a portion of the interlayer dielectric layer filling the first via. The portion of the interlayer dielectric layer filling the first via is removed, and a second via communicating with the first via is formed in the interlayer dielectric layer. A third via is formed penetrating the interlayer dielectric layer and at least a portion of the second functional layer, the third via exposing a portion of the surface of the second active layer.

[0007] In some embodiments, during the process of removing the portion of the interlayer dielectric layer that fills the first via and forming a second via in the interlayer dielectric layer communicating with the first via, the fabrication method further includes: forming a fourth via penetrating the interlayer dielectric layer, wherein the orthographic projection of the fourth via on the substrate is located within the orthographic projection range of the second active layer on the substrate. Forming a third via penetrating the interlayer dielectric layer and at least a portion of the second functional layer includes: patterning the second functional layer through the fourth via to form a fifth via penetrating at least a portion of the second functional layer. The third via includes the fourth via and the fifth via.

[0008] In some embodiments, the substrate has a display area and a non-display area, the non-display area including a bending region, and the first active layer and the second active layer are located in the display area. Before sequentially forming the first active layer, the first functional layer, the second active layer, and the second functional layer on the substrate, the fabrication method further includes: forming an inorganic layer on the substrate. During the formation of a first via penetrating at least a portion of the second functional layer and at least a portion of the first functional layer, the fabrication method further includes: forming a first groove penetrating at least a portion of the second functional layer and the at least a portion of the first functional layer, the first groove being located in the bending region and exposing a portion of the surface of the inorganic layer.

[0009] In some embodiments, the fabrication method further includes: forming a first conductive film on the interlayer dielectric layer, the first conductive film covering the surface of the interlayer dielectric layer and located within the first via, the second via, the third via, and the first groove; patterning the first conductive film, retaining the portions of the first conductive film located in the first via and the second via to obtain a first conductive pattern, and retaining the portion of the first conductive film located in the third via to obtain a second conductive pattern.

[0010] In some embodiments, the contact resistance between the first conductive pattern and the first active layer ranges from 969Ω to 1747Ω.

[0011] In some embodiments, the fabrication method further includes: forming a passivation layer on the first conductive pattern and the second conductive pattern, a portion of the passivation layer being located within the first groove and in contact with a portion of the exposed surface of the inorganic layer; and patterning the passivation layer to at least remove the portion of the passivation layer located within the first groove.

[0012] In some embodiments, the fabrication method further includes: patterning the inorganic layer through the first groove to form a second groove communicating with the first groove, the second groove exposing a portion of the surface of the substrate; forming a first planarization layer, a portion of the first planarization layer filling the first groove and the second groove, and contacting the exposed portion of the surface of the substrate.

[0013] In some embodiments, the non-display area further includes a cut area located on the side of the bending area away from the display area. During the process of forming a first groove penetrating at least a portion of the second functional layer and at least a portion of the first functional layer, the fabrication method further includes: forming a third groove penetrating at least a portion of the second functional layer and at least a portion of the first functional layer, the third groove being located in the cut area and exposing a portion of the surface of the inorganic layer.

[0014] In some embodiments, the fabrication method further includes: patterning the inorganic layer through the third groove to form a fourth groove communicating with the third groove, the fourth groove exposing a portion of the substrate surface; forming a first planarization layer, a portion of the first planarization layer filling the third groove and the fourth groove, and contacting the exposed portion of the substrate surface.

[0015] In some embodiments, the step of forming the first functional layer includes: sequentially forming a first gate insulating layer, a first gate, a second gate insulating layer, a second gate, and a third gate insulating layer, wherein the orthographic projection of the first gate on the substrate overlaps with a portion of the orthographic projection of the first active layer on the substrate, and the orthographic projection of the second gate on the substrate overlaps with a portion of the orthographic projection of the second active layer on the substrate. The step of forming the second functional layer includes: sequentially forming a fourth gate insulating layer, a third gate, and a fifth gate insulating layer, wherein the orthographic projection of the third gate on the substrate overlaps with a portion of the orthographic projection of the second active layer on the substrate.

[0016] In some embodiments, the substrate has a display area, which includes a plurality of pixel circuit areas. During the formation of the first via penetrating at least a portion of the second functional layer and at least a portion of the first functional layer, the fabrication method further includes: forming a fifth groove penetrating at least a portion of the second functional layer and at least a portion of the first functional layer, the fifth groove being located between two adjacent pixel circuit areas. During the formation of an interlayer dielectric layer on the second functional layer, the interlayer dielectric layer further fills the fifth groove.

[0017] In some embodiments, forming a fifth groove penetrating at least a portion of the second functional layer and at least a portion of the first functional layer includes: before forming a first via penetrating at least a portion of the second functional layer and at least a portion of the first functional layer, forming a sixth groove penetrating at least a portion of the second functional layer and the third gate insulating layer, the sixth groove being located between two adjacent pixel circuit regions. During the process of forming the first via penetrating at least a portion of the second functional layer and at least a portion of the first functional layer, a seventh groove is formed through the sixth groove, penetrating the second gate insulating layer and the first gate insulating layer and communicating with the sixth groove, the fifth groove including the sixth groove and the seventh groove.

[0018] In some embodiments, the orthographic projection of the fourth gate insulating layer on the substrate and the orthographic projection of the third gate on the substrate coincide.

[0019] In some embodiments, the material of the first active layer includes polycrystalline silicon, and the material of the second active layer includes metal oxide.

[0020] In another aspect, a display device is provided. The display device includes a display substrate as described in any of the above embodiments. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual process of the method, etc. involved in the embodiments of this disclosure.

[0022] Figure 1 This is a cross-sectional view of a display substrate to be formed in one implementation method; Figure 2 This is a cross-sectional view of another display substrate to be formed in one implementation method; Figure 3This is a flowchart of a method for fabricating a display substrate according to some embodiments of the present disclosure; Figures 4a-4o This is a diagram illustrating the fabrication steps of a display substrate according to some embodiments of the present disclosure; Figure 5 for Figure 4g A magnified view of a portion of region X in the middle; Figure 6a This is a schematic diagram illustrating the principle of water vapor release from the substrate in one implementation method. Figure 6b An optical detection image of a structure formed by a first conductive thin film in one implementation method; Figure 6c An optical detection image of a structure formed by another first conductive thin film in one implementation method; Figure 6d Optical detection patterns of a first conductive pattern and a second conductive pattern formed according to some embodiments of this disclosure; Figure 7 This is a cross-sectional view of another display substrate to be formed in one implementation method; Figures 8a-8d This is a top view of a display substrate to be formed according to some embodiments of the present disclosure; Figure 9 This is a structural diagram of a display substrate according to some embodiments of the present disclosure; Figure 10 A circuit diagram of a pixel circuit according to some embodiments of the present disclosure; Figure 11 This is a structural diagram of another display substrate according to some embodiments of the present disclosure; Figure 12 This is a structural diagram of a display device according to some embodiments of the present disclosure. Detailed Implementation

[0023] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0024] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular "comprises" and the present participle "comprising," are interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0025] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0026] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. Similarly, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0027] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0028] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0029] The use of “configured as” in this article implies an open and inclusive language that does not exclude the applicability to or configuration of devices to perform additional tasks or steps.

[0030] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0031] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0032] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0033] In one implementation, during the fabrication process of the display substrate, see [reference needed]. Figure 1 Typically, a first active layer 2', a first functional layer 3', a second active layer 4', and a second functional layer 5' are sequentially formed on a substrate 1', wherein the material of the second active layer 4' includes a metal oxide. Then, a first connection hole 6' exposing the first active layer 2' and a second connection hole 7' exposing the second active layer 4' are simultaneously formed at corresponding positions on the second functional layer 5'. See [link to documentation]. Figure 2Then, an interlayer dielectric layer 8' is formed on the second functional layer 5', located outside the area of ​​the first connecting hole 6' and the second connecting hole 7'. During the formation of the interlayer dielectric layer 8', material of the interlayer dielectric layer 8' will be located in the first connecting hole 6' and the second connecting hole 7'. Therefore, it is necessary to remove the material of the interlayer dielectric layer 8' located in the first connecting hole 6' and the second connecting hole 7' to obtain the interlayer dielectric layer 8'. This can easily result in material of the interlayer dielectric layer 8' remaining on the first active layer 2' in the first connecting hole 6'. The cleaning agent that can remove the material of the interlayer dielectric layer 8' will corrode the exposed second active layer 4', which will result in the inability to effectively remove the material of the interlayer dielectric layer 8' remaining on the first active layer 2'. Therefore, after the source and drain are formed in the first connection hole 6' to form a transistor, the material of the residual interlayer dielectric layer 8' will cause the contact resistance between the source and the first active layer 2' and the contact resistance between the drain and the first active layer 2' to increase, affecting the electrical characteristics of the formed transistor and the display effect of the display substrate.

[0034] Based on this, some embodiments of this disclosure provide a method for preparing a display substrate, such as... Figure 3 As shown, the preparation method includes: S100~S600.

[0035] S100, such as Figure 4a As shown, substrate 1 is provided.

[0036] For example, the structure and material of substrate 1 include a variety of options, which can be selected and set according to actual needs.

[0037] For example, substrate 1 can be a single-layer structure.

[0038] For example, substrate 1 can be a rigid substrate. This rigid substrate can be, for example, a glass substrate or a PMMA (Polymethyl methacrylate) substrate. In this case, the aforementioned display substrate 100 can be a rigid display substrate.

[0039] For example, substrate 1 can be a flexible substrate. This flexible substrate can be, for example, a PET (Polyethylene terephthalate) substrate, a PEN (Polyethylene naphthalate twoformic acid glycol ester) substrate, or a PI (Polyimide) substrate. In this case, the aforementioned display substrate 100 can be a flexible display substrate.

[0040] For example, substrate 1 can be a multilayer structure, that is, substrate 1 includes multiple sub-film layers, and the material of each sub-film layer can be the same or different.

[0041] For example, see Figure 4a The substrate 1 includes three sub-film layers stacked sequentially. The materials of the three sub-film layers of the substrate 1 may, in sequence, be: polyimide (PI), silicon oxide (SiO), and polyimide (PI).

[0042] The accompanying drawings of this disclosure illustrate a three-layer structure for substrate 1, namely, substrate 1 includes three sub-film layers stacked sequentially.

[0043] S200, see S200 Figure 4b A first active layer 2, a first functional layer 3, a second active layer 4, and a second functional layer 5 are sequentially formed on a substrate 1.

[0044] For example, in S200, the step of forming a first active layer 2 on the substrate 1 may include: forming a first active thin film on the substrate 1, and patterning the first active thin film through a patterning process to form the first active layer 2.

[0045] For example, the patterning process described above may include plasma etching, photolithography, etc.

[0046] For example, the number of first active layers 2 formed is multiple. The specific number of first active layers 2 can be determined according to the number of transistors to be formed, and this disclosure does not limit it.

[0047] In some examples, the material of the first active layer 2 includes polycrystalline silicon.

[0048] It is understood that transistors containing polycrystalline silicon have high mobility. This is beneficial for improving the mobility of the transistors fabricated in this disclosure.

[0049] For example, the first functional layer 3 includes multiple sub-membrane layers with different functions, which are not limited in this disclosure.

[0050] For example, the first functional layer 3 includes a first gate insulating layer 6, a first gate 7, a second gate insulating layer 8, a second gate 9 and a third gate insulating layer 10 sequentially stacked in a direction away from the substrate 1.

[0051] See in some examples Figure 4b In the above S200, the method for forming the first functional layer 3 includes: S210.

[0052] S210, a first gate insulating layer 6, a first gate 7, a second gate insulating layer 8, a second gate 9, and a third gate insulating layer 10 are formed sequentially. The orthogonal projection of the first gate 7 onto the substrate 1 overlaps with the orthogonal projection of the first active layer 2 onto the substrate 1. The orthogonal projection of the second gate 9 onto the substrate 1 overlaps with the orthogonal projection of the second active layer 4 onto the substrate 1.

[0053] For example, the material of the first gate insulating layer 6 is an inorganic material. For instance, the material of the first gate insulating layer 6 includes at least one of silicon oxide (SiO), silicon nitride (SiN), and silicon oxynitride (SiON). The first gate insulating layer 6 can provide insulation protection between the first active layer 2 and the first gate 26.

[0054] For example, a method for forming the first gate insulating layer 6 includes a deposition process.

[0055] Optionally, this disclosure allows for the deposition of a first gate insulating layer 6 of a certain thickness on the side of the first active layer 2 away from the substrate 1 using methods such as PVD (Physical Vapor Deposition) or PECVD (Plasma Enhanced Chemical Vapor Deposition).

[0056] For example, the material of the first gate 7 is a conductive material. For example, the material of the first gate 7 includes metals or alloys such as molybdenum (Mo), aluminum (Al), and copper (Cu). The method of forming the first gate 7 includes: forming a first gate conductive film on the side of the first gate insulating layer 6 away from the substrate 1, and then patterning the first gate conductive film using a photolithography process to obtain the first gate 7.

[0057] An exemplary method for patterning a first gate conductive film using photolithography includes: coating a photoresist onto the first gate conductive film; then placing a mask on the side of the photoresist away from the substrate 1; exposing and developing the photoresist through the mask to remove the exposed portions and retain the unexposed portions, thereby forming a patterned photoresist; next, using the patterned photoresist as a mask to etch the first gate conductive film to remove the portions not covered by the patterned photoresist, forming the first gate 7. Finally, the display substrate to be formed can be placed in a stripping solution to dissolve and remove the patterned photoresist.

[0058] For example, the material of the second gate insulating layer 8 is an inorganic material. For instance, the material of the second gate insulating layer 8 includes at least one of silicon nitride (SiN), silicon oxide (SiO), and silicon oxynitride (SiON). The second gate insulating layer 8 can provide insulating protection between the first gate 7 and the second gate 9.

[0059] For example, a method for forming the second gate insulating layer 8 includes a deposition process.

[0060] Optionally, the method for forming the second gate insulating layer 8 can refer to the method for forming the first gate insulating layer 6 described above, and will not be repeated here.

[0061] For example, the material of the second gate 9 is a conductive material. For instance, the material of the second gate 9 includes metals or alloys such as molybdenum (Mo), aluminum (Al), and copper (Cu). The method of forming the second gate 9 may include: forming a second gate conductive film on the side of the second gate insulating layer 8 away from the substrate 1, and then patterning the second gate conductive film using a photolithography process to obtain the second gate 9.

[0062] For example, the material of the third gate insulating layer 10 includes an inorganic material. For instance, the material of the third gate insulating layer 10 includes at least one of silicon oxide (SiO), silicon nitride (SiN), and silicon oxynitride (SiON). The third gate insulating layer 10 can provide insulating protection between the second gate 9 and the second active layer 4.

[0063] For example, a method for forming the third gate insulating layer 10 includes a deposition process.

[0064] Optionally, the method for forming the third gate insulating layer 10 can refer to the method for forming the first gate insulating layer 6 described above, and will not be repeated here.

[0065] For example, by setting the orthogonal projection of the first gate 7 on the substrate 1 to overlap with the orthogonal projection of the first active layer 2 on the substrate 1, it is beneficial to realize the control of the transistor containing the first active layer 2 by the first gate 7.

[0066] It is understandable that after patterning the first gate conductive film, multiple first plates can be obtained simultaneously. Similarly, after patterning the second gate conductive film, multiple second plates can be obtained simultaneously. For example, a first plate and a second plate can be arranged opposite each other to form a storage capacitor Cst.

[0067] Furthermore, after patterning either the first gate conductive film or the second gate conductive film, multiple signal lines can be obtained simultaneously. These multiple signal lines include, for example, at least one of: a first gate line GateP, a second gate line GateN, an enable signal line EM, a reset signal line ResetN, and an initial signal line.

[0068] For example, when the first gate line GateP is obtained from the first gate conductive film, the first gate line GateP overlaps with the first active layer 2, and the overlapping portion, for example, constitutes the first gate 7. When the enable signal line EM is obtained from the first gate conductive film, the enable signal line EM overlaps with the first active layer 2, and the overlapping portion, for example, also constitutes the first gate 7. When the second gate line GateN is obtained from the second gate conductive film, the second gate line GateN overlaps with the second active layer 4, and the overlapping portion, for example, constitutes the second gate 9. When the reset signal line ResetN is obtained from the second gate conductive film, the reset signal line ResetN overlaps with the second active layer 4, and the overlapping portion, for example, constitutes the second gate 9.

[0069] For details on the first gate line GateP, the second gate line GateN, the enable signal line EM, and the reset signal line ResetN, please refer to the descriptions below; they will not be repeated here.

[0070] For example, in the above S200, the step of forming the second active layer 4 may include: forming a second active layer thin film on the first functional layer 3, and patterning the second active layer thin film by a patterning process to form the second active layer 4.

[0071] For example, the patterning process described above may include plasma etching, photolithography, etc.

[0072] For example, there can be multiple second active layers 4. The specific number of second active layers 4 can be determined according to the number of transistors to be formed, and this disclosure does not limit this number.

[0073] In some examples, the material of the second active layer 4 includes a metal oxide. For example, the material of the second active layer 4 includes indium gallium zinc oxide (IGZO).

[0074] It is understood that transistors containing metal oxides have the characteristic of low leakage current. This is beneficial for reducing the leakage current of the transistors fabricated in this disclosure.

[0075] For example, the second functional layer 5 includes multiple sub-membrane layers with different functions. This disclosure does not limit the number or material of the sub-membrane layers.

[0076] For example, see Figure 4b The second functional layer 5 includes a fourth gate insulating layer 11, a third gate 12 and a fifth gate insulating layer 13 stacked in sequence.

[0077] See in some examples Figure 4b In the above S200, the method for forming the second functional layer 5 includes: S220.

[0078] S220, a fourth gate insulating layer 11, a third gate 12 and a fifth gate insulating layer 13 are formed in sequence, and the orthogonal projection of the third gate 12 on the substrate 1 overlaps with the orthogonal projection of the second active layer 4 on the substrate 1.

[0079] For example, the material of the fourth gate insulating layer 11 is an inorganic material. For instance, the material of the fourth gate insulating layer 11 includes at least one of silicon oxide (SiO), silicon nitride (SiN), and silicon oxynitride (SiON). The fourth gate insulating layer 11 can provide insulating protection between the third gate 12 and the second active layer 4.

[0080] For example, the method of forming the fourth gate insulating layer 11 includes a deposition process and a photolithography process.

[0081] For example, the material of the third gate 12 is a metallic conductive material. For example, the material of the third gate 12 includes molybdenum (Mo) and titanium nitride (TiN) stacked sequentially. The method of forming the third gate 12 may include: forming a third gate conductive film including the third gate 12 on the side of the fourth gate insulating layer 11, the second active layer 4 and the third insulating layer 10 away from the substrate 1, and then patterning the third gate conductive film to obtain the third gate 12.

[0082] For example, a method for patterning the third gate conductive film includes a photolithography process.

[0083] It is understandable that multiple signal lines can be obtained after patterning the third gate conductive film. These multiple signal lines may include, for example, at least one of the second gate line GateN and the reset signal line ResetN.

[0084] In the case where the second gate line GateN is obtained from the third gate conductive film, the second gate line GateN overlaps with the second active layer 4, and the overlapping portion constitutes, for example, the third gate 12. In the case where the reset signal line ResetN is obtained from the third gate conductive film, the reset signal line ResetN overlaps with the second active layer 4, and the overlapping portion constitutes, for example, the third gate 12.

[0085] For example, the second gate line GateN obtained from the second gate conductive film and the second gate line GateN obtained from the third gate conductive film partially overlap, and the reset signal line ResetN obtained from the second gate conductive film and the reset signal line ResetN obtained from the third gate conductive film partially overlap.

[0086] Furthermore, after patterning the third gate conductive film, a first initial signal line Vinit1 or a second initial signal line Vinit2 can also be obtained. For details regarding the first initial signal line Vinit1 or the second initial signal line Vinit2, please refer to the explanation below; it will not be repeated here.

[0087] In some examples, the fourth gate insulating layer 11 is a single layer, and its orthographic projection shape on the substrate 1 is different from that of the third gate 12 on the substrate 1. Therefore, after forming the fourth gate insulating layer 11 and the third gate conductive film, the third gate conductive film needs to be patterned to form the third gate 12.

[0088] In other examples, see Figure 4c The fourth gate insulating layer 11 is not a whole layer. The orthographic projection of the fourth gate insulating layer 11 on the substrate 1 coincides with the orthographic projection of the third gate 12 on the substrate 1.

[0089] For example, after forming the thin film containing the fourth gate insulating layer 11 and the third gate conductive film, the fourth gate insulating layer 11 and the third gate conductive film can be patterned simultaneously to obtain the fourth gate insulating layer 11 and the third gate 12, and the orthographic projection of the fourth gate insulating layer 11 on the substrate 1 and the orthographic projection of the third gate 12 on the substrate 1 can be made to coincide. In this way, while ensuring the insulating protection function of the fourth gate insulating layer 11, the number of film layers in the display substrate outside the third gate 12 area can be reduced, and the thickness of the display substrate can be reduced to a certain extent.

[0090] For example, the material of the fifth gate insulating layer 13 includes an inorganic material. For instance, the material of the fifth gate insulating layer 13 includes at least one of silicon oxide (SiO), silicon nitride (SiN), and silicon oxynitride (SiON). The fifth gate insulating layer 13 can provide insulating protection for the third gate 12 and the second active layer 4.

[0091] For example, a method for forming the fifth gate insulating layer 13 includes a deposition process.

[0092] Optionally, the method for forming the fifth gate insulating layer 13 can refer to the method for forming the first gate insulating layer 6 described above, and will not be repeated here.

[0093] For example, by setting the orthogonal projection of the second gate 9 on the substrate 1 to overlap with the orthogonal projection of the second active layer 4 on the substrate 1, and by setting the orthogonal projection of the third gate 12 on the substrate 1 to overlap with the orthogonal projection of the second active layer 4 on the substrate 1, a transistor with a top-bottom gate structure can be obtained. Moreover, it is advantageous to realize the control of the transistor containing the second active layer 4 by the second gate 9 and the third gate 12.

[0094] For example, the orthographic projections of the first active layer 2 and the second active layer 4 on the substrate 1 do not overlap; that is, in the direction perpendicular to the substrate 1, the first active layer 2 and the second active layer 4 have no overlapping portions. With this configuration, interference between the second active layer 4 and the aforementioned vias can be avoided in the subsequent step of forming vias on the first active layer 2 and the second active layer 4.

[0095] S300, see S300 Figure 4d A first via 14 is formed that penetrates at least a portion of the second functional layer 5 and at least a portion of the first functional layer 3, and the first via 14 exposes a portion of the surface of the first active layer 2.

[0096] For example, the present disclosure may use photolithography to etch the first functional layer 3 and the second functional layer 5 to form the first via 14.

[0097] It should be noted that, see Figure 4d The first via 14 can penetrate at least a portion of the first gate insulating layer 6, the second gate insulating layer 8 and the third gate insulating layer 10 of the first functional layer 3, as well as the fifth gate insulating layer 13 of the second functional layer 5.

[0098] By exposing a portion of the surface of the first active layer 2 through the first via 14, it is convenient to form the source and drain of the transistor in each of the first vias 14 in the later stage, and make the source and drain contact with a portion of the surface of the first active layer 2 to form an electrical connection.

[0099] For example, the number of first vias 14 is set to correspond to the number of first active layers 2.

[0100] Optionally, the number of first vias 14 is two, three, or four times the number of first active layers 2. For example, the number of first active layers 2 is two, and the number of first vias 14 is four, six, or eight. Or, the number of first active layers 2 is six, and the number of first vias 14 is twelve, eighteen, or twenty-four.

[0101] S400, see S400 Figure 4e An interlayer dielectric layer 15 is formed on the second functional layer 5, and a portion of the interlayer dielectric layer 15 fills the first via 14.

[0102] For example, the material of the interlayer dielectric layer 15 includes an organic material. For instance, the material of the interlayer dielectric layer 15 includes polyimide (PI).

[0103] An exemplary method of forming the interlayer dielectric layer 15 includes a coating process.

[0104] It should be noted that organic materials have fluidity. Therefore, during the process of forming the interlayer dielectric layer 15 on the second functional layer 5, a portion of the interlayer dielectric layer 15 will fill the first via 14, and the upper surface of the interlayer dielectric layer 15 is a flat surface.

[0105] S500, see S500 Figure 4f-1 and Figure 4f-2 Remove the portion of the interlayer dielectric layer 15 that was filled with the first via 14, and form a second via 16 in the interlayer dielectric layer 15 that communicates with the first via 14.

[0106] For example, the method of removing the portion of the interlayer dielectric layer 15 that fills the first via 14 and forming a second via 16 in the interlayer dielectric layer 15 that communicates with the first via 14 may include a photolithography process.

[0107] Furthermore, the portion of the interlayer dielectric layer 15 that fills the first via 14 is removed, and a second via 16 that communicates with the first via 14 is formed in the interlayer dielectric layer 15. These processes can be completed in one step, which simplifies the fabrication process of the display substrate 100.

[0108] For example, the diameter of the second via 16 is larger than the diameter of the first via 14. Here, the diameter refers, for example, to the average diameter of the via, or to the diameter of the via at the end away from the substrate 1.

[0109] By connecting the first via 14 with the second via 16, a portion of the surface of the first active layer 2 can be exposed, facilitating the later formation of the source and drain of the transistor in the first via 14 and the second via 16, and allowing the first active layer 2 to contact the source and drain formed in the first via 14 and the second via 16 to form an electrical connection.

[0110] It should be noted that after the S500, combined with Figure 4e , Figure 4f-1 and Figure 4f-2 The exposed surface of the first active layer 2 through the first via 14 and the second via 16 may have residual material of the interlayer dielectric layer 15. Afterwards, the display substrate can be cleaned with a cleaning agent to remove the residual material of the interlayer dielectric layer 15 on the exposed surface of the first active layer 2. Subsequently, after the source and drain of the transistor are formed on the first active layer 2, the contact resistance between the source of the transistor and the first active layer 2 can be reduced, and the contact resistance between the drain of the transistor and the first active layer 2 can be reduced. This can avoid affecting the electrical characteristics of the transistor containing the first active layer 2 and improve the display effect of the display substrate.

[0111] S600, see S600 Figure 4gA third via 17 is formed that penetrates the interlayer dielectric layer 15 and at least part of the second functional layer 5, and the third via 17 exposes part of the surface of the second active layer 4.

[0112] For example, a method of forming a third via 17 that penetrates the interlayer dielectric layer 15 and at least part of the second functional layer 5 includes a photolithography process.

[0113] It should be noted that, see Figure 4g The third via 17 penetrates at least part of the fifth gate insulating layer 13 in the second functional layer 5.

[0114] For example, the diameter of the first via 14 is smaller than the diameter of the third via 17.

[0115] By exposing a portion of the surface of the second active layer 4 through the third via 17, it is convenient to form the source and drain of the transistor in the third via 17 in subsequent steps, and to make the source and drain contact with a portion of the surface of the second active layer 4 to form an electrical connection.

[0116] Since the third via 17 is formed after the first via 14 and the second via 16, see [link / reference] Figure 4g During the process of removing the material of the interlayer dielectric layer 15 remaining on part of the surface of the first active layer 2 by using a cleaning agent through the first via 14 and the second via 16, the second functional layer 5 on the second active layer 4 can protect the second active layer 4 and prevent the second active layer 4 from being exposed to the cleaning agent and causing corrosion.

[0117] Therefore, the method for fabricating a display substrate provided in some embodiments of this disclosure involves first forming a first via 14 that penetrates at least a portion of the second functional layer 5 and at least a portion of the first functional layer 3 and exposes a portion of the surface of the first active layer 2, then forming an interlayer dielectric layer 15 on the second functional layer 5, and finally forming a third via 17 that penetrates the interlayer dielectric layer 15 and at least a portion of the second functional layer 5. This allows the display substrate to be cleaned with a cleaning agent before forming the third via 17 to remove residual material of the interlayer dielectric layer 15 on the exposed surface of the first active layer 2. This not only protects the second active layer 4 using the second functional layer 5, preventing corrosion caused by exposure to the cleaning agent, but also avoids increasing the contact resistance between the source and the first active layer 2, and between the drain and the first active layer 2, after the source and drain are subsequently formed on the first active layer 2. This also avoids affecting the electrical characteristics of the finally formed transistors and the display effect of the display substrate.

[0118] The inventors of this disclosure have verified the fabrication method of the display substrate disclosed herein. The verification method includes: ① fabricating a display substrate using the fabrication method of this disclosure, and testing the electrical characteristics of the transistor (taking a driving transistor as an example) formed in the display substrate containing a first active layer 2. ② fabricating a display substrate using one of the implementation methods mentioned above, and testing the electrical characteristics of the transistor (taking a driving transistor as an example) formed in the display substrate containing a first active layer 2'. The aspect ratio of the channel of the thin-film transistor formed in both fabrication methods is, for example, 3 / 23.

[0119] Table 1

[0120] Referring to Table 1 above, the standard requirements for the mobility of transistors are: 80cm² / Vs to 130cm² / Vs, and the standard requirements for the contact resistance of transistors (i.e., the contact resistance between the active layer and the source, and the contact resistance between the active layer and the drain) are: less than 2000Ω.

[0121] In the display substrate fabricated using one of the implementation methods mentioned above, the transistor mobility is 5 cm² / Vs, which is outside the standard mobility requirement (80 cm² / Vs~130 cm² / Vs). In other words, the transistor mobility does not meet the standard. The transistor contact resistance is 603662 Ω, which is also outside the standard contact resistance requirement (<2000 Ω). In other words, the transistor contact resistance does not meet the standard.

[0122] The display substrate fabricated using the method of this disclosure exhibits a transistor mobility of 135 cm² / Vs, which falls within the standard mobility requirement range (80 cm² / Vs to 130 cm² / Vs). In other words, the transistor mobility in this disclosure essentially meets the standard. The transistor contact resistance is 1358 ± 389 Ω, which falls within the standard contact resistance requirement range (< 2000 Ω). In other words, the transistor contact resistance in this disclosure meets the standard.

[0123] Therefore, it can be demonstrated that the display substrate fabrication method disclosed herein can effectively increase the mobility of the fabricated transistors and effectively reduce the contact resistance between the active layer and the source electrode, and the contact resistance between the active layer and the drain electrode of the transistors.

[0124] In some embodiments, combined with Figure 4e , Figure 4f-1 and Figure 4f-2In the above S500, during the process of removing the portion of the interlayer dielectric layer 15 that fills the first via 14 and forming a second via 16 in the interlayer dielectric layer 15 that communicates with the first via 14, the method for preparing the display substrate further includes S510.

[0125] S510, a fourth via 18 is formed that penetrates the interlayer dielectric layer 15. The orthogonal projection of the fourth via 18 onto the substrate 1 is within the orthogonal projection range of the second active layer 4 onto the substrate 1.

[0126] For example, the present disclosure may employ photolithography to etch the interlayer dielectric layer 15 to form the fourth via 18.

[0127] By positioning the orthogonal projection of the fourth via 18 onto the substrate 1 within the orthogonal projection range of the second active layer 4 onto the substrate 1, it is convenient to later form the fifth via 19, as described below, through the fourth via 18, penetrating at least a portion of the second functional layer 5.

[0128] For example, the number of fourth vias 18 is set to correspond to the number of second active layers 4.

[0129] Optionally, the number of fourth vias 18 is twice the number of second active layers 4. For example, there are two second active layers 4 and four fourth vias 18. Or, there are six second active layers 4 and twelve fourth vias 18.

[0130] At this point, in the aforementioned S600, combined with Figure 4g and Figure 5 The step of forming a third via 17 that penetrates the interlayer dielectric layer 15 and at least part of the second functional layer 5 includes: S610.

[0131] S610, see S610. Figure 5 The second functional layer 5 is patterned through the fourth via 18 to form a fifth via 19 that penetrates at least a portion of the second functional layer 5. The third via 17 includes the fourth via 18 and the fifth via 19.

[0132] For example, the process of forming the fourth via 18 through the interlayer dielectric layer 15 may include a photolithography process.

[0133] By forming a fourth via 18 that penetrates the interlayer dielectric layer 15, the film thickness of the display substrate at the fourth via 18 can be reduced, which is beneficial for the film thickness that needs to be etched when patterning the second functional layer 5 through the fourth via 18.

[0134] Combination Figure 4e and Figure 5The second functional layer 5 is patterned by passing through the fourth via 18 through the interlayer dielectric layer 15 to form a fifth via 19 that passes through at least a portion of the second functional layer 5. This allows the fourth via 18 and the fifth via 19 to be interconnected, thereby forming a third via 17 that includes the fourth via 18 and the fifth via 19. This exposes a portion of the surface of the second active layer 4, which is beneficial for subsequent processes to form the first conductive film as described below in the third via 17 and to couple the first conductive film with a portion of the surface of the second active layer 4.

[0135] For example, the method of patterning the second functional layer 5 includes a photolithography process. The diameter of the fourth via 18 is, for example, larger than the diameter of the fifth via 19.

[0136] In other examples, combined Figure 4e and Figure 4f-1 During the process of removing the portion of the interlayer dielectric layer 15 that fills the first via 14, the fourth via 18 may not be formed. In this case, during the process of forming the third via 17 that penetrates the interlayer dielectric layer 15 and at least part of the second functional layer 5 in the above S600, it is necessary to etch the interlayer dielectric layer 15 and the second functional layer 5 simultaneously.

[0137] See in some examples Figure 4b Before the first active layer 2, the first functional layer 3, the second active layer 4, and the second functional layer 5 are sequentially formed on the substrate 1, the method for fabricating the display substrate further includes: forming an inorganic layer 20 on the substrate 1. The first active layer 2 is formed on the inorganic layer 20.

[0138] For example, the inorganic layer 20 includes a barrier layer 21 and a first buffer layer 22. The inorganic layer 20 is used to protect the display substrate.

[0139] For example, a method for forming the inorganic layer 20 may include: sequentially forming a barrier layer 21 and a first buffer layer 22 on a substrate 1.

[0140] For example, the materials of the barrier layer 21 and the first buffer layer 22 are both inorganic materials.

[0141] For example, the barrier layer 21 may be a single-layer structure, and the material of the barrier layer 21 may include silicon oxide (SiO). The first buffer layer 22 may be a double-layer structure, and the material of each layer in the double-layer structure of the first buffer layer 22 may include one of silicon oxide (SiO) and silicon nitride (SiN).

[0142] For example, during the process of sequentially forming a barrier layer 21 and a first buffer layer 22 on a substrate 1, the method for fabricating a display substrate further includes forming a light-shielding layer 22 located between the barrier layer 21 and the first buffer layer 22. The orthographic projection of the first active layer 2 on the substrate 1 is located within the orthographic projection range of the light-shielding layer 22 on the substrate 1.

[0143] For example, the light-shielding layer 23 is used to block light from the side of the display substrate closest to the substrate 1 that is incident on the display substrate. The material of the light-shielding layer 23 may include, for example, a metal or a black organic material.

[0144] It is understandable that the electrical characteristics of the first active layer 2 are greatly affected by light. By setting the orthographic projection of the first active layer 2 on the substrate 1 within the orthographic projection range of the light-shielding layer 23 on the substrate 1, the light-shielding layer 23 can block the light rays that are emitted from the side of the substrate 1 away from the first active layer, thereby avoiding the influence of the light rays on the electrical characteristics of the first active layer 2.

[0145] In some embodiments, see Figure 4b The substrate 1 has a display area A and a non-display area B. The non-display area includes a bending area (also known as a Pad Bending area) B1. The first active layer 2 and the second active layer 4 are located in the display area A.

[0146] For example, display area A is the area used to display images. Non-display area B is the area other than display area A.

[0147] The bending region B1 is a region in the formed display substrate that can be bent. By bending the display substrate in the bending region, a portion of the display substrate can be bent to the side of the display substrate closer to the substrate 1. In this way, the space occupied by the display substrate can be reduced on the plane where the display substrate is located.

[0148] In some examples, in the above S300, the method for fabricating the display substrate further includes S310a during the process of forming the first via 14 that penetrates at least a portion of the second functional layer 5 and at least a portion of the first functional layer 3.

[0149] S310a, see S310a. Figure 4d A first groove 24 is formed that penetrates at least a portion of the second functional layer 5 and at least a portion of the first functional layer 3. The first groove 24 is located in the bending area and exposes a portion of the surface of the inorganic layer 20.

[0150] For example, see Figure 4c and Figure 4dDuring the formation of the first via 14, the portions of the first functional layer 3 and the second functional layer 5 located within the first via 14 need to be removed. Similarly, during the formation of the first groove 24, the portions of the first functional layer 3 and the second functional layer 5 located within the first groove 24 need to be removed. The removed film layers are the same. By forming the first groove 24 during the formation of the first via 14, the first via 14 and the first groove 24 can be formed in a single patterning process, simplifying the fabrication process of the display substrate 100.

[0151] Furthermore, by forming the first groove 24, the thickness of the display substrate located in the bending region B1 can be reduced, which is beneficial for subsequent steps to remove the portion of the inorganic layer 20 located in the bending region B1.

[0152] Understandably, after the first recess 24 is formed on the display substrate, during the process of forming the interlayer dielectric layer 15 on the second functional layer 5 in the above-described S400, [the following occurs]... Figure 4d and Figure 4e A portion of the interlayer dielectric layer 15 will also fill the first groove 24. See S500 thereafter. Figure 4f-1 and Figure 4f-2 During the process of removing the portion of the interlayer dielectric layer 15 that fills the first via 14, the portion of the interlayer dielectric layer 15 that fills the first groove 24 will also be removed simultaneously.

[0153] In some embodiments, the method for preparing the display substrate further includes steps S700 to S800.

[0154] S700, see S700 Figure 4h A first conductive film 25 is formed on the interlayer dielectric layer 15. The first conductive film 25 covers the surface of the interlayer dielectric layer 15 and is located in the first via 14, the second via 16, the third via 17 and the first groove 24.

[0155] S800, combined with Figure 4h and Figure 4i The first conductive film 25 is patterned, and the portion of the first conductive film 25 located in the first via 14 and the second via 16 is retained to obtain the first conductive pattern 26. The portion of the first conductive film 25 located in the third via 17 is retained to obtain the second conductive pattern 27.

[0156] For example, the material of the first conductive film 25 may include titanium (Ti), aluminum (Al), and titanium (Ti) stacked sequentially.

[0157] For example, the process of forming the first conductive film 25 on the interlayer dielectric layer 15 may include a metal sputtering process.

[0158] It should be noted that metal sputtering is a process in which high-energy particles (ions or neutral atoms and molecules) bombard the surface of a metal target, causing the atoms or molecules near the surface of the metal target to gain sufficient energy and eventually escape from the surface. Sputtering can only be performed under certain vacuum conditions.

[0159] See Figure 4h By placing the display substrate to be formed in the sputtering chamber, the material of the first conductive film 25 is formed on the interlayer dielectric layer 15 and in the first via 14, the second via 16, the third via 17 and the first groove 24 by the sputtering process.

[0160] For example, a method for patterning the first conductive film 25 includes a photolithography process.

[0161] It needs to be explained that, in combination Figure 4g , Figure 4h and Figure 4i The first conductive pattern 26 is in contact with the first active layer 2, and different first conductive patterns 26 respectively constitute the source and drain of the transistor.

[0162] The second conductive pattern 27 is in contact with the second active layer 4, and different second conductive patterns 27 respectively constitute the source and drain of the transistor.

[0163] In one implementation method, see [link to implementation details]. Figure 1 During the process of forming the first connection hole 6' exposing the first active layer 2' and the second connection hole 7' exposing the second active layer 4' at corresponding positions in the second insulating layer 5', a bending groove 9' is formed in the bending region B1'. The bending groove 9' penetrates the second insulating layer 5' and the first insulating layer 3' and exposes a portion of the surface of the substrate 1'. The material of the substrate 1' includes polyimide (PI), which readily absorbs moisture during the fabrication of the display substrate.

[0164] Therefore, combining Figure 2 and Figure 6a Subsequently, during the sputtering process to form the first conductive thin film 10' on the interlayer dielectric layer 8', moisture absorbed by the substrate 1' easily diffuses into the sputtering chamber. After the moisture is released, it affects the bombardment and deposition of the metal target by high-energy particles during the sputtering process. (See [link to relevant documentation]). Figure 6b This results in small protrusions forming on the final formed first conductive film 10', affecting the film formation quality of the final formed first conductive film 10', and ultimately affecting the quality of the structure obtained by etching the first conductive film 10'. See also Figure 6b and Figure 6c Because there are too many small protrusions in the structure obtained by etching the first conductive film 10', the structure obtained by etching the first conductive film 10' appears as multiple "small black dots" in optical inspection.

[0165] To address the aforementioned issues, one solution involves preheating the display substrate to be formed in a chemical vapor deposition (CVD) chamber before forming the first conductive film 10' on the surface of the second insulating layer 5'. The preheating conditions are: a preheating temperature of 150°C and a preheating time of 30 minutes. This preheating removes moisture absorbed from the substrate 1'. However, this solution requires additional fabrication steps for the display substrate, increases fabrication time, and raises fabrication costs.

[0166] In this disclosure, see [link to relevant document]. Figure 4f-1 , Figure 4f-2 and Figure 4g Before forming the first conductive thin film 25 by sputtering, the first groove 24 located in the bending region B1 penetrates only a portion of the second functional layer 5 and at least a portion of the first functional layer 3, exposing the inorganic layer 20, which covers the substrate 1. During the formation of the first conductive thin film 25 by sputtering, even if moisture is absorbed in the substrate 1, the inorganic layer 20 can block the moisture in the substrate 1, preventing it from being released into the sputtering chamber, thereby ensuring the film formation quality of the first conductive thin film 25. See also Figure 6d The surfaces of the first conductive pattern 26 and the second conductive pattern 27 formed using the preparation method of this disclosure do not exhibit "small black dots".

[0167] In some embodiments, the contact resistance between the first conductive pattern 26 and the first active layer 2 ranges from 969Ω to 1747Ω.

[0168] For example, the contact resistance of the first conductive pattern 26 and the first active layer 2 can be: 969Ω, 1100Ω, 1300Ω, 1358Ω, 1747Ω, etc.

[0169] In some embodiments, the method for preparing the display substrate further includes steps S900 to S1000.

[0170] S900, combined with Figure 4i and Figure 4j A passivation layer 28 is formed on the first conductive pattern 26 and the second conductive pattern 27. A portion of the passivation layer 28 is located within the first groove 24 and contacts the exposed portion of the inorganic layer 20.

[0171] S1000, see S1000. Figure 4k The passivation layer 28 is patterned, and at least the portion of the passivation layer 28 located within the first groove 24 is removed.

[0172] For example, the passivation layer 28 is used to provide insulating protection for the first conductive pattern 26 and the second conductive pattern 27. The material of the passivation layer 28 may include inorganic materials, for example, the material of the passivation layer 28 includes silicon oxide (SiO).

[0173] An exemplary method for forming a passivation layer 28 on a first conductive pattern 26 and a second conductive pattern 27 includes a deposition process.

[0174] Understandable, reference Figure 4i and Figure 4j Because the first groove 24 was formed before the passivation layer 28 was formed, the passivation layer 28 will also be formed in the first groove 24 during the formation of the passivation layer 28, and the passivation layer 28 formed in the first groove 24 will contact the exposed part of the inorganic layer 20 surface.

[0175] For example, a method for patterning the passivation layer 28 includes a photolithography process.

[0176] In one implementation, as described above, during the process of forming a first connection hole 6' exposing the first active layer 2' and a second connection hole 7' exposing the second active layer 4' at corresponding positions in the second insulating layer 5', see [reference needed]. Figure 2 A bending groove 9' is formed in the bending region B1'. The bending groove 9' penetrates the second insulating layer 5' and the first insulating layer 3', and exposes a portion of the surface of the substrate 1'. Figure 1 and Figure 7 Then, a first conductive pattern 10' is formed in the first connecting hole 6' and the second connecting hole 7', followed by the formation of a passivation layer 11'. Therefore, see... Figure 7 The passivation layer 11' is formed on the exposed surface of the substrate 1'. However, in one implementation, the portion of the passivation layer 11' located within the bending groove 9' is not removed during the patterning process. Since the photoresist used as a mask needs to be removed during the patterning process of the passivation layer 11', and the material of the passivation layer 11' includes inorganic materials while the material of the substrate 1' includes organic materials, the adhesion between the passivation layer 11' and the substrate 1' is weak. Therefore, a portion of the passivation layer 11' located within the bending groove 9' may peel off from the substrate 1' as the photoresist is removed. These peeled-off passivation layer fragments may enter the display area A' of the display substrate, causing display defects.

[0177] In this disclosure, see Figure 4k During the patterning process of the passivation layer 28, the portion of the passivation layer 28 located in the first groove 24 has been removed. Therefore, the method for preparing the display substrate disclosed herein can avoid the peeling of the passivation layer 28 as described above, thus avoiding display defects in the display substrate.

[0178] Furthermore, before the passivation layer 28 is formed in this disclosure, an inorganic layer 20 is covered on the substrate 1 in the first groove 24, and the material of the passivation layer 28 includes inorganic materials. Therefore, the passivation layer 28 has strong adhesion to the inorganic layer 20. Even if the portion of the passivation layer 28 located in the first groove 24 is not removed in S1000, the passivation layer 28 can be prevented from falling off the inorganic layer 20 and entering the display area A of the display substrate during the subsequent cleaning step after patterning the passivation layer 28, thereby avoiding display defects of the display substrate.

[0179] On the other hand, by removing at least the portion of the passivation layer 28 located within the first groove 24, it is beneficial to subsequently pattern the inorganic layer 20 exposed through the first groove 24. It is understood that the more inorganic layers in a display substrate, the greater its rigidity and the lower its resistance to deformation. Therefore, during the patterning process of the passivation layer 28, removing at least the portion of the passivation layer 28 located within the first groove 24 maximizes the removal of inorganic layers from the display substrate, thereby reducing its rigidity and increasing its resistance to deformation.

[0180] In some embodiments, combined with Figure 4k , Figure 4l and Figure 4m The methods for preparing the display substrate also include: S1100a~S1200a.

[0181] S1100a, the inorganic layer 20 is patterned through the first groove 24 to form a second groove 29 that communicates with the first groove 24, and the second groove 29 exposes a portion of the surface of the substrate 1.

[0182] S1200a, a first planarization layer 33 is formed, a portion of the first planarization layer 33 fills the first groove 24 and the second groove 29, and contacts the exposed portion of the surface of the substrate 1.

[0183] For example, a method for patterning the inorganic layer 20 includes a photolithography process.

[0184] By forming a second groove 29 that communicates with the first groove 24 and exposes a portion of the surface of the substrate 1, each film layer in the regions of the first groove 24 and the second groove 29 can be completely removed, reducing the film thickness of the inorganic layer located in the bending region B1. This allows for the filling of more organic material into the bending region B1 in subsequent steps, thereby increasing the resistance of the display substrate 100 to deformation.

[0185] For example, the first planarization layer 33 is used to form a flat surface, which is beneficial for the subsequent formation of other film layers on the first planarization layer 33.

[0186] For example, the material of the first planarization layer 33 may include an organic material. For instance, the material of the first planarization layer 33 may include polyimide (PI).

[0187] For example, a method of forming the first planarization layer 33 includes a coating process.

[0188] By filling a portion of the first planarization layer 33 into the first groove 24 and the second groove 29 and making contact with the exposed surface of the substrate 1, as much material of the first planarization layer 33 as possible can be filled into the bending region B1, thereby enhancing the bending performance of the bending region B1 located in the areas of the first groove 24 and the second groove 29.

[0189] In some embodiments, see Figure 4d The non-display area B also includes a cutting area B2 located on the side of the bending area B1 away from the display area A. During the process of forming the first groove 24 penetrating at least a portion of the second functional layer 5 and at least a portion of the first functional layer 3 in S310a, the method for fabricating the display substrate further includes: S310b.

[0190] S310b, see S310b Figure 4d A third groove 31 is formed that penetrates at least a portion of the second functional layer 5 and at least a portion of the first functional layer 3. The third groove 31 is located in the cutting area B2 and exposes a portion of the surface of the inorganic layer 20.

[0191] For example, the cutting area B2 is used to cut the display substrate.

[0192] For example, the substrate described above can be used to form a display motherboard, which includes a plurality of correspondingly arranged display areas A and non-display areas B. By cutting the display motherboard, it can be divided into multiple display substrates, each of which has a display area A and a non-display area B.

[0193] For example, see Figure 4d In the process of forming a first groove 24 that penetrates at least a portion of the first functional layer 3 and at least a portion of the second functional layer 5, a third groove 31 that penetrates at least a portion of the first functional layer 3 and at least a portion of the second functional layer 5 is formed. This allows the first groove 24 and the third groove 31 to be formed in a single patterning process, thereby simplifying the manufacturing process of the display substrate.

[0194] For example, by exposing a portion of the surface of the inorganic layer 20 in the third groove 31, the thickness of the display substrate 100 in the cutting region B2 can be reduced, which is beneficial for subsequent steps to continue processing of the inorganic layer 20 in the cutting region B2.

[0195] Understandably, after the third recess 31 is formed on the display substrate, in S400, during the process of forming the interlayer dielectric layer 15 on the second functional layer 5, [the following occurs]... Figure 4dand Figure 4e A portion of the interlayer dielectric layer 15 will also fill the third groove 31.

[0196] In the subsequent S500, see Figure 4f-1 and Figure 4f-2 During the process of removing the portion of the interlayer dielectric layer 15 that fills the first via 14, the portion of the interlayer dielectric layer 15 that fills the third groove 31 will also be removed.

[0197] Afterwards, combined Figure 4g and Figure 4h During the formation of the first conductive film 25 on the interlayer dielectric layer 15, i.e., in S700, a portion of the first conductive film 25 is also formed within the third groove 31. Combined with... Figure 4g , Figure 4h and Figure 4i During the patterning process of the first conductive film 25, i.e. in S700, the portion of the first conductive film 25 located in the third groove 31 is also removed.

[0198] Afterwards, combined Figure 4j and 4k During the formation of the passivation layer 28 on the first conductive pattern 26 and the second conductive pattern 27, i.e., in S900, a portion of the passivation layer 28 is formed within the third groove 31 and contacts the exposed surface of the inorganic layer 20. During the patterning of the passivation layer 28, i.e., in S1000, the portion of the passivation layer 28 located within the third groove 31 is also removed.

[0199] In some embodiments, combined with Figure 4k , Figure 4l and Figure 4m The methods for preparing the display substrate also include: S1100b~S1200b.

[0200] S1100b, the inorganic layer 20 is patterned through the third groove 31 to form a fourth groove 32 that communicates with the third groove 31, and the fourth groove 32 exposes part of the surface of the substrate 1.

[0201] S1200b, a first planarization layer 33 is formed, a portion of the first planarization layer 33 fills the third groove 31 and the fourth groove 32, and contacts the exposed portion of the surface of the substrate 1.

[0202] For example, a method for patterning the inorganic layer 20 includes a photolithography process.

[0203] For example, S1100a and S1100b can be performed in a single patterning process; S1200a and S1200b can be performed in a single patterning process; this simplifies the fabrication process of the display substrate.

[0204] By forming a fourth groove 32 that communicates with the third groove 31 and exposes a portion of the surface of the substrate 1, the portions of each film layer located in the regions of the third groove 31 and the fourth groove 32 can be completely removed, thereby reducing the film thickness of the inorganic layer located in the cutting region B2, and then in subsequent steps, organic materials can be filled into the cutting region B2.

[0205] It should be noted that when inorganic materials fracture, cracks can easily propagate through the inorganic layer to other areas. Organic materials, on the other hand, are more flexible and can prevent crack propagation to other areas when fracture occurs.

[0206] By filling the third groove 31 and the fourth groove 32 with a portion of the first planarization layer 33 and making contact with the exposed surface of the substrate 1, cracks can be avoided in the cutting area B2 and prevented from propagating to other areas (e.g., display area A) during subsequent cutting of the cutting area B2.

[0207] In some embodiments, combined with Figure 4d The display area A of the display substrate includes multiple pixel circuit areas A1 ( Figure 4c Only one pixel circuit area A1 is shown in the diagram. In the process of forming the first via 14 that penetrates at least a portion of the first functional layer 3 and at least a portion of the second functional layer 5, i.e., in S300, the method for fabricating the display substrate further includes: S310c.

[0208] S310c, forming a fifth groove 34 that penetrates at least a portion of the second functional layer 5 and at least a portion of the first functional layer 3, the fifth groove 34 being located between two adjacent pixel circuit regions A1.

[0209] Combination Figure 4d and Figure 4e During the process of forming the interlayer dielectric layer 15 on the second functional layer 5, that is, in S400, a portion of the interlayer dielectric layer 15 is also filled with the fifth groove 34.

[0210] For example, pixel circuit area A1 represents the area in the display substrate where pixel circuitry is disposed. For instance, in conjunction with... Figure 4c and Figure 4i The region is provided with a first active layer 2, a second active layer 4, a first conductive pattern 26, and a second conductive pattern 27.

[0211] Understandably, the display substrate contains multiple pixel driving circuits, with each pixel driving circuit located in a pixel circuit area A1.

[0212] It should be noted that, see Figure 4c The fifth groove 34 penetrates at least a portion of the second functional layer 5 and at least a portion of the first functional layer 3, including the fifth gate insulating layer 13, the third gate insulating layer 10, the second gate insulating layer 8, and the first gate insulating layer 6.

[0213] For example, see Figure 4c The method of forming a fifth groove 34 that penetrates at least a portion of the second functional layer 5 and at least a portion of the first functional layer 3 includes a photolithography process.

[0214] By forming a fifth groove 34 between two adjacent pixel circuit regions A1, the portion of the first functional layer 3 and the second functional layer 5 located between two adjacent pixel circuit regions A1 can be removed.

[0215] Understandably, the more inorganic layers in a display substrate, the greater its rigidity and the lower its resistance to deformation. Therefore, by removing the inorganic film layer between two adjacent pixel circuit areas, the rigidity of the portion of the display substrate located between these areas can be reduced, thereby increasing the substrate's resistance to deformation.

[0216] Furthermore, the interlayer dielectric layer 15 includes organic materials with good toughness. By filling a portion of the interlayer dielectric layer 15 into the fifth groove 34, the toughness between two adjacent pixel circuit regions A1 can be increased, further increasing the display substrate's ability to withstand deformation.

[0217] In some embodiments, the step of forming the fifth groove 34 penetrating at least a portion of the second functional layer 5 and at least a portion of the first functional layer 3 includes: see Figure 4c Before forming the first via 14 penetrating at least a portion of the first functional layer 3 and at least a portion of the second functional layer 5 in S300: a sixth groove 35 penetrating at least a portion of the second functional layer 5 and the third gate insulating layer 10 is formed, the sixth groove 35 being located between two adjacent pixel circuit regions. Then, during the formation of the first via 14 penetrating at least a portion of the second functional layer 5 and at least a portion of the first functional layer 3 in S300, see [link to S300 documentation]. Figure 4d A seventh groove 36 is formed through the sixth groove 35, penetrating the second gate insulating layer 27 and the first gate insulating layer 25 and communicating with the sixth groove 35. The fifth groove 34 includes the sixth groove 35 and the seventh groove 36.

[0218] For example, see Figure 4c The method for forming the sixth groove 35 that penetrates at least a portion of the second functional layer 5 and the third gate insulating layer 10 includes a photolithography process.

[0219] For example, by forming the sixth groove 35, the thickness of the display substrate located in the portion of the sixth groove 35 can be reduced, which is beneficial for the subsequent formation of the seventh groove 34 through the sixth groove 35.

[0220] For example, see Figure 4cThe method for forming the seventh groove 36, which penetrates the second gate insulating layer 27 and the first gate insulating layer 25 and communicates with the sixth groove 35, includes a photolithography process.

[0221] Furthermore, the first via 14 and the seventh groove 36 can be formed in the same process, which can simplify the manufacturing process of the display substrate.

[0222] Understandably, after the formation of the first planarization layer 33, the fabrication method of the display substrate also includes S1300 and S1400.

[0223] S1300, see S1300. Figure 4n A via is formed on the first planarization layer 33, and a third conductive pattern 36 is formed thereon. A second planarization layer 37 is then formed on the third conductive pattern 36.

[0224] S1400, see S1400. Figure 4o An anode 38, a pixel defining layer 39, a blocking portion 40, a light-emitting layer 41, a cathode 42, an encapsulation layer 43, and a cover plate 44 are sequentially formed on the second flat layer 37.

[0225] For example, the third conductive pattern 36 is used to relay the signal from the first conductive pattern 36. The second planarization layer 37 is used to provide a flat surface for subsequent film layers. The anode 38 is used to receive the signal from the third conductive pattern 36 and transmit it to the light-emitting layer 41. The pixel defining layer 39 is used to form an opening. The barrier portion 40 is used to support the display substrate to be formed during the formation of the light-emitting layer 41 using a vapor deposition process. The anode 38, the light-emitting layer 41, and the cathode 42 form a light-emitting device, which is used to display an image in the display area A of the display substrate. The encapsulation layer 43 is used to protect the light-emitting device. The cover plate 44 is used to protect the formed display substrate.

[0226] The following is combined with Figures 8a-8d The regions formed by certain steps in the fabrication method of the display substrate are explained.

[0227] As mentioned above, combined Figure 4c and Figure 8a In the method for fabricating the display substrate disclosed herein, before forming a first via 14 penetrating at least a portion of the second functional layer 5 and at least a portion of the first functional layer 3 in S300: a sixth groove 35 penetrating at least a portion of the second functional layer 5 and the third gate insulating layer 10 is formed, the sixth groove 35 being located between two adjacent pixel circuit regions A1.

[0228] It should be noted that Figure 8aRegion A in the text refers to the region where the sixth groove 35 is located. That is, before the first via 14 penetrating at least part of the second functional layer 5 and at least part of the first functional layer 3 is formed in S300, the portion of the second functional layer 5 and the third gate insulating layer 10 located in this region is removed.

[0229] Combination Figure 4c and Figure 8b After S300 forms the first through hole 14, S310a forms the first groove 24, S310b forms the third groove 31, and S310c forms the fifth groove 34, Figure 8a Become Figure 8b .

[0230] It should be noted that, Figure 8b Region B in the diagram refers to the area containing the first through-hole 14, the first groove 24, and the third groove 31. (See also...) Figure 4d It is understandable that the area where the fifth groove 34 formed by S310c is located coincides with area A.

[0231] Combination Figure 4e and Figure 8c In S400, an interlayer dielectric layer 15 is formed. In S500, the portion of the interlayer dielectric layer 15 that filled the first via 14, the first groove 24, and the third groove 31 is removed. In S510, a fourth via 18 penetrating the interlayer dielectric layer 15 is formed. Figure 8b Become Figure 8c .

[0232] It should be noted that, in combination Figures 4d to 4f-2 , Figure 8c Region C in the diagram refers to the area where the interlayer dielectric layer 15 remains after the portion of the interlayer dielectric layer 15 that was used to fill the first via 14, the first groove 24, and the third groove 31 has been removed. (See also...) Figure 4f-1 and Figure 4f-2 It is understandable that the remaining part of the interlayer dielectric layer 15 is located in the same region as... Figure 8c The regions A in the diagram overlap. (Combined) Figure 4f-2 , Figure 8c The D region in the diagram refers to the region where the fourth via 18, which forms a through-layer dielectric layer 15, is located in S510.

[0233] Combination Figure 4f-1 , Figure 4f-2 , Figure 4g and Figure 8c After the third via 17, which penetrates the interlayer dielectric layer 15 and at least part of the second functional layer 5, is formed in S600, the region where the third via 17 is located coincides with the region where the fourth via 18 is located. Therefore, after S600, Figure 8c No change.

[0234] Combination Figure 4h , Figure 4i and Figure 8d In step S700, a first conductive thin film 25 is formed on the interlayer dielectric layer 15. The first conductive thin film 25 is then patterned to obtain a first conductive pattern 26 and a second conductive pattern 27. Figure 8c Become Figure 8d .

[0235] It should be noted that, in combination Figure 4i The area where the first conductive pattern 26 and the second conductive pattern 27 are located is Figure 8d Region E in the text.

[0236] On the other hand, some embodiments of this disclosure provide a display substrate 100, which is formed, for example, by the display substrate preparation method provided in the above embodiments.

[0237] See Figure 9 The display substrate 100 includes a substrate 1 and a first active layer 2, a first functional layer 3, a second active layer 4, a second functional layer 5, and an interlayer dielectric layer 15 sequentially stacked on the substrate 1. The display substrate 100 also includes a first via 14, a second via 16, and a third via 17. The first via 14 penetrates at least a portion of the second functional layer 5 and at least a portion of the first functional layer 3, and exposes a portion of the surface of the first active layer 2. The second via 16 penetrates the interlayer dielectric layer 15 and communicates with the first via 14. The third via 17 exposes a portion of the surface of the second active layer 4. The first via 14 is formed first, and the third via 17 is formed later, compared to the interlayer dielectric layer. The diameter of the first via 14 is smaller than the diameter of the second via 16, and the diameter of the first via 14 is smaller than the diameter of the third via 17.

[0238] For example, by making the aperture of the first via 14 smaller than the aperture of the second via 16, interference can be avoided in the process of removing the interlayer dielectric layer 15 formed in the first via 14 due to the second via 16 being too small.

[0239] In one of the above implementations, as shown above, the first connecting hole 6' and the second connecting hole 7' are formed simultaneously, so the diameters of the first connecting hole 6' and the second connecting hole 7' are approximately the same.

[0240] In this disclosure, the first via 14 is formed first, and the third via 17 is formed later than the interlayer dielectric layer 15. This means that the first via 14 and the third via 17 are not formed simultaneously. Instead, after the first via 14 is formed, the interlayer dielectric layer 15 with the second via 16 is formed first, and then the third via 17 is formed.

[0241] It should be noted that the forming process of the first via 14 in this disclosure and the first connecting hole 6' in the above-mentioned implementation is the same, for example. Therefore, the hole diameter of the first via 14 in this disclosure and the first connecting hole 6' in the above-mentioned implementation is the same.

[0242] Therefore, in this disclosure, the aperture of the third via 17 is larger than that of the second connection hole 7' in the above-mentioned implementation, thereby increasing the area of ​​the second active layer 4 exposed by the third via 17 in this disclosure, which in turn increases the contact area between the source and drain and the second active layer 4, thereby reducing the contact resistance between the source and drain and the second active layer 4.

[0243] Furthermore, in this disclosure, the step of cleaning the display substrate with a cleaning agent is performed before the formation of the third via 17, thus avoiding corrosion of the second active layer 4 exposed by the cleaning agent in the subsequently formed third via 17.

[0244] The beneficial effects that the display substrate 100 provided in some embodiments of this disclosure can achieve are the same as the beneficial effects that the display substrate preparation method provided in some embodiments above can achieve, and will not be repeated here.

[0245] In some embodiments, see Figure 9 The display substrate 100 has a display area A and a non-display area B. The display area A includes a pixel circuit area A1. The display substrate 100 also includes a fifth recess 34 and a first recess 24. The fifth recess 34 penetrates at least a portion of the second functional layer 5 and at least a portion of the first functional layer 3, and is located between two adjacent pixel circuit areas A1. The first recess 24 penetrates at least a portion of the second functional layer 5 and at least a portion of the first functional layer 3. The depth of the second via 16 is less than or equal to the depth of the third via 17. The depth of the third via 17 is less than the depth of the first via 14. The depth of the first via 14 is less than the depth of the fifth recess 34. The depth of the fifth recess 34 is equal to the depth of the first recess 24.

[0246] For example, at least one pixel driving circuit P (such as...) is disposed within at least one pixel circuit region A1. Figure 10 (As shown).

[0247] The structure of the pixel driving circuit P described above can include various types, and can be selected and configured according to actual needs. For example, the structure of the pixel driving circuit P can include "2T1C", "6T1C", "7T1C", "6T2C" or "7T2C", etc. Here, "T" represents a thin-film transistor, and the number before "T" indicates the number of thin-film transistors; "C" represents a storage capacitor, and the number before "C" indicates the number of storage capacitors.

[0248] See Figure 10The following explanation will take the 7T1C structure of the pixel driving circuit P as an example.

[0249] It should be noted that the pixel driving circuit P may include multiple transistors. These multiple transistors may include a driving transistor T1, a compensation transistor T2, a first reset transistor T3, a first light-emitting control transistor T4, a second light-emitting control transistor T5, a switching transistor T6, and a second reset transistor T7.

[0250] In some examples, the control terminal of the first reset transistor T3 is electrically connected to the reset signal line ResetN, the first terminal of the first reset transistor T3 is electrically connected to the first initial signal line Vinit1, and the second terminal of the first reset transistor T3 is electrically connected to the fourth node N4. The first reset transistor T3 is configured to transmit the first initial signal provided by the first initial signal line Vinit1 to the fourth node N4 under the control of the reset signal provided by the reset signal line ResetN.

[0251] In some examples, the control terminal of the second reset transistor T7 is electrically connected to the first gate line GateP, the first terminal of the second reset transistor T7 is electrically connected to the second initial signal line Vinit2, and the second terminal of the second reset transistor T7 is electrically connected to the first node N1. The second reset transistor T7 is configured to transmit the second initial signal provided by the second initial signal line Vinit2 to the fourth node N4 under the control of the first gate signal provided by the first gate line GateP.

[0252] In some examples, the control terminal of the switching transistor T6 is electrically connected to the first gate line GateP, the first terminal of the switching transistor T6 is electrically connected to the data signal line Data, and the second terminal of the switching transistor T6 is electrically connected to the second node N2. The switching transistor T6 is configured to transmit the data signal provided by the data signal line Data to the second node N2 under the control of the first gate signal provided by the first gate line GateP.

[0253] In some examples, the control terminal of the driving transistor T1 is electrically connected to the fourth node N4, the first terminal of the driving transistor T1 is electrically connected to the second node N2, and the second terminal of the driving transistor T1 is electrically connected to the third node N3. The driving transistor T1 is configured to transmit an electrical signal (e.g., a data signal) from the second node N2 to the third node N3 under the control of the voltage of the fourth node N4.

[0254] In some examples, the control terminal of the compensation transistor T2 is electrically connected to the second gate line GateN, the first terminal of the compensation transistor T2 is electrically connected to the third node N3, and the second terminal of the compensation transistor T2 is electrically connected to the fourth node N4. The compensation transistor T2 is configured to transmit an electrical signal (e.g., a data signal) from the third node N3 to the fourth node N4 under the control of a second gate signal provided by the second gate line GateN.

[0255] In some examples, the control electrode of the first light-emitting control transistor T4 is electrically connected to the enable signal line EM, the first electrode of the first light-emitting control transistor T4 is electrically connected to the first power supply line VDD, and the second electrode of the first light-emitting control transistor T4 is electrically connected to the second node N2. The first light-emitting control transistor T4 is configured to transmit a first power signal provided by the first power supply line VDD to the second node N2 under the control of the enable signal provided by the enable signal line EM. The driving transistor T1 can transmit an electrical signal (e.g., the first power signal) from the second node to the third node N3.

[0256] In some examples, the control electrode of the second light-emitting control transistor T5 is electrically connected to the enable signal line EM, the first electrode of the second light-emitting control transistor T5 is electrically connected to the third node N3, and the second electrode of the second light-emitting control transistor T5 is electrically connected to the first node N1. The second light-emitting control transistor T5 is configured to transmit an electrical signal (e.g., a first power signal) from the third node N3 to the first node N1 under the control of the enable signal provided by the enable signal line EM.

[0257] It is understood that the control electrode of each transistor is the gate (e.g., the first gate 7, the second gate 9, or the third gate 12 mentioned in some of the above embodiments), the first electrode of each transistor is one of the source and the drain (e.g., the first conductive pattern 26 or the second conductive pattern 27 mentioned in some of the above embodiments), and the first electrode of each transistor is the other of the source and the drain (e.g., the first conductive pattern 26 or the second conductive pattern 27 mentioned in some of the above embodiments).

[0258] For example, see Figure 11 The diagram shows three transistors, 38-1, 38-2, and 38-3.

[0259] For example, the active layers of transistors 38-1 and 38-3 include polysilicon, so transistors 38-1 and 38-3 have high mobility, which can speed up the charging speed of the storage capacitor in the pixel driving circuit P.

[0260] Optionally, transistor 38-1 may include a second light-emitting control transistor T5 or a second reset transistor T7. Transistor 38-3 may include a driving transistor T1 or a first light-emitting control transistor T4.

[0261] For example, the active layer of transistor 38-2 includes metal oxide, so transistor 38-2 has lower leakage current.

[0262] Optionally, transistor 38-2 may include compensation transistor T2 or first reset transistor T3.

[0263] For example, in combination Figure 10 and Figure 11 The diagram illustrates an initial signal line 39 (which could be, for example, the first initial signal line Vinit1 or the second initial signal line Vinit2 mentioned in the example above). See also Figure 10 The initial signal line 39 is used to provide an initial signal. When the first reset transistor T3 and / or the second reset transistor T7 are turned on, the initial signal provided in the initial signal line 39 can reset the corresponding capacitor Cst and / or the light-emitting diode L.

[0264] For example, the interlayer dielectric layer 15 includes an organic material with good toughness. A portion of the interlayer dielectric layer 15 can fill the fifth groove 34, which can increase the toughness between two adjacent pixel circuit regions A1 and increase the display substrate 100's ability to withstand deformation.

[0265] It should be noted that the above depth represents the distance between the upper and lower surfaces of the via or groove in a direction perpendicular to the plane of the display substrate 100.

[0266] By setting the depth of the fifth groove 34 to be equal to the depth of the first groove 24, the thickness of the film layer removed during the formation of the fifth groove 34 and the first groove 24 can be the same. Therefore, the process parameters for forming the fifth groove 34 and the first groove 24 are the same, which simplifies the manufacturing process of the display substrate.

[0267] On the other hand, see Figure 12 Some embodiments of this disclosure provide a display device 1000, which includes a display substrate 100 as described in any of the examples above.

[0268] For example, the display device 1000 also includes a housing for protecting the display substrate 100.

[0269] The display substrate 100 included in the above-described display device 1000 has the same structure and beneficial effects as the display substrate 100 provided in some of the above examples, and will not be described again here.

[0270] In some examples, the display device 1000 can be any device that displays text or images, whether moving (e.g., video) or stationary (e.g., still images). More specifically, the embodiments described are contemplated to be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal digital assistants (PDAs), handheld or portable computers, Global Positioning System (GPS) receivers / navigators, cameras, Moving Picture Experts Group 4 (MP4) video players, camcorders, game consoles, watches, clocks, calculators, television monitors, computer monitors, automotive displays (e.g., odometer displays, etc.), navigators, cockpit controllers and / or displays, displays of camera views (e.g., displays of rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging and aesthetic structures (e.g., displays of images of a piece of jewelry), etc.

[0271] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A display substrate, characterized in that, The display substrate includes: Substrate; A first active layer, a first functional layer, a second active layer, a second functional layer, and an interlayer dielectric layer are sequentially formed on the substrate; the material of the second functional layer includes an inorganic material, and the material of the interlayer dielectric layer includes an organic material. A first via penetrates at least a portion of the second functional layer and at least a portion of the first functional layer, and the first via exposes a portion of the surface of the first active layer; The second via penetrates the interlayer dielectric layer and communicates with the first via; and, A third via penetrates the interlayer dielectric layer and at least a portion of the second functional layer, the third via exposing a portion of the surface of the second active layer; Wherein, the diameter of the first via is smaller than the diameter of the second via, and the diameter of the first via is smaller than the diameter of the third via.

2. The display substrate according to claim 1, characterized in that, The display substrate has a display area and a non-display area; the display area includes a pixel circuit area. The display substrate further includes: A fifth groove, penetrating at least a portion of the second functional layer and at least a portion of the first functional layer, is located between two adjacent pixel circuit regions; and, A first groove extends through at least a portion of the second functional layer and at least a portion of the first functional layer; Wherein, the depth of the second via is less than or equal to the depth of the third via, the depth of the third via is less than the depth of the first via, the depth of the first via is less than the depth of the fifth groove, and the depth of the fifth groove is equal to the depth of the first groove.

3. The display substrate according to claim 2, characterized in that, The display substrate includes a pixel driving circuit, a first gate line, a second gate line, a reset signal line, an initial signal line, and a data signal line; One of the pixel driving circuits is disposed in one of the pixel circuit regions, and the pixel driving circuit includes: A driving transistor, wherein the control electrode of the driving transistor is electrically connected to the fourth node, the first electrode is electrically connected to the second node, and the second electrode is electrically connected to the third node; A compensation transistor, wherein the control electrode of the compensation transistor is electrically connected to the second gate line, the first electrode is electrically connected to the third node, and the second electrode is electrically connected to the fourth node; A first reset transistor, wherein the control electrode of the first reset transistor is electrically connected to the reset signal line, the first electrode is electrically connected to the initial signal line, and the second electrode is electrically connected to the fourth node; A switching transistor, wherein the control electrode of the switching transistor is electrically connected to the first gate line, the first electrode is electrically connected to the data signal line, and the second electrode is electrically connected to the second node.

4. The display substrate according to claim 3, characterized in that, The display substrate also includes an enable signal line, a first power supply line, and a second initial signal line; The pixel driving circuit also includes: The first light-emitting control transistor has its control electrode electrically connected to the enable signal line, its first electrode electrically connected to the first power line, and its second electrode electrically connected to the second node. The second light-emitting control transistor has its control electrode electrically connected to the enable signal line, its first electrode electrically connected to the third node, and its second electrode electrically connected to the first node. The second reset transistor has its control electrode electrically connected to the first gate line, its first electrode electrically connected to the second initial signal line, and its second electrode electrically connected to the first node.

5. The display substrate according to claim 4, characterized in that, At least one of the driving transistor, the first light-emitting control transistor, the second light-emitting control transistor, the switching transistor, and the second reset transistor includes the first active layer; at least one of the compensation transistor and the first reset transistor includes the second active layer.

6. The display substrate according to claim 1, characterized in that, Also includes: A first conductive pattern is disposed on the side of the interlayer dielectric layer away from the substrate, and fills the first via and the second via; A second conductive pattern is disposed on the side of the interlayer dielectric layer away from the substrate and fills the third via.

7. The display substrate according to claim 6, characterized in that, Also includes: A passivation layer is located on the side of the first conductive pattern and the second conductive pattern away from the substrate; The orthographic projection of the passivation layer on the substrate at least partially overlaps with the orthographic projection of the pixel circuit region on the substrate, and there is an opening between the portion of the passivation layer covering the first conductive pattern and the portion of the passivation layer covering the second conductive pattern.

8. The display substrate according to claim 7, characterized in that, The portion of the passivation layer covering the first conductive pattern and the portion of the passivation layer covering the second conductive pattern include vias that penetrate the passivation layer.

9. The display substrate according to claim 7, characterized in that, The orthographic projections of the first via, the second via, and the third via onto the substrate are located within the range of the orthographic projection of the passivation layer onto the substrate.

10. The display substrate according to claim 7, characterized in that, The display substrate has a display area and a non-display area. The non-display area includes a bending area and a cutting area. The bending area is located on one side of the display area, and the cutting area is located on the side of the bending area away from the display area. The orthographic projection of the passivation layer on the substrate does not overlap with the orthographic projection of the bending region and / or the cutting region on the substrate.

11. A display device, characterized in that, The display device includes: a display substrate according to any one of claims 1 to 10.

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