Display module and preparation method therefor, display panel, and display device

Abstract

A display module, a manufacturing method thereof, a display panel and a display device are provided. The display module comprises a substrate and a first circuit layer. The first circuit layer is arranged on one side of the substrate. The first circuit layer comprises a first pixel circuit part, a second pixel circuit part and a gate drive circuit arranged between the first pixel circuit part and the second pixel circuit part. The first pixel circuit part and the second pixel circuit part are electrically connected with the gate drive circuit. By arranging the gate drive circuit between the two pixel circuit parts, the maximum length of the conductive path between the gate drive circuit and the light emitting unit can be reduced, and the signal delay can be reduced.

Description

Technical Field

[0001] This application belongs to the field of display panel technology, and particularly relates to a display module and its manufacturing method, a display panel and a display device. Background Technology

[0002] Currently, organic light-emitting diode (OLED) and flat panel display devices based on light-emitting diode (LED) technologies are widely used and have become the mainstream of display devices due to their advantages such as high image quality, power saving, thin body and wide range of applications. Summary of the Invention

[0003] The purpose of this application is to provide a display module and its manufacturing method, a display panel and a display device.

[0004] A first aspect of this application provides a display module, including: a substrate; a first circuit layer disposed on one side of the substrate, the first circuit layer including a first pixel circuit portion and a second pixel circuit portion and a gate driving circuit disposed between the first pixel circuit portion and the second pixel circuit portion, the first pixel circuit portion and the second pixel circuit portion being electrically connected to the gate driving circuit.

[0005] In one embodiment, the system further includes: a light-emitting layer located on the side of the first circuit layer away from the substrate, the light-emitting layer including a plurality of light-emitting units; and a second circuit layer disposed between the first circuit layer and the light-emitting layer, the second circuit layer being used to electrically connect each of the light-emitting units to the first pixel circuit section or the second pixel circuit section.

[0006] In one embodiment, the light-emitting layer includes a first light-emitting region and a second light-emitting region; the orthogonal projection of the boundary line between the first light-emitting region and the second light-emitting region onto the first circuit layer is located in the gate driving circuit.

[0007] In one embodiment, the orthographic projection of the first light-emitting area onto the first circuit layer at least partially overlaps with the first pixel circuit portion, and the orthographic projection of the second light-emitting area onto the first circuit layer at least partially overlaps with the second pixel circuit portion.

[0008] In one embodiment, each light-emitting unit in the first light-emitting area is electrically connected to the first pixel circuit section through the second circuit layer; each light-emitting unit in the second light-emitting area is electrically connected to the second pixel circuit section through the second circuit layer.

[0009] In one embodiment, the number of light-emitting units in the first light-emitting region is the same as the number of light-emitting units in the second light-emitting region.

[0010] In one embodiment, the shape of the first light-emitting area is the same as the shape of the second light-emitting area.

[0011] In one embodiment, a pixel defining layer is further included. The pixel defining layer is disposed on the surface of the first circuit layer away from the substrate. The pixel defining layer encloses a pixel opening, and the light-emitting unit is located within the pixel opening.

[0012] In one embodiment, an isolation structure is further included, the isolation structure being disposed on the side surface of the pixel defining layer away from the substrate, the isolation structure enclosing to form a plurality of isolation openings, and the pixel openings being located within the isolation openings.

[0013] In one embodiment, the isolation structure includes a first isolation portion and a second isolation portion in sequence along the direction away from the substrate; the orthographic projection of the first isolation portion on the substrate is located within the orthographic projection of the second isolation portion on the substrate.

[0014] In one embodiment, the material of the first isolation portion includes aluminum, and the material of the second isolation portion includes titanium.

[0015] In one embodiment, an encapsulation layer is further included, which at least covers the surface of the light-emitting unit.

[0016] In one embodiment, the second circuit layer is provided with a plurality of conductive traces, one end of which is electrically connected to the first circuit layer, and the other end of which is electrically connected to the corresponding light-emitting unit.

[0017] In one embodiment, at least a portion of the conductive traces are made of indium tin oxide.

[0018] A second aspect of this application provides a method for fabricating a display module, comprising: providing a substrate; constructing a first circuit layer on one side of the substrate; wherein the first circuit layer includes a first pixel circuit portion and a second pixel circuit portion, and a gate driving circuit disposed between the first pixel circuit portion and the second pixel circuit portion, and both the first pixel circuit portion and the second pixel circuit portion are electrically connected to the gate driving circuit.

[0019] In one embodiment, the method further includes: sequentially constructing a second circuit layer and a light-emitting layer on the surface of the first circuit layer away from the substrate.

[0020] In one embodiment, the step of sequentially constructing a second circuit layer and a light-emitting layer on the side of the first circuit layer away from the substrate includes: sequentially constructing a second circuit layer, a first material layer, a second material layer, and a third material layer on the side of the first circuit layer away from the substrate; etching the third material layer to form a second isolation portion; etching the second material layer to form a first isolation portion; etching the first material layer within the isolation opening to construct a pixel defining layer; the pixel defining layer enclosing to form a pixel opening; and constructing a light-emitting unit within the pixel opening; wherein the orthographic projection of the first isolation portion on the substrate is located within the orthographic projection of the second isolation portion on the substrate.

[0021] A third aspect of this application provides a display panel, including at least one display module as described above.

[0022] In one embodiment, two display modules are arranged adjacent to each other along a first direction; the gate driving circuit of each display module extends along a second direction, wherein the first direction is perpendicular to the second direction.

[0023] A fourth aspect of this application provides a display device, including a display panel as described above.

[0024] The beneficial effects of the embodiments of this application compared with the prior art are: by placing the gate driving circuit between the two pixel circuit sections, the maximum length of the conductive path between the gate driving circuit and the light-emitting unit can be reduced, thereby reducing signal delay. Attached Figure Description

[0025] Figure 1 A cross-sectional schematic diagram of a display module provided in an embodiment of this application;

[0026] Figure 2 A top view schematic diagram of a display module provided in an embodiment of this application;

[0027] Figure 3 This is another cross-sectional schematic diagram of a display module provided in an embodiment of this application;

[0028] Figure 4 Another cross-sectional schematic diagram of a display module provided in an embodiment of this application;

[0029] Figure 5 Another cross-sectional schematic diagram of a display module provided in an embodiment of this application;

[0030] Figure 6 A flowchart illustrating a preparation method provided in one embodiment of this application;

[0031] Figure 7 A detailed flowchart of step S300 provided in an embodiment of this application;

[0032] Figure 8 A structural diagram of the device after step S310 is executed;

[0033] Figure 9 A structural diagram of the device after step S350 is executed;

[0034] Figure 10 A schematic diagram of a display panel provided in one embodiment of this application;

[0035] Figure 11 This is a schematic diagram of a display device provided in an embodiment of this application.

[0036] Reference numerals: 10, display module; 20, display panel; 30, display device; 100, substrate; 200, first circuit layer; 210, gate driving circuit; 220, first pixel circuit section; 221, first conductive trace; 222, second conductive trace; 230, second pixel circuit section; 300, second circuit layer; 310, third conductive trace; 320, fourth conductive trace; 400, light-emitting layer; 410, light-emitting unit; 420, first light-emitting area; 430, second light-emitting area; 440, pixel limiting layer; 450, isolation structure; 451, first isolation section; 452, second isolation section; 460, encapsulation layer; 500, first material layer; 600, second material layer; 700, third material layer. Detailed Implementation

[0037] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0038] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0039] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0040] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0041] In the field of display panel technology, display panels typically include display areas and non-display areas. Existing driving circuits are usually located in the non-display area and connected to the pixel circuits of the display area from the outside. As the size of display panels continues to increase, the conductive paths between the existing driving circuits and some pixels in the display area become longer and longer. Consequently, the transmission distance of the driving signals also becomes longer and longer, and the wiring load between the driving circuits and some pixels also increases accordingly. Excessive wiring load can lead to signal delay, which can even reach 100 milliseconds.

[0042] In particular, for the scanning signal generated by the Gate In Panel (GIP) circuit (or gate scan drive circuit), a large delay will affect the final display effect of the display panel.

[0043] Figure 1 A schematic diagram of a display module provided in one embodiment of this application is shown. For ease of explanation, only the parts relevant to this embodiment are shown, and the details are as follows:

[0044] The display module 10 includes a substrate 100 and a first circuit layer 200.

[0045] The first circuit layer 200 is disposed on one side of the substrate 100. The first circuit layer 200 includes a first pixel circuit section 220 and a second pixel circuit section 230, and a gate driving circuit 210 disposed between the first pixel circuit section 220 and the second pixel circuit section 230. Both the first pixel circuit section 220 and the second pixel circuit section 230 are electrically connected to the gate driving circuit 210.

[0046] It should be noted that the gate driving circuit 210 is used to generate and output multiple driving signals, one driving signal is used to drive multiple light-emitting units, and the first pixel circuit section 220 and the second pixel circuit section 230 are used to generate and output sub-driving signals corresponding to each light-emitting unit based on the driving signals.

[0047] By placing the gate driving circuit 210 in the middle of the first circuit layer 200, the gate driving circuit 210 can provide driving signals from the middle to the light-emitting units on both sides, thereby reducing the maximum length of the conductive path between the gate driving circuit 210 and the light-emitting unit and reducing signal delay.

[0048] In one embodiment, the display module 10 further includes a second circuit layer 300 and a light-emitting layer 400.

[0049] The light-emitting layer 400 is located on the side of the first circuit layer 200 away from the substrate 100, and the light-emitting layer 400 includes a plurality of light-emitting units 410. The second circuit layer 300 is disposed between the first circuit layer 200 and the light-emitting layer 400. The second circuit layer 300 is used to electrically connect each light-emitting unit 410 to the first pixel circuit section 220 or the second pixel circuit section 230.

[0050] The second circuit layer 300 is used to transmit the sub-driving signals provided by the first circuit layer 200 to each light-emitting unit 410. In some embodiments, the first pixel circuit section 220 and the second pixel circuit section 230 are used to transmit the driving signals to the second circuit layer 300, and the second circuit layer 300 is used to generate sub-driving signals corresponding to each light-emitting unit 410 based on the driving signals, and transmit each sub-driving signal to each light-emitting unit 410. It is understood that the first pixel circuit section 220, the second pixel circuit section 230 and the second circuit layer 300 all include a plurality of signal traces, and each signal trace can be set at the same or different levels. Signal traces at different levels can be connected through corresponding vias. This embodiment does not limit the specific structure and circuit of the first pixel circuit section 220, the second pixel circuit section 230 and the second circuit layer 300, and therefore will not be described in detail.

[0051] Specifically, the light-emitting layer 400 may include light-emitting units 410 of at least three colors, specifically red, green, and blue light-emitting units. This embodiment does not limit the specific structure of the light-emitting units 410 or the arrangement of each light-emitting unit 410. The composition and preparation of the light-emitting units 410 are further described in patents CN118251982A, 202410864269.8, PCT / CN2024 / 098407, PCT / CN2024 / 102783, PCT / CN2024 / 098217, PCT / CN2024 / 100935, PCT / CN2024 / 102785, PCT / CN2024 / 099419, PCT / CN2024 / 099072, and CN116685174A for reference.

[0052] In this embodiment, when the first circuit layer 200, the second circuit layer 300, and the light-emitting layer 400 are stacked sequentially, by placing the gate driving circuit 210 between the first pixel circuit section 220 and the second pixel circuit section 230, and connecting the gate driving circuit 210 to the stacked light-emitting layer 400 through the first pixel circuit section 220 and the second pixel circuit section 230 on both sides, the gate driving circuit 210 can provide driving signals from the middle to the light-emitting units 410 on both sides, thereby reducing the maximum length of the conductive path between the gate driving circuit 210 and the light-emitting unit 410 and reducing signal delay.

[0053] In one embodiment, such as Figure 2 As shown, the light-emitting layer 400 includes a first light-emitting region 420 and a second light-emitting region 430. The boundary line between the first light-emitting region 420 and the second light-emitting region 430 is located in the gate driving circuit 210 in the orthogonal projection of the first circuit layer 200.

[0054] It is understood that both the first light-emitting region 420 and the second light-emitting region 430 include multiple light-emitting units 410. When the boundary line between the first light-emitting region 420 and the second light-emitting region 430 is projected onto the gate driving circuit 210 in the first circuit layer 200, the gate driving circuit 210 penetrates the entire first circuit layer 200. Most of the light-emitting units 410 in the first light-emitting region 420 and most of the light-emitting units 410 in the second light-emitting region 430 are projected onto the gate driving circuit 210 on both sides of the first circuit layer 200. At the same time, a small portion of the light-emitting units 410 in the first light-emitting region 420 and a small portion of the light-emitting units 410 in the second light-emitting region 430 can also be projected onto the gate driving circuit 210 in the first circuit layer 200.

[0055] It should be noted that the area corresponding to the light-emitting layer 400 is the display area. The gate driving circuit 210 connects the light-emitting units 410 from the middle of the display area to both sides, which can reduce the maximum length of the conductive path between the gate driving circuit 210 and the light-emitting unit 410, thereby reducing the delay of the signal output by the gate driving circuit 210.

[0056] Specifically, the gate drive circuit 210 can provide low-latency scan signals from the center of the display area to each light-emitting unit 410 on both sides.

[0057] In one embodiment, the first light-emitting area 420 at least partially overlaps with the first pixel circuit section 220 in the orthographic projection of the first circuit layer 200, and the second light-emitting area 430 at least partially overlaps with the second pixel circuit section 230 in the orthographic projection of the first circuit layer 200.

[0058] Preferably, each light-emitting unit 410 in the first light-emitting area 420 is electrically connected to the first pixel circuit section 220 through the second circuit layer 300. Each light-emitting unit 410 in the second light-emitting area 430 is electrically connected to the second pixel circuit section 230 through the second circuit layer 300.

[0059] When the light-emitting layer 400 is divided into a first light-emitting region 420 and a second light-emitting region 430 by the gate driving circuit 210, and the orthographic projection of the first light-emitting region 420 on the first circuit layer 200 at least partially overlaps with the first pixel circuit section 220, and the orthographic projection of the second light-emitting region 430 on the first circuit layer 200 at least partially overlaps with the second pixel circuit section 230, the straight-line distance between the first pixel circuit section 220 and each light-emitting unit 410 in the first light-emitting region 420 is closer, and the straight-line distance between the second pixel circuit section 230 and each light-emitting unit 410 in the second light-emitting region 430 is closer, on this basis, each light-emitting unit 410 in the first light-emitting region 420 is electrically connected to the first pixel circuit section 220 through the second circuit layer 300, thereby obtaining the signal output by the gate driving circuit 210. Each light-emitting unit 410 in the second light-emitting area 430 is electrically connected to the second pixel circuit section 230 through the second circuit layer 300, thereby obtaining the signal output by the gate driving circuit 210, achieving the effect of shortening the length of the conductive path between each light-emitting unit 410 and the gate driving circuit 210, and reducing signal delay.

[0060] In some embodiments, the orthographic projection of the first light-emitting area 420 onto the first circuit layer 200 covers the entire first pixel circuit section 220, and the orthographic projection of the second light-emitting area 430 onto the first circuit layer 200 covers the entire second pixel circuit section 230.

[0061] It should be noted that the specific size and structure of the first pixel circuit section 220 and the second pixel circuit section 230 can be set according to actual needs. The first pixel circuit section 220 and the second pixel circuit section 230 can also exceed the orthographic projection of the first light-emitting area 420 and the second light-emitting area 430 on the first circuit layer 200. This application embodiment does not limit them, and only describes the spatial positional relationship between the first pixel circuit section 220, the second pixel circuit section 230, the first light-emitting area 420 and the second light-emitting area 430.

[0062] In one embodiment, the number of light-emitting units 410 in the first light-emitting region 420 is the same as the number of light-emitting units 410 in the second light-emitting region 430.

[0063] It should be noted that when the number of light-emitting units 410 in the first light-emitting area 420 is the same as the number of light-emitting units 410 in the second light-emitting area 430, that is, when the number of light-emitting units 410 electrically connected to the first pixel circuit section 220 is equal to the number of light-emitting units 410 electrically connected to the second pixel circuit section 230, the wiring density in the first pixel circuit section 220 and the wiring density in the second pixel circuit section 230 can be more balanced.

[0064] Furthermore, in some embodiments, each light-emitting unit 410 can be evenly distributed in the light-emitting layer 400, so that the length of the conductive path between the gate driving circuit 210 and each light-emitting unit 410 is more balanced.

[0065] In one embodiment, the shape of the first light-emitting area 420 is the same as the shape of the second light-emitting area 430. The shapes of the first light-emitting area 420 and the second light-emitting area 430 can be rectangular, annular, semi-circular, etc.

[0066] It should be noted that when the shape of the first light-emitting region 420 is the same as the shape of the second light-emitting region 430, the spatial distance between the light-emitting unit 410 and the gate driving circuit 210 is limited, so that the maximum length of the conductive path between the gate driving circuit 210 and the light-emitting unit 410 in the first light-emitting region 420 is equal to the maximum length of the conductive path between the gate driving circuit 210 and the light-emitting unit 410 in the second light-emitting region 430, thereby regulating the signal delay of each light-emitting unit 410.

[0067] Furthermore, in some embodiments, the geometric center of the orthographic projection of the light-emitting layer 400 onto the first circuit layer 200 is located on the gate driving circuit 210, and the arrangement pattern of the light-emitting units 410 in the first light-emitting region 420 is the same as the arrangement pattern of the light-emitting units 410 in the second light-emitting region 430. It can be understood that the number of light-emitting units 410 in the first light-emitting region 420 is the same as the number of light-emitting units 410 in the second light-emitting region 430. Exemplarily, in some embodiments, the light-emitting units 410 in the light-emitting layer 400 are arranged in a regular rectangular array, and the shape of the first light-emitting region 420 and the second light-emitting region 430 are both rectangular. The light-emitting units 410 in the light-emitting layer 400 are symmetrically arranged about the boundary line between the first light-emitting region 420 and the second light-emitting region 430 as an axis of symmetry. In this case, the gate driving circuit 210, which overlaps with the boundary line, can provide driving signals to the light-emitting units 410 on both sides of the boundary line with a low delay.

[0068] In one embodiment, such as Figure 3As shown, the display module 10 also includes a pixel limiting layer 440, which is disposed on the side surface of the first circuit layer 200 away from the substrate 100. The pixel limiting layer 440 encloses and forms a pixel opening, and the light-emitting unit 410 is located inside the pixel opening.

[0069] The pixel limiting layer 440 defines the boundary of the light-emitting unit 410. It should be noted that a circuit connected to the light-emitting unit 410 and used to drive the corresponding light-emitting unit 410 can be further constructed within the pixel limiting layer 440.

[0070] In one embodiment, such as Figure 3 As shown, the display module 10 also includes an isolation structure 450, which is disposed on the side surface of the pixel limiting layer 440 away from the substrate 100. The isolation structure 450 encloses and forms a plurality of isolation openings, and the pixel openings are located within the isolation openings.

[0071] The isolation structure 450 can isolate adjacent light-emitting units 410 and improve the light mixing effect between different light-emitting units 410.

[0072] In one embodiment, such as Figure 3 As shown, the isolation structure 450 includes a first isolation portion 451 and a second isolation portion 452 in sequence along the direction away from the substrate 100. The orthographic projection of the first isolation portion 451 on the substrate 100 lies within the orthographic projection of the second isolation portion 452 on the substrate 100.

[0073] When constructing the light-emitting unit 410, the isolation between pixel openings can be further strengthened by the first isolation portion 451 and the second isolation portion 452 to prevent the light-emitting materials used to construct the light-emitting unit 410 in different pixel openings from connecting together.

[0074] In one embodiment, the first isolation portion 451 is made of aluminum, and the second isolation portion 452 is made of titanium.

[0075] Compared to aluminum, titanium has stronger corrosion resistance, and the second isolation part 452 can protect the first isolation part 451 to a certain extent.

[0076] In one embodiment, the display module 10 further includes an encapsulation layer 460, which at least covers the surface of the light-emitting unit 410.

[0077] In some embodiments, such as Figure 3 As shown, the encapsulation layer 460 also covers the exposed surfaces of the various isolation structures and the pixel defining layer 440. Specifically, the encapsulation layer 460 may cover the surface of the first isolation portion 451 and the sidewall of the second isolation portion 452.

[0078] The encapsulation layer 460 can isolate the display module 10 from the external environment and fix and protect the structure of the display module 10.

[0079] In one embodiment, the second circuit layer 300 is provided with a plurality of conductive traces, one end of which is electrically connected to the first circuit layer 200, and the other end of which is electrically connected to the corresponding light-emitting unit 410. The first circuit layer 200 can transmit electrical signals to the light-emitting unit 410 through the conductive traces.

[0080] For example, such as Figure 4 , Figure 5 As shown, taking the circuit corresponding to a light-emitting unit 410 in the first light-emitting area 420 as an example, the first pixel circuit section 220 includes a first conductive trace 221 and a second conductive trace 222. The first conductive trace 221 and the second conductive trace 222 can be electrically connected to the gate driving circuit 210 to obtain a scanning signal. The second circuit layer 300 includes a third conductive trace 310 and a fourth conductive trace 320. The first conductive trace 221 can be connected to the third conductive trace 310 through a corresponding via, and the second conductive trace 222 can be connected to the fourth conductive trace 320 through a corresponding via. The third conductive trace 310 and the fourth conductive trace 320 can also be connected to the corresponding light-emitting unit 410 through corresponding vias. Finally, the signal transmission between the gate driving circuit 210 and the light-emitting unit 410 is realized through the first conductive trace 221, the second conductive trace 222, the third conductive trace 310, and the fourth conductive trace 320.

[0081] In one embodiment, the conductive traces are typically made of a conductive metal, and at least a portion of the conductive traces are made of indium tin oxide (ITO).

[0082] In some embodiments, the gate drive circuit 210 may also include other circuits to provide other signals as needed, which will not be described in detail in the embodiments of this application.

[0083] Figure 6 A flowchart of a preparation method provided in an embodiment of this application is shown. For ease of explanation, only the parts relevant to this embodiment are shown, and are described in detail below:

[0084] A preparation method can be used to prepare a display module as described in any of the above embodiments, including steps S100 to S200.

[0085] Step S100: Provide a substrate.

[0086] Step S200: Construct a first circuit layer on one side of the substrate. (e.g.) Figure 1As shown, the first circuit layer 200 includes a first pixel circuit section 220 and a second pixel circuit section 230, as well as a gate driving circuit 210 disposed between the first pixel circuit section 220 and the second pixel circuit section 230. Both the first pixel circuit section 220 and the second pixel circuit section 230 are electrically connected to the gate driving circuit 210.

[0087] By placing the gate driving circuit 210 in the middle of the first circuit layer 200, the gate driving circuit 210 can provide driving signals from the middle to the light-emitting units on both sides, thereby reducing the maximum length of the conductive path between the gate driving circuit 210 and the light-emitting unit and reducing signal delay.

[0088] In one embodiment, the preparation method further includes step S300.

[0089] Step S300: On the side of the first circuit layer away from the substrate, a second circuit layer and a light-emitting layer are sequentially constructed.

[0090] After performing step S300, the obtained device is as follows: Figure 1 As shown, the second circuit layer 300 is used to transmit the sub-driving signals provided by the first circuit layer 200 to each light-emitting unit 410. In some embodiments, the first pixel circuit section 220 and the second pixel circuit section 230 are used to transmit driving signals to the second circuit layer 300, and the second circuit layer 300 is used to generate sub-driving signals corresponding to each light-emitting unit 410 based on the driving signals, and transmit each sub-driving signal to each light-emitting unit 410. It is understood that the first pixel circuit section 220, the second pixel circuit section 230 and the second circuit layer 300 all include a plurality of signal traces, and each signal trace can be disposed at the same or different layers, and signal traces at different layers can be connected through corresponding vias.

[0091] In one embodiment, as shown in the figure, step S300 includes steps S310 to S350.

[0092] Step S310: On the side surface of the first circuit layer away from the substrate, a second circuit layer, a first material layer, a second material layer and a third material layer are constructed sequentially.

[0093] After performing step S310, the structure of the obtained device is as follows: Figure 8 As shown, the second circuit layer 300, the first material layer 500, the second material layer 600 and the third material layer 700 are stacked sequentially on one side of the first circuit layer 200 along the direction away from the substrate 100.

[0094] Step S320: Etch the third material layer to form the second isolation layer.

[0095] Step S330: Etch the second material layer to form the first isolation portion. The first isolation portion 451 and the second isolation portion 452 can enclose and form multiple isolation openings.

[0096] Step S340: Etch the first material layer within the isolation opening to construct a pixel defining layer. The pixel defining layer 440 encloses and forms the pixel opening.

[0097] Step S350: Construct a light-emitting unit within the pixel opening.

[0098] After performing step S350, the structure of the obtained device is as follows: Figure 9 As shown, the orthographic projection of the first isolation portion 451 on the substrate 100 is located within the orthographic projection of the second isolation portion 452 on the substrate 100.

[0099] When constructing the light-emitting unit 410, the isolation between pixel openings can be further strengthened by the first isolation portion 451 and the second isolation portion 452 to prevent the light-emitting materials used to construct the light-emitting unit 410 in different pixel openings from connecting together.

[0100] Figure 10 A schematic diagram of a display panel according to an embodiment of this application is shown. For ease of explanation, only the parts relevant to this embodiment are shown, and the details are as follows:

[0101] The display panel 20 includes at least one display module 10 as described in any of the above embodiments. When there are multiple display modules 10, the structures of each display module 10 may be identical. Multiple display modules 10 may share the same substrate 100.

[0102] For example, such as Figure 10 As shown, Figure 10 Only two display modules 10 are shown. When multiple display modules 10 are used to form a display panel 20, each display module 10 can be driven independently by the gate drive circuit 210 in each display module 10. This can realize the partitioned driving of the display panel 20, reduce the signal delay of each light-emitting unit 410, and improve the response speed of the display panel 20.

[0103] In one embodiment, such as Figure 10 As shown, two display modules 10 are arranged adjacent to each other along the first direction. The gate driving circuit 210 of each display module 10 extends along the second direction, and the first direction is perpendicular to the second direction. That is, the four light-emitting areas are arranged adjacent to each other along the first direction in the order of first light-emitting area 420, second light-emitting area 430, and second light-emitting area 430.

[0104] Since each display module 10 includes two light-emitting areas and an independent gate driving circuit 210, the display panel 20 can be considered as having four light-emitting areas driven by two gate driving circuits 210. Because the gate driving circuit 210 provides driving signals from the center to the light-emitting units 410 on both sides, the length of the conductive path between the gate driving circuit 210 and each light-emitting unit 410 can be shortened, reducing signal delay.

[0105] Figure 11 A schematic diagram of a display device according to an embodiment of this application is shown. For ease of explanation, only the parts relevant to this embodiment are shown, and the details are as follows:

[0106] The display device 30 includes a display panel 20 as described in any of the above embodiments. Since the display device 30 includes the display panel 20 of any of the above embodiments, the display device 30 has the beneficial effects of the display panel 20 of any of the above embodiments, which will not be described again here.

[0107] The display device 30 in this application embodiment includes, but is not limited to, mobile phones, personal digital assistants (PDAs), tablet computers, e-books, televisions, access control systems, smart landline phones, control consoles, and other devices with display functions.

[0108] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0109] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0110] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A display module, characterized in that, include: Substrate (100); A first circuit layer (200) is disposed on one side of the substrate (100). The first circuit layer (200) includes a first pixel circuit section (220) and a second pixel circuit section (230) and a gate driving circuit (210) disposed between the first pixel circuit section (220) and the second pixel circuit section (230). Both the first pixel circuit section (220) and the second pixel circuit section (230) are electrically connected to the gate driving circuit (210).

2. The display module as described in claim 1, characterized in that, Also includes: A light-emitting layer (400) is located on the side of the first circuit layer (200) away from the substrate (100), and the light-emitting layer (400) includes a plurality of light-emitting units (410); A second circuit layer (300) is disposed between the first circuit layer (200) and the light-emitting layer (400). The second circuit layer (300) is used to electrically connect each of the light-emitting units (410) to the first pixel circuit section (220) or the second pixel circuit section (230).

3. The display module as described in claim 2, characterized in that, The light-emitting layer (400) includes a first light-emitting region (420) and a second light-emitting region (430); The orthographic projection of the boundary line between the first light-emitting area (420) and the second light-emitting area (430) onto the first circuit layer (200) is located in the gate driving circuit (210).

4. The display module as described in claim 3, characterized in that, The orthographic projection of the first light-emitting area (420) onto the first circuit layer (200) at least partially overlaps with the first pixel circuit section (220), and the orthographic projection of the second light-emitting area (430) onto the first circuit layer (200) at least partially overlaps with the second pixel circuit section (230).

5. The display module as described in claim 3, characterized in that, Each light-emitting unit (410) in the first light-emitting area (420) is electrically connected to the first pixel circuit section (220) through the second circuit layer (300); Each light-emitting unit (410) in the second light-emitting area (430) is electrically connected to the second pixel circuit section (230) through the second circuit layer (300).

6. The display module as described in claim 3, characterized in that, The number of light-emitting units (410) in the first light-emitting area (420) is the same as the number of light-emitting units (410) in the second light-emitting area (430).

7. The display module as described in claim 5, characterized in that, The shape of the first light-emitting area (420) is the same as the shape of the second light-emitting area (430).

8. The display module as described in any one of claims 2 to 7, characterized in that, It also includes a pixel defining layer (440), which is disposed on the side surface of the first circuit layer (200) away from the substrate (100). The pixel defining layer (440) encloses and forms a pixel opening, and the light-emitting unit (410) is located in the pixel opening.

9. The display module as described in claim 8, characterized in that, It also includes an isolation structure (450) disposed on the side surface of the pixel defining layer (440) away from the substrate (100), the isolation structure (450) enclosing to form a plurality of isolation openings, the pixel openings being located within the isolation openings.

10. The display module as described in claim 9, characterized in that, The isolation structure (450) includes a first isolation portion (451) and a second isolation portion (452) in sequence along the direction away from the substrate (100); The orthographic projection of the first isolation portion (451) on the substrate (100) lies within the orthographic projection of the second isolation portion (452) on the substrate (100).

11. The display module as described in claim 10, characterized in that, The first isolation portion (451) is made of aluminum, and the second isolation portion (452) is made of titanium.

12. The display module according to any one of claims 2 to 7, characterized in that, It also includes an encapsulation layer (460) that at least covers the surface of the light-emitting unit (410).

13. The display module according to any one of claims 2 to 7, characterized in that, The second circuit layer (300) is provided with a plurality of conductive traces, one end of which is electrically connected to the first circuit layer (200), and the other end of which is electrically connected to the corresponding light-emitting unit (410).

14. The display module as described in claim 13, characterized in that, At least some of the conductive traces are made of indium tin oxide.

15. A method for manufacturing a display module, characterized in that, include: Provide substrate (100); A first circuit layer (200) is constructed on one side of the substrate (100); wherein the first circuit layer (200) includes a first pixel circuit section (220) and a second pixel circuit section (230) and a gate driving circuit (210) disposed between the first pixel circuit section (220) and the second pixel circuit section (230), and both the first pixel circuit section (220) and the second pixel circuit section (230) are electrically connected to the gate driving circuit (210).

16. The preparation method according to claim 15, characterized in that, Also includes: On the side surface of the first circuit layer (200) away from the substrate (100), a second circuit layer (300) and a light-emitting layer (400) are sequentially constructed.

17. The preparation method according to claim 16, characterized in that, The construction of a second circuit layer (300) and a light-emitting layer (400) sequentially on the surface of the first circuit layer (200) away from the substrate (100) includes: On the side surface of the first circuit layer (200) away from the substrate (100), a second circuit layer (300), a first material layer (500), a second material layer (600), and a third material layer (700) are sequentially constructed. The third material layer (700) is etched to form the second isolation portion (452); The second material layer (600) is etched to form a first isolation portion (451); the first isolation portion (451) and the second isolation portion (452) enclose and form a plurality of isolation openings; The first material layer (500) within the isolation opening is etched to form a pixel opening; A light-emitting unit (410) is constructed within the pixel opening; The orthographic projection of the first isolation portion (451) on the substrate (100) is located within the orthographic projection of the second isolation portion (452) on the substrate (100).

18. A display panel, characterized in that, include: At least one display module (10) as described in any one of claims 1 to 14.

19. The display panel as claimed in claim 18, characterized in that, The two display modules (10) are arranged adjacent to each other along the first direction; The gate drive circuit (210) of each of the display modules (10) extends along a second direction, which is perpendicular to the second direction.

20. A display device, characterized in that, include: The display panel as described in claim 18 or 19.

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